From b6dace73c942cfee5186456e2b7d79d43a2bbbdf Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@nvidia.com>
Date: Fri, 16 Nov 2012 10:53:04 -0700
Subject: [PATCH] --- yaml --- r: 342272 b: refs/heads/master c:
 2658ef15b27e0fb166f4b7b997b027a223cd0793 h: refs/heads/master v: v3

---
 [refs]                                       |  2 +-
 trunk/arch/arm/boot/dts/tegra20-whistler.dts | 21 ++++++++++++++++++--
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index 2b50a55fba87..0d1aec713986 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: cab2ed62fe378be22c9de12ff8a616622b68c70c
+refs/heads/master: 2658ef15b27e0fb166f4b7b997b027a223cd0793
diff --git a/trunk/arch/arm/boot/dts/tegra20-whistler.dts b/trunk/arch/arm/boot/dts/tegra20-whistler.dts
index 94a71c91beb5..20d576ecd555 100644
--- a/trunk/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/trunk/arch/arm/boot/dts/tegra20-whistler.dts
@@ -10,6 +10,18 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
+	host1x {
+		hdmi {
+			status = "okay";
+
+			vdd-supply = <&hdmi_vdd_reg>;
+			pll-supply = <&hdmi_pll_reg>;
+
+			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+			nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+		};
+	};
+
 	pinmux {
 		pinctrl-names = "default";
 		pinctrl-0 = <&state_default>;
@@ -246,6 +258,11 @@
 		clock-frequency = <216000000>;
 	};
 
+	hdmi_ddc: i2c@7000c400 {
+		status = "okay";
+		clock-frequency = <100000>;
+	};
+
 	i2c@7000d000 {
 		status = "okay";
 		clock-frequency = <100000>;
@@ -356,7 +373,7 @@
 					regulator-always-on;
 				};
 
-				ldo6 {
+				hdmi_pll_reg: ldo6 {
 					regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
 					regulator-min-microvolt = <1800000>;
 					regulator-max-microvolt = <1800000>;
@@ -388,7 +405,7 @@
 					regulator-always-on;
 				};
 
-				ldo11 {
+				hdmi_vdd_reg: ldo11 {
 					regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
 					regulator-min-microvolt = <3300000>;
 					regulator-max-microvolt = <3300000>;