From b72b887695ee4b8671758cde6c83caa3d7c7caeb Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Mon, 8 Apr 2013 15:48:08 -0300 Subject: [PATCH] --- yaml --- r: 371491 b: refs/heads/master c: dc4bd2d1095d0a7b45dcd23cc8a423a2952cbf4d h: refs/heads/master i: 371489: 1012b8a0a7e8539ca9c3e509cc57bca4b68710f6 371487: 9e0966da57b01067762894bf41cb2a4d09ba8b52 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 7 +++++-- trunk/drivers/gpu/drm/i915/intel_pm.c | 7 ++++++- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 08319b1b160b..9c339c118bea 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3f704fa2778d3fe45e6529825a5c7a8bcbc686f4 +refs/heads/master: dc4bd2d1095d0a7b45dcd23cc8a423a2952cbf4d diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index fc8a4a940e92..31de7e4b1f3e 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -3959,8 +3959,11 @@ #define _TRANSA_CHICKEN2 0xf0064 #define _TRANSB_CHICKEN2 0xf1064 #define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) -#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) -#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) +#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31) +#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29) +#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27) +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26) +#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25) #define SOUTH_CHICKEN1 0xc2000 #define FDIA_PHASE_SYNC_SHIFT_OVR 19 diff --git a/trunk/drivers/gpu/drm/i915/intel_pm.c b/trunk/drivers/gpu/drm/i915/intel_pm.c index 6f67fa122f81..e34ad9642519 100644 --- a/trunk/drivers/gpu/drm/i915/intel_pm.c +++ b/trunk/drivers/gpu/drm/i915/intel_pm.c @@ -3604,9 +3604,14 @@ static void cpt_init_clock_gating(struct drm_device *dev) * downward, on (only) LVDS of some HP laptops with IVY. */ for_each_pipe(pipe) { - val = TRANS_CHICKEN2_TIMING_OVERRIDE; + val = I915_READ(TRANS_CHICKEN2(pipe)); + val |= TRANS_CHICKEN2_TIMING_OVERRIDE; + val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; if (dev_priv->fdi_rx_polarity_inverted) val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; + val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; + val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; + val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; I915_WRITE(TRANS_CHICKEN2(pipe), val); } /* WADP0ClockGatingDisable */