From b80ebff1e65b5e55b8a59a4d8f2c18ec7cb245e4 Mon Sep 17 00:00:00 2001 From: Jean-Hugues Deschenes Date: Thu, 6 Oct 2011 11:26:25 -0700 Subject: [PATCH] --- yaml --- r: 272445 b: refs/heads/master c: 7f279601c59b814314083d572e7c0df11d09cad8 h: refs/heads/master i: 272443: 9650e7e72aded729230f004ea774e9a3b9e4e513 v: v3 --- [refs] | 2 +- trunk/drivers/i2c/busses/i2c-designware.c | 88 +++---- trunk/drivers/i2c/busses/i2c-eg20t.c | 270 ++++++---------------- 3 files changed, 124 insertions(+), 236 deletions(-) diff --git a/[refs] b/[refs] index f0558489eeda..75628dfcea51 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 24597bf8012cf3fa5703c38e1bb13df3118d7588 +refs/heads/master: 7f279601c59b814314083d572e7c0df11d09cad8 diff --git a/trunk/drivers/i2c/busses/i2c-designware.c b/trunk/drivers/i2c/busses/i2c-designware.c index 1b42b50b5992..28335c3717d9 100644 --- a/trunk/drivers/i2c/busses/i2c-designware.c +++ b/trunk/drivers/i2c/busses/i2c-designware.c @@ -220,6 +220,16 @@ struct dw_i2c_dev { unsigned int rx_fifo_depth; }; +static u32 dw_readl(struct dw_i2c_dev *dev, int offset) +{ + return readl(dev->base + offset); +} + +static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) +{ + writel(b, dev->base + offset); +} + static u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) { @@ -289,7 +299,7 @@ static void i2c_dw_init(struct dw_i2c_dev *dev) u32 ic_con, hcnt, lcnt; /* Disable the adapter */ - writel(0, dev->base + DW_IC_ENABLE); + dw_writel(dev, 0, DW_IC_ENABLE); /* set standard and fast speed deviders for high/low periods */ @@ -303,8 +313,8 @@ static void i2c_dw_init(struct dw_i2c_dev *dev) 47, /* tLOW = 4.7 us */ 3, /* tf = 0.3 us */ 0); /* No offset */ - writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); - writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); + dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); + dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); /* Fast-mode */ @@ -317,18 +327,18 @@ static void i2c_dw_init(struct dw_i2c_dev *dev) 13, /* tLOW = 1.3 us */ 3, /* tf = 0.3 us */ 0); /* No offset */ - writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); - writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); + dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); + dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); /* Configure Tx/Rx FIFO threshold levels */ - writel(dev->tx_fifo_depth - 1, dev->base + DW_IC_TX_TL); - writel(0, dev->base + DW_IC_RX_TL); + dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); + dw_writel(dev, 0, DW_IC_RX_TL); /* configure the i2c master */ ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; - writel(ic_con, dev->base + DW_IC_CON); + dw_writel(dev, ic_con, DW_IC_CON); } /* @@ -338,7 +348,7 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) { int timeout = TIMEOUT; - while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { + while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { if (timeout <= 0) { dev_warn(dev->dev, "timeout waiting for bus ready\n"); return -ETIMEDOUT; @@ -356,24 +366,24 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) u32 ic_con; /* Disable the adapter */ - writel(0, dev->base + DW_IC_ENABLE); + dw_writel(dev, 0, DW_IC_ENABLE); /* set the slave (target) address */ - writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); + dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); /* if the slave address is ten bit address, enable 10BITADDR */ - ic_con = readl(dev->base + DW_IC_CON); + ic_con = dw_readl(dev, DW_IC_CON); if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) ic_con |= DW_IC_CON_10BITADDR_MASTER; else ic_con &= ~DW_IC_CON_10BITADDR_MASTER; - writel(ic_con, dev->base + DW_IC_CON); + dw_writel(dev, ic_con, DW_IC_CON); /* Enable the adapter */ - writel(1, dev->base + DW_IC_ENABLE); + dw_writel(dev, 1, DW_IC_ENABLE); /* Enable interrupts */ - writel(DW_IC_INTR_DEFAULT_MASK, dev->base + DW_IC_INTR_MASK); + dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); } /* @@ -420,15 +430,15 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) buf_len = msgs[dev->msg_write_idx].len; } - tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); - rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); + tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); + rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { - writel(0x100, dev->base + DW_IC_DATA_CMD); + dw_writel(dev, 0x100, DW_IC_DATA_CMD); rx_limit--; } else - writel(*buf++, dev->base + DW_IC_DATA_CMD); + dw_writel(dev, *buf++, DW_IC_DATA_CMD); tx_limit--; buf_len--; } @@ -453,7 +463,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) if (dev->msg_err) intr_mask = 0; - writel(intr_mask, dev->base + DW_IC_INTR_MASK); + dw_writel(dev, intr_mask, DW_IC_INTR_MASK); } static void @@ -477,10 +487,10 @@ i2c_dw_read(struct dw_i2c_dev *dev) buf = dev->rx_buf; } - rx_valid = readl(dev->base + DW_IC_RXFLR); + rx_valid = dw_readl(dev, DW_IC_RXFLR); for (; len > 0 && rx_valid > 0; len--, rx_valid--) - *buf++ = readl(dev->base + DW_IC_DATA_CMD); + *buf++ = dw_readl(dev, DW_IC_DATA_CMD); if (len > 0) { dev->status |= STATUS_READ_IN_PROGRESS; @@ -563,7 +573,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) /* no error */ if (likely(!dev->cmd_err)) { /* Disable the adapter */ - writel(0, dev->base + DW_IC_ENABLE); + dw_writel(dev, 0, DW_IC_ENABLE); ret = num; goto done; } @@ -607,7 +617,7 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) * * The raw version might be useful for debugging purposes. */ - stat = readl(dev->base + DW_IC_INTR_STAT); + stat = dw_readl(dev, DW_IC_INTR_STAT); /* * Do not use the IC_CLR_INTR register to clear interrupts, or @@ -617,31 +627,31 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) * Instead, use the separately-prepared IC_CLR_* registers. */ if (stat & DW_IC_INTR_RX_UNDER) - readl(dev->base + DW_IC_CLR_RX_UNDER); + dw_readl(dev, DW_IC_CLR_RX_UNDER); if (stat & DW_IC_INTR_RX_OVER) - readl(dev->base + DW_IC_CLR_RX_OVER); + dw_readl(dev, DW_IC_CLR_RX_OVER); if (stat & DW_IC_INTR_TX_OVER) - readl(dev->base + DW_IC_CLR_TX_OVER); + dw_readl(dev, DW_IC_CLR_TX_OVER); if (stat & DW_IC_INTR_RD_REQ) - readl(dev->base + DW_IC_CLR_RD_REQ); + dw_readl(dev, DW_IC_CLR_RD_REQ); if (stat & DW_IC_INTR_TX_ABRT) { /* * The IC_TX_ABRT_SOURCE register is cleared whenever * the IC_CLR_TX_ABRT is read. Preserve it beforehand. */ - dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); - readl(dev->base + DW_IC_CLR_TX_ABRT); + dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); + dw_readl(dev, DW_IC_CLR_TX_ABRT); } if (stat & DW_IC_INTR_RX_DONE) - readl(dev->base + DW_IC_CLR_RX_DONE); + dw_readl(dev, DW_IC_CLR_RX_DONE); if (stat & DW_IC_INTR_ACTIVITY) - readl(dev->base + DW_IC_CLR_ACTIVITY); + dw_readl(dev, DW_IC_CLR_ACTIVITY); if (stat & DW_IC_INTR_STOP_DET) - readl(dev->base + DW_IC_CLR_STOP_DET); + dw_readl(dev, DW_IC_CLR_STOP_DET); if (stat & DW_IC_INTR_START_DET) - readl(dev->base + DW_IC_CLR_START_DET); + dw_readl(dev, DW_IC_CLR_START_DET); if (stat & DW_IC_INTR_GEN_CALL) - readl(dev->base + DW_IC_CLR_GEN_CALL); + dw_readl(dev, DW_IC_CLR_GEN_CALL); return stat; } @@ -666,7 +676,7 @@ static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) * Anytime TX_ABRT is set, the contents of the tx/rx * buffers are flushed. Make sure to skip them. */ - writel(0, dev->base + DW_IC_INTR_MASK); + dw_writel(dev, 0, DW_IC_INTR_MASK); goto tx_aborted; } @@ -747,14 +757,14 @@ static int __devinit dw_i2c_probe(struct platform_device *pdev) goto err_unuse_clocks; } { - u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1); + u32 param1 = dw_readl(dev, DW_IC_COMP_PARAM_1); dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; } i2c_dw_init(dev); - writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */ + dw_writel(dev, 0, DW_IC_INTR_MASK); /* disable IRQ */ r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev); if (r) { dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); @@ -810,7 +820,7 @@ static int __devexit dw_i2c_remove(struct platform_device *pdev) clk_put(dev->clk); dev->clk = NULL; - writel(0, dev->base + DW_IC_ENABLE); + dw_writel(dev, 0, DW_IC_ENABLE); free_irq(dev->irq, dev); kfree(dev); diff --git a/trunk/drivers/i2c/busses/i2c-eg20t.c b/trunk/drivers/i2c/busses/i2c-eg20t.c index 8cebef49aeac..ce1a32b71e47 100644 --- a/trunk/drivers/i2c/busses/i2c-eg20t.c +++ b/trunk/drivers/i2c/busses/i2c-eg20t.c @@ -64,7 +64,6 @@ #define TEN_BIT_ADDR_DEFAULT 0xF000 #define TEN_BIT_ADDR_MASK 0xF0 #define PCH_START 0x0020 -#define PCH_RESTART 0x0004 #define PCH_ESR_START 0x0001 #define PCH_BUFF_START 0x1 #define PCH_REPSTART 0x0004 @@ -274,24 +273,23 @@ static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap, s32 timeout) { void __iomem *p = adap->pch_base_address; - ktime_t ns_val; - - if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0) - return 0; /* MAX timeout value is timeout*1000*1000nsec */ - ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000); + ktime_t ns_val = ktime_add_ns(ktime_get(), timeout*1000*1000); do { - msleep(20); if ((ioread32(p + PCH_I2CSR) & I2CMBB_BIT) == 0) - return 0; + break; + msleep(20); } while (ktime_lt(ktime_get(), ns_val)); pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR)); - pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME); - pch_i2c_init(adap); - return -ETIME; + if (timeout == 0) { + pch_err(adap, "%s: Timeout Error.return%d\n", __func__, -ETIME); + return -ETIME; + } + + return 0; } /** @@ -313,19 +311,21 @@ static void pch_i2c_start(struct i2c_algo_pch_data *adap) */ static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap) { - long ret; + s32 ret; ret = wait_event_timeout(pch_event, (adap->pch_event_flag != 0), msecs_to_jiffies(50)); + if (ret < 0) { + pch_err(adap, "timeout: %x\n", adap->pch_event_flag); + return ret; + } if (ret == 0) { pch_err(adap, "timeout: %x\n", adap->pch_event_flag); - adap->pch_event_flag = 0; return -ETIMEDOUT; } if (adap->pch_event_flag & I2C_ERROR_MASK) { pch_err(adap, "error bits set: %x\n", adap->pch_event_flag); - adap->pch_event_flag = 0; return -EIO; } @@ -394,7 +394,6 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap, u32 addr_2_msb; u32 addr_8_lsb; s32 wrcount; - s32 rtn; void __iomem *p = adap->pch_base_address; length = msgs->len; @@ -413,29 +412,15 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap, } if (msgs->flags & I2C_M_TEN) { - addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06; + addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7); iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); if (first) pch_i2c_start(adap); - - rtn = pch_i2c_wait_for_xfer_complete(adap); - if (rtn == 0) { - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave address" - "setting\n"); - return -EIO; - } + if (pch_i2c_wait_for_xfer_complete(adap) == 0 && + pch_i2c_getack(adap) == 0) { addr_8_lsb = (addr & I2C_ADDR_MSK); iowrite32(addr_8_lsb, p + PCH_I2CDR); - } else if (rtn == -EIO) { /* Arbitration Lost */ - pch_err(adap, "Lost Arbitration\n"); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, - I2CMAL_BIT); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, - I2CMIF_BIT); - pch_i2c_init(adap); - return -EAGAIN; - } else { /* wait-event timeout */ + } else { pch_i2c_stop(adap); return -ETIME; } @@ -446,51 +431,30 @@ static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap, pch_i2c_start(adap); } - rtn = pch_i2c_wait_for_xfer_complete(adap); - if (rtn == 0) { - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave address" - "setting\n"); - return -EIO; - } - } else if (rtn == -EIO) { /* Arbitration Lost */ - pch_err(adap, "Lost Arbitration\n"); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT); - pch_i2c_init(adap); - return -EAGAIN; - } else { /* wait-event timeout */ - pch_i2c_stop(adap); - return -ETIME; - } + if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && + (pch_i2c_getack(adap) == 0)) { + for (wrcount = 0; wrcount < length; ++wrcount) { + /* write buffer value to I2C data register */ + iowrite32(buf[wrcount], p + PCH_I2CDR); + pch_dbg(adap, "writing %x to Data register\n", + buf[wrcount]); - for (wrcount = 0; wrcount < length; ++wrcount) { - /* write buffer value to I2C data register */ - iowrite32(buf[wrcount], p + PCH_I2CDR); - pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]); + if (pch_i2c_wait_for_xfer_complete(adap) != 0) + return -ETIME; - rtn = pch_i2c_wait_for_xfer_complete(adap); - if (rtn == 0) { - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave address" - "setting\n"); + if (pch_i2c_getack(adap)) return -EIO; - } - pch_clrbit(adap->pch_base_address, PCH_I2CSR, - I2CMCF_BIT); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, - I2CMIF_BIT); - } else { /* wait-event timeout */ - pch_i2c_stop(adap); - return -ETIME; } - } - /* check if this is the last message */ - if (last) + /* check if this is the last message */ + if (last) + pch_i2c_stop(adap); + else + pch_i2c_repstart(adap); + } else { pch_i2c_stop(adap); - else - pch_i2c_repstart(adap); + return -EIO; + } pch_dbg(adap, "return=%d\n", wrcount); @@ -519,19 +483,6 @@ static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap) pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK); } -/** - * pch_i2c_restart() - Generate I2C restart condition in normal mode. - * @adap: Pointer to struct i2c_algo_pch_data. - * - * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA. - */ -static void pch_i2c_restart(struct i2c_algo_pch_data *adap) -{ - void __iomem *p = adap->pch_base_address; - pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL)); - pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART); -} - /** * pch_i2c_readbytes() - read data from I2C bus in normal mode. * @i2c_adap: Pointer to the struct i2c_adapter. @@ -549,9 +500,7 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, u32 length; u32 addr; u32 addr_2_msb; - u32 addr_8_lsb; void __iomem *p = adap->pch_base_address; - s32 rtn; length = msgs->len; buf = msgs->buf; @@ -566,55 +515,9 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, } if (msgs->flags & I2C_M_TEN) { - addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7); + addr_2_msb = (((addr & I2C_MSB_2B_MSK) >> 7) | (I2C_RD)); iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR); - if (first) - pch_i2c_start(adap); - rtn = pch_i2c_wait_for_xfer_complete(adap); - if (rtn == 0) { - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave address" - "setting\n"); - return -EIO; - } - addr_8_lsb = (addr & I2C_ADDR_MSK); - iowrite32(addr_8_lsb, p + PCH_I2CDR); - } else if (rtn == -EIO) { /* Arbitration Lost */ - pch_err(adap, "Lost Arbitration\n"); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, - I2CMAL_BIT); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, - I2CMIF_BIT); - pch_i2c_init(adap); - return -EAGAIN; - } else { /* wait-event timeout */ - pch_i2c_stop(adap); - return -ETIME; - } - pch_i2c_restart(adap); - rtn = pch_i2c_wait_for_xfer_complete(adap); - if (rtn == 0) { - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave address" - "setting\n"); - return -EIO; - } - addr_2_msb |= I2C_RD; - iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, - p + PCH_I2CDR); - } else if (rtn == -EIO) { /* Arbitration Lost */ - pch_err(adap, "Lost Arbitration\n"); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, - I2CMAL_BIT); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, - I2CMIF_BIT); - pch_i2c_init(adap); - return -EAGAIN; - } else { /* wait-event timeout */ - pch_i2c_stop(adap); - return -ETIME; - } } else { /* 7 address bits + R/W bit */ addr = (((addr) << 1) | (I2C_RD)); @@ -625,81 +528,56 @@ static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, if (first) pch_i2c_start(adap); - rtn = pch_i2c_wait_for_xfer_complete(adap); - if (rtn == 0) { - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave address" - "setting\n"); - return -EIO; - } - } else if (rtn == -EIO) { /* Arbitration Lost */ - pch_err(adap, "Lost Arbitration\n"); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT); - pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT); - pch_i2c_init(adap); - return -EAGAIN; - } else { /* wait-event timeout */ - pch_i2c_stop(adap); - return -ETIME; - } + if ((pch_i2c_wait_for_xfer_complete(adap) == 0) && + (pch_i2c_getack(adap) == 0)) { + pch_dbg(adap, "return %d\n", 0); - if (length == 0) { - pch_i2c_stop(adap); - ioread32(p + PCH_I2CDR); /* Dummy read needs */ + if (length == 0) { + pch_i2c_stop(adap); + ioread32(p + PCH_I2CDR); /* Dummy read needs */ - count = length; - } else { - int read_index; - int loop; - pch_i2c_sendack(adap); + count = length; + } else { + int read_index; + int loop; + pch_i2c_sendack(adap); - /* Dummy read */ - for (loop = 1, read_index = 0; loop < length; loop++) { - buf[read_index] = ioread32(p + PCH_I2CDR); + /* Dummy read */ + for (loop = 1, read_index = 0; loop < length; loop++) { + buf[read_index] = ioread32(p + PCH_I2CDR); - if (loop != 1) - read_index++; + if (loop != 1) + read_index++; - rtn = pch_i2c_wait_for_xfer_complete(adap); - if (rtn == 0) { - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave" - "address setting\n"); - return -EIO; + if (pch_i2c_wait_for_xfer_complete(adap) != 0) { + pch_i2c_stop(adap); + return -ETIME; } - } else { /* wait-event timeout */ - pch_i2c_stop(adap); - return -ETIME; - } + } /* end for */ - } /* end for */ + pch_i2c_sendnack(adap); - pch_i2c_sendnack(adap); + buf[read_index] = ioread32(p + PCH_I2CDR); - buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */ + if (length != 1) + read_index++; - if (length != 1) - read_index++; + if (pch_i2c_wait_for_xfer_complete(adap) == 0) { + if (last) + pch_i2c_stop(adap); + else + pch_i2c_repstart(adap); - rtn = pch_i2c_wait_for_xfer_complete(adap); - if (rtn == 0) { - if (pch_i2c_getack(adap)) { - pch_dbg(adap, "Receive NACK for slave" - "address setting\n"); - return -EIO; + buf[read_index++] = ioread32(p + PCH_I2CDR); + count = read_index; + } else { + count = -ETIME; } - } else { /* wait-event timeout */ - pch_i2c_stop(adap); - return -ETIME; - } - - if (last) - pch_i2c_stop(adap); - else - pch_i2c_repstart(adap); - buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */ - count = read_index; + } + } else { + count = -ETIME; + pch_i2c_stop(adap); } return count;