diff --git a/[refs] b/[refs]
index 0683f22570b8..7ab0eab6c8f7 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3bd8ef6799524fd48044a83aab38da57d9a98dbc
+refs/heads/master: adf27befdc79a9403bfba82ee84f02a47bcd546c
diff --git a/trunk/drivers/staging/brcm80211/brcmsmac/dma.h b/trunk/drivers/staging/brcm80211/brcmsmac/dma.h
index 134402cc008a..2ce5963818d4 100644
--- a/trunk/drivers/staging/brcm80211/brcmsmac/dma.h
+++ b/trunk/drivers/staging/brcm80211/brcmsmac/dma.h
@@ -100,21 +100,21 @@ void dma_walk_packets(struct dma_pub *dmah, void (*callback_fnc)
 		      (void *pkt, void *arg_a), void *arg_a);
 
 /*
- * DMA(Bug) on some chips seems to declare that the packet is ready, but the
- * packet length is not updated yet (by DMA) on the expected time.
+ * DMA(Bug) on bcm47xx chips seems to declare that the packet is ready, but
+ * the packet length is not updated yet (by DMA) on the expected time.
  * Workaround is to hold processor till DMA updates the length, and stay off
  * the bus to allow DMA update the length in buffer
  */
 static inline void dma_spin_for_len(uint len, struct sk_buff *head)
 {
-#if defined(__mips__)
+#if defined(CONFIG_BCM47XX)
 	if (!len) {
 		while (!(len = *(u16 *) KSEG1ADDR(head->data)))
 			udelay(1);
 
 		*(u16 *) (head->data) = cpu_to_le16((u16) len);
 	}
-#endif				/* defined(__mips__) */
+#endif				/* defined(CONFIG_BCM47XX) */
 }
 
 #endif				/* _BRCM_DMA_H_ */