From b8b98f70c88efe1682e7bbd45e5b295edf0a3d61 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Fri, 14 Dec 2012 11:36:43 +0100 Subject: [PATCH] --- yaml --- r: 355437 b: refs/heads/master c: f50a0380897d2a5e61b251b07c50ee48fa298cfd h: refs/heads/master i: 355435: 67ed933553de1dcb711d201984ffb2640a1ad8ab v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/gpmc-nand.c | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index ce7be2dca02b..654800fe6d4d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 504f3c6d73650d2afeabb86e29bfeb465f2b15df +refs/heads/master: f50a0380897d2a5e61b251b07c50ee48fa298cfd diff --git a/trunk/arch/arm/mach-omap2/gpmc-nand.c b/trunk/arch/arm/mach-omap2/gpmc-nand.c index 3059f5e8ee85..afc1e8c32d6c 100644 --- a/trunk/arch/arm/mach-omap2/gpmc-nand.c +++ b/trunk/arch/arm/mach-omap2/gpmc-nand.c @@ -92,17 +92,18 @@ static int omap2_nand_gpmc_retime( static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { /* support only OMAP3 class */ - if (!cpu_is_omap34xx()) { + if (!cpu_is_omap34xx() && !soc_is_am33xx()) { pr_err("BCH ecc is not supported on this CPU\n"); return 0; } /* - * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1. - * Other chips may be added if confirmed to work. + * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 + * and AM33xx derivates. Other chips may be added if confirmed to work. */ if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) { + (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && + (!soc_is_am33xx())) { pr_err("BCH 4-bit mode is not supported on this CPU\n"); return 0; }