From b8d61d8e245698dbdb91619033b919e20c7d2f3e Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Wed, 19 Dec 2012 10:18:39 -0800 Subject: [PATCH] --- yaml --- r: 355241 b: refs/heads/master c: d16aaf47ee2e668cc68a881bb957f0a7273d30ab h: refs/heads/master i: 355239: f3476fc2195ece525c18261deb583f7f29e3f9c2 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-zynq/timer.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 331e7fbab6c4..5824c8307387 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ec5b849ed77cd583fd888dfb41b6ebeb3989ec1a +refs/heads/master: d16aaf47ee2e668cc68a881bb957f0a7273d30ab diff --git a/trunk/arch/arm/mach-zynq/timer.c b/trunk/arch/arm/mach-zynq/timer.c index 80bf4742fe37..4b81ae1153d3 100644 --- a/trunk/arch/arm/mach-zynq/timer.c +++ b/trunk/arch/arm/mach-zynq/timer.c @@ -35,9 +35,9 @@ * Timer Register Offset Definitions of Timer 1, Increment base address by 4 * and use same offsets for Timer 2 */ -#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ -#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ -#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ +#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ #define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ #define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ #define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */