From ba182140f7653307b2f59912af9229a4cf094e1a Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 26 Jun 2006 16:16:07 -0700 Subject: [PATCH] --- yaml --- r: 31674 b: refs/heads/master c: 99c477074de4a91a388aff863646dc3e2eb783e2 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-omap/gpio.c | 17 ++++++++++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 2a7601617372..f2f78f283d4d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: eca9e56eb8dfcf2b8b966c1c49e4622196f0586d +refs/heads/master: 99c477074de4a91a388aff863646dc3e2eb783e2 diff --git a/trunk/arch/arm/plat-omap/gpio.c b/trunk/arch/arm/plat-omap/gpio.c index cd1e508f90c1..e75a2ca70ba1 100644 --- a/trunk/arch/arm/plat-omap/gpio.c +++ b/trunk/arch/arm/plat-omap/gpio.c @@ -540,29 +540,44 @@ static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) { void __iomem *reg = bank->base; + int inv = 0; + u32 l; + u32 mask; switch (bank->method) { case METHOD_MPUIO: reg += OMAP_MPUIO_GPIO_MASKIT; + mask = 0xffff; + inv = 1; break; case METHOD_GPIO_1510: reg += OMAP1510_GPIO_INT_MASK; + mask = 0xffff; + inv = 1; break; case METHOD_GPIO_1610: reg += OMAP1610_GPIO_IRQENABLE1; + mask = 0xffff; break; case METHOD_GPIO_730: reg += OMAP730_GPIO_INT_MASK; + mask = 0xffffffff; + inv = 1; break; case METHOD_GPIO_24XX: reg += OMAP24XX_GPIO_IRQENABLE1; + mask = 0xffffffff; break; default: BUG(); return 0; } - return __raw_readl(reg); + l = __raw_readl(reg); + if (inv) + l = ~l; + l &= mask; + return l; } static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)