From baad3d4e5ce53f7ac8b6be7c74b21be1f789a25e Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 23 May 2012 11:30:55 +0200 Subject: [PATCH] --- yaml --- r: 309373 b: refs/heads/master c: 0af78a2bb4296839cfe7a855cd128e8687e77bc1 h: refs/heads/master i: 309371: 068b3f139b64961a4643dffccbcd3f62a66a2f57 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_dp.c | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 2369b1f72543..54d7d13d4da3 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9589919fb3d269d4202a112b197468c7db1f97a3 +refs/heads/master: 0af78a2bb4296839cfe7a855cd128e8687e77bc1 diff --git a/trunk/drivers/gpu/drm/i915/intel_dp.c b/trunk/drivers/gpu/drm/i915/intel_dp.c index 3bbd7540bcd8..eb57ec7b36f4 100644 --- a/trunk/drivers/gpu/drm/i915/intel_dp.c +++ b/trunk/drivers/gpu/drm/i915/intel_dp.c @@ -266,6 +266,9 @@ intel_dp_mode_valid(struct drm_connector *connector, if (mode->clock < 10000) return MODE_CLOCK_LOW; + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return MODE_H_ILLEGAL; + return MODE_OK; } @@ -702,6 +705,9 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, mode->clock = intel_dp->panel_fixed_mode->clock; } + if (mode->flags & DRM_MODE_FLAG_DBLCLK) + return false; + DRM_DEBUG_KMS("DP link computation with max lane count %i " "max bw %02x pixel clock %iKHz\n", max_lane_count, bws[max_clock], mode->clock);