From bb7e06494d0d51deb7f977fb700385d963ce1fb3 Mon Sep 17 00:00:00 2001
From: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Date: Tue, 20 Jun 2006 23:26:30 +0900
Subject: [PATCH] --- yaml --- r: 31236 b: refs/heads/master c:
 08aecfb9eaf019f07384175101c970ede271c17a h: refs/heads/master v: v3

---
 [refs]                               | 2 +-
 trunk/arch/mips/gt64120/wrppmc/irq.c | 3 ---
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index f92cca7ebcb0..02991def5cc8 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1500b9a0f4381831e41f7e02f61dbef980ded342
+refs/heads/master: 08aecfb9eaf019f07384175101c970ede271c17a
diff --git a/trunk/arch/mips/gt64120/wrppmc/irq.c b/trunk/arch/mips/gt64120/wrppmc/irq.c
index 26cf360f1694..8d75a43ce877 100644
--- a/trunk/arch/mips/gt64120/wrppmc/irq.c
+++ b/trunk/arch/mips/gt64120/wrppmc/irq.c
@@ -62,9 +62,6 @@ void gt64120_init_pic(void)
 
 void __init arch_init_irq(void)
 {
-	/* enable all CPU interrupt bits. */
-	set_c0_status(ST0_IM);	/* IE bit is still 0 */
-
 	/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
 	mips_cpu_irq_init(0);