From bcb14c3854bce6f312bfe32bf3b67ef60cb83cc2 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 4 Dec 2012 22:55:13 +0800 Subject: [PATCH] --- yaml --- r: 355526 b: refs/heads/master c: 485863b8fa02d515e48ce6b59f01d62172d2fe0d h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-imx/gpc.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 5a2d3f143a03..09f8a0ca10b9 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: eea8e326ff476e418b99b6daa97f9bd85ac6c523 +refs/heads/master: 485863b8fa02d515e48ce6b59f01d62172d2fe0d diff --git a/trunk/arch/arm/mach-imx/gpc.c b/trunk/arch/arm/mach-imx/gpc.c index e1537f9e45b8..722e5df7e44e 100644 --- a/trunk/arch/arm/mach-imx/gpc.c +++ b/trunk/arch/arm/mach-imx/gpc.c @@ -101,11 +101,16 @@ static void imx_gpc_irq_mask(struct irq_data *d) void __init imx_gpc_init(void) { struct device_node *np; + int i; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); gpc_base = of_iomap(np, 0); WARN_ON(!gpc_base); + /* Initially mask all interrupts */ + for (i = 0; i < IMR_NUM; i++) + writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4); + /* Register GPC as the secondary interrupt controller behind GIC */ gic_arch_extn.irq_mask = imx_gpc_irq_mask; gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;