From be15aae5479f05b29c6a4f25fa46bb100c11dd9c Mon Sep 17 00:00:00 2001 From: Alexandre Pereira da Silva Date: Fri, 20 Jul 2012 14:01:51 +0200 Subject: [PATCH] --- yaml --- r: 313209 b: refs/heads/master c: 1f37a3a32b86c443396293b1f9d3e23b0a0344e5 h: refs/heads/master i: 313207: 2f4686c6841fd61ab39741c528b48d45c7ab8c9b v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-lpc32xx/clock.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index c72586abbfe3..86f1d6daf0b4 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e39942f527fb02b73236d872d22c1b6b8335266c +refs/heads/master: 1f37a3a32b86c443396293b1f9d3e23b0a0344e5 diff --git a/trunk/arch/arm/mach-lpc32xx/clock.c b/trunk/arch/arm/mach-lpc32xx/clock.c index 8a4e7cb74ae1..f48c2e961b84 100644 --- a/trunk/arch/arm/mach-lpc32xx/clock.c +++ b/trunk/arch/arm/mach-lpc32xx/clock.c @@ -607,6 +607,19 @@ static struct clk clk_dma = { .get_rate = local_return_parent_rate, }; +static struct clk clk_pwm = { + .parent = &clk_pclk, + .enable = local_onoff_enable, + .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL, + .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) | + LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN | + LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK | + LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1), + .get_rate = local_return_parent_rate, +}; + static struct clk clk_uart3 = { .parent = &clk_pclk, .enable = local_onoff_enable, @@ -1188,6 +1201,7 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), + CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm), CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),