From be3591b02880aa7867d64031e1cf24d1a085c629 Mon Sep 17 00:00:00 2001
From: Magnus Damm <magnus.damm@gmail.com>
Date: Thu, 24 Apr 2008 21:41:12 +0900
Subject: [PATCH] --- yaml --- r: 96293 b: refs/heads/master c:
 995d538a5b09e3c129d8aac559f07a0f5cc3fc3c h: refs/heads/master i:   96291:
 b81c6a8b9202c98e8eaf3cc12602ecf5aad849bf v: v3

---
 [refs]                                      | 2 +-
 trunk/arch/sh/kernel/cpu/sh3/setup-sh7710.c | 5 +----
 trunk/arch/sh/kernel/cpu/sh3/setup-sh7720.c | 4 ----
 3 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/[refs] b/[refs]
index c312ff3df8e7..7766c25a2d63 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: d58876e289b0153bf86162aa1a43249e0f0aa03d
+refs/heads/master: 995d538a5b09e3c129d8aac559f07a0f5cc3fc3c
diff --git a/trunk/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/trunk/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index f353a001fba6..77eee481de47 100644
--- a/trunk/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/trunk/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -79,10 +79,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
 	{ 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
 	{ 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
 	{ 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
-	{ 0xa4080000, 0, 16, 4, /* IPRF */ { 0, DMAC2 } },
-#ifdef CONFIG_CPU_SUBTYPE_SH7710
-	{ 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC } },
-#endif
+	{ 0xa4080000, 0, 16, 4, /* IPRF */ { IPSEC, DMAC2 } },
 	{ 0xa4080002, 0, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
 	{ 0xa4080004, 0, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
 	{ 0xa4080006, 0, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
diff --git a/trunk/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/trunk/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 0e6e66e7b584..f807a21b066c 100644
--- a/trunk/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/trunk/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -211,11 +211,7 @@ static struct intc_prio_reg prio_registers[] __initdata = {
 	{ 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
 	{ 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
 	{ 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
-#if defined(CONFIG_CPU_SUBTYPE_SH7720)
 	{ 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
-#else
-	{ 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } },
-#endif
 	{ 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
 	{ 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
 	{ 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },