From be379768de9d5d5ac05d1f40b5887cf4fcbc8a30 Mon Sep 17 00:00:00 2001
From: Yaniv Rosner <yanivr@broadcom.com>
Date: Wed, 4 Apr 2012 01:29:01 +0000
Subject: [PATCH] --- yaml --- r: 298770 b: refs/heads/master c:
 99bf7f34368aac9b54dfa8801ae490a2326704f9 h: refs/heads/master v: v3

---
 [refs]                                                 | 2 +-
 trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c | 9 +++++++++
 trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h  | 3 +++
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 5fae816b066b..1a164dfcc66e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8267bbb01f005fa8d0c8d046ecc24ae0b52e4d70
+refs/heads/master: 99bf7f34368aac9b54dfa8801ae490a2326704f9
diff --git a/trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index b576a3ae8e91..ce95ef71f96f 100644
--- a/trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -9858,6 +9858,15 @@ static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
 				other_shmem_base_addr));
 
 	u32 shmem_base_path[2];
+
+	/* Work around for 84833 LED failure inside RESET status */
+	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
+		MDIO_AN_REG_8481_LEGACY_MII_CTRL,
+		MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
+	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
+		MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
+		MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
+
 	shmem_base_path[0] = params->shmem_base;
 	shmem_base_path[1] = other_shmem_base_addr;
 
diff --git a/trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
index 1ea2b956e194..c25803b9c0ca 100644
--- a/trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
+++ b/trunk/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
@@ -6821,10 +6821,13 @@ Theotherbitsarereservedandshouldbezero*/
 
 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL	0x0020
 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL	0xffe0
+#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G	0x40
 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS	0xffe1
 #define MDIO_AN_REG_8481_LEGACY_AN_ADV		0xffe4
 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION	0xffe6
 #define MDIO_AN_REG_8481_1000T_CTRL		0xffe9
+#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL	0xfff0
+#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF	0x0008
 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW	0xfff5
 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS	0xfff7
 #define MDIO_AN_REG_8481_AUX_CTRL		0xfff8