From bf865fe7bcb602273c4f5f3424a0f67ede842f82 Mon Sep 17 00:00:00 2001 From: "hdoyu@nvidia.com" Date: Wed, 9 May 2012 21:50:21 +0000 Subject: [PATCH] --- yaml --- r: 308369 b: refs/heads/master c: 54174a33da64536d6840ffa5ae9edc71cb9bf3a1 h: refs/heads/master i: 308367: f9ecfa7b9753aafe03654741e3902226ca7f188c v: v3 --- [refs] | 2 +- trunk/arch/arm/boot/dts/tegra30.dtsi | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 279347c34ee9..3760cef56456 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6a943e0e13900881ff6b980441233e10a6642904 +refs/heads/master: 54174a33da64536d6840ffa5ae9edc71cb9bf3a1 diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index 167ccbcd9b86..e9792ac03635 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -238,4 +238,14 @@ 0x7000f284 0x17c>; interrupts = <0 77 0x04>; }; + + smmu { + compatible = "nvidia,tegra30-smmu"; + reg = <0x7000f010 0x02c + 0x7000f1f0 0x010 + 0x7000f228 0x05c>; + nvidia,#asids = <4>; /* # of ASIDs */ + dma-window = <0 0x40000000>; /* IOVA start & length */ + nvidia,ahb = <&ahb>; + }; };