From bf9d65096128e96eb76141ac8b83c7274edb99ef Mon Sep 17 00:00:00 2001 From: John Crispin Date: Fri, 20 Jul 2012 18:58:34 +0200 Subject: [PATCH] --- yaml --- r: 360061 b: refs/heads/master c: 247796175ea5dc7c838e8e76a14795fb09360649 h: refs/heads/master i: 360059: c7f7c1665afe7aa9e3af66f5b763b2780256bfe7 v: v3 --- [refs] | 2 +- .../devicetree/bindings/serial/lantiq_asc.txt | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 trunk/Documentation/devicetree/bindings/serial/lantiq_asc.txt diff --git a/[refs] b/[refs] index a10d752acf36..c233254b8c51 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 9c099c4e79b67d5578ce8142e6214950be4fcf43 +refs/heads/master: 247796175ea5dc7c838e8e76a14795fb09360649 diff --git a/trunk/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/trunk/Documentation/devicetree/bindings/serial/lantiq_asc.txt new file mode 100644 index 000000000000..5b78591aaa46 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/serial/lantiq_asc.txt @@ -0,0 +1,16 @@ +Lantiq SoC ASC serial controller + +Required properties: +- compatible : Should be "lantiq,asc" +- reg : Address and length of the register set for the device +- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier + depends on the interrupt-parent interrupt controller. + +Example: + +asc1: serial@E100C00 { + compatible = "lantiq,asc"; + reg = <0xE100C00 0x400>; + interrupt-parent = <&icu0>; + interrupts = <112 113 114>; +};