diff --git a/[refs] b/[refs]
index a2bcccc4977c..19f03713959d 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b15a6d62b5482966d0605e24c728bea8f7f876eb
+refs/heads/master: 1bbb6c1b7b6c4dffd0d5ff8787691e0ea4c6a796
diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig
index d46f1da18a3c..e7587ac3265a 100644
--- a/trunk/arch/mips/Kconfig
+++ b/trunk/arch/mips/Kconfig
@@ -1413,51 +1413,36 @@ config CPU_CAVIUM_OCTEON
 config CPU_BMIPS3300
 	bool "BMIPS3300"
 	depends on SYS_HAS_CPU_BMIPS3300
-	select DMA_NONCOHERENT
-	select IRQ_CPU
-	select SWAP_IO_SPACE
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select WEAK_ORDERING
+	select CPU_BMIPS
 	help
 	  Broadcom BMIPS3300 processors.
 
 config CPU_BMIPS4350
 	bool "BMIPS4350"
 	depends on SYS_HAS_CPU_BMIPS4350
-	select CPU_SUPPORTS_32BIT_KERNEL
-	select DMA_NONCOHERENT
-	select IRQ_CPU
-	select SWAP_IO_SPACE
+	select CPU_BMIPS
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
-	select WEAK_ORDERING
 	help
 	  Broadcom BMIPS4350 ("VIPER") processors.
 
 config CPU_BMIPS4380
 	bool "BMIPS4380"
 	depends on SYS_HAS_CPU_BMIPS4380
-	select CPU_SUPPORTS_32BIT_KERNEL
-	select DMA_NONCOHERENT
-	select IRQ_CPU
-	select SWAP_IO_SPACE
+	select CPU_BMIPS
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
-	select WEAK_ORDERING
 	help
 	  Broadcom BMIPS4380 processors.
 
 config CPU_BMIPS5000
 	bool "BMIPS5000"
 	depends on SYS_HAS_CPU_BMIPS5000
-	select CPU_SUPPORTS_32BIT_KERNEL
+	select CPU_BMIPS
 	select CPU_SUPPORTS_HIGHMEM
-	select DMA_NONCOHERENT
-	select IRQ_CPU
-	select SWAP_IO_SPACE
+	select MIPS_CPU_SCACHE
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
-	select WEAK_ORDERING
 	help
 	  Broadcom BMIPS5000 processors.
 
@@ -1518,6 +1503,15 @@ config CPU_LOONGSON2
 	select CPU_SUPPORTS_64BIT_KERNEL
 	select CPU_SUPPORTS_HIGHMEM
 
+config CPU_BMIPS
+	bool
+	select CPU_MIPS32
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select DMA_NONCOHERENT
+	select IRQ_CPU
+	select SWAP_IO_SPACE
+	select WEAK_ORDERING
+
 config SYS_HAS_CPU_LOONGSON2E
 	bool
 
diff --git a/trunk/arch/mips/bcm63xx/Kconfig b/trunk/arch/mips/bcm63xx/Kconfig
index 6b1b9ad8d857..fb177d6df066 100644
--- a/trunk/arch/mips/bcm63xx/Kconfig
+++ b/trunk/arch/mips/bcm63xx/Kconfig
@@ -20,10 +20,6 @@ config BCM63XX_CPU_6348
 config BCM63XX_CPU_6358
 	bool "support 6358 CPU"
 	select HW_HAS_PCI
-
-config BCM63XX_CPU_6368
-	bool "support 6368 CPU"
-	select HW_HAS_PCI
 endmenu
 
 source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c b/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c
index e62461f817d7..40b223b603be 100644
--- a/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -709,9 +709,15 @@ void __init board_prom_init(void)
 	char cfe_version[32];
 	u32 val;
 
-	/* read base address of boot chip select (0) */
-	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-	val &= MPI_CSBASE_BASE_MASK;
+	/* read base address of boot chip select (0)
+	 * 6345 does not have MPI but boots from standard
+	 * MIPS Flash address */
+	if (BCMCPU_IS_6345())
+		val = 0x1fc00000;
+	else {
+		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+		val &= MPI_CSBASE_BASE_MASK;
+	}
 	boot_addr = (u8 *)KSEG1ADDR(val);
 
 	/* dump cfe version */
@@ -791,6 +797,18 @@ void __init board_prom_init(void)
 	}
 
 	bcm_gpio_writel(val, GPIO_MODE_REG);
+
+	/* Generate MAC address for WLAN and
+	 * register our SPROM */
+#ifdef CONFIG_SSB_PCIHOST
+	if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
+		memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+		memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
+		if (ssb_arch_register_fallback_sprom(
+				&bcm63xx_get_fallback_sprom) < 0)
+			printk(KERN_ERR PFX "failed to register fallback SPROM\n");
+	}
+#endif
 }
 
 /*
@@ -874,23 +892,13 @@ int __init board_register_devices(void)
 	if (board.has_dsp)
 		bcm63xx_dsp_register(&board.dsp);
 
-	/* Generate MAC address for WLAN and register our SPROM,
-	 * do this after registering enet devices
-	 */
-#ifdef CONFIG_SSB_PCIHOST
-	if (!board_get_mac_address(bcm63xx_sprom.il0mac)) {
-		memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN);
-		memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN);
-		if (ssb_arch_register_fallback_sprom(
-				&bcm63xx_get_fallback_sprom) < 0)
-			pr_err(PFX "failed to register fallback SPROM\n");
-	}
-#endif
-
 	/* read base address of boot chip select (0) */
-	val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-	val &= MPI_CSBASE_BASE_MASK;
-
+	if (BCMCPU_IS_6345())
+		val = 0x1fc00000;
+	else {
+		val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+		val &= MPI_CSBASE_BASE_MASK;
+	}
 	mtd_resources[0].start = val;
 	mtd_resources[0].end = 0x1FFFFFFF;
 
diff --git a/trunk/arch/mips/bcm63xx/clk.c b/trunk/arch/mips/bcm63xx/clk.c
index 9d57c71b7b58..2c68ee9ccee2 100644
--- a/trunk/arch/mips/bcm63xx/clk.c
+++ b/trunk/arch/mips/bcm63xx/clk.c
@@ -10,7 +10,6 @@
 #include <linux/mutex.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <linux/delay.h>
 #include <bcm63xx_cpu.h>
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
@@ -113,34 +112,6 @@ static struct clk clk_ephy = {
 	.set	= ephy_set,
 };
 
-/*
- * Ethernet switch clock
- */
-static void enetsw_set(struct clk *clk, int enable)
-{
-	if (!BCMCPU_IS_6368())
-		return;
-	bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
-			CKCTL_6368_SWPKT_USB_EN |
-			CKCTL_6368_SWPKT_SAR_EN, enable);
-	if (enable) {
-		u32 val;
-
-		/* reset switch core afer clock change */
-		val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
-		val &= ~SOFTRESET_6368_ENETSW_MASK;
-		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
-		msleep(10);
-		val |= SOFTRESET_6368_ENETSW_MASK;
-		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
-		msleep(10);
-	}
-}
-
-static struct clk clk_enetsw = {
-	.set	= enetsw_set,
-};
-
 /*
  * PCM clock
  */
@@ -160,10 +131,9 @@ static struct clk clk_pcm = {
  */
 static void usbh_set(struct clk *clk, int enable)
 {
-	if (BCMCPU_IS_6348())
-		bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
-	else if (BCMCPU_IS_6368())
-		bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
+	if (!BCMCPU_IS_6348())
+		return;
+	bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
 }
 
 static struct clk clk_usbh = {
@@ -191,36 +161,6 @@ static struct clk clk_spi = {
 	.set	= spi_set,
 };
 
-/*
- * XTM clock
- */
-static void xtm_set(struct clk *clk, int enable)
-{
-	if (!BCMCPU_IS_6368())
-		return;
-
-	bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
-			CKCTL_6368_SWPKT_SAR_EN, enable);
-
-	if (enable) {
-		u32 val;
-
-		/* reset sar core afer clock change */
-		val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
-		val &= ~SOFTRESET_6368_SAR_MASK;
-		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
-		mdelay(1);
-		val |= SOFTRESET_6368_SAR_MASK;
-		bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
-		mdelay(1);
-	}
-}
-
-
-static struct clk clk_xtm = {
-	.set	= xtm_set,
-};
-
 /*
  * Internal peripheral clock
  */
@@ -264,16 +204,12 @@ struct clk *clk_get(struct device *dev, const char *id)
 		return &clk_enet0;
 	if (!strcmp(id, "enet1"))
 		return &clk_enet1;
-	if (!strcmp(id, "enetsw"))
-		return &clk_enetsw;
 	if (!strcmp(id, "ephy"))
 		return &clk_ephy;
 	if (!strcmp(id, "usbh"))
 		return &clk_usbh;
 	if (!strcmp(id, "spi"))
 		return &clk_spi;
-	if (!strcmp(id, "xtm"))
-		return &clk_xtm;
 	if (!strcmp(id, "periph"))
 		return &clk_periph;
 	if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
diff --git a/trunk/arch/mips/bcm63xx/cpu.c b/trunk/arch/mips/bcm63xx/cpu.c
index 8f0d6c7725ea..7c7e4d4486ce 100644
--- a/trunk/arch/mips/bcm63xx/cpu.c
+++ b/trunk/arch/mips/bcm63xx/cpu.c
@@ -29,47 +29,166 @@ static u16 bcm63xx_cpu_rev;
 static unsigned int bcm63xx_cpu_freq;
 static unsigned int bcm63xx_memory_size;
 
-static const unsigned long bcm6338_regs_base[] = {
-	__GEN_CPU_REGS_TABLE(6338)
-};
-
-static const int bcm6338_irqs[] = {
-	__GEN_CPU_IRQ_TABLE(6338)
-};
-
-static const unsigned long bcm6345_regs_base[] = {
-	__GEN_CPU_REGS_TABLE(6345)
+/*
+ * 6338 register sets and irqs
+ */
+static const unsigned long bcm96338_regs_base[] = {
+	[RSET_DSL_LMEM]		= BCM_6338_DSL_LMEM_BASE,
+	[RSET_PERF]		= BCM_6338_PERF_BASE,
+	[RSET_TIMER]		= BCM_6338_TIMER_BASE,
+	[RSET_WDT]		= BCM_6338_WDT_BASE,
+	[RSET_UART0]		= BCM_6338_UART0_BASE,
+	[RSET_UART1]		= BCM_6338_UART1_BASE,
+	[RSET_GPIO]		= BCM_6338_GPIO_BASE,
+	[RSET_SPI]		= BCM_6338_SPI_BASE,
+	[RSET_OHCI0]		= BCM_6338_OHCI0_BASE,
+	[RSET_OHCI_PRIV]	= BCM_6338_OHCI_PRIV_BASE,
+	[RSET_USBH_PRIV]	= BCM_6338_USBH_PRIV_BASE,
+	[RSET_UDC0]		= BCM_6338_UDC0_BASE,
+	[RSET_MPI]		= BCM_6338_MPI_BASE,
+	[RSET_PCMCIA]		= BCM_6338_PCMCIA_BASE,
+	[RSET_SDRAM]		= BCM_6338_SDRAM_BASE,
+	[RSET_DSL]		= BCM_6338_DSL_BASE,
+	[RSET_ENET0]		= BCM_6338_ENET0_BASE,
+	[RSET_ENET1]		= BCM_6338_ENET1_BASE,
+	[RSET_ENETDMA]		= BCM_6338_ENETDMA_BASE,
+	[RSET_MEMC]		= BCM_6338_MEMC_BASE,
+	[RSET_DDR]		= BCM_6338_DDR_BASE,
 };
 
-static const int bcm6345_irqs[] = {
-	__GEN_CPU_IRQ_TABLE(6345)
+static const int bcm96338_irqs[] = {
+	[IRQ_TIMER]		= BCM_6338_TIMER_IRQ,
+	[IRQ_UART0]		= BCM_6338_UART0_IRQ,
+	[IRQ_DSL]		= BCM_6338_DSL_IRQ,
+	[IRQ_ENET0]		= BCM_6338_ENET0_IRQ,
+	[IRQ_ENET_PHY]		= BCM_6338_ENET_PHY_IRQ,
+	[IRQ_ENET0_RXDMA]	= BCM_6338_ENET0_RXDMA_IRQ,
+	[IRQ_ENET0_TXDMA]	= BCM_6338_ENET0_TXDMA_IRQ,
 };
 
-static const unsigned long bcm6348_regs_base[] = {
-	__GEN_CPU_REGS_TABLE(6348)
+/*
+ * 6345 register sets and irqs
+ */
+static const unsigned long bcm96345_regs_base[] = {
+	[RSET_DSL_LMEM]		= BCM_6345_DSL_LMEM_BASE,
+	[RSET_PERF]		= BCM_6345_PERF_BASE,
+	[RSET_TIMER]		= BCM_6345_TIMER_BASE,
+	[RSET_WDT]		= BCM_6345_WDT_BASE,
+	[RSET_UART0]		= BCM_6345_UART0_BASE,
+	[RSET_UART1]		= BCM_6345_UART1_BASE,
+	[RSET_GPIO]		= BCM_6345_GPIO_BASE,
+	[RSET_SPI]		= BCM_6345_SPI_BASE,
+	[RSET_UDC0]		= BCM_6345_UDC0_BASE,
+	[RSET_OHCI0]		= BCM_6345_OHCI0_BASE,
+	[RSET_OHCI_PRIV]	= BCM_6345_OHCI_PRIV_BASE,
+	[RSET_USBH_PRIV]	= BCM_6345_USBH_PRIV_BASE,
+	[RSET_MPI]		= BCM_6345_MPI_BASE,
+	[RSET_PCMCIA]		= BCM_6345_PCMCIA_BASE,
+	[RSET_DSL]		= BCM_6345_DSL_BASE,
+	[RSET_ENET0]		= BCM_6345_ENET0_BASE,
+	[RSET_ENET1]		= BCM_6345_ENET1_BASE,
+	[RSET_ENETDMA]		= BCM_6345_ENETDMA_BASE,
+	[RSET_EHCI0]		= BCM_6345_EHCI0_BASE,
+	[RSET_SDRAM]		= BCM_6345_SDRAM_BASE,
+	[RSET_MEMC]		= BCM_6345_MEMC_BASE,
+	[RSET_DDR]		= BCM_6345_DDR_BASE,
 };
 
-static const int bcm6348_irqs[] = {
-	__GEN_CPU_IRQ_TABLE(6348)
-
+static const int bcm96345_irqs[] = {
+	[IRQ_TIMER]		= BCM_6345_TIMER_IRQ,
+	[IRQ_UART0]		= BCM_6345_UART0_IRQ,
+	[IRQ_DSL]		= BCM_6345_DSL_IRQ,
+	[IRQ_ENET0]		= BCM_6345_ENET0_IRQ,
+	[IRQ_ENET_PHY]		= BCM_6345_ENET_PHY_IRQ,
+	[IRQ_ENET0_RXDMA]	= BCM_6345_ENET0_RXDMA_IRQ,
+	[IRQ_ENET0_TXDMA]	= BCM_6345_ENET0_TXDMA_IRQ,
 };
 
-static const unsigned long bcm6358_regs_base[] = {
-	__GEN_CPU_REGS_TABLE(6358)
+/*
+ * 6348 register sets and irqs
+ */
+static const unsigned long bcm96348_regs_base[] = {
+	[RSET_DSL_LMEM]		= BCM_6348_DSL_LMEM_BASE,
+	[RSET_PERF]		= BCM_6348_PERF_BASE,
+	[RSET_TIMER]		= BCM_6348_TIMER_BASE,
+	[RSET_WDT]		= BCM_6348_WDT_BASE,
+	[RSET_UART0]		= BCM_6348_UART0_BASE,
+	[RSET_UART1]		= BCM_6348_UART1_BASE,
+	[RSET_GPIO]		= BCM_6348_GPIO_BASE,
+	[RSET_SPI]		= BCM_6348_SPI_BASE,
+	[RSET_OHCI0]		= BCM_6348_OHCI0_BASE,
+	[RSET_OHCI_PRIV]	= BCM_6348_OHCI_PRIV_BASE,
+	[RSET_USBH_PRIV]	= BCM_6348_USBH_PRIV_BASE,
+	[RSET_MPI]		= BCM_6348_MPI_BASE,
+	[RSET_PCMCIA]		= BCM_6348_PCMCIA_BASE,
+	[RSET_SDRAM]		= BCM_6348_SDRAM_BASE,
+	[RSET_DSL]		= BCM_6348_DSL_BASE,
+	[RSET_ENET0]		= BCM_6348_ENET0_BASE,
+	[RSET_ENET1]		= BCM_6348_ENET1_BASE,
+	[RSET_ENETDMA]		= BCM_6348_ENETDMA_BASE,
+	[RSET_MEMC]		= BCM_6348_MEMC_BASE,
+	[RSET_DDR]		= BCM_6348_DDR_BASE,
 };
 
-static const int bcm6358_irqs[] = {
-	__GEN_CPU_IRQ_TABLE(6358)
-
+static const int bcm96348_irqs[] = {
+	[IRQ_TIMER]		= BCM_6348_TIMER_IRQ,
+	[IRQ_UART0]		= BCM_6348_UART0_IRQ,
+	[IRQ_DSL]		= BCM_6348_DSL_IRQ,
+	[IRQ_ENET0]		= BCM_6348_ENET0_IRQ,
+	[IRQ_ENET1]		= BCM_6348_ENET1_IRQ,
+	[IRQ_ENET_PHY]		= BCM_6348_ENET_PHY_IRQ,
+	[IRQ_OHCI0]		= BCM_6348_OHCI0_IRQ,
+	[IRQ_PCMCIA]		= BCM_6348_PCMCIA_IRQ,
+	[IRQ_ENET0_RXDMA]	= BCM_6348_ENET0_RXDMA_IRQ,
+	[IRQ_ENET0_TXDMA]	= BCM_6348_ENET0_TXDMA_IRQ,
+	[IRQ_ENET1_RXDMA]	= BCM_6348_ENET1_RXDMA_IRQ,
+	[IRQ_ENET1_TXDMA]	= BCM_6348_ENET1_TXDMA_IRQ,
+	[IRQ_PCI]		= BCM_6348_PCI_IRQ,
 };
 
-static const unsigned long bcm6368_regs_base[] = {
-	__GEN_CPU_REGS_TABLE(6368)
+/*
+ * 6358 register sets and irqs
+ */
+static const unsigned long bcm96358_regs_base[] = {
+	[RSET_DSL_LMEM]		= BCM_6358_DSL_LMEM_BASE,
+	[RSET_PERF]		= BCM_6358_PERF_BASE,
+	[RSET_TIMER]		= BCM_6358_TIMER_BASE,
+	[RSET_WDT]		= BCM_6358_WDT_BASE,
+	[RSET_UART0]		= BCM_6358_UART0_BASE,
+	[RSET_UART1]		= BCM_6358_UART1_BASE,
+	[RSET_GPIO]		= BCM_6358_GPIO_BASE,
+	[RSET_SPI]		= BCM_6358_SPI_BASE,
+	[RSET_OHCI0]		= BCM_6358_OHCI0_BASE,
+	[RSET_EHCI0]		= BCM_6358_EHCI0_BASE,
+	[RSET_OHCI_PRIV]	= BCM_6358_OHCI_PRIV_BASE,
+	[RSET_USBH_PRIV]	= BCM_6358_USBH_PRIV_BASE,
+	[RSET_MPI]		= BCM_6358_MPI_BASE,
+	[RSET_PCMCIA]		= BCM_6358_PCMCIA_BASE,
+	[RSET_SDRAM]		= BCM_6358_SDRAM_BASE,
+	[RSET_DSL]		= BCM_6358_DSL_BASE,
+	[RSET_ENET0]		= BCM_6358_ENET0_BASE,
+	[RSET_ENET1]		= BCM_6358_ENET1_BASE,
+	[RSET_ENETDMA]		= BCM_6358_ENETDMA_BASE,
+	[RSET_MEMC]		= BCM_6358_MEMC_BASE,
+	[RSET_DDR]		= BCM_6358_DDR_BASE,
 };
 
-static const int bcm6368_irqs[] = {
-	__GEN_CPU_IRQ_TABLE(6368)
-
+static const int bcm96358_irqs[] = {
+	[IRQ_TIMER]		= BCM_6358_TIMER_IRQ,
+	[IRQ_UART0]		= BCM_6358_UART0_IRQ,
+	[IRQ_UART1]		= BCM_6358_UART1_IRQ,
+	[IRQ_DSL]		= BCM_6358_DSL_IRQ,
+	[IRQ_ENET0]		= BCM_6358_ENET0_IRQ,
+	[IRQ_ENET1]		= BCM_6358_ENET1_IRQ,
+	[IRQ_ENET_PHY]		= BCM_6358_ENET_PHY_IRQ,
+	[IRQ_OHCI0]		= BCM_6358_OHCI0_IRQ,
+	[IRQ_EHCI0]		= BCM_6358_EHCI0_IRQ,
+	[IRQ_PCMCIA]		= BCM_6358_PCMCIA_IRQ,
+	[IRQ_ENET0_RXDMA]	= BCM_6358_ENET0_RXDMA_IRQ,
+	[IRQ_ENET0_TXDMA]	= BCM_6358_ENET0_TXDMA_IRQ,
+	[IRQ_ENET1_RXDMA]	= BCM_6358_ENET1_RXDMA_IRQ,
+	[IRQ_ENET1_TXDMA]	= BCM_6358_ENET1_TXDMA_IRQ,
+	[IRQ_PCI]		= BCM_6358_PCI_IRQ,
 };
 
 u16 __bcm63xx_get_cpu_id(void)
@@ -98,19 +217,20 @@ unsigned int bcm63xx_get_memory_size(void)
 
 static unsigned int detect_cpu_clock(void)
 {
-	switch (bcm63xx_get_cpu_id()) {
-	case BCM6338_CPU_ID:
-		/* BCM6338 has a fixed 240 Mhz frequency */
+	unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
+
+	/* BCM6338 has a fixed 240 Mhz frequency */
+	if (BCMCPU_IS_6338())
 		return 240000000;
 
-	case BCM6345_CPU_ID:
-		/* BCM6345 has a fixed 140Mhz frequency */
+	/* BCM6345 has a fixed 140Mhz frequency */
+	if (BCMCPU_IS_6345())
 		return 140000000;
 
-	case BCM6348_CPU_ID:
-	{
-		unsigned int tmp, n1, n2, m1;
-
+	/*
+	 * frequency depends on PLL configuration:
+	 */
+	if (BCMCPU_IS_6348()) {
 		/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 		tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 		n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
@@ -119,47 +239,17 @@ static unsigned int detect_cpu_clock(void)
 		n1 += 1;
 		n2 += 2;
 		m1 += 1;
-		return (16 * 1000000 * n1 * n2) / m1;
 	}
 
-	case BCM6358_CPU_ID:
-	{
-		unsigned int tmp, n1, n2, m1;
-
+	if (BCMCPU_IS_6358()) {
 		/* 16MHz * N1 * N2 / M1_CPU */
 		tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 		n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 		n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 		m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
-		return (16 * 1000000 * n1 * n2) / m1;
 	}
 
-	case BCM6368_CPU_ID:
-	{
-		unsigned int tmp, p1, p2, ndiv, m1;
-
-		/* (64MHz / P1) * P2 * NDIV / M1_CPU */
-		tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
-
-		p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
-			DMIPSPLLCFG_6368_P1_SHIFT;
-
-		p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
-			DMIPSPLLCFG_6368_P2_SHIFT;
-
-		ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
-			DMIPSPLLCFG_6368_NDIV_SHIFT;
-
-		tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
-		m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
-			DMIPSPLLDIV_6368_MDIV_SHIFT;
-
-		return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
-	}
-
-	default:
-		BUG();
-	}
+	return (16 * 1000000 * n1 * n2) / m1;
 }
 
 /*
@@ -170,10 +260,8 @@ static unsigned int detect_memory_size(void)
 	unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 	u32 val;
 
-	if (BCMCPU_IS_6345()) {
-		val = bcm_sdram_readl(SDRAM_MBASE_REG);
-		return (val * 8 * 1024 * 1024);
-	}
+	if (BCMCPU_IS_6345())
+		return (8 * 1024 * 1024);
 
 	if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 		val = bcm_sdram_readl(SDRAM_CFG_REG);
@@ -183,7 +271,7 @@ static unsigned int detect_memory_size(void)
 		banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 	}
 
-	if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+	if (BCMCPU_IS_6358()) {
 		val = bcm_memc_readl(MEMC_CFG_REG);
 		rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 		cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -213,33 +301,24 @@ void __init bcm63xx_cpu_init(void)
 	case CPU_BMIPS3300:
 		if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
 			expected_cpu_id = BCM6348_CPU_ID;
-			bcm63xx_regs_base = bcm6348_regs_base;
-			bcm63xx_irqs = bcm6348_irqs;
+			bcm63xx_regs_base = bcm96348_regs_base;
+			bcm63xx_irqs = bcm96348_irqs;
 		} else {
 			__cpu_name[cpu] = "Broadcom BCM6338";
 			expected_cpu_id = BCM6338_CPU_ID;
-			bcm63xx_regs_base = bcm6338_regs_base;
-			bcm63xx_irqs = bcm6338_irqs;
+			bcm63xx_regs_base = bcm96338_regs_base;
+			bcm63xx_irqs = bcm96338_irqs;
 		}
 		break;
 	case CPU_BMIPS32:
 		expected_cpu_id = BCM6345_CPU_ID;
-		bcm63xx_regs_base = bcm6345_regs_base;
-		bcm63xx_irqs = bcm6345_irqs;
+		bcm63xx_regs_base = bcm96345_regs_base;
+		bcm63xx_irqs = bcm96345_irqs;
 		break;
 	case CPU_BMIPS4350:
-		switch (read_c0_prid() & 0xf0) {
-		case 0x10:
-			expected_cpu_id = BCM6358_CPU_ID;
-			bcm63xx_regs_base = bcm6358_regs_base;
-			bcm63xx_irqs = bcm6358_irqs;
-			break;
-		case 0x30:
-			expected_cpu_id = BCM6368_CPU_ID;
-			bcm63xx_regs_base = bcm6368_regs_base;
-			bcm63xx_irqs = bcm6368_irqs;
-			break;
-		}
+		expected_cpu_id = BCM6358_CPU_ID;
+		bcm63xx_regs_base = bcm96358_regs_base;
+		bcm63xx_irqs = bcm96358_irqs;
 		break;
 	}
 
diff --git a/trunk/arch/mips/bcm63xx/dev-uart.c b/trunk/arch/mips/bcm63xx/dev-uart.c
index d6e42c608325..c2963da0253e 100644
--- a/trunk/arch/mips/bcm63xx/dev-uart.c
+++ b/trunk/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
 	if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
 		return -ENODEV;
 
-	if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
+	if (id == 1 && !BCMCPU_IS_6358())
 		return -ENODEV;
 
 	if (id == 0) {
diff --git a/trunk/arch/mips/bcm63xx/gpio.c b/trunk/arch/mips/bcm63xx/gpio.c
index a6c2135dbf38..f560fe7d38dd 100644
--- a/trunk/arch/mips/bcm63xx/gpio.c
+++ b/trunk/arch/mips/bcm63xx/gpio.c
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
- * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
  */
 
 #include <linux/kernel.h>
@@ -18,34 +18,6 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_regs.h>
 
-#ifndef BCMCPU_RUNTIME_DETECT
-#define gpio_out_low_reg	GPIO_DATA_LO_REG
-#ifdef CONFIG_BCM63XX_CPU_6345
-#ifdef gpio_out_low_reg
-#undef gpio_out_low_reg
-#define gpio_out_low_reg	GPIO_DATA_LO_REG_6345
-#endif /* gpio_out_low_reg */
-#endif /* CONFIG_BCM63XX_CPU_6345 */
-
-static inline void bcm63xx_gpio_out_low_reg_init(void)
-{
-}
-#else /* ! BCMCPU_RUNTIME_DETECT */
-static u32 gpio_out_low_reg;
-
-static void bcm63xx_gpio_out_low_reg_init(void)
-{
-	switch (bcm63xx_get_cpu_id()) {
-	case BCM6345_CPU_ID:
-		gpio_out_low_reg = GPIO_DATA_LO_REG_6345;
-		break;
-	default:
-		gpio_out_low_reg = GPIO_DATA_LO_REG;
-		break;
-	}
-}
-#endif /* ! BCMCPU_RUNTIME_DETECT */
-
 static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
 static u32 gpio_out_low, gpio_out_high;
 
@@ -61,7 +33,7 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip,
 		BUG();
 
 	if (gpio < 32) {
-		reg = gpio_out_low_reg;
+		reg = GPIO_DATA_LO_REG;
 		mask = 1 << gpio;
 		v = &gpio_out_low;
 	} else {
@@ -88,7 +60,7 @@ static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
 		BUG();
 
 	if (gpio < 32) {
-		reg = gpio_out_low_reg;
+		reg = GPIO_DATA_LO_REG;
 		mask = 1 << gpio;
 	} else {
 		reg = GPIO_DATA_HI_REG;
@@ -153,11 +125,8 @@ static struct gpio_chip bcm63xx_gpio_chip = {
 
 int __init bcm63xx_gpio_init(void)
 {
-	bcm63xx_gpio_out_low_reg_init();
-
-	gpio_out_low = bcm_gpio_readl(gpio_out_low_reg);
-	if (!BCMCPU_IS_6345())
-		gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
+	gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG);
+	gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
 	bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
 	pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
 
diff --git a/trunk/arch/mips/bcm63xx/irq.c b/trunk/arch/mips/bcm63xx/irq.c
index 9a216a451d92..162e11b4ed75 100644
--- a/trunk/arch/mips/bcm63xx/irq.c
+++ b/trunk/arch/mips/bcm63xx/irq.c
@@ -19,187 +19,19 @@
 #include <bcm63xx_io.h>
 #include <bcm63xx_irq.h>
 
-static void __dispatch_internal(void) __maybe_unused;
-static void __dispatch_internal_64(void) __maybe_unused;
-static void __internal_irq_mask_32(unsigned int irq) __maybe_unused;
-static void __internal_irq_mask_64(unsigned int irq) __maybe_unused;
-static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
-static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
-
-#ifndef BCMCPU_RUNTIME_DETECT
-#ifdef CONFIG_BCM63XX_CPU_6338
-#define irq_stat_reg		PERF_IRQSTAT_6338_REG
-#define irq_mask_reg		PERF_IRQMASK_6338_REG
-#define irq_bits		32
-#define is_ext_irq_cascaded	0
-#define ext_irq_start		0
-#define ext_irq_end		0
-#define ext_irq_count		4
-#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6338
-#define ext_irq_cfg_reg2	0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6345
-#define irq_stat_reg		PERF_IRQSTAT_6345_REG
-#define irq_mask_reg		PERF_IRQMASK_6345_REG
-#define irq_bits		32
-#define is_ext_irq_cascaded	0
-#define ext_irq_start		0
-#define ext_irq_end		0
-#define ext_irq_count		0
-#define ext_irq_cfg_reg1	0
-#define ext_irq_cfg_reg2	0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6348
-#define irq_stat_reg		PERF_IRQSTAT_6348_REG
-#define irq_mask_reg		PERF_IRQMASK_6348_REG
-#define irq_bits		32
-#define is_ext_irq_cascaded	0
-#define ext_irq_start		0
-#define ext_irq_end		0
-#define ext_irq_count		4
-#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6348
-#define ext_irq_cfg_reg2	0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6358
-#define irq_stat_reg		PERF_IRQSTAT_6358_REG
-#define irq_mask_reg		PERF_IRQMASK_6358_REG
-#define irq_bits		32
-#define is_ext_irq_cascaded	1
-#define ext_irq_start		(BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end		(BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE)
-#define ext_irq_count		4
-#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6358
-#define ext_irq_cfg_reg2	0
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6368
-#define irq_stat_reg		PERF_IRQSTAT_6368_REG
-#define irq_mask_reg		PERF_IRQMASK_6368_REG
-#define irq_bits		64
-#define is_ext_irq_cascaded	1
-#define ext_irq_start		(BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
-#define ext_irq_end		(BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
-#define ext_irq_count		6
-#define ext_irq_cfg_reg1	PERF_EXTIRQ_CFG_REG_6368
-#define ext_irq_cfg_reg2	PERF_EXTIRQ_CFG_REG2_6368
-#endif
-
-#if irq_bits == 32
-#define dispatch_internal			__dispatch_internal
-#define internal_irq_mask			__internal_irq_mask_32
-#define internal_irq_unmask			__internal_irq_unmask_32
-#else
-#define dispatch_internal			__dispatch_internal_64
-#define internal_irq_mask			__internal_irq_mask_64
-#define internal_irq_unmask			__internal_irq_unmask_64
-#endif
-
-#define irq_stat_addr	(bcm63xx_regset_address(RSET_PERF) + irq_stat_reg)
-#define irq_mask_addr	(bcm63xx_regset_address(RSET_PERF) + irq_mask_reg)
-
-static inline void bcm63xx_init_irq(void)
-{
-}
-#else /* ! BCMCPU_RUNTIME_DETECT */
-
-static u32 irq_stat_addr, irq_mask_addr;
-static void (*dispatch_internal)(void);
-static int is_ext_irq_cascaded;
-static unsigned int ext_irq_count;
-static unsigned int ext_irq_start, ext_irq_end;
-static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
-static void (*internal_irq_mask)(unsigned int irq);
-static void (*internal_irq_unmask)(unsigned int irq);
-
-static void bcm63xx_init_irq(void)
-{
-	int irq_bits;
-
-	irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
-	irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
-
-	switch (bcm63xx_get_cpu_id()) {
-	case BCM6338_CPU_ID:
-		irq_stat_addr += PERF_IRQSTAT_6338_REG;
-		irq_mask_addr += PERF_IRQMASK_6338_REG;
-		irq_bits = 32;
-		break;
-	case BCM6345_CPU_ID:
-		irq_stat_addr += PERF_IRQSTAT_6345_REG;
-		irq_mask_addr += PERF_IRQMASK_6345_REG;
-		irq_bits = 32;
-		break;
-	case BCM6348_CPU_ID:
-		irq_stat_addr += PERF_IRQSTAT_6348_REG;
-		irq_mask_addr += PERF_IRQMASK_6348_REG;
-		irq_bits = 32;
-		ext_irq_count = 4;
-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
-		break;
-	case BCM6358_CPU_ID:
-		irq_stat_addr += PERF_IRQSTAT_6358_REG;
-		irq_mask_addr += PERF_IRQMASK_6358_REG;
-		irq_bits = 32;
-		ext_irq_count = 4;
-		is_ext_irq_cascaded = 1;
-		ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
-		ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
-		break;
-	case BCM6368_CPU_ID:
-		irq_stat_addr += PERF_IRQSTAT_6368_REG;
-		irq_mask_addr += PERF_IRQMASK_6368_REG;
-		irq_bits = 64;
-		ext_irq_count = 6;
-		is_ext_irq_cascaded = 1;
-		ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
-		ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
-		ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
-		ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
-		break;
-	default:
-		BUG();
-	}
-
-	if (irq_bits == 32) {
-		dispatch_internal = __dispatch_internal;
-		internal_irq_mask = __internal_irq_mask_32;
-		internal_irq_unmask = __internal_irq_unmask_32;
-	} else {
-		dispatch_internal = __dispatch_internal_64;
-		internal_irq_mask = __internal_irq_mask_64;
-		internal_irq_unmask = __internal_irq_unmask_64;
-	}
-}
-#endif /* ! BCMCPU_RUNTIME_DETECT */
-
-static inline u32 get_ext_irq_perf_reg(int irq)
-{
-	if (irq < 4)
-		return ext_irq_cfg_reg1;
-	return ext_irq_cfg_reg2;
-}
-
-static inline void handle_internal(int intbit)
-{
-	if (is_ext_irq_cascaded &&
-	    intbit >= ext_irq_start && intbit <= ext_irq_end)
-		do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
-	else
-		do_IRQ(intbit + IRQ_INTERNAL_BASE);
-}
-
 /*
  * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
  * prioritize any interrupt relatively to another. the static counter
  * will resume the loop where it ended the last time we left this
  * function.
  */
-static void __dispatch_internal(void)
+static void bcm63xx_irq_dispatch_internal(void)
 {
 	u32 pending;
 	static int i;
 
-	pending = bcm_readl(irq_stat_addr) & bcm_readl(irq_mask_addr);
+	pending = bcm_perf_readl(PERF_IRQMASK_REG) &
+		bcm_perf_readl(PERF_IRQSTAT_REG);
 
 	if (!pending)
 		return ;
@@ -209,28 +41,7 @@ static void __dispatch_internal(void)
 
 		i = (i + 1) & 0x1f;
 		if (pending & (1 << to_call)) {
-			handle_internal(to_call);
-			break;
-		}
-	}
-}
-
-static void __dispatch_internal_64(void)
-{
-	u64 pending;
-	static int i;
-
-	pending = bcm_readq(irq_stat_addr) & bcm_readq(irq_mask_addr);
-
-	if (!pending)
-		return ;
-
-	while (1) {
-		int to_call = i;
-
-		i = (i + 1) & 0x3f;
-		if (pending & (1ull << to_call)) {
-			handle_internal(to_call);
+			do_IRQ(to_call + IRQ_INTERNAL_BASE);
 			break;
 		}
 	}
@@ -249,17 +60,15 @@ asmlinkage void plat_irq_dispatch(void)
 		if (cause & CAUSEF_IP7)
 			do_IRQ(7);
 		if (cause & CAUSEF_IP2)
-			dispatch_internal();
-		if (!is_ext_irq_cascaded) {
-			if (cause & CAUSEF_IP3)
-				do_IRQ(IRQ_EXT_0);
-			if (cause & CAUSEF_IP4)
-				do_IRQ(IRQ_EXT_1);
-			if (cause & CAUSEF_IP5)
-				do_IRQ(IRQ_EXT_2);
-			if (cause & CAUSEF_IP6)
-				do_IRQ(IRQ_EXT_3);
-		}
+			bcm63xx_irq_dispatch_internal();
+		if (cause & CAUSEF_IP3)
+			do_IRQ(IRQ_EXT_0);
+		if (cause & CAUSEF_IP4)
+			do_IRQ(IRQ_EXT_1);
+		if (cause & CAUSEF_IP5)
+			do_IRQ(IRQ_EXT_2);
+		if (cause & CAUSEF_IP6)
+			do_IRQ(IRQ_EXT_3);
 	} while (1);
 }
 
@@ -267,50 +76,24 @@ asmlinkage void plat_irq_dispatch(void)
  * internal IRQs operations: only mask/unmask on PERF irq mask
  * register.
  */
-static void __internal_irq_mask_32(unsigned int irq)
+static inline void bcm63xx_internal_irq_mask(struct irq_data *d)
 {
+	unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
 	u32 mask;
 
-	mask = bcm_readl(irq_mask_addr);
+	mask = bcm_perf_readl(PERF_IRQMASK_REG);
 	mask &= ~(1 << irq);
-	bcm_writel(mask, irq_mask_addr);
+	bcm_perf_writel(mask, PERF_IRQMASK_REG);
 }
 
-static void __internal_irq_mask_64(unsigned int irq)
-{
-	u64 mask;
-
-	mask = bcm_readq(irq_mask_addr);
-	mask &= ~(1ull << irq);
-	bcm_writeq(mask, irq_mask_addr);
-}
-
-static void __internal_irq_unmask_32(unsigned int irq)
+static void bcm63xx_internal_irq_unmask(struct irq_data *d)
 {
+	unsigned int irq = d->irq - IRQ_INTERNAL_BASE;
 	u32 mask;
 
-	mask = bcm_readl(irq_mask_addr);
+	mask = bcm_perf_readl(PERF_IRQMASK_REG);
 	mask |= (1 << irq);
-	bcm_writel(mask, irq_mask_addr);
-}
-
-static void __internal_irq_unmask_64(unsigned int irq)
-{
-	u64 mask;
-
-	mask = bcm_readq(irq_mask_addr);
-	mask |= (1ull << irq);
-	bcm_writeq(mask, irq_mask_addr);
-}
-
-static void bcm63xx_internal_irq_mask(struct irq_data *d)
-{
-	internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
-}
-
-static void bcm63xx_internal_irq_unmask(struct irq_data *d)
-{
-	internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
+	bcm_perf_writel(mask, PERF_IRQMASK_REG);
 }
 
 /*
@@ -319,131 +102,94 @@ static void bcm63xx_internal_irq_unmask(struct irq_data *d)
  */
 static void bcm63xx_external_irq_mask(struct irq_data *d)
 {
-	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
-	u32 reg, regaddr;
+	unsigned int irq = d->irq - IRQ_EXT_BASE;
+	u32 reg;
 
-	regaddr = get_ext_irq_perf_reg(irq);
-	reg = bcm_perf_readl(regaddr);
-
-	if (BCMCPU_IS_6348())
-		reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
-	else
-		reg &= ~EXTIRQ_CFG_MASK(irq % 4);
-
-	bcm_perf_writel(reg, regaddr);
-	if (is_ext_irq_cascaded)
-		internal_irq_mask(irq + ext_irq_start);
+	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+	reg &= ~EXTIRQ_CFG_MASK(irq);
+	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 }
 
 static void bcm63xx_external_irq_unmask(struct irq_data *d)
 {
-	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
-	u32 reg, regaddr;
+	unsigned int irq = d->irq - IRQ_EXT_BASE;
+	u32 reg;
 
-	regaddr = get_ext_irq_perf_reg(irq);
-	reg = bcm_perf_readl(regaddr);
-
-	if (BCMCPU_IS_6348())
-		reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
-	else
-		reg |= EXTIRQ_CFG_MASK(irq % 4);
-
-	bcm_perf_writel(reg, regaddr);
-
-	if (is_ext_irq_cascaded)
-		internal_irq_unmask(irq + ext_irq_start);
+	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+	reg |= EXTIRQ_CFG_MASK(irq);
+	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 }
 
 static void bcm63xx_external_irq_clear(struct irq_data *d)
 {
-	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
-	u32 reg, regaddr;
+	unsigned int irq = d->irq - IRQ_EXT_BASE;
+	u32 reg;
 
-	regaddr = get_ext_irq_perf_reg(irq);
-	reg = bcm_perf_readl(regaddr);
+	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+	reg |= EXTIRQ_CFG_CLEAR(irq);
+	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
+}
 
-	if (BCMCPU_IS_6348())
-		reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
-	else
-		reg |= EXTIRQ_CFG_CLEAR(irq % 4);
+static unsigned int bcm63xx_external_irq_startup(struct irq_data *d)
+{
+	set_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
+	irq_enable_hazard();
+	bcm63xx_external_irq_unmask(d);
+	return 0;
+}
 
-	bcm_perf_writel(reg, regaddr);
+static void bcm63xx_external_irq_shutdown(struct irq_data *d)
+{
+	bcm63xx_external_irq_mask(d);
+	clear_c0_status(0x100 << (d->irq - IRQ_MIPS_BASE));
+	irq_disable_hazard();
 }
 
 static int bcm63xx_external_irq_set_type(struct irq_data *d,
 					 unsigned int flow_type)
 {
-	unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
-	u32 reg, regaddr;
-	int levelsense, sense, bothedge;
+	unsigned int irq = d->irq - IRQ_EXT_BASE;
+	u32 reg;
 
 	flow_type &= IRQ_TYPE_SENSE_MASK;
 
 	if (flow_type == IRQ_TYPE_NONE)
 		flow_type = IRQ_TYPE_LEVEL_LOW;
 
-	levelsense = sense = bothedge = 0;
+	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
 	switch (flow_type) {
 	case IRQ_TYPE_EDGE_BOTH:
-		bothedge = 1;
+		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
+		reg |= EXTIRQ_CFG_BOTHEDGE(irq);
 		break;
 
 	case IRQ_TYPE_EDGE_RISING:
-		sense = 1;
+		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
+		reg |= EXTIRQ_CFG_SENSE(irq);
+		reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
 		break;
 
 	case IRQ_TYPE_EDGE_FALLING:
+		reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
+		reg &= ~EXTIRQ_CFG_SENSE(irq);
+		reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
 		break;
 
 	case IRQ_TYPE_LEVEL_HIGH:
-		levelsense = 1;
-		sense = 1;
+		reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+		reg |= EXTIRQ_CFG_SENSE(irq);
 		break;
 
 	case IRQ_TYPE_LEVEL_LOW:
-		levelsense = 1;
+		reg |= EXTIRQ_CFG_LEVELSENSE(irq);
+		reg &= ~EXTIRQ_CFG_SENSE(irq);
 		break;
 
 	default:
 		printk(KERN_ERR "bogus flow type combination given !\n");
 		return -EINVAL;
 	}
-
-	regaddr = get_ext_irq_perf_reg(irq);
-	reg = bcm_perf_readl(regaddr);
-	irq %= 4;
-
-	if (BCMCPU_IS_6348()) {
-		if (levelsense)
-			reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
-		else
-			reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
-		if (sense)
-			reg |= EXTIRQ_CFG_SENSE_6348(irq);
-		else
-			reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
-		if (bothedge)
-			reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
-		else
-			reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
-	}
-
-	if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
-		if (levelsense)
-			reg |= EXTIRQ_CFG_LEVELSENSE(irq);
-		else
-			reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
-		if (sense)
-			reg |= EXTIRQ_CFG_SENSE(irq);
-		else
-			reg &= ~EXTIRQ_CFG_SENSE(irq);
-		if (bothedge)
-			reg |= EXTIRQ_CFG_BOTHEDGE(irq);
-		else
-			reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
-	}
-
-	bcm_perf_writel(reg, regaddr);
+	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 
 	irqd_set_trigger_type(d, flow_type);
 	if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -462,6 +208,9 @@ static struct irq_chip bcm63xx_internal_irq_chip = {
 
 static struct irq_chip bcm63xx_external_irq_chip = {
 	.name		= "bcm63xx_epic",
+	.irq_startup	= bcm63xx_external_irq_startup,
+	.irq_shutdown	= bcm63xx_external_irq_shutdown,
+
 	.irq_ack	= bcm63xx_external_irq_clear,
 
 	.irq_mask	= bcm63xx_external_irq_mask,
@@ -476,30 +225,18 @@ static struct irqaction cpu_ip2_cascade_action = {
 	.flags		= IRQF_NO_THREAD,
 };
 
-static struct irqaction cpu_ext_cascade_action = {
-	.handler	= no_action,
-	.name		= "cascade_extirq",
-	.flags		= IRQF_NO_THREAD,
-};
-
 void __init arch_init_irq(void)
 {
 	int i;
 
-	bcm63xx_init_irq();
 	mips_cpu_irq_init();
 	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
 		irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
 					 handle_level_irq);
 
-	for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
+	for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
 		irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
 					 handle_edge_irq);
 
-	if (!is_ext_irq_cascaded) {
-		for (i = 3; i < 3 + ext_irq_count; ++i)
-			setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
-	}
-
-	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
+	setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
 }
diff --git a/trunk/arch/mips/bcm63xx/prom.c b/trunk/arch/mips/bcm63xx/prom.c
index 99d7f405cbeb..be252efa0757 100644
--- a/trunk/arch/mips/bcm63xx/prom.c
+++ b/trunk/arch/mips/bcm63xx/prom.c
@@ -32,12 +32,9 @@ void __init prom_init(void)
 		mask = CKCTL_6345_ALL_SAFE_EN;
 	else if (BCMCPU_IS_6348())
 		mask = CKCTL_6348_ALL_SAFE_EN;
-	else if (BCMCPU_IS_6358())
-		mask = CKCTL_6358_ALL_SAFE_EN;
-	else if (BCMCPU_IS_6368())
-		mask = CKCTL_6368_ALL_SAFE_EN;
 	else
-		mask = 0;
+		/* BCMCPU_IS_6358() */
+		mask = CKCTL_6358_ALL_SAFE_EN;
 
 	reg = bcm_perf_readl(PERF_CKCTL_REG);
 	reg &= ~mask;
diff --git a/trunk/arch/mips/bcm63xx/setup.c b/trunk/arch/mips/bcm63xx/setup.c
index d209f85d87bb..d0056598fbfc 100644
--- a/trunk/arch/mips/bcm63xx/setup.c
+++ b/trunk/arch/mips/bcm63xx/setup.c
@@ -63,33 +63,13 @@ static void bcm6348_a1_reboot(void)
 
 void bcm63xx_machine_reboot(void)
 {
-	u32 reg, perf_regs[2] = { 0, 0 };
-	unsigned int i;
+	u32 reg;
 
 	/* mask and clear all external irq */
-	switch (bcm63xx_get_cpu_id()) {
-	case BCM6338_CPU_ID:
-		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
-		break;
-	case BCM6348_CPU_ID:
-		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
-		break;
-	case BCM6358_CPU_ID:
-		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
-		break;
-	}
-
-	for (i = 0; i < 2; i++) {
-		reg = bcm_perf_readl(perf_regs[i]);
-		if (BCMCPU_IS_6348()) {
-			reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
-			reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
-		} else {
-			reg &= ~EXTIRQ_CFG_MASK_ALL;
-			reg |= EXTIRQ_CFG_CLEAR_ALL;
-		}
-		bcm_perf_writel(reg, perf_regs[i]);
-	}
+	reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG);
+	reg &= ~EXTIRQ_CFG_MASK_ALL;
+	reg |= EXTIRQ_CFG_CLEAR_ALL;
+	bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG);
 
 	if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
 		bcm6348_a1_reboot();
@@ -144,4 +124,4 @@ int __init bcm63xx_register_devices(void)
 	return board_register_devices();
 }
 
-device_initcall(bcm63xx_register_devices);
+arch_initcall(bcm63xx_register_devices);
diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 5b8d15bb5fe8..96a2391ad85b 100644
--- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,7 +13,6 @@
 #define BCM6345_CPU_ID		0x6345
 #define BCM6348_CPU_ID		0x6348
 #define BCM6358_CPU_ID		0x6358
-#define BCM6368_CPU_ID		0x6368
 
 void __init bcm63xx_cpu_init(void);
 u16 __bcm63xx_get_cpu_id(void);
@@ -72,19 +71,6 @@ unsigned int bcm63xx_get_cpu_freq(void);
 # define BCMCPU_IS_6358()	(0)
 #endif
 
-#ifdef CONFIG_BCM63XX_CPU_6368
-# ifdef bcm63xx_get_cpu_id
-#  undef bcm63xx_get_cpu_id
-#  define bcm63xx_get_cpu_id()	__bcm63xx_get_cpu_id()
-#  define BCMCPU_RUNTIME_DETECT
-# else
-#  define bcm63xx_get_cpu_id()	BCM6368_CPU_ID
-# endif
-# define BCMCPU_IS_6368()	(bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
-#else
-# define BCMCPU_IS_6368()	(0)
-#endif
-
 #ifndef bcm63xx_get_cpu_id
 #error "No CPU support configured"
 #endif
@@ -102,7 +88,6 @@ enum bcm63xx_regs_set {
 	RSET_UART1,
 	RSET_GPIO,
 	RSET_SPI,
-	RSET_SPI2,
 	RSET_UDC0,
 	RSET_OHCI0,
 	RSET_OHCI_PRIV,
@@ -113,23 +98,10 @@ enum bcm63xx_regs_set {
 	RSET_ENET0,
 	RSET_ENET1,
 	RSET_ENETDMA,
-	RSET_ENETDMAC,
-	RSET_ENETDMAS,
-	RSET_ENETSW,
 	RSET_EHCI0,
 	RSET_SDRAM,
 	RSET_MEMC,
 	RSET_DDR,
-	RSET_M2M,
-	RSET_ATM,
-	RSET_XTM,
-	RSET_XTMDMA,
-	RSET_XTMDMAC,
-	RSET_XTMDMAS,
-	RSET_PCM,
-	RSET_PCMDMA,
-	RSET_PCMDMAC,
-	RSET_PCMDMAS,
 };
 
 #define RSET_DSL_LMEM_SIZE		(64 * 1024 * 4)
@@ -137,18 +109,11 @@ enum bcm63xx_regs_set {
 #define RSET_WDT_SIZE			12
 #define RSET_ENET_SIZE			2048
 #define RSET_ENETDMA_SIZE		2048
-#define RSET_ENETSW_SIZE		65536
 #define RSET_UART_SIZE			24
 #define RSET_UDC_SIZE			256
 #define RSET_OHCI_SIZE			256
 #define RSET_EHCI_SIZE			256
 #define RSET_PCMCIA_SIZE		12
-#define RSET_M2M_SIZE			256
-#define RSET_ATM_SIZE			4096
-#define RSET_XTM_SIZE			10240
-#define RSET_XTMDMA_SIZE		256
-#define RSET_XTMDMAC_SIZE(chans)	(16 * (chans))
-#define RSET_XTMDMAS_SIZE(chans)	(16 * (chans))
 
 /*
  * 6338 register sets base address
@@ -162,7 +127,6 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UART1_BASE		(0xdeadbeef)
 #define BCM_6338_GPIO_BASE		(0xfffe0400)
 #define BCM_6338_SPI_BASE		(0xfffe0c00)
-#define BCM_6338_SPI2_BASE		(0xdeadbeef)
 #define BCM_6338_UDC0_BASE		(0xdeadbeef)
 #define BCM_6338_USBDMA_BASE		(0xfffe2400)
 #define BCM_6338_OHCI0_BASE		(0xdeadbeef)
@@ -172,27 +136,15 @@ enum bcm63xx_regs_set {
 #define BCM_6338_PCMCIA_BASE		(0xdeadbeef)
 #define BCM_6338_SDRAM_REGS_BASE	(0xfffe3100)
 #define BCM_6338_DSL_BASE		(0xfffe1000)
+#define BCM_6338_SAR_BASE		(0xfffe2000)
 #define BCM_6338_UBUS_BASE		(0xdeadbeef)
 #define BCM_6338_ENET0_BASE		(0xfffe2800)
 #define BCM_6338_ENET1_BASE		(0xdeadbeef)
 #define BCM_6338_ENETDMA_BASE		(0xfffe2400)
-#define BCM_6338_ENETDMAC_BASE		(0xfffe2500)
-#define BCM_6338_ENETDMAS_BASE		(0xfffe2600)
-#define BCM_6338_ENETSW_BASE		(0xdeadbeef)
 #define BCM_6338_EHCI0_BASE		(0xdeadbeef)
 #define BCM_6338_SDRAM_BASE		(0xfffe3100)
 #define BCM_6338_MEMC_BASE		(0xdeadbeef)
 #define BCM_6338_DDR_BASE		(0xdeadbeef)
-#define BCM_6338_M2M_BASE		(0xdeadbeef)
-#define BCM_6338_ATM_BASE		(0xfffe2000)
-#define BCM_6338_XTM_BASE		(0xdeadbeef)
-#define BCM_6338_XTMDMA_BASE		(0xdeadbeef)
-#define BCM_6338_XTMDMAC_BASE		(0xdeadbeef)
-#define BCM_6338_XTMDMAS_BASE		(0xdeadbeef)
-#define BCM_6338_PCM_BASE		(0xdeadbeef)
-#define BCM_6338_PCMDMA_BASE		(0xdeadbeef)
-#define BCM_6338_PCMDMAC_BASE		(0xdeadbeef)
-#define BCM_6338_PCMDMAS_BASE		(0xdeadbeef)
 
 /*
  * 6345 register sets base address
@@ -206,37 +158,24 @@ enum bcm63xx_regs_set {
 #define BCM_6345_UART1_BASE		(0xdeadbeef)
 #define BCM_6345_GPIO_BASE		(0xfffe0400)
 #define BCM_6345_SPI_BASE		(0xdeadbeef)
-#define BCM_6345_SPI2_BASE		(0xdeadbeef)
 #define BCM_6345_UDC0_BASE		(0xdeadbeef)
 #define BCM_6345_USBDMA_BASE		(0xfffe2800)
 #define BCM_6345_ENET0_BASE		(0xfffe1800)
 #define BCM_6345_ENETDMA_BASE		(0xfffe2800)
-#define BCM_6345_ENETDMAC_BASE		(0xfffe2900)
-#define BCM_6345_ENETDMAS_BASE		(0xfffe2a00)
-#define BCM_6345_ENETSW_BASE		(0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE		(0xfffe2028)
-#define BCM_6345_MPI_BASE		(0xfffe2000)
+#define BCM_6345_MPI_BASE		(0xdeadbeef)
 #define BCM_6345_OHCI0_BASE		(0xfffe2100)
 #define BCM_6345_OHCI_PRIV_BASE		(0xfffe2200)
 #define BCM_6345_USBH_PRIV_BASE		(0xdeadbeef)
 #define BCM_6345_SDRAM_REGS_BASE	(0xfffe2300)
 #define BCM_6345_DSL_BASE		(0xdeadbeef)
+#define BCM_6345_SAR_BASE		(0xdeadbeef)
 #define BCM_6345_UBUS_BASE		(0xdeadbeef)
 #define BCM_6345_ENET1_BASE		(0xdeadbeef)
 #define BCM_6345_EHCI0_BASE		(0xdeadbeef)
 #define BCM_6345_SDRAM_BASE		(0xfffe2300)
 #define BCM_6345_MEMC_BASE		(0xdeadbeef)
 #define BCM_6345_DDR_BASE		(0xdeadbeef)
-#define BCM_6345_M2M_BASE		(0xdeadbeef)
-#define BCM_6345_ATM_BASE		(0xfffe4000)
-#define BCM_6345_XTM_BASE		(0xdeadbeef)
-#define BCM_6345_XTMDMA_BASE		(0xdeadbeef)
-#define BCM_6345_XTMDMAC_BASE		(0xdeadbeef)
-#define BCM_6345_XTMDMAS_BASE		(0xdeadbeef)
-#define BCM_6345_PCM_BASE		(0xdeadbeef)
-#define BCM_6345_PCMDMA_BASE		(0xdeadbeef)
-#define BCM_6345_PCMDMAC_BASE		(0xdeadbeef)
-#define BCM_6345_PCMDMAS_BASE		(0xdeadbeef)
 
 /*
  * 6348 register sets base address
@@ -249,7 +188,6 @@ enum bcm63xx_regs_set {
 #define BCM_6348_UART1_BASE		(0xdeadbeef)
 #define BCM_6348_GPIO_BASE		(0xfffe0400)
 #define BCM_6348_SPI_BASE		(0xfffe0c00)
-#define BCM_6348_SPI2_BASE		(0xdeadbeef)
 #define BCM_6348_UDC0_BASE		(0xfffe1000)
 #define BCM_6348_OHCI0_BASE		(0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE		(0xfffe1c00)
@@ -257,27 +195,14 @@ enum bcm63xx_regs_set {
 #define BCM_6348_MPI_BASE		(0xfffe2000)
 #define BCM_6348_PCMCIA_BASE		(0xfffe2054)
 #define BCM_6348_SDRAM_REGS_BASE	(0xfffe2300)
-#define BCM_6348_M2M_BASE		(0xfffe2800)
 #define BCM_6348_DSL_BASE		(0xfffe3000)
 #define BCM_6348_ENET0_BASE		(0xfffe6000)
 #define BCM_6348_ENET1_BASE		(0xfffe6800)
 #define BCM_6348_ENETDMA_BASE		(0xfffe7000)
-#define BCM_6348_ENETDMAC_BASE		(0xfffe7100)
-#define BCM_6348_ENETDMAS_BASE		(0xfffe7200)
-#define BCM_6348_ENETSW_BASE		(0xdeadbeef)
 #define BCM_6348_EHCI0_BASE		(0xdeadbeef)
 #define BCM_6348_SDRAM_BASE		(0xfffe2300)
 #define BCM_6348_MEMC_BASE		(0xdeadbeef)
 #define BCM_6348_DDR_BASE		(0xdeadbeef)
-#define BCM_6348_ATM_BASE		(0xfffe4000)
-#define BCM_6348_XTM_BASE		(0xdeadbeef)
-#define BCM_6348_XTMDMA_BASE		(0xdeadbeef)
-#define BCM_6348_XTMDMAC_BASE		(0xdeadbeef)
-#define BCM_6348_XTMDMAS_BASE		(0xdeadbeef)
-#define BCM_6348_PCM_BASE		(0xdeadbeef)
-#define BCM_6348_PCMDMA_BASE		(0xdeadbeef)
-#define BCM_6348_PCMDMAC_BASE		(0xdeadbeef)
-#define BCM_6348_PCMDMAS_BASE		(0xdeadbeef)
 
 /*
  * 6358 register sets base address
@@ -290,7 +215,6 @@ enum bcm63xx_regs_set {
 #define BCM_6358_UART1_BASE		(0xfffe0120)
 #define BCM_6358_GPIO_BASE		(0xfffe0080)
 #define BCM_6358_SPI_BASE		(0xdeadbeef)
-#define BCM_6358_SPI2_BASE		(0xfffe0800)
 #define BCM_6358_UDC0_BASE		(0xfffe0800)
 #define BCM_6358_OHCI0_BASE		(0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE		(0xdeadbeef)
@@ -298,175 +222,214 @@ enum bcm63xx_regs_set {
 #define BCM_6358_MPI_BASE		(0xfffe1000)
 #define BCM_6358_PCMCIA_BASE		(0xfffe1054)
 #define BCM_6358_SDRAM_REGS_BASE	(0xfffe2300)
-#define BCM_6358_M2M_BASE		(0xdeadbeef)
 #define BCM_6358_DSL_BASE		(0xfffe3000)
 #define BCM_6358_ENET0_BASE		(0xfffe4000)
 #define BCM_6358_ENET1_BASE		(0xfffe4800)
 #define BCM_6358_ENETDMA_BASE		(0xfffe5000)
-#define BCM_6358_ENETDMAC_BASE		(0xfffe5100)
-#define BCM_6358_ENETDMAS_BASE		(0xfffe5200)
-#define BCM_6358_ENETSW_BASE		(0xdeadbeef)
 #define BCM_6358_EHCI0_BASE		(0xfffe1300)
 #define BCM_6358_SDRAM_BASE		(0xdeadbeef)
 #define BCM_6358_MEMC_BASE		(0xfffe1200)
 #define BCM_6358_DDR_BASE		(0xfffe12a0)
-#define BCM_6358_ATM_BASE		(0xfffe2000)
-#define BCM_6358_XTM_BASE		(0xdeadbeef)
-#define BCM_6358_XTMDMA_BASE		(0xdeadbeef)
-#define BCM_6358_XTMDMAC_BASE		(0xdeadbeef)
-#define BCM_6358_XTMDMAS_BASE		(0xdeadbeef)
-#define BCM_6358_PCM_BASE		(0xfffe1600)
-#define BCM_6358_PCMDMA_BASE		(0xfffe1800)
-#define BCM_6358_PCMDMAC_BASE		(0xfffe1900)
-#define BCM_6358_PCMDMAS_BASE		(0xfffe1a00)
-
-
-/*
- * 6368 register sets base address
- */
-#define BCM_6368_DSL_LMEM_BASE		(0xdeadbeef)
-#define BCM_6368_PERF_BASE		(0xb0000000)
-#define BCM_6368_TIMER_BASE		(0xb0000040)
-#define BCM_6368_WDT_BASE		(0xb000005c)
-#define BCM_6368_UART0_BASE		(0xb0000100)
-#define BCM_6368_UART1_BASE		(0xb0000120)
-#define BCM_6368_GPIO_BASE		(0xb0000080)
-#define BCM_6368_SPI_BASE		(0xdeadbeef)
-#define BCM_6368_SPI2_BASE		(0xb0000800)
-#define BCM_6368_UDC0_BASE		(0xdeadbeef)
-#define BCM_6368_OHCI0_BASE		(0xb0001600)
-#define BCM_6368_OHCI_PRIV_BASE		(0xdeadbeef)
-#define BCM_6368_USBH_PRIV_BASE		(0xb0001700)
-#define BCM_6368_MPI_BASE		(0xb0001000)
-#define BCM_6368_PCMCIA_BASE		(0xb0001054)
-#define BCM_6368_SDRAM_REGS_BASE	(0xdeadbeef)
-#define BCM_6368_M2M_BASE		(0xdeadbeef)
-#define BCM_6368_DSL_BASE		(0xdeadbeef)
-#define BCM_6368_ENET0_BASE		(0xdeadbeef)
-#define BCM_6368_ENET1_BASE		(0xdeadbeef)
-#define BCM_6368_ENETDMA_BASE		(0xb0006800)
-#define BCM_6368_ENETDMAC_BASE		(0xb0006a00)
-#define BCM_6368_ENETDMAS_BASE		(0xb0006c00)
-#define BCM_6368_ENETSW_BASE		(0xb0f00000)
-#define BCM_6368_EHCI0_BASE		(0xb0001500)
-#define BCM_6368_SDRAM_BASE		(0xdeadbeef)
-#define BCM_6368_MEMC_BASE		(0xb0001200)
-#define BCM_6368_DDR_BASE		(0xb0001280)
-#define BCM_6368_ATM_BASE		(0xdeadbeef)
-#define BCM_6368_XTM_BASE		(0xb0001800)
-#define BCM_6368_XTMDMA_BASE		(0xb0005000)
-#define BCM_6368_XTMDMAC_BASE		(0xb0005200)
-#define BCM_6368_XTMDMAS_BASE		(0xb0005400)
-#define BCM_6368_PCM_BASE		(0xb0004000)
-#define BCM_6368_PCMDMA_BASE		(0xb0005800)
-#define BCM_6368_PCMDMAC_BASE		(0xb0005a00)
-#define BCM_6368_PCMDMAS_BASE		(0xb0005c00)
 
 
 extern const unsigned long *bcm63xx_regs_base;
 
-#define __GEN_RSET_BASE(__cpu, __rset)					\
-	case RSET_## __rset :						\
-		return BCM_## __cpu ##_## __rset ##_BASE;
-
-#define __GEN_RSET(__cpu)						\
-	switch (set) {							\
-	__GEN_RSET_BASE(__cpu, DSL_LMEM)				\
-	__GEN_RSET_BASE(__cpu, PERF)					\
-	__GEN_RSET_BASE(__cpu, TIMER)					\
-	__GEN_RSET_BASE(__cpu, WDT)					\
-	__GEN_RSET_BASE(__cpu, UART0)					\
-	__GEN_RSET_BASE(__cpu, UART1)					\
-	__GEN_RSET_BASE(__cpu, GPIO)					\
-	__GEN_RSET_BASE(__cpu, SPI)					\
-	__GEN_RSET_BASE(__cpu, SPI2)					\
-	__GEN_RSET_BASE(__cpu, UDC0)					\
-	__GEN_RSET_BASE(__cpu, OHCI0)					\
-	__GEN_RSET_BASE(__cpu, OHCI_PRIV)				\
-	__GEN_RSET_BASE(__cpu, USBH_PRIV)				\
-	__GEN_RSET_BASE(__cpu, MPI)					\
-	__GEN_RSET_BASE(__cpu, PCMCIA)					\
-	__GEN_RSET_BASE(__cpu, DSL)					\
-	__GEN_RSET_BASE(__cpu, ENET0)					\
-	__GEN_RSET_BASE(__cpu, ENET1)					\
-	__GEN_RSET_BASE(__cpu, ENETDMA)					\
-	__GEN_RSET_BASE(__cpu, ENETDMAC)				\
-	__GEN_RSET_BASE(__cpu, ENETDMAS)				\
-	__GEN_RSET_BASE(__cpu, ENETSW)					\
-	__GEN_RSET_BASE(__cpu, EHCI0)					\
-	__GEN_RSET_BASE(__cpu, SDRAM)					\
-	__GEN_RSET_BASE(__cpu, MEMC)					\
-	__GEN_RSET_BASE(__cpu, DDR)					\
-	__GEN_RSET_BASE(__cpu, M2M)					\
-	__GEN_RSET_BASE(__cpu, ATM)					\
-	__GEN_RSET_BASE(__cpu, XTM)					\
-	__GEN_RSET_BASE(__cpu, XTMDMA)					\
-	__GEN_RSET_BASE(__cpu, XTMDMAC)					\
-	__GEN_RSET_BASE(__cpu, XTMDMAS)					\
-	__GEN_RSET_BASE(__cpu, PCM)					\
-	__GEN_RSET_BASE(__cpu, PCMDMA)					\
-	__GEN_RSET_BASE(__cpu, PCMDMAC)					\
-	__GEN_RSET_BASE(__cpu, PCMDMAS)					\
-	}
-
-#define __GEN_CPU_REGS_TABLE(__cpu)					\
-	[RSET_DSL_LMEM]		= BCM_## __cpu ##_DSL_LMEM_BASE,	\
-	[RSET_PERF]		= BCM_## __cpu ##_PERF_BASE,		\
-	[RSET_TIMER]		= BCM_## __cpu ##_TIMER_BASE,		\
-	[RSET_WDT]		= BCM_## __cpu ##_WDT_BASE,		\
-	[RSET_UART0]		= BCM_## __cpu ##_UART0_BASE,		\
-	[RSET_UART1]		= BCM_## __cpu ##_UART1_BASE,		\
-	[RSET_GPIO]		= BCM_## __cpu ##_GPIO_BASE,		\
-	[RSET_SPI]		= BCM_## __cpu ##_SPI_BASE,		\
-	[RSET_SPI2]		= BCM_## __cpu ##_SPI2_BASE,		\
-	[RSET_UDC0]		= BCM_## __cpu ##_UDC0_BASE,		\
-	[RSET_OHCI0]		= BCM_## __cpu ##_OHCI0_BASE,		\
-	[RSET_OHCI_PRIV]	= BCM_## __cpu ##_OHCI_PRIV_BASE,	\
-	[RSET_USBH_PRIV]	= BCM_## __cpu ##_USBH_PRIV_BASE,	\
-	[RSET_MPI]		= BCM_## __cpu ##_MPI_BASE,		\
-	[RSET_PCMCIA]		= BCM_## __cpu ##_PCMCIA_BASE,		\
-	[RSET_DSL]		= BCM_## __cpu ##_DSL_BASE,		\
-	[RSET_ENET0]		= BCM_## __cpu ##_ENET0_BASE,		\
-	[RSET_ENET1]		= BCM_## __cpu ##_ENET1_BASE,		\
-	[RSET_ENETDMA]		= BCM_## __cpu ##_ENETDMA_BASE,		\
-	[RSET_ENETDMAC]		= BCM_## __cpu ##_ENETDMAC_BASE,	\
-	[RSET_ENETDMAS]		= BCM_## __cpu ##_ENETDMAS_BASE,	\
-	[RSET_ENETSW]		= BCM_## __cpu ##_ENETSW_BASE,		\
-	[RSET_EHCI0]		= BCM_## __cpu ##_EHCI0_BASE,		\
-	[RSET_SDRAM]		= BCM_## __cpu ##_SDRAM_BASE,		\
-	[RSET_MEMC]		= BCM_## __cpu ##_MEMC_BASE,		\
-	[RSET_DDR]		= BCM_## __cpu ##_DDR_BASE,		\
-	[RSET_M2M]		= BCM_## __cpu ##_M2M_BASE,		\
-	[RSET_ATM]		= BCM_## __cpu ##_ATM_BASE,		\
-	[RSET_XTM]		= BCM_## __cpu ##_XTM_BASE,		\
-	[RSET_XTMDMA]		= BCM_## __cpu ##_XTMDMA_BASE,		\
-	[RSET_XTMDMAC]		= BCM_## __cpu ##_XTMDMAC_BASE,		\
-	[RSET_XTMDMAS]		= BCM_## __cpu ##_XTMDMAS_BASE,		\
-	[RSET_PCM]		= BCM_## __cpu ##_PCM_BASE,		\
-	[RSET_PCMDMA]		= BCM_## __cpu ##_PCMDMA_BASE,		\
-	[RSET_PCMDMAC]		= BCM_## __cpu ##_PCMDMAC_BASE,		\
-	[RSET_PCMDMAS]		= BCM_## __cpu ##_PCMDMAS_BASE,		\
-
-
 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 {
 #ifdef BCMCPU_RUNTIME_DETECT
 	return bcm63xx_regs_base[set];
 #else
 #ifdef CONFIG_BCM63XX_CPU_6338
-	__GEN_RSET(6338)
+	switch (set) {
+	case RSET_DSL_LMEM:
+		return BCM_6338_DSL_LMEM_BASE;
+	case RSET_PERF:
+		return BCM_6338_PERF_BASE;
+	case RSET_TIMER:
+		return BCM_6338_TIMER_BASE;
+	case RSET_WDT:
+		return BCM_6338_WDT_BASE;
+	case RSET_UART0:
+		return BCM_6338_UART0_BASE;
+	case RSET_UART1:
+		return BCM_6338_UART1_BASE;
+	case RSET_GPIO:
+		return BCM_6338_GPIO_BASE;
+	case RSET_SPI:
+		return BCM_6338_SPI_BASE;
+	case RSET_UDC0:
+		return BCM_6338_UDC0_BASE;
+	case RSET_OHCI0:
+		return BCM_6338_OHCI0_BASE;
+	case RSET_OHCI_PRIV:
+		return BCM_6338_OHCI_PRIV_BASE;
+	case RSET_USBH_PRIV:
+		return BCM_6338_USBH_PRIV_BASE;
+	case RSET_MPI:
+		return BCM_6338_MPI_BASE;
+	case RSET_PCMCIA:
+		return BCM_6338_PCMCIA_BASE;
+	case RSET_DSL:
+		return BCM_6338_DSL_BASE;
+	case RSET_ENET0:
+		return BCM_6338_ENET0_BASE;
+	case RSET_ENET1:
+		return BCM_6338_ENET1_BASE;
+	case RSET_ENETDMA:
+		return BCM_6338_ENETDMA_BASE;
+	case RSET_EHCI0:
+		return BCM_6338_EHCI0_BASE;
+	case RSET_SDRAM:
+		return BCM_6338_SDRAM_BASE;
+	case RSET_MEMC:
+		return BCM_6338_MEMC_BASE;
+	case RSET_DDR:
+		return BCM_6338_DDR_BASE;
+	}
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6345
-	__GEN_RSET(6345)
+	switch (set) {
+	case RSET_DSL_LMEM:
+		return BCM_6345_DSL_LMEM_BASE;
+	case RSET_PERF:
+		return BCM_6345_PERF_BASE;
+	case RSET_TIMER:
+		return BCM_6345_TIMER_BASE;
+	case RSET_WDT:
+		return BCM_6345_WDT_BASE;
+	case RSET_UART0:
+		return BCM_6345_UART0_BASE;
+	case RSET_UART1:
+		return BCM_6345_UART1_BASE;
+	case RSET_GPIO:
+		return BCM_6345_GPIO_BASE;
+	case RSET_SPI:
+		return BCM_6345_SPI_BASE;
+	case RSET_UDC0:
+		return BCM_6345_UDC0_BASE;
+	case RSET_OHCI0:
+		return BCM_6345_OHCI0_BASE;
+	case RSET_OHCI_PRIV:
+		return BCM_6345_OHCI_PRIV_BASE;
+	case RSET_USBH_PRIV:
+		return BCM_6345_USBH_PRIV_BASE;
+	case RSET_MPI:
+		return BCM_6345_MPI_BASE;
+	case RSET_PCMCIA:
+		return BCM_6345_PCMCIA_BASE;
+	case RSET_DSL:
+		return BCM_6345_DSL_BASE;
+	case RSET_ENET0:
+		return BCM_6345_ENET0_BASE;
+	case RSET_ENET1:
+		return BCM_6345_ENET1_BASE;
+	case RSET_ENETDMA:
+		return BCM_6345_ENETDMA_BASE;
+	case RSET_EHCI0:
+		return BCM_6345_EHCI0_BASE;
+	case RSET_SDRAM:
+		return BCM_6345_SDRAM_BASE;
+	case RSET_MEMC:
+		return BCM_6345_MEMC_BASE;
+	case RSET_DDR:
+		return BCM_6345_DDR_BASE;
+	}
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6348
-	__GEN_RSET(6348)
+	switch (set) {
+	case RSET_DSL_LMEM:
+		return BCM_6348_DSL_LMEM_BASE;
+	case RSET_PERF:
+		return BCM_6348_PERF_BASE;
+	case RSET_TIMER:
+		return BCM_6348_TIMER_BASE;
+	case RSET_WDT:
+		return BCM_6348_WDT_BASE;
+	case RSET_UART0:
+		return BCM_6348_UART0_BASE;
+	case RSET_UART1:
+		return BCM_6348_UART1_BASE;
+	case RSET_GPIO:
+		return BCM_6348_GPIO_BASE;
+	case RSET_SPI:
+		return BCM_6348_SPI_BASE;
+	case RSET_UDC0:
+		return BCM_6348_UDC0_BASE;
+	case RSET_OHCI0:
+		return BCM_6348_OHCI0_BASE;
+	case RSET_OHCI_PRIV:
+		return BCM_6348_OHCI_PRIV_BASE;
+	case RSET_USBH_PRIV:
+		return BCM_6348_USBH_PRIV_BASE;
+	case RSET_MPI:
+		return BCM_6348_MPI_BASE;
+	case RSET_PCMCIA:
+		return BCM_6348_PCMCIA_BASE;
+	case RSET_DSL:
+		return BCM_6348_DSL_BASE;
+	case RSET_ENET0:
+		return BCM_6348_ENET0_BASE;
+	case RSET_ENET1:
+		return BCM_6348_ENET1_BASE;
+	case RSET_ENETDMA:
+		return BCM_6348_ENETDMA_BASE;
+	case RSET_EHCI0:
+		return BCM_6348_EHCI0_BASE;
+	case RSET_SDRAM:
+		return BCM_6348_SDRAM_BASE;
+	case RSET_MEMC:
+		return BCM_6348_MEMC_BASE;
+	case RSET_DDR:
+		return BCM_6348_DDR_BASE;
+	}
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6358
-	__GEN_RSET(6358)
-#endif
-#ifdef CONFIG_BCM63XX_CPU_6368
-	__GEN_RSET(6368)
+	switch (set) {
+	case RSET_DSL_LMEM:
+		return BCM_6358_DSL_LMEM_BASE;
+	case RSET_PERF:
+		return BCM_6358_PERF_BASE;
+	case RSET_TIMER:
+		return BCM_6358_TIMER_BASE;
+	case RSET_WDT:
+		return BCM_6358_WDT_BASE;
+	case RSET_UART0:
+		return BCM_6358_UART0_BASE;
+	case RSET_UART1:
+		return BCM_6358_UART1_BASE;
+	case RSET_GPIO:
+		return BCM_6358_GPIO_BASE;
+	case RSET_SPI:
+		return BCM_6358_SPI_BASE;
+	case RSET_UDC0:
+		return BCM_6358_UDC0_BASE;
+	case RSET_OHCI0:
+		return BCM_6358_OHCI0_BASE;
+	case RSET_OHCI_PRIV:
+		return BCM_6358_OHCI_PRIV_BASE;
+	case RSET_USBH_PRIV:
+		return BCM_6358_USBH_PRIV_BASE;
+	case RSET_MPI:
+		return BCM_6358_MPI_BASE;
+	case RSET_PCMCIA:
+		return BCM_6358_PCMCIA_BASE;
+	case RSET_ENET0:
+		return BCM_6358_ENET0_BASE;
+	case RSET_ENET1:
+		return BCM_6358_ENET1_BASE;
+	case RSET_ENETDMA:
+		return BCM_6358_ENETDMA_BASE;
+	case RSET_DSL:
+		return BCM_6358_DSL_BASE;
+	case RSET_EHCI0:
+		return BCM_6358_EHCI0_BASE;
+	case RSET_SDRAM:
+		return BCM_6358_SDRAM_BASE;
+	case RSET_MEMC:
+		return BCM_6358_MEMC_BASE;
+	case RSET_DDR:
+		return BCM_6358_DDR_BASE;
+	}
 #endif
 #endif
 	/* unreached */
@@ -486,114 +449,75 @@ enum bcm63xx_irq {
 	IRQ_ENET_PHY,
 	IRQ_OHCI0,
 	IRQ_EHCI0,
+	IRQ_PCMCIA0,
 	IRQ_ENET0_RXDMA,
 	IRQ_ENET0_TXDMA,
 	IRQ_ENET1_RXDMA,
 	IRQ_ENET1_TXDMA,
 	IRQ_PCI,
 	IRQ_PCMCIA,
-	IRQ_ATM,
-	IRQ_ENETSW_RXDMA0,
-	IRQ_ENETSW_RXDMA1,
-	IRQ_ENETSW_RXDMA2,
-	IRQ_ENETSW_RXDMA3,
-	IRQ_ENETSW_TXDMA0,
-	IRQ_ENETSW_TXDMA1,
-	IRQ_ENETSW_TXDMA2,
-	IRQ_ENETSW_TXDMA3,
-	IRQ_XTM,
-	IRQ_XTM_DMA0,
 };
 
 /*
  * 6338 irqs
  */
 #define BCM_6338_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
+#define BCM_6338_SPI_IRQ		(IRQ_INTERNAL_BASE + 1)
 #define BCM_6338_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
-#define BCM_6338_UART1_IRQ		0
+#define BCM_6338_DG_IRQ			(IRQ_INTERNAL_BASE + 4)
 #define BCM_6338_DSL_IRQ		(IRQ_INTERNAL_BASE + 5)
+#define BCM_6338_ATM_IRQ		(IRQ_INTERNAL_BASE + 6)
+#define BCM_6338_UDC0_IRQ		(IRQ_INTERNAL_BASE + 7)
 #define BCM_6338_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
-#define BCM_6338_ENET1_IRQ		0
 #define BCM_6338_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-#define BCM_6338_OHCI0_IRQ		0
-#define BCM_6338_EHCI0_IRQ		0
+#define BCM_6338_SDRAM_IRQ		(IRQ_INTERNAL_BASE + 10)
+#define BCM_6338_USB_CNTL_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 11)
+#define BCM_6338_USB_CNTL_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 12)
+#define BCM_6338_USB_BULK_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13)
+#define BCM_6338_USB_BULK_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 14)
 #define BCM_6338_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
 #define BCM_6338_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
-#define BCM_6338_ENET1_RXDMA_IRQ	0
-#define BCM_6338_ENET1_TXDMA_IRQ	0
-#define BCM_6338_PCI_IRQ		0
-#define BCM_6338_PCMCIA_IRQ		0
-#define BCM_6338_ATM_IRQ		0
-#define BCM_6338_ENETSW_RXDMA0_IRQ	0
-#define BCM_6338_ENETSW_RXDMA1_IRQ	0
-#define BCM_6338_ENETSW_RXDMA2_IRQ	0
-#define BCM_6338_ENETSW_RXDMA3_IRQ	0
-#define BCM_6338_ENETSW_TXDMA0_IRQ	0
-#define BCM_6338_ENETSW_TXDMA1_IRQ	0
-#define BCM_6338_ENETSW_TXDMA2_IRQ	0
-#define BCM_6338_ENETSW_TXDMA3_IRQ	0
-#define BCM_6338_XTM_IRQ		0
-#define BCM_6338_XTM_DMA0_IRQ		0
+#define BCM_6338_SDIO_IRQ		(IRQ_INTERNAL_BASE + 17)
 
 /*
  * 6345 irqs
  */
 #define BCM_6345_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
 #define BCM_6345_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
-#define BCM_6345_UART1_IRQ		0
 #define BCM_6345_DSL_IRQ		(IRQ_INTERNAL_BASE + 3)
+#define BCM_6345_ATM_IRQ		(IRQ_INTERNAL_BASE + 4)
+#define BCM_6345_USB_IRQ		(IRQ_INTERNAL_BASE + 5)
 #define BCM_6345_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
-#define BCM_6345_ENET1_IRQ		0
 #define BCM_6345_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 12)
-#define BCM_6345_OHCI0_IRQ		0
-#define BCM_6345_EHCI0_IRQ		0
 #define BCM_6345_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 1)
 #define BCM_6345_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 2)
-#define BCM_6345_ENET1_RXDMA_IRQ	0
-#define BCM_6345_ENET1_TXDMA_IRQ	0
-#define BCM_6345_PCI_IRQ		0
-#define BCM_6345_PCMCIA_IRQ		0
-#define BCM_6345_ATM_IRQ		0
-#define BCM_6345_ENETSW_RXDMA0_IRQ	0
-#define BCM_6345_ENETSW_RXDMA1_IRQ	0
-#define BCM_6345_ENETSW_RXDMA2_IRQ	0
-#define BCM_6345_ENETSW_RXDMA3_IRQ	0
-#define BCM_6345_ENETSW_TXDMA0_IRQ	0
-#define BCM_6345_ENETSW_TXDMA1_IRQ	0
-#define BCM_6345_ENETSW_TXDMA2_IRQ	0
-#define BCM_6345_ENETSW_TXDMA3_IRQ	0
-#define BCM_6345_XTM_IRQ		0
-#define BCM_6345_XTM_DMA0_IRQ		0
+#define BCM_6345_EBI_RX_IRQ		(IRQ_INTERNAL_BASE + 13 + 5)
+#define BCM_6345_EBI_TX_IRQ		(IRQ_INTERNAL_BASE + 13 + 6)
+#define BCM_6345_RESERVED_RX_IRQ	(IRQ_INTERNAL_BASE + 13 + 9)
+#define BCM_6345_RESERVED_TX_IRQ	(IRQ_INTERNAL_BASE + 13 + 10)
+#define BCM_6345_USB_BULK_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 13)
+#define BCM_6345_USB_BULK_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 14)
+#define BCM_6345_USB_CNTL_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 15)
+#define BCM_6345_USB_CNTL_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 16)
+#define BCM_6345_USB_ISO_RX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 17)
+#define BCM_6345_USB_ISO_TX_DMA_IRQ	(IRQ_INTERNAL_BASE + 13 + 18)
 
 /*
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
 #define BCM_6348_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
-#define BCM_6348_UART1_IRQ		0
 #define BCM_6348_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
-#define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
 #define BCM_6348_ENET1_IRQ		(IRQ_INTERNAL_BASE + 7)
+#define BCM_6348_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
 #define BCM_6348_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
 #define BCM_6348_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 12)
-#define BCM_6348_EHCI0_IRQ		0
 #define BCM_6348_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 20)
 #define BCM_6348_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 21)
 #define BCM_6348_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 22)
 #define BCM_6348_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 23)
-#define BCM_6348_PCI_IRQ		(IRQ_INTERNAL_BASE + 24)
 #define BCM_6348_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
-#define BCM_6348_ATM_IRQ		(IRQ_INTERNAL_BASE + 5)
-#define BCM_6348_ENETSW_RXDMA0_IRQ	0
-#define BCM_6348_ENETSW_RXDMA1_IRQ	0
-#define BCM_6348_ENETSW_RXDMA2_IRQ	0
-#define BCM_6348_ENETSW_RXDMA3_IRQ	0
-#define BCM_6348_ENETSW_TXDMA0_IRQ	0
-#define BCM_6348_ENETSW_TXDMA1_IRQ	0
-#define BCM_6348_ENETSW_TXDMA2_IRQ	0
-#define BCM_6348_ENETSW_TXDMA3_IRQ	0
-#define BCM_6348_XTM_IRQ		0
-#define BCM_6348_XTM_DMA0_IRQ		0
+#define BCM_6348_PCI_IRQ		(IRQ_INTERNAL_BASE + 24)
 
 /*
  * 6358 irqs
@@ -601,108 +525,21 @@ enum bcm63xx_irq {
 #define BCM_6358_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
 #define BCM_6358_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
-#define BCM_6358_DSL_IRQ		(IRQ_INTERNAL_BASE + 29)
-#define BCM_6358_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
+#define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_ENET1_IRQ		(IRQ_INTERNAL_BASE + 6)
+#define BCM_6358_ENET0_IRQ		(IRQ_INTERNAL_BASE + 8)
 #define BCM_6358_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 9)
-#define BCM_6358_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 10)
 #define BCM_6358_ENET0_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 15)
 #define BCM_6358_ENET0_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 16)
 #define BCM_6358_ENET1_RXDMA_IRQ	(IRQ_INTERNAL_BASE + 17)
 #define BCM_6358_ENET1_TXDMA_IRQ	(IRQ_INTERNAL_BASE + 18)
+#define BCM_6358_DSL_IRQ		(IRQ_INTERNAL_BASE + 29)
 #define BCM_6358_PCI_IRQ		(IRQ_INTERNAL_BASE + 31)
 #define BCM_6358_PCMCIA_IRQ		(IRQ_INTERNAL_BASE + 24)
-#define BCM_6358_ATM_IRQ		(IRQ_INTERNAL_BASE + 19)
-#define BCM_6358_ENETSW_RXDMA0_IRQ	0
-#define BCM_6358_ENETSW_RXDMA1_IRQ	0
-#define BCM_6358_ENETSW_RXDMA2_IRQ	0
-#define BCM_6358_ENETSW_RXDMA3_IRQ	0
-#define BCM_6358_ENETSW_TXDMA0_IRQ	0
-#define BCM_6358_ENETSW_TXDMA1_IRQ	0
-#define BCM_6358_ENETSW_TXDMA2_IRQ	0
-#define BCM_6358_ENETSW_TXDMA3_IRQ	0
-#define BCM_6358_XTM_IRQ		0
-#define BCM_6358_XTM_DMA0_IRQ		0
-
-#define BCM_6358_PCM_DMA0_IRQ		(IRQ_INTERNAL_BASE + 23)
-#define BCM_6358_PCM_DMA1_IRQ		(IRQ_INTERNAL_BASE + 24)
-#define BCM_6358_EXT_IRQ0		(IRQ_INTERNAL_BASE + 25)
-#define BCM_6358_EXT_IRQ1		(IRQ_INTERNAL_BASE + 26)
-#define BCM_6358_EXT_IRQ2		(IRQ_INTERNAL_BASE + 27)
-#define BCM_6358_EXT_IRQ3		(IRQ_INTERNAL_BASE + 28)
-
-/*
- * 6368 irqs
- */
-#define BCM_6368_HIGH_IRQ_BASE		(IRQ_INTERNAL_BASE + 32)
-
-#define BCM_6368_TIMER_IRQ		(IRQ_INTERNAL_BASE + 0)
-#define BCM_6368_UART0_IRQ		(IRQ_INTERNAL_BASE + 2)
-#define BCM_6368_UART1_IRQ		(IRQ_INTERNAL_BASE + 3)
-#define BCM_6368_DSL_IRQ		(IRQ_INTERNAL_BASE + 4)
-#define BCM_6368_ENET0_IRQ		0
-#define BCM_6368_ENET1_IRQ		0
-#define BCM_6368_ENET_PHY_IRQ		(IRQ_INTERNAL_BASE + 15)
-#define BCM_6368_OHCI0_IRQ		(IRQ_INTERNAL_BASE + 5)
-#define BCM_6368_EHCI0_IRQ		(IRQ_INTERNAL_BASE + 7)
-#define BCM_6368_PCMCIA_IRQ		0
-#define BCM_6368_ENET0_RXDMA_IRQ	0
-#define BCM_6368_ENET0_TXDMA_IRQ	0
-#define BCM_6368_ENET1_RXDMA_IRQ	0
-#define BCM_6368_ENET1_TXDMA_IRQ	0
-#define BCM_6368_PCI_IRQ		(IRQ_INTERNAL_BASE + 13)
-#define BCM_6368_ATM_IRQ		0
-#define BCM_6368_ENETSW_RXDMA0_IRQ	(BCM_6368_HIGH_IRQ_BASE + 0)
-#define BCM_6368_ENETSW_RXDMA1_IRQ	(BCM_6368_HIGH_IRQ_BASE + 1)
-#define BCM_6368_ENETSW_RXDMA2_IRQ	(BCM_6368_HIGH_IRQ_BASE + 2)
-#define BCM_6368_ENETSW_RXDMA3_IRQ	(BCM_6368_HIGH_IRQ_BASE + 3)
-#define BCM_6368_ENETSW_TXDMA0_IRQ	(BCM_6368_HIGH_IRQ_BASE + 4)
-#define BCM_6368_ENETSW_TXDMA1_IRQ	(BCM_6368_HIGH_IRQ_BASE + 5)
-#define BCM_6368_ENETSW_TXDMA2_IRQ	(BCM_6368_HIGH_IRQ_BASE + 6)
-#define BCM_6368_ENETSW_TXDMA3_IRQ	(BCM_6368_HIGH_IRQ_BASE + 7)
-#define BCM_6368_XTM_IRQ		(IRQ_INTERNAL_BASE + 11)
-#define BCM_6368_XTM_DMA0_IRQ		(BCM_6368_HIGH_IRQ_BASE + 8)
-
-#define BCM_6368_PCM_DMA0_IRQ		(BCM_6368_HIGH_IRQ_BASE + 30)
-#define BCM_6368_PCM_DMA1_IRQ		(BCM_6368_HIGH_IRQ_BASE + 31)
-#define BCM_6368_EXT_IRQ0		(IRQ_INTERNAL_BASE + 20)
-#define BCM_6368_EXT_IRQ1		(IRQ_INTERNAL_BASE + 21)
-#define BCM_6368_EXT_IRQ2		(IRQ_INTERNAL_BASE + 22)
-#define BCM_6368_EXT_IRQ3		(IRQ_INTERNAL_BASE + 23)
-#define BCM_6368_EXT_IRQ4		(IRQ_INTERNAL_BASE + 24)
-#define BCM_6368_EXT_IRQ5		(IRQ_INTERNAL_BASE + 25)
 
 extern const int *bcm63xx_irqs;
 
-#define __GEN_CPU_IRQ_TABLE(__cpu)					\
-	[IRQ_TIMER]		= BCM_## __cpu ##_TIMER_IRQ,		\
-	[IRQ_UART0]		= BCM_## __cpu ##_UART0_IRQ,		\
-	[IRQ_UART1]		= BCM_## __cpu ##_UART1_IRQ,		\
-	[IRQ_DSL]		= BCM_## __cpu ##_DSL_IRQ,		\
-	[IRQ_ENET0]		= BCM_## __cpu ##_ENET0_IRQ,		\
-	[IRQ_ENET1]		= BCM_## __cpu ##_ENET1_IRQ,		\
-	[IRQ_ENET_PHY]		= BCM_## __cpu ##_ENET_PHY_IRQ,		\
-	[IRQ_OHCI0]		= BCM_## __cpu ##_OHCI0_IRQ,		\
-	[IRQ_EHCI0]		= BCM_## __cpu ##_EHCI0_IRQ,		\
-	[IRQ_ENET0_RXDMA]	= BCM_## __cpu ##_ENET0_RXDMA_IRQ,	\
-	[IRQ_ENET0_TXDMA]	= BCM_## __cpu ##_ENET0_TXDMA_IRQ,	\
-	[IRQ_ENET1_RXDMA]	= BCM_## __cpu ##_ENET1_RXDMA_IRQ,	\
-	[IRQ_ENET1_TXDMA]	= BCM_## __cpu ##_ENET1_TXDMA_IRQ,	\
-	[IRQ_PCI]		= BCM_## __cpu ##_PCI_IRQ,		\
-	[IRQ_PCMCIA]		= BCM_## __cpu ##_PCMCIA_IRQ,		\
-	[IRQ_ATM]		= BCM_## __cpu ##_ATM_IRQ,		\
-	[IRQ_ENETSW_RXDMA0]	= BCM_## __cpu ##_ENETSW_RXDMA0_IRQ,	\
-	[IRQ_ENETSW_RXDMA1]	= BCM_## __cpu ##_ENETSW_RXDMA1_IRQ,	\
-	[IRQ_ENETSW_RXDMA2]	= BCM_## __cpu ##_ENETSW_RXDMA2_IRQ,	\
-	[IRQ_ENETSW_RXDMA3]	= BCM_## __cpu ##_ENETSW_RXDMA3_IRQ,	\
-	[IRQ_ENETSW_TXDMA0]	= BCM_## __cpu ##_ENETSW_TXDMA0_IRQ,	\
-	[IRQ_ENETSW_TXDMA1]	= BCM_## __cpu ##_ENETSW_TXDMA1_IRQ,	\
-	[IRQ_ENETSW_TXDMA2]	= BCM_## __cpu ##_ENETSW_TXDMA2_IRQ,	\
-	[IRQ_ENETSW_TXDMA3]	= BCM_## __cpu ##_ENETSW_TXDMA3_IRQ,	\
-	[IRQ_XTM]		= BCM_## __cpu ##_XTM_IRQ,		\
-	[IRQ_XTM_DMA0]		= BCM_## __cpu ##_XTM_DMA0_IRQ,		\
-
 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 {
 	return bcm63xx_irqs[irq];
@@ -713,8 +550,4 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
  */
 unsigned int bcm63xx_get_memory_size(void);
 
-void bcm63xx_machine_halt(void);
-
-void bcm63xx_machine_reboot(void);
-
 #endif /* !BCM63XX_CPU_H_ */
diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3d5de96d4036..3999ec0aa7f5 100644
--- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,8 +14,6 @@ static inline unsigned long bcm63xx_gpio_count(void)
 		return 8;
 	case BCM6345_CPU_ID:
 		return 16;
-	case BCM6368_CPU_ID:
-		return 38;
 	case BCM6348_CPU_ID:
 	default:
 		return 37;
diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 72477a6441dd..91180fac6ed9 100644
--- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -49,11 +49,9 @@
 #define bcm_readb(a)	(*(volatile unsigned char *)	BCM_REGS_VA(a))
 #define bcm_readw(a)	(*(volatile unsigned short *)	BCM_REGS_VA(a))
 #define bcm_readl(a)	(*(volatile unsigned int *)	BCM_REGS_VA(a))
-#define bcm_readq(a)	(*(volatile u64 *)		BCM_REGS_VA(a))
 #define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
 #define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
 #define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
-#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
 
 /*
  * IO helpers to access register set for current CPU
diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 0c3074b871b8..5f95577c8213 100644
--- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,11 +3,13 @@
 
 #include <bcm63xx_cpu.h>
 
+#define IRQ_MIPS_BASE			0
 #define IRQ_INTERNAL_BASE		8
-#define IRQ_EXTERNAL_BASE		100
-#define IRQ_EXT_0			(IRQ_EXTERNAL_BASE + 0)
-#define IRQ_EXT_1			(IRQ_EXTERNAL_BASE + 1)
-#define IRQ_EXT_2			(IRQ_EXTERNAL_BASE + 2)
-#define IRQ_EXT_3			(IRQ_EXTERNAL_BASE + 3)
+
+#define IRQ_EXT_BASE			(IRQ_MIPS_BASE + 3)
+#define IRQ_EXT_0			(IRQ_EXT_BASE + 0)
+#define IRQ_EXT_1			(IRQ_EXT_BASE + 1)
+#define IRQ_EXT_2			(IRQ_EXT_BASE + 2)
+#define IRQ_EXT_3			(IRQ_EXT_BASE + 3)
 
 #endif /* ! BCM63XX_IRQ_H_ */
diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 94d4faad29a1..0ed5230243c9 100644
--- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,86 +83,30 @@
 					CKCTL_6358_USBSU_EN |		\
 					CKCTL_6358_EPHY_EN)
 
-#define CKCTL_6368_VDSL_QPROC_EN	(1 << 2)
-#define CKCTL_6368_VDSL_AFE_EN		(1 << 3)
-#define CKCTL_6368_VDSL_BONDING_EN	(1 << 4)
-#define CKCTL_6368_VDSL_EN		(1 << 5)
-#define CKCTL_6368_PHYMIPS_EN		(1 << 6)
-#define CKCTL_6368_SWPKT_USB_EN		(1 << 7)
-#define CKCTL_6368_SWPKT_SAR_EN		(1 << 8)
-#define CKCTL_6368_SPI_CLK_EN		(1 << 9)
-#define CKCTL_6368_USBD_CLK_EN		(1 << 10)
-#define CKCTL_6368_SAR_CLK_EN		(1 << 11)
-#define CKCTL_6368_ROBOSW_CLK_EN	(1 << 12)
-#define CKCTL_6368_UTOPIA_CLK_EN	(1 << 13)
-#define CKCTL_6368_PCM_CLK_EN		(1 << 14)
-#define CKCTL_6368_USBH_CLK_EN		(1 << 15)
-#define CKCTL_6368_DISABLE_GLESS_EN	(1 << 16)
-#define CKCTL_6368_NAND_CLK_EN		(1 << 17)
-#define CKCTL_6368_IPSEC_CLK_EN		(1 << 17)
-
-#define CKCTL_6368_ALL_SAFE_EN		(CKCTL_6368_SWPKT_USB_EN |	\
-					CKCTL_6368_SWPKT_SAR_EN |	\
-					CKCTL_6368_SPI_CLK_EN |		\
-					CKCTL_6368_USBD_CLK_EN |	\
-					CKCTL_6368_SAR_CLK_EN |		\
-					CKCTL_6368_ROBOSW_CLK_EN |	\
-					CKCTL_6368_UTOPIA_CLK_EN |	\
-					CKCTL_6368_PCM_CLK_EN |		\
-					CKCTL_6368_USBH_CLK_EN |	\
-					CKCTL_6368_DISABLE_GLESS_EN |	\
-					CKCTL_6368_NAND_CLK_EN |	\
-					CKCTL_6368_IPSEC_CLK_EN)
-
 /* System PLL Control register  */
 #define PERF_SYS_PLL_CTL_REG		0x8
 #define SYS_PLL_SOFT_RESET		0x1
 
 /* Interrupt Mask register */
-#define PERF_IRQMASK_6338_REG		0xc
-#define PERF_IRQMASK_6345_REG		0xc
-#define PERF_IRQMASK_6348_REG		0xc
-#define PERF_IRQMASK_6358_REG		0xc
-#define PERF_IRQMASK_6368_REG		0x20
+#define PERF_IRQMASK_REG		0xc
 
 /* Interrupt Status register */
-#define PERF_IRQSTAT_6338_REG		0x10
-#define PERF_IRQSTAT_6345_REG		0x10
-#define PERF_IRQSTAT_6348_REG		0x10
-#define PERF_IRQSTAT_6358_REG		0x10
-#define PERF_IRQSTAT_6368_REG		0x28
+#define PERF_IRQSTAT_REG		0x10
 
 /* External Interrupt Configuration register */
-#define PERF_EXTIRQ_CFG_REG_6338	0x14
-#define PERF_EXTIRQ_CFG_REG_6348	0x14
-#define PERF_EXTIRQ_CFG_REG_6358	0x14
-#define PERF_EXTIRQ_CFG_REG_6368	0x18
-
-#define PERF_EXTIRQ_CFG_REG2_6368	0x1c
-
-/* for 6348 only */
-#define EXTIRQ_CFG_SENSE_6348(x)	(1 << (x))
-#define EXTIRQ_CFG_STAT_6348(x)		(1 << (x + 5))
-#define EXTIRQ_CFG_CLEAR_6348(x)	(1 << (x + 10))
-#define EXTIRQ_CFG_MASK_6348(x)		(1 << (x + 15))
-#define EXTIRQ_CFG_BOTHEDGE_6348(x)	(1 << (x + 20))
-#define EXTIRQ_CFG_LEVELSENSE_6348(x)	(1 << (x + 25))
-#define EXTIRQ_CFG_CLEAR_ALL_6348	(0xf << 10)
-#define EXTIRQ_CFG_MASK_ALL_6348	(0xf << 15)
-
-/* for all others */
+#define PERF_EXTIRQ_CFG_REG		0x14
 #define EXTIRQ_CFG_SENSE(x)		(1 << (x))
-#define EXTIRQ_CFG_STAT(x)		(1 << (x + 4))
-#define EXTIRQ_CFG_CLEAR(x)		(1 << (x + 8))
-#define EXTIRQ_CFG_MASK(x)		(1 << (x + 12))
-#define EXTIRQ_CFG_BOTHEDGE(x)		(1 << (x + 16))
-#define EXTIRQ_CFG_LEVELSENSE(x)	(1 << (x + 20))
-#define EXTIRQ_CFG_CLEAR_ALL		(0xf << 8)
-#define EXTIRQ_CFG_MASK_ALL		(0xf << 12)
+#define EXTIRQ_CFG_STAT(x)		(1 << (x + 5))
+#define EXTIRQ_CFG_CLEAR(x)		(1 << (x + 10))
+#define EXTIRQ_CFG_MASK(x)		(1 << (x + 15))
+#define EXTIRQ_CFG_BOTHEDGE(x)		(1 << (x + 20))
+#define EXTIRQ_CFG_LEVELSENSE(x)	(1 << (x + 25))
+
+#define EXTIRQ_CFG_CLEAR_ALL		(0xf << 10)
+#define EXTIRQ_CFG_MASK_ALL		(0xf << 15)
 
 /* Soft Reset register */
 #define PERF_SOFTRESET_REG		0x28
-#define PERF_SOFTRESET_6368_REG		0x10
 
 #define SOFTRESET_6338_SPI_MASK		(1 << 0)
 #define SOFTRESET_6338_ENET_MASK	(1 << 2)
@@ -203,15 +147,6 @@
 				  SOFTRESET_6348_ACLC_MASK |		\
 				  SOFTRESET_6348_ADSLMIPSPLL_MASK)
 
-#define SOFTRESET_6368_SPI_MASK		(1 << 0)
-#define SOFTRESET_6368_MPI_MASK		(1 << 3)
-#define SOFTRESET_6368_EPHY_MASK	(1 << 6)
-#define SOFTRESET_6368_SAR_MASK		(1 << 7)
-#define SOFTRESET_6368_ENETSW_MASK	(1 << 10)
-#define SOFTRESET_6368_USBS_MASK	(1 << 11)
-#define SOFTRESET_6368_USBH_MASK	(1 << 12)
-#define SOFTRESET_6368_PCM_MASK		(1 << 13)
-
 /* MIPS PLL control register */
 #define PERF_MIPSPLLCTL_REG		0x34
 #define MIPSPLLCTL_N1_SHIFT		20
@@ -437,7 +372,6 @@
 #define GPIO_CTL_LO_REG			0x4
 #define GPIO_DATA_HI_REG		0x8
 #define GPIO_DATA_LO_REG		0xC
-#define GPIO_DATA_LO_REG_6345		0x8
 
 /* GPIO mux registers and constants */
 #define GPIO_MODE_REG			0x18
@@ -468,44 +402,6 @@
 #define GPIO_MODE_6358_SERIAL_LED	(1 << 10)
 #define GPIO_MODE_6358_UTOPIA		(1 << 12)
 
-#define GPIO_MODE_6368_ANALOG_AFE_0	(1 << 0)
-#define GPIO_MODE_6368_ANALOG_AFE_1	(1 << 1)
-#define GPIO_MODE_6368_SYS_IRQ		(1 << 2)
-#define GPIO_MODE_6368_SERIAL_LED_DATA	(1 << 3)
-#define GPIO_MODE_6368_SERIAL_LED_CLK	(1 << 4)
-#define GPIO_MODE_6368_INET_LED		(1 << 5)
-#define GPIO_MODE_6368_EPHY0_LED	(1 << 6)
-#define GPIO_MODE_6368_EPHY1_LED	(1 << 7)
-#define GPIO_MODE_6368_EPHY2_LED	(1 << 8)
-#define GPIO_MODE_6368_EPHY3_LED	(1 << 9)
-#define GPIO_MODE_6368_ROBOSW_LED_DAT	(1 << 10)
-#define GPIO_MODE_6368_ROBOSW_LED_CLK	(1 << 11)
-#define GPIO_MODE_6368_ROBOSW_LED0	(1 << 12)
-#define GPIO_MODE_6368_ROBOSW_LED1	(1 << 13)
-#define GPIO_MODE_6368_USBD_LED		(1 << 14)
-#define GPIO_MODE_6368_NTR_PULSE	(1 << 15)
-#define GPIO_MODE_6368_PCI_REQ1		(1 << 16)
-#define GPIO_MODE_6368_PCI_GNT1		(1 << 17)
-#define GPIO_MODE_6368_PCI_INTB		(1 << 18)
-#define GPIO_MODE_6368_PCI_REQ0		(1 << 19)
-#define GPIO_MODE_6368_PCI_GNT0		(1 << 20)
-#define GPIO_MODE_6368_PCMCIA_CD1	(1 << 22)
-#define GPIO_MODE_6368_PCMCIA_CD2	(1 << 23)
-#define GPIO_MODE_6368_PCMCIA_VS1	(1 << 24)
-#define GPIO_MODE_6368_PCMCIA_VS2	(1 << 25)
-#define GPIO_MODE_6368_EBI_CS2		(1 << 26)
-#define GPIO_MODE_6368_EBI_CS3		(1 << 27)
-#define GPIO_MODE_6368_SPI_SSN2		(1 << 28)
-#define GPIO_MODE_6368_SPI_SSN3		(1 << 29)
-#define GPIO_MODE_6368_SPI_SSN4		(1 << 30)
-#define GPIO_MODE_6368_SPI_SSN5		(1 << 31)
-
-
-#define GPIO_BASEMODE_6368_REG		0x38
-#define GPIO_BASEMODE_6368_UART2	0x1
-#define GPIO_BASEMODE_6368_GPIO		0x0
-#define GPIO_BASEMODE_6368_MASK		0x7
-/* those bits must be kept as read in gpio basemode register*/
 
 /*************************************************************************
  * _REG relative to RSET_ENET
@@ -651,56 +547,6 @@
 #define ENETDMA_SRAM4_REG(x)		(0x20c + (x) * 0x10)
 
 
-/*************************************************************************
- * _REG relative to RSET_ENETDMAC
- *************************************************************************/
-
-/* Channel Configuration register */
-#define ENETDMAC_CHANCFG_REG(x)		((x) * 0x10)
-#define ENETDMAC_CHANCFG_EN_SHIFT	0
-#define ENETDMAC_CHANCFG_EN_MASK	(1 << ENETDMA_CHANCFG_EN_SHIFT)
-#define ENETDMAC_CHANCFG_PKTHALT_SHIFT	1
-#define ENETDMAC_CHANCFG_PKTHALT_MASK	(1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
-
-/* Interrupt Control/Status register */
-#define ENETDMAC_IR_REG(x)		(0x4 + (x) * 0x10)
-#define ENETDMAC_IR_BUFDONE_MASK	(1 << 0)
-#define ENETDMAC_IR_PKTDONE_MASK	(1 << 1)
-#define ENETDMAC_IR_NOTOWNER_MASK	(1 << 2)
-
-/* Interrupt Mask register */
-#define ENETDMAC_IRMASK_REG(x)		(0x8 + (x) * 0x10)
-
-/* Maximum Burst Length */
-#define ENETDMAC_MAXBURST_REG(x)	(0xc + (x) * 0x10)
-
-
-/*************************************************************************
- * _REG relative to RSET_ENETDMAS
- *************************************************************************/
-
-/* Ring Start Address register */
-#define ENETDMAS_RSTART_REG(x)		((x) * 0x10)
-
-/* State Ram Word 2 */
-#define ENETDMAS_SRAM2_REG(x)		(0x4 + (x) * 0x10)
-
-/* State Ram Word 3 */
-#define ENETDMAS_SRAM3_REG(x)		(0x8 + (x) * 0x10)
-
-/* State Ram Word 4 */
-#define ENETDMAS_SRAM4_REG(x)		(0xc + (x) * 0x10)
-
-
-/*************************************************************************
- * _REG relative to RSET_ENETSW
- *************************************************************************/
-
-/* MIB register */
-#define ENETSW_MIB_REG(x)		(0x2800 + (x) * 4)
-#define ENETSW_MIB_REG_COUNT		47
-
-
 /*************************************************************************
  * _REG relative to RSET_OHCI_PRIV
  *************************************************************************/
@@ -716,9 +562,7 @@
  * _REG relative to RSET_USBH_PRIV
  *************************************************************************/
 
-#define USBH_PRIV_SWAP_6358_REG		0x0
-#define USBH_PRIV_SWAP_6368_REG		0x1c
-
+#define USBH_PRIV_SWAP_REG		0x0
 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT	4
 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK	(1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT	3
@@ -728,13 +572,7 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT	0
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK	(1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
-#define USBH_PRIV_TEST_6358_REG		0x24
-#define USBH_PRIV_TEST_6368_REG		0x14
-
-#define USBH_PRIV_SETUP_6368_REG	0x28
-#define USBH_PRIV_SETUP_IOC_SHIFT	4
-#define USBH_PRIV_SETUP_IOC_MASK	(1 << USBH_PRIV_SETUP_IOC_SHIFT)
-
+#define USBH_PRIV_TEST_REG		0x24
 
 
 /*************************************************************************
@@ -896,8 +734,6 @@
 #define SDRAM_CFG_BANK_SHIFT		13
 #define SDRAM_CFG_BANK_MASK		(1 << SDRAM_CFG_BANK_SHIFT)
 
-#define SDRAM_MBASE_REG			0xc
-
 #define SDRAM_PRIO_REG			0x2C
 #define SDRAM_PRIO_MIPS_SHIFT		29
 #define SDRAM_PRIO_MIPS_MASK		(1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -932,45 +768,4 @@
 #define DMIPSPLLCFG_N2_SHIFT		29
 #define DMIPSPLLCFG_N2_MASK		(0x7 << DMIPSPLLCFG_N2_SHIFT)
 
-#define DDR_DMIPSPLLCFG_6368_REG	0x20
-#define DMIPSPLLCFG_6368_P1_SHIFT	0
-#define DMIPSPLLCFG_6368_P1_MASK	(0xf << DMIPSPLLCFG_6368_P1_SHIFT)
-#define DMIPSPLLCFG_6368_P2_SHIFT	4
-#define DMIPSPLLCFG_6368_P2_MASK	(0xf << DMIPSPLLCFG_6368_P2_SHIFT)
-#define DMIPSPLLCFG_6368_NDIV_SHIFT	16
-#define DMIPSPLLCFG_6368_NDIV_MASK	(0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
-
-#define DDR_DMIPSPLLDIV_6368_REG	0x24
-#define DMIPSPLLDIV_6368_MDIV_SHIFT	0
-#define DMIPSPLLDIV_6368_MDIV_MASK	(0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
-
-
-/*************************************************************************
- * _REG relative to RSET_M2M
- *************************************************************************/
-
-#define M2M_RX				0
-#define M2M_TX				1
-
-#define M2M_SRC_REG(x)			((x) * 0x40 + 0x00)
-#define M2M_DST_REG(x)			((x) * 0x40 + 0x04)
-#define M2M_SIZE_REG(x)			((x) * 0x40 + 0x08)
-
-#define M2M_CTRL_REG(x)			((x) * 0x40 + 0x0c)
-#define M2M_CTRL_ENABLE_MASK		(1 << 0)
-#define M2M_CTRL_IRQEN_MASK		(1 << 1)
-#define M2M_CTRL_ERROR_CLR_MASK		(1 << 6)
-#define M2M_CTRL_DONE_CLR_MASK		(1 << 7)
-#define M2M_CTRL_NOINC_MASK		(1 << 8)
-#define M2M_CTRL_PCMCIASWAP_MASK	(1 << 9)
-#define M2M_CTRL_SWAPBYTE_MASK		(1 << 10)
-#define M2M_CTRL_ENDIAN_MASK		(1 << 11)
-
-#define M2M_STAT_REG(x)			((x) * 0x40 + 0x10)
-#define M2M_STAT_DONE			(1 << 0)
-#define M2M_STAT_ERROR			(1 << 1)
-
-#define M2M_SRCID_REG(x)		((x) * 0x40 + 0x14)
-#define M2M_DSTID_REG(x)		((x) * 0x40 + 0x18)
-
 #endif /* BCM63XX_REGS_H_ */
diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/trunk/arch/mips/include/asm/mach-bcm63xx/ioremap.h
deleted file mode 100644
index ef94ba73646e..000000000000
--- a/trunk/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef BCM63XX_IOREMAP_H_
-#define BCM63XX_IOREMAP_H_
-
-#include <bcm63xx_cpu.h>
-
-static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-	return phys_addr;
-}
-
-static inline int is_bcm63xx_internal_registers(phys_t offset)
-{
-	switch (bcm63xx_get_cpu_id()) {
-	case BCM6338_CPU_ID:
-	case BCM6345_CPU_ID:
-	case BCM6348_CPU_ID:
-	case BCM6358_CPU_ID:
-		if (offset >= 0xfff00000)
-			return 1;
-		break;
-	case BCM6368_CPU_ID:
-		if (offset >= 0xb0000000 && offset < 0xb1000000)
-			return 1;
-		break;
-	}
-	return 0;
-}
-
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
-					 unsigned long flags)
-{
-	if (is_bcm63xx_internal_registers(offset))
-		return (void __iomem *)offset;
-	return NULL;
-}
-
-static inline int plat_iounmap(const volatile void __iomem *addr)
-{
-	return is_bcm63xx_internal_registers((unsigned long)addr);
-}
-
-#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/irq.h b/trunk/arch/mips/include/asm/mach-bcm63xx/irq.h
deleted file mode 100644
index 9332e788a5c9..000000000000
--- a/trunk/arch/mips/include/asm/mach-bcm63xx/irq.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_BCM63XX_IRQ_H
-#define __ASM_MACH_BCM63XX_IRQ_H
-
-#define NR_IRQS	128
-#define MIPS_CPU_IRQ_BASE 0
-
-#endif
diff --git a/trunk/arch/mips/pci/pci-bcm63xx.c b/trunk/arch/mips/pci/pci-bcm63xx.c
index 39eb7c417e2f..82e0fde1dba0 100644
--- a/trunk/arch/mips/pci/pci-bcm63xx.c
+++ b/trunk/arch/mips/pci/pci-bcm63xx.c
@@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void)
 	unsigned int mem_size;
 	u32 val;
 
-	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
+	if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358())
 		return -ENODEV;
 
 	if (!bcm63xx_pci_enabled)
@@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void)
 	/* setup PCI to local bus access, used by PCI device to target
 	 * local RAM while bus mastering */
 	bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
-	if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
+	if (BCMCPU_IS_6358())
 		val = MPI_SP0_REMAP_ENABLE_MASK;
 	else
 		val = 0;