From c0a6020e7e8a07c0e869d077bfbd7ec4db28854a Mon Sep 17 00:00:00 2001
From: Zhao Yakui <yakui.zhao@intel.com>
Date: Mon, 4 Jan 2010 16:29:32 +0800
Subject: [PATCH] --- yaml --- r: 178855 b: refs/heads/master c:
 e5a95eb778690bc864eb330202d2c1b974caaeb4 h: refs/heads/master i:   178853:
 6d3eacd25e26d5114301d8deaeb5a0db31cec76d   178851:
 c6d87b7f400ec45e2f007897b9b1047e047450eb   178847:
 996f3a287ebe1c038612cfdb58a835ecf3318a27 v: v3

---
 [refs]                                     |  2 +-
 trunk/drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index d4ba8e9a03e6..3a2644d9f384 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8faf3b317471179c02db339aa80955a2e88c036d
+refs/heads/master: e5a95eb778690bc864eb330202d2c1b974caaeb4
diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c
index 63e8e9fd6793..5e2159b59920 100644
--- a/trunk/drivers/gpu/drm/i915/intel_display.c
+++ b/trunk/drivers/gpu/drm/i915/intel_display.c
@@ -2993,6 +2993,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
 		/* determine panel color depth */
 		temp = I915_READ(pipeconf_reg);
+		temp &= ~PIPE_BPC_MASK;
+		if (is_lvds) {
+			int lvds_reg = I915_READ(PCH_LVDS);
+			/* the BPC will be 6 if it is 18-bit LVDS panel */
+			if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
+				temp |= PIPE_8BPC;
+			else
+				temp |= PIPE_6BPC;
+		} else
+			temp |= PIPE_8BPC;
+		I915_WRITE(pipeconf_reg, temp);
+		I915_READ(pipeconf_reg);
 
 		switch (temp & PIPE_BPC_MASK) {
 		case PIPE_8BPC: