From c0c452d69d3623b584f03f33c991596fb8d6eb6a Mon Sep 17 00:00:00 2001 From: Mark Nelson Date: Mon, 27 Oct 2008 00:46:51 +0000 Subject: [PATCH] --- yaml --- r: 123005 b: refs/heads/master c: 25d6e2d7c58ddc4a3b614fc5381591c0cfe66556 h: refs/heads/master i: 123003: 0eb5eaeef787d30037962c8d0c6489ce94b09987 v: v3 --- [refs] | 2 +- trunk/arch/powerpc/lib/memcpy_64.S | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 8261e105d4c2..9dd19267bea1 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4ec577a28980a0790df3c3dfe9c81f6e2222acfb +refs/heads/master: 25d6e2d7c58ddc4a3b614fc5381591c0cfe66556 diff --git a/trunk/arch/powerpc/lib/memcpy_64.S b/trunk/arch/powerpc/lib/memcpy_64.S index 3f131129d1c1..fe2d34e5332d 100644 --- a/trunk/arch/powerpc/lib/memcpy_64.S +++ b/trunk/arch/powerpc/lib/memcpy_64.S @@ -18,11 +18,23 @@ _GLOBAL(memcpy) andi. r6,r6,7 dcbt 0,r4 blt cr1,.Lshort_copy +/* Below we want to nop out the bne if we're on a CPU that has the + CPU_FTR_UNALIGNED_LD_STD bit set and the CPU_FTR_CP_USE_DCBTZ bit + cleared. + At the time of writing the only CPU that has this combination of bits + set is Power6. */ +BEGIN_FTR_SECTION + nop +FTR_SECTION_ELSE bne .Ldst_unaligned +ALT_FTR_SECTION_END(CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_CP_USE_DCBTZ, \ + CPU_FTR_UNALIGNED_LD_STD) .Ldst_aligned: - andi. r0,r4,7 addi r3,r3,-16 +BEGIN_FTR_SECTION + andi. r0,r4,7 bne .Lsrc_unaligned +END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD) srdi r7,r5,4 ld r9,0(r4) addi r4,r4,-8 @@ -131,7 +143,7 @@ _GLOBAL(memcpy) PPC_MTOCRF 0x01,r6 # put #bytes to 8B bdry into cr7 subf r5,r6,r5 li r7,0 - cmpldi r1,r5,16 + cmpldi cr1,r5,16 bf cr7*4+3,1f lbz r0,0(r4) stb r0,0(r3)