From c0c8abe8e41e74f585811acc1010fb0b0077ee18 Mon Sep 17 00:00:00 2001 From: Olof Johansson Date: Tue, 15 Dec 2009 10:34:12 -0800 Subject: [PATCH] --- yaml --- r: 177974 b: refs/heads/master c: 35358281bbc527cd4b0a8d39266c9ad554643e9f h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/.gitignore | 7 +- .../ABI/testing/sysfs-memory-page-offline | 44 - trunk/Documentation/Changes | 2 - trunk/Documentation/DocBook/Makefile | 38 +- .../Documentation/DocBook/media-entities.tmpl | 18 - .../Documentation/DocBook/media-indices.tmpl | 4 - trunk/Documentation/DocBook/procfs-guide.tmpl | 626 ++ trunk/Documentation/DocBook/procfs_example.c | 201 + trunk/Documentation/DocBook/v4l/common.xml | 35 - trunk/Documentation/DocBook/v4l/compat.xml | 16 +- trunk/Documentation/DocBook/v4l/v4l2.xml | 26 +- .../Documentation/DocBook/v4l/videodev2.h.xml | 116 +- .../DocBook/v4l/vidioc-enum-dv-presets.xml | 238 - .../DocBook/v4l/vidioc-enuminput.xml | 36 +- .../DocBook/v4l/vidioc-enumoutput.xml | 36 +- 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trunk/scripts/Makefile.modbuiltin delete mode 100644 trunk/tools/perf/Documentation/perf-diff.txt delete mode 100644 trunk/tools/perf/builtin-diff.c create mode 100644 trunk/tools/perf/util/data_map.h diff --git a/[refs] b/[refs] index a27ea22d8faa..6c0d4bf0f8d3 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e82b1dae2a8730c89e2a30c5c28562ef066f39d9 +refs/heads/master: 35358281bbc527cd4b0a8d39266c9ad554643e9f diff --git a/trunk/.gitignore b/trunk/.gitignore index fb2190c61af0..946c7ec5c922 100644 --- a/trunk/.gitignore +++ b/trunk/.gitignore @@ -22,7 +22,6 @@ *.lst *.symtypes *.order -modules.builtin *.elf *.bin *.gz @@ -46,8 +45,14 @@ Module.symvers # # Generated include files # +include/asm +include/asm-*/asm-offsets.h include/config +include/linux/autoconf.h +include/linux/compile.h include/linux/version.h +include/linux/utsrelease.h +include/linux/bounds.h include/generated # stgit generated dirs diff --git a/trunk/Documentation/ABI/testing/sysfs-memory-page-offline b/trunk/Documentation/ABI/testing/sysfs-memory-page-offline deleted file mode 100644 index e14703f12fdf..000000000000 --- a/trunk/Documentation/ABI/testing/sysfs-memory-page-offline +++ /dev/null @@ -1,44 +0,0 @@ -What: /sys/devices/system/memory/soft_offline_page -Date: Sep 2009 -KernelVersion: 2.6.33 -Contact: andi@firstfloor.org -Description: - Soft-offline the memory page containing the physical address - written into this file. Input is a hex number specifying the - physical address of the page. The kernel will then attempt - to soft-offline it, by moving the contents elsewhere or - dropping it if possible. The kernel will then be placed - on the bad page list and never be reused. - - The offlining is done in kernel specific granuality. - Normally it's the base page size of the kernel, but - this might change. - - The page must be still accessible, not poisoned. The - kernel will never kill anything for this, but rather - fail the offline. Return value is the size of the - number, or a error when the offlining failed. Reading - the file is not allowed. - -What: /sys/devices/system/memory/hard_offline_page -Date: Sep 2009 -KernelVersion: 2.6.33 -Contact: andi@firstfloor.org -Description: - Hard-offline the memory page containing the physical - address written into this file. Input is a hex number - specifying the physical address of the page. The - kernel will then attempt to hard-offline the page, by - trying to drop the page or killing any owner or - triggering IO errors if needed. Note this may kill - any processes owning the page. The kernel will avoid - to access this page assuming it's poisoned by the - hardware. - - The offlining is done in kernel specific granuality. - Normally it's the base page size of the kernel, but - this might change. - - Return value is the size of the number, or a error when - the offlining failed. - Reading the file is not allowed. diff --git a/trunk/Documentation/Changes b/trunk/Documentation/Changes index f08b313cd235..6d0f1efc5bf6 100644 --- a/trunk/Documentation/Changes +++ b/trunk/Documentation/Changes @@ -49,8 +49,6 @@ o oprofile 0.9 # oprofiled --version o udev 081 # udevinfo -V o grub 0.93 # grub --version o mcelog 0.6 -o iptables 1.4.1 # iptables -V - Kernel compilation ================== diff --git a/trunk/Documentation/DocBook/Makefile b/trunk/Documentation/DocBook/Makefile index 325cfd1d6d99..ab8300f67182 100644 --- a/trunk/Documentation/DocBook/Makefile +++ b/trunk/Documentation/DocBook/Makefile @@ -8,7 +8,7 @@ DOCBOOKS := z8530book.xml mcabook.xml device-drivers.xml \ kernel-hacking.xml kernel-locking.xml deviceiobook.xml \ - writing_usb_driver.xml networking.xml \ + procfs-guide.xml writing_usb_driver.xml networking.xml \ kernel-api.xml filesystems.xml lsm.xml usb.xml kgdb.xml \ gadget.xml libata.xml mtdnand.xml librs.xml rapidio.xml \ genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \ @@ -32,10 +32,10 @@ PS_METHOD = $(prefer-db2x) ### # The targets that may be used. -PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs xmldoclinks +PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs media BOOKS := $(addprefix $(obj)/,$(DOCBOOKS)) -xmldocs: $(BOOKS) xmldoclinks +xmldocs: $(BOOKS) sgmldocs: xmldocs PS := $(patsubst %.xml, %.ps, $(BOOKS)) @@ -45,24 +45,15 @@ PDF := $(patsubst %.xml, %.pdf, $(BOOKS)) pdfdocs: $(PDF) HTML := $(sort $(patsubst %.xml, %.html, $(BOOKS))) -htmldocs: $(HTML) +htmldocs: media $(HTML) $(call build_main_index) - $(call build_images) MAN := $(patsubst %.xml, %.9, $(BOOKS)) mandocs: $(MAN) -build_images = mkdir -p $(objtree)/Documentation/DocBook/media/ && \ - cp $(srctree)/Documentation/DocBook/dvb/*.png $(srctree)/Documentation/DocBook/v4l/*.gif $(objtree)/Documentation/DocBook/media/ - -xmldoclinks: -ifneq ($(objtree),$(srctree)) - for dep in dvb media-entities.tmpl media-indices.tmpl v4l; do \ - rm -f $(objtree)/Documentation/DocBook/$$dep \ - && ln -s $(srctree)/Documentation/DocBook/$$dep $(objtree)/Documentation/DocBook/ \ - || exit; \ - done -endif +media: + mkdir -p $(srctree)/Documentation/DocBook/media/ + cp $(srctree)/Documentation/DocBook/dvb/*.png $(srctree)/Documentation/DocBook/v4l/*.gif $(srctree)/Documentation/DocBook/media/ installmandocs: mandocs mkdir -p /usr/local/man/man9/ @@ -74,7 +65,7 @@ KERNELDOC = $(srctree)/scripts/kernel-doc DOCPROC = $(objtree)/scripts/basic/docproc XMLTOFLAGS = -m $(srctree)/Documentation/DocBook/stylesheet.xsl -XMLTOFLAGS += --skip-validation +#XMLTOFLAGS += --skip-validation ### # DOCPROC is used for two purposes: @@ -110,6 +101,17 @@ endif # Changes in kernel-doc force a rebuild of all documentation $(BOOKS): $(KERNELDOC) +### +# procfs guide uses a .c file as example code. +# This requires an explicit dependency +C-procfs-example = procfs_example.xml +C-procfs-example2 = $(addprefix $(obj)/,$(C-procfs-example)) +$(obj)/procfs-guide.xml: $(C-procfs-example2) + +# List of programs to build +##oops, this is a kernel module::hostprogs-y := procfs_example +obj-m += procfs_example.o + # Tell kbuild to always build the programs always := $(hostprogs-y) @@ -236,7 +238,7 @@ clean-files := $(DOCBOOKS) \ $(patsubst %.xml, %.pdf, $(DOCBOOKS)) \ $(patsubst %.xml, %.html, $(DOCBOOKS)) \ $(patsubst %.xml, %.9, $(DOCBOOKS)) \ - $(index) + $(C-procfs-example) $(index) clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man diff --git a/trunk/Documentation/DocBook/media-entities.tmpl b/trunk/Documentation/DocBook/media-entities.tmpl index c725cb852c54..bb5ab741220e 100644 --- a/trunk/Documentation/DocBook/media-entities.tmpl +++ b/trunk/Documentation/DocBook/media-entities.tmpl @@ -23,7 +23,6 @@ VIDIOC_ENUMINPUT"> VIDIOC_ENUMOUTPUT"> VIDIOC_ENUMSTD"> -VIDIOC_ENUM_DV_PRESETS"> VIDIOC_ENUM_FMT"> VIDIOC_ENUM_FRAMEINTERVALS"> VIDIOC_ENUM_FRAMESIZES"> @@ -31,8 +30,6 @@ VIDIOC_G_AUDOUT"> VIDIOC_G_CROP"> VIDIOC_G_CTRL"> -VIDIOC_G_DV_PRESET"> -VIDIOC_G_DV_TIMINGS"> VIDIOC_G_ENC_INDEX"> VIDIOC_G_EXT_CTRLS"> VIDIOC_G_FBUF"> @@ -56,7 +53,6 @@ VIDIOC_QUERYCTRL"> VIDIOC_QUERYMENU"> VIDIOC_QUERYSTD"> -VIDIOC_QUERY_DV_PRESET"> VIDIOC_REQBUFS"> VIDIOC_STREAMOFF"> VIDIOC_STREAMON"> @@ -64,8 +60,6 @@ VIDIOC_S_AUDOUT"> VIDIOC_S_CROP"> VIDIOC_S_CTRL"> -VIDIOC_S_DV_PRESET"> -VIDIOC_S_DV_TIMINGS"> VIDIOC_S_EXT_CTRLS"> VIDIOC_S_FBUF"> VIDIOC_S_FMT"> @@ -124,7 +118,6 @@ v4l2_audio"> v4l2_audioout"> -v4l2_bt_timings"> v4l2_buffer"> v4l2_capability"> v4l2_captureparm"> @@ -135,9 +128,6 @@ v4l2_dbg_chip_ident"> v4l2_dbg_match"> v4l2_dbg_register"> -v4l2_dv_enum_preset"> -v4l2_dv_preset"> -v4l2_dv_timings"> v4l2_enc_idx"> v4l2_enc_idx_entry"> v4l2_encoder_cmd"> @@ -253,10 +243,6 @@ - - - - @@ -347,10 +333,6 @@ - - - - diff --git a/trunk/Documentation/DocBook/media-indices.tmpl b/trunk/Documentation/DocBook/media-indices.tmpl index 78d6031de001..9e30a236d74f 100644 --- a/trunk/Documentation/DocBook/media-indices.tmpl +++ b/trunk/Documentation/DocBook/media-indices.tmpl @@ -36,7 +36,6 @@ enum v4l2_preemphasis struct v4l2_audio struct v4l2_audioout -struct v4l2_bt_timings struct v4l2_buffer struct v4l2_capability struct v4l2_captureparm @@ -47,9 +46,6 @@ struct v4l2_dbg_chip_ident struct v4l2_dbg_match struct v4l2_dbg_register -struct v4l2_dv_enum_preset -struct v4l2_dv_preset -struct v4l2_dv_timings struct v4l2_enc_idx struct v4l2_enc_idx_entry struct v4l2_encoder_cmd diff --git a/trunk/Documentation/DocBook/procfs-guide.tmpl b/trunk/Documentation/DocBook/procfs-guide.tmpl new file mode 100644 index 000000000000..9eba4b7af73d --- /dev/null +++ b/trunk/Documentation/DocBook/procfs-guide.tmpl @@ -0,0 +1,626 @@ + + +]> + + + + Linux Kernel Procfs Guide + + + + Erik + (J.A.K.) + Mouw + +
+ mouw@nl.linux.org +
+ + + + + This software and documentation were written while working on the + LART computing board + (http://www.lartmaker.nl/), + which was sponsored by the Delt University of Technology projects + Mobile Multi-media Communications and Ubiquitous Communications. + + + + + + + 1.0 + May 30, 2001 + Initial revision posted to linux-kernel + + + 1.1 + June 3, 2001 + Revised after comments from linux-kernel + + + + + 2001 + Erik Mouw + + + + + + This documentation is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later + version. + + + + This documentation is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU General Public License for more details. + + + + You should have received a copy of the GNU General Public + License along with this program; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, + MA 02111-1307 USA + + + + For more details see the file COPYING in the source + distribution of Linux. + + + + + + + + + + + + + + + Preface + + + This guide describes the use of the procfs file system from + within the Linux kernel. The idea to write this guide came up on + the #kernelnewbies IRC channel (see http://www.kernelnewbies.org/), + when Jeff Garzik explained the use of procfs and forwarded me a + message Alexander Viro wrote to the linux-kernel mailing list. I + agreed to write it up nicely, so here it is. + + + + I'd like to thank Jeff Garzik + jgarzik@pobox.com and Alexander Viro + viro@parcelfarce.linux.theplanet.co.uk for their input, + Tim Waugh twaugh@redhat.com for his Selfdocbook, + and Marc Joosen marcj@historia.et.tudelft.nl for + proofreading. + + + + Erik + + + + + + + + Introduction + + + The /proc file system + (procfs) is a special file system in the linux kernel. It's a + virtual file system: it is not associated with a block device + but exists only in memory. The files in the procfs are there to + allow userland programs access to certain information from the + kernel (like process information in /proc/[0-9]+/), but also for debug + purposes (like /proc/ksyms). + + + + This guide describes the use of the procfs file system from + within the Linux kernel. It starts by introducing all relevant + functions to manage the files within the file system. After that + it shows how to communicate with userland, and some tips and + tricks will be pointed out. Finally a complete example will be + shown. + + + + Note that the files in /proc/sys are sysctl files: they + don't belong to procfs and are governed by a completely + different API described in the Kernel API book. + + + + + + + + Managing procfs entries + + + This chapter describes the functions that various kernel + components use to populate the procfs with files, symlinks, + device nodes, and directories. + + + + A minor note before we start: if you want to use any of the + procfs functions, be sure to include the correct header file! + This should be one of the first lines in your code: + + + +#include <linux/proc_fs.h> + + + + + + + Creating a regular file + + + + struct proc_dir_entry* create_proc_entry + const char* name + mode_t mode + struct proc_dir_entry* parent + + + + + This function creates a regular file with the name + name, file mode + mode in the directory + parent. To create a file in the root of + the procfs, use NULL as + parent parameter. When successful, the + function will return a pointer to the freshly created + struct proc_dir_entry; otherwise it + will return NULL. describes how to do something useful with + regular files. + + + + Note that it is specifically supported that you can pass a + path that spans multiple directories. For example + create_proc_entry("drivers/via0/info") + will create the via0 + directory if necessary, with standard + 0755 permissions. + + + + If you only want to be able to read the file, the function + create_proc_read_entry described in may be used to create and initialise + the procfs entry in one single call. + + + + + + + + Creating a symlink + + + + struct proc_dir_entry* + proc_symlink const + char* name + struct proc_dir_entry* + parent const + char* dest + + + + + This creates a symlink in the procfs directory + parent that points from + name to + dest. This translates in userland to + ln -s dest + name. + + + + + Creating a directory + + + + struct proc_dir_entry* proc_mkdir + const char* name + struct proc_dir_entry* parent + + + + + Create a directory name in the procfs + directory parent. + + + + + + + + Removing an entry + + + + void remove_proc_entry + const char* name + struct proc_dir_entry* parent + + + + + Removes the entry name in the directory + parent from the procfs. Entries are + removed by their name, not by the + struct proc_dir_entry returned by the + various create functions. Note that this function doesn't + recursively remove entries. + + + + Be sure to free the data entry from + the struct proc_dir_entry before + remove_proc_entry is called (that is: if + there was some data allocated, of + course). See for more information + on using the data entry. + + + + + + + + + Communicating with userland + + + Instead of reading (or writing) information directly from + kernel memory, procfs works with call back + functions for files: functions that are called when + a specific file is being read or written. Such functions have + to be initialised after the procfs file is created by setting + the read_proc and/or + write_proc fields in the + struct proc_dir_entry* that the + function create_proc_entry returned: + + + +struct proc_dir_entry* entry; + +entry->read_proc = read_proc_foo; +entry->write_proc = write_proc_foo; + + + + If you only want to use a the + read_proc, the function + create_proc_read_entry described in may be used to create and initialise the + procfs entry in one single call. + + + + + + Reading data + + + The read function is a call back function that allows userland + processes to read data from the kernel. The read function + should have the following format: + + + + + int read_func + char* buffer + char** start + off_t off + int count + int* peof + void* data + + + + + The read function should write its information into the + buffer, which will be exactly + PAGE_SIZE bytes long. + + + + The parameter + peof should be used to signal that the + end of the file has been reached by writing + 1 to the memory location + peof points to. + + + + The data + parameter can be used to create a single call back function for + several files, see . + + + + The rest of the parameters and the return value are described + by a comment in fs/proc/generic.c as follows: + + +
+ + You have three ways to return data: + + + + + Leave *start = NULL. (This is the default.) + Put the data of the requested offset at that + offset within the buffer. Return the number (n) + of bytes there are from the beginning of the + buffer up to the last byte of data. If the + number of supplied bytes (= n - offset) is + greater than zero and you didn't signal eof + and the reader is prepared to take more data + you will be called again with the requested + offset advanced by the number of bytes + absorbed. This interface is useful for files + no larger than the buffer. + + + + + Set *start to an unsigned long value less than + the buffer address but greater than zero. + Put the data of the requested offset at the + beginning of the buffer. Return the number of + bytes of data placed there. If this number is + greater than zero and you didn't signal eof + and the reader is prepared to take more data + you will be called again with the requested + offset advanced by *start. This interface is + useful when you have a large file consisting + of a series of blocks which you want to count + and return as wholes. + (Hack by Paul.Russell@rustcorp.com.au) + + + + + Set *start to an address within the buffer. + Put the data of the requested offset at *start. + Return the number of bytes of data placed there. + If this number is greater than zero and you + didn't signal eof and the reader is prepared to + take more data you will be called again with the + requested offset advanced by the number of bytes + absorbed. + + + +
+ + + shows how to use a read call back + function. + + + + + + + + Writing data + + + The write call back function allows a userland process to write + data to the kernel, so it has some kind of control over the + kernel. The write function should have the following format: + + + + + int write_func + struct file* file + const char* buffer + unsigned long count + void* data + + + + + The write function should read count + bytes at maximum from the buffer. Note + that the buffer doesn't live in the + kernel's memory space, so it should first be copied to kernel + space with copy_from_user. The + file parameter is usually + ignored. shows how to use the + data parameter. + + + + Again, shows how to use this call back + function. + + + + + + + + A single call back for many files + + + When a large number of almost identical files is used, it's + quite inconvenient to use a separate call back function for + each file. A better approach is to have a single call back + function that distinguishes between the files by using the + data field in struct + proc_dir_entry. First of all, the + data field has to be initialised: + + + +struct proc_dir_entry* entry; +struct my_file_data *file_data; + +file_data = kmalloc(sizeof(struct my_file_data), GFP_KERNEL); +entry->data = file_data; + + + + The data field is a void + *, so it can be initialised with anything. + + + + Now that the data field is set, the + read_proc and + write_proc can use it to distinguish + between files because they get it passed into their + data parameter: + + + +int foo_read_func(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + + if(data == file_data) { + /* special case for this file */ + } else { + /* normal processing */ + } + + return len; +} + + + + Be sure to free the data data field + when removing the procfs entry. + + + + + + + + + Tips and tricks + + + + + + Convenience functions + + + + struct proc_dir_entry* create_proc_read_entry + const char* name + mode_t mode + struct proc_dir_entry* parent + read_proc_t* read_proc + void* data + + + + + This function creates a regular file in exactly the same way + as create_proc_entry from does, but also allows to set the read + function read_proc in one call. This + function can set the data as well, like + explained in . + + + + + + + Modules + + + If procfs is being used from within a module, be sure to set + the owner field in the + struct proc_dir_entry to + THIS_MODULE. + + + +struct proc_dir_entry* entry; + +entry->owner = THIS_MODULE; + + + + + + + + Mode and ownership + + + Sometimes it is useful to change the mode and/or ownership of + a procfs entry. Here is an example that shows how to achieve + that: + + + +struct proc_dir_entry* entry; + +entry->mode = S_IWUSR |S_IRUSR | S_IRGRP | S_IROTH; +entry->uid = 0; +entry->gid = 100; + + + + + + + + + + Example + + + +&procfsexample; + + + diff --git a/trunk/Documentation/DocBook/procfs_example.c b/trunk/Documentation/DocBook/procfs_example.c new file mode 100644 index 000000000000..a5b11793b1e0 --- /dev/null +++ b/trunk/Documentation/DocBook/procfs_example.c @@ -0,0 +1,201 @@ +/* + * procfs_example.c: an example proc interface + * + * Copyright (C) 2001, Erik Mouw (mouw@nl.linux.org) + * + * This file accompanies the procfs-guide in the Linux kernel + * source. Its main use is to demonstrate the concepts and + * functions described in the guide. + * + * This software has been developed while working on the LART + * computing board (http://www.lartmaker.nl), which was sponsored + * by the Delt University of Technology projects Mobile Multi-media + * Communications and Ubiquitous Communications. + * + * This program is free software; you can redistribute + * it and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the + * Free Software Foundation, Inc., 59 Temple Place, + * Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + + +#define MODULE_VERS "1.0" +#define MODULE_NAME "procfs_example" + +#define FOOBAR_LEN 8 + +struct fb_data_t { + char name[FOOBAR_LEN + 1]; + char value[FOOBAR_LEN + 1]; +}; + + +static struct proc_dir_entry *example_dir, *foo_file, + *bar_file, *jiffies_file, *symlink; + + +struct fb_data_t foo_data, bar_data; + + +static int proc_read_jiffies(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + int len; + + len = sprintf(page, "jiffies = %ld\n", + jiffies); + + return len; +} + + +static int proc_read_foobar(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + int len; + struct fb_data_t *fb_data = (struct fb_data_t *)data; + + /* DON'T DO THAT - buffer overruns are bad */ + len = sprintf(page, "%s = '%s'\n", + fb_data->name, fb_data->value); + + return len; +} + + +static int proc_write_foobar(struct file *file, + const char *buffer, + unsigned long count, + void *data) +{ + int len; + struct fb_data_t *fb_data = (struct fb_data_t *)data; + + if(count > FOOBAR_LEN) + len = FOOBAR_LEN; + else + len = count; + + if(copy_from_user(fb_data->value, buffer, len)) + return -EFAULT; + + fb_data->value[len] = '\0'; + + return len; +} + + +static int __init init_procfs_example(void) +{ + int rv = 0; + + /* create directory */ + example_dir = proc_mkdir(MODULE_NAME, NULL); + if(example_dir == NULL) { + rv = -ENOMEM; + goto out; + } + /* create jiffies using convenience function */ + jiffies_file = create_proc_read_entry("jiffies", + 0444, example_dir, + proc_read_jiffies, + NULL); + if(jiffies_file == NULL) { + rv = -ENOMEM; + goto no_jiffies; + } + + /* create foo and bar files using same callback + * functions + */ + foo_file = create_proc_entry("foo", 0644, example_dir); + if(foo_file == NULL) { + rv = -ENOMEM; + goto no_foo; + } + + strcpy(foo_data.name, "foo"); + strcpy(foo_data.value, "foo"); + foo_file->data = &foo_data; + foo_file->read_proc = proc_read_foobar; + foo_file->write_proc = proc_write_foobar; + + bar_file = create_proc_entry("bar", 0644, example_dir); + if(bar_file == NULL) { + rv = -ENOMEM; + goto no_bar; + } + + strcpy(bar_data.name, "bar"); + strcpy(bar_data.value, "bar"); + bar_file->data = &bar_data; + bar_file->read_proc = proc_read_foobar; + bar_file->write_proc = proc_write_foobar; + + /* create symlink */ + symlink = proc_symlink("jiffies_too", example_dir, + "jiffies"); + if(symlink == NULL) { + rv = -ENOMEM; + goto no_symlink; + } + + /* everything OK */ + printk(KERN_INFO "%s %s initialised\n", + MODULE_NAME, MODULE_VERS); + return 0; + +no_symlink: + remove_proc_entry("bar", example_dir); +no_bar: + remove_proc_entry("foo", example_dir); +no_foo: + remove_proc_entry("jiffies", example_dir); +no_jiffies: + remove_proc_entry(MODULE_NAME, NULL); +out: + return rv; +} + + +static void __exit cleanup_procfs_example(void) +{ + remove_proc_entry("jiffies_too", example_dir); + remove_proc_entry("bar", example_dir); + remove_proc_entry("foo", example_dir); + remove_proc_entry("jiffies", example_dir); + remove_proc_entry(MODULE_NAME, NULL); + + printk(KERN_INFO "%s %s removed\n", + MODULE_NAME, MODULE_VERS); +} + + +module_init(init_procfs_example); +module_exit(cleanup_procfs_example); + +MODULE_AUTHOR("Erik Mouw"); +MODULE_DESCRIPTION("procfs examples"); +MODULE_LICENSE("GPL"); diff --git a/trunk/Documentation/DocBook/v4l/common.xml b/trunk/Documentation/DocBook/v4l/common.xml index c65f0ac9b6ee..b1a81d246d58 100644 --- a/trunk/Documentation/DocBook/v4l/common.xml +++ b/trunk/Documentation/DocBook/v4l/common.xml @@ -716,41 +716,6 @@ if (-1 == ioctl (fd, &VIDIOC-S-STD;, &std_id)) { } -
- Digital Video (DV) Timings - - The video standards discussed so far has been dealing with Analog TV and the -corresponding video timings. Today there are many more different hardware interfaces -such as High Definition TV interfaces (HDMI), VGA, DVI connectors etc., that carry -video signals and there is a need to extend the API to select the video timings -for these interfaces. Since it is not possible to extend the &v4l2-std-id; due to -the limited bits available, a new set of IOCTLs is added to set/get video timings at -the input and output: - - DV Presets: Digital Video (DV) presets. These are IDs representing a -video timing at the input/output. Presets are pre-defined timings implemented -by the hardware according to video standards. A __u32 data type is used to represent -a preset unlike the bit mask that is used in &v4l2-std-id; allowing future extensions -to support as many different presets as needed. - - - Custom DV Timings: This will allow applications to define more detailed -custom video timings for the interface. This includes parameters such as width, height, -polarities, frontporch, backporch etc. - - - - To enumerate and query the attributes of DV presets supported by a device, -applications use the &VIDIOC-ENUM-DV-PRESETS; ioctl. To get the current DV preset, -applications use the &VIDIOC-G-DV-PRESET; ioctl and to set a preset they use the -&VIDIOC-S-DV-PRESET; ioctl. - To set custom DV timings for the device, applications use the -&VIDIOC-S-DV-TIMINGS; ioctl and to get current custom DV timings they use the -&VIDIOC-G-DV-TIMINGS; ioctl. - Applications can make use of the and - flags to decide what ioctls are available to set the -video timings for the device. -
&sub-controls; diff --git a/trunk/Documentation/DocBook/v4l/compat.xml b/trunk/Documentation/DocBook/v4l/compat.xml index b9dbdf9e6d29..4d1902a54d61 100644 --- a/trunk/Documentation/DocBook/v4l/compat.xml +++ b/trunk/Documentation/DocBook/v4l/compat.xml @@ -2291,8 +2291,8 @@ was renamed to v4l2_chip_ident_old New control V4L2_CID_COLORFX was added. - - + +
V4L2 in Linux 2.6.32 @@ -2322,16 +2322,8 @@ more information. Added Remote Controller chapter, describing the default Remote Controller mapping for media devices. - -
-
- V4L2 in Linux 2.6.33 - - - Added support for Digital Video timings in order to support HDTV receivers and transmitters. - - -
+ +
diff --git a/trunk/Documentation/DocBook/v4l/v4l2.xml b/trunk/Documentation/DocBook/v4l/v4l2.xml index 060105af49e5..937b4157a5d0 100644 --- a/trunk/Documentation/DocBook/v4l/v4l2.xml +++ b/trunk/Documentation/DocBook/v4l/v4l2.xml @@ -74,17 +74,6 @@ Remote Controller chapter. - - - Muralidharan - Karicheri - Documented the Digital Video timings API. - -
- m-karicheri2@ti.com -
- - @@ -100,7 +89,7 @@ Remote Controller chapter. 2008 2009 Bill Dirks, Michael H. Schimek, Hans Verkuil, Martin -Rubli, Andy Walls, Muralidharan Karicheri, Mauro Carvalho Chehab +Rubli, Andy Walls, Mauro Carvalho Chehab Except when explicitly stated as GPL, programming examples within @@ -113,13 +102,6 @@ structs, ioctls) must be noted in more detail in the history chapter (compat.sgml), along with the possible impact on existing drivers and applications. --> - - 2.6.33 - 2009-12-03 - mk - Added documentation for the Digital Video timings API. - - 2.6.32 2009-08-31 @@ -373,7 +355,7 @@ and discussions on the V4L mailing list. Video for Linux Two API Specification - Revision 2.6.33 + Revision 2.6.32 &sub-common; @@ -429,7 +411,6 @@ and discussions on the V4L mailing list. &sub-encoder-cmd; &sub-enumaudio; &sub-enumaudioout; - &sub-enum-dv-presets; &sub-enum-fmt; &sub-enum-framesizes; &sub-enum-frameintervals; @@ -440,8 +421,6 @@ and discussions on the V4L mailing list. &sub-g-audioout; &sub-g-crop; &sub-g-ctrl; - &sub-g-dv-preset; - &sub-g-dv-timings; &sub-g-enc-index; &sub-g-ext-ctrls; &sub-g-fbuf; @@ -462,7 +441,6 @@ and discussions on the V4L mailing list. &sub-querybuf; &sub-querycap; &sub-queryctrl; - &sub-query-dv-preset; &sub-querystd; &sub-reqbufs; &sub-s-hw-freq-seek; diff --git a/trunk/Documentation/DocBook/v4l/videodev2.h.xml b/trunk/Documentation/DocBook/v4l/videodev2.h.xml index 068325940658..3e282ed9f593 100644 --- a/trunk/Documentation/DocBook/v4l/videodev2.h.xml +++ b/trunk/Documentation/DocBook/v4l/videodev2.h.xml @@ -733,99 +733,6 @@ struct v4l2_standard { __u32 reserved[4]; }; -/* - * V I D E O T I M I N G S D V P R E S E T - */ -struct v4l2_dv_preset { - __u32 preset; - __u32 reserved[4]; -}; - -/* - * D V P R E S E T S E N U M E R A T I O N - */ -struct v4l2_dv_enum_preset { - __u32 index; - __u32 preset; - __u8 name[32]; /* Name of the preset timing */ - __u32 width; - __u32 height; - __u32 reserved[4]; -}; - -/* - * D V P R E S E T V A L U E S - */ -#define V4L2_DV_INVALID 0 -#define V4L2_DV_480P59_94 1 /* BT.1362 */ -#define V4L2_DV_576P50 2 /* BT.1362 */ -#define V4L2_DV_720P24 3 /* SMPTE 296M */ -#define V4L2_DV_720P25 4 /* SMPTE 296M */ -#define V4L2_DV_720P30 5 /* SMPTE 296M */ -#define V4L2_DV_720P50 6 /* SMPTE 296M */ -#define V4L2_DV_720P59_94 7 /* SMPTE 274M */ -#define V4L2_DV_720P60 8 /* SMPTE 274M/296M */ -#define V4L2_DV_1080I29_97 9 /* BT.1120/ SMPTE 274M */ -#define V4L2_DV_1080I30 10 /* BT.1120/ SMPTE 274M */ -#define V4L2_DV_1080I25 11 /* BT.1120 */ -#define V4L2_DV_1080I50 12 /* SMPTE 296M */ -#define V4L2_DV_1080I60 13 /* SMPTE 296M */ -#define V4L2_DV_1080P24 14 /* SMPTE 296M */ -#define V4L2_DV_1080P25 15 /* SMPTE 296M */ -#define V4L2_DV_1080P30 16 /* SMPTE 296M */ -#define V4L2_DV_1080P50 17 /* BT.1120 */ -#define V4L2_DV_1080P60 18 /* BT.1120 */ - -/* - * D V B T T I M I N G S - */ - -/* BT.656/BT.1120 timing data */ -struct v4l2_bt_timings { - __u32 width; /* width in pixels */ - __u32 height; /* height in lines */ - __u32 interlaced; /* Interlaced or progressive */ - __u32 polarities; /* Positive or negative polarity */ - __u64 pixelclock; /* Pixel clock in HZ. Ex. 74.25MHz->74250000 */ - __u32 hfrontporch; /* Horizpontal front porch in pixels */ - __u32 hsync; /* Horizontal Sync length in pixels */ - __u32 hbackporch; /* Horizontal back porch in pixels */ - __u32 vfrontporch; /* Vertical front porch in pixels */ - __u32 vsync; /* Vertical Sync length in lines */ - __u32 vbackporch; /* Vertical back porch in lines */ - __u32 il_vfrontporch; /* Vertical front porch for bottom field of - * interlaced field formats - */ - __u32 il_vsync; /* Vertical sync length for bottom field of - * interlaced field formats - */ - __u32 il_vbackporch; /* Vertical back porch for bottom field of - * interlaced field formats - */ - __u32 reserved[16]; -} __attribute__ ((packed)); - -/* Interlaced or progressive format */ -#define V4L2_DV_PROGRESSIVE 0 -#define V4L2_DV_INTERLACED 1 - -/* Polarities. If bit is not set, it is assumed to be negative polarity */ -#define V4L2_DV_VSYNC_POS_POL 0x00000001 -#define V4L2_DV_HSYNC_POS_POL 0x00000002 - - -/* DV timings */ -struct v4l2_dv_timings { - __u32 type; - union { - struct v4l2_bt_timings bt; - __u32 reserved[32]; - }; -} __attribute__ ((packed)); - -/* Values for the type field */ -#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */ - /* * V I D E O I N P U T S */ @@ -837,8 +744,7 @@ struct v4l2_input { __u32 tuner; /* Associated tuner */ v4l2_std_id std; __u32 status; - __u32 capabilities; - __u32 reserved[3]; + __u32 reserved[4]; }; /* Values for the 'type' field */ @@ -869,11 +775,6 @@ struct v4l2_input { #define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */ #define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */ -/* capabilities flags */ -#define V4L2_IN_CAP_PRESETS 0x00000001 /* Supports S_DV_PRESET */ -#define V4L2_IN_CAP_CUSTOM_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ -#define V4L2_IN_CAP_STD 0x00000004 /* Supports S_STD */ - /* * V I D E O O U T P U T S */ @@ -884,19 +785,13 @@ struct v4l2_output { __u32 audioset; /* Associated audios (bitfield) */ __u32 modulator; /* Associated modulator */ v4l2_std_id std; - __u32 capabilities; - __u32 reserved[3]; + __u32 reserved[4]; }; /* Values for the 'type' field */ #define V4L2_OUTPUT_TYPE_MODULATOR 1 #define V4L2_OUTPUT_TYPE_ANALOG 2 #define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 -/* capabilities flags */ -#define V4L2_OUT_CAP_PRESETS 0x00000001 /* Supports S_DV_PRESET */ -#define V4L2_OUT_CAP_CUSTOM_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ -#define V4L2_OUT_CAP_STD 0x00000004 /* Supports S_STD */ - /* * C O N T R O L S */ @@ -1731,13 +1626,6 @@ struct v4l2_dbg_chip_ident { #endif #define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) -#define VIDIOC_ENUM_DV_PRESETS _IOWR('V', 83, struct v4l2_dv_enum_preset) -#define VIDIOC_S_DV_PRESET _IOWR('V', 84, struct v4l2_dv_preset) -#define VIDIOC_G_DV_PRESET _IOWR('V', 85, struct v4l2_dv_preset) -#define VIDIOC_QUERY_DV_PRESET _IOR('V', 86, struct v4l2_dv_preset) -#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) -#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) - /* Reminder: when adding new ioctls please add support for them to drivers/media/video/v4l2-compat-ioctl32.c as well! */ diff --git a/trunk/Documentation/DocBook/v4l/vidioc-enum-dv-presets.xml b/trunk/Documentation/DocBook/v4l/vidioc-enum-dv-presets.xml deleted file mode 100644 index 1d31427edd1b..000000000000 --- a/trunk/Documentation/DocBook/v4l/vidioc-enum-dv-presets.xml +++ /dev/null @@ -1,238 +0,0 @@ - - - ioctl VIDIOC_ENUM_DV_PRESETS - &manvol; - - - - VIDIOC_ENUM_DV_PRESETS - Enumerate supported Digital Video presets - - - - - - int ioctl - int fd - int request - struct v4l2_dv_enum_preset *argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_ENUM_DV_PRESETS - - - - argp - - - - - - - - - Description - - To query the attributes of a DV preset, applications initialize the -index field and zero the reserved array of &v4l2-dv-enum-preset; -and call the VIDIOC_ENUM_DV_PRESETS ioctl with a pointer to this -structure. Drivers fill the rest of the structure or return an -&EINVAL; when the index is out of bounds. To enumerate all DV Presets supported, -applications shall begin at index zero, incrementing by one until the -driver returns EINVAL. Drivers may enumerate a -different set of DV presets after switching the video input or -output. - - - struct <structname>v4l2_dv_enum_presets</structname> - - &cs-str; - - - __u32 - index - Number of the DV preset, set by the -application. - - - __u32 - preset - This field identifies one of the DV preset values listed in . - - - __u8 - name[24] - Name of the preset, a NUL-terminated ASCII string, for example: "720P-60", "1080I-60". This information is -intended for the user. - - - __u32 - width - Width of the active video in pixels for the DV preset. - - - __u32 - height - Height of the active video in lines for the DV preset. - - - __u32 - reserved[4] - Reserved for future extensions. Drivers must set the array to zero. - - - -
- - - struct <structname>DV Presets</structname> - - &cs-str; - - - Preset - Preset value - Description - - - - - - - - V4L2_DV_INVALID - 0 - Invalid preset value. - - - V4L2_DV_480P59_94 - 1 - 720x480 progressive video at 59.94 fps as per BT.1362. - - - V4L2_DV_576P50 - 2 - 720x576 progressive video at 50 fps as per BT.1362. - - - V4L2_DV_720P24 - 3 - 1280x720 progressive video at 24 fps as per SMPTE 296M. - - - V4L2_DV_720P25 - 4 - 1280x720 progressive video at 25 fps as per SMPTE 296M. - - - V4L2_DV_720P30 - 5 - 1280x720 progressive video at 30 fps as per SMPTE 296M. - - - V4L2_DV_720P50 - 6 - 1280x720 progressive video at 50 fps as per SMPTE 296M. - - - V4L2_DV_720P59_94 - 7 - 1280x720 progressive video at 59.94 fps as per SMPTE 274M. - - - V4L2_DV_720P60 - 8 - 1280x720 progressive video at 60 fps as per SMPTE 274M/296M. - - - V4L2_DV_1080I29_97 - 9 - 1920x1080 interlaced video at 29.97 fps as per BT.1120/SMPTE 274M. - - - V4L2_DV_1080I30 - 10 - 1920x1080 interlaced video at 30 fps as per BT.1120/SMPTE 274M. - - - V4L2_DV_1080I25 - 11 - 1920x1080 interlaced video at 25 fps as per BT.1120. - - - V4L2_DV_1080I50 - 12 - 1920x1080 interlaced video at 50 fps as per SMPTE 296M. - - - V4L2_DV_1080I60 - 13 - 1920x1080 interlaced video at 60 fps as per SMPTE 296M. - - - V4L2_DV_1080P24 - 14 - 1920x1080 progressive video at 24 fps as per SMPTE 296M. - - - V4L2_DV_1080P25 - 15 - 1920x1080 progressive video at 25 fps as per SMPTE 296M. - - - V4L2_DV_1080P30 - 16 - 1920x1080 progressive video at 30 fps as per SMPTE 296M. - - - V4L2_DV_1080P50 - 17 - 1920x1080 progressive video at 50 fps as per BT.1120. - - - V4L2_DV_1080P60 - 18 - 1920x1080 progressive video at 60 fps as per BT.1120. - - - -
- - - - &return-value; - - - - EINVAL - - The &v4l2-dv-enum-preset; index -is out of bounds. - - - - - - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-enuminput.xml b/trunk/Documentation/DocBook/v4l/vidioc-enuminput.xml index 71b868e2fb8f..414856b82473 100644 --- a/trunk/Documentation/DocBook/v4l/vidioc-enuminput.xml +++ b/trunk/Documentation/DocBook/v4l/vidioc-enuminput.xml @@ -124,13 +124,7 @@ current input. __u32 - capabilities - This field provides capabilities for the -input. See for flags. - - - __u32 - reserved[3] + reserved[4] Reserved for future extensions. Drivers must set the array to zero. @@ -267,34 +261,6 @@ flag is set Macrovision has been detected. - - - - Input capabilities - - &cs-def; - - - V4L2_IN_CAP_PRESETS - 0x00000001 - This input supports setting DV presets by using VIDIOC_S_DV_PRESET. - - - V4L2_OUT_CAP_CUSTOM_TIMINGS - 0x00000002 - This input supports setting custom video timings by using VIDIOC_S_DV_TIMINGS. - - - V4L2_IN_CAP_STD - 0x00000004 - This input supports setting the TV standard by using VIDIOC_S_STD. - - - -
diff --git a/trunk/Documentation/DocBook/v4l/vidioc-enumoutput.xml b/trunk/Documentation/DocBook/v4l/vidioc-enumoutput.xml index a281d26a195f..e8d16dcd50cf 100644 --- a/trunk/Documentation/DocBook/v4l/vidioc-enumoutput.xml +++ b/trunk/Documentation/DocBook/v4l/vidioc-enumoutput.xml @@ -114,13 +114,7 @@ details on video standards and how to switch see __u32 - capabilities - This field provides capabilities for the -output. See for flags. - - - __u32 - reserved[3] + reserved[4] Reserved for future extensions. Drivers must set the array to zero. @@ -153,34 +147,6 @@ CVBS, S-Video, RGB. - - - Output capabilities - - &cs-def; - - - V4L2_OUT_CAP_PRESETS - 0x00000001 - This output supports setting DV presets by using VIDIOC_S_DV_PRESET. - - - V4L2_OUT_CAP_CUSTOM_TIMINGS - 0x00000002 - This output supports setting custom video timings by using VIDIOC_S_DV_TIMINGS. - - - V4L2_OUT_CAP_STD - 0x00000004 - This output supports setting the TV standard by using VIDIOC_S_STD. - - - -
- &return-value; diff --git a/trunk/Documentation/DocBook/v4l/vidioc-g-dv-preset.xml b/trunk/Documentation/DocBook/v4l/vidioc-g-dv-preset.xml deleted file mode 100644 index 3c6784e132f3..000000000000 --- a/trunk/Documentation/DocBook/v4l/vidioc-g-dv-preset.xml +++ /dev/null @@ -1,111 +0,0 @@ - - - ioctl VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET - &manvol; - - - - VIDIOC_G_DV_PRESET - VIDIOC_S_DV_PRESET - Query or select the DV preset of the current input or output - - - - - - int ioctl - int fd - int request - &v4l2-dv-preset; -*argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET - - - - argp - - - - - - - - - Description - To query and select the current DV preset, applications -use the VIDIOC_G_DV_PRESET and VIDIOC_S_DV_PRESET -ioctls which take a pointer to a &v4l2-dv-preset; type as argument. -Applications must zero the reserved array in &v4l2-dv-preset;. -VIDIOC_G_DV_PRESET returns a dv preset in the field -preset of &v4l2-dv-preset;. - - VIDIOC_S_DV_PRESET accepts a pointer to a &v4l2-dv-preset; -that has the preset value to be set. Applications must zero the reserved array in &v4l2-dv-preset;. -If the preset is not supported, it returns an &EINVAL; - - - - &return-value; - - - - EINVAL - - This ioctl is not supported, or the -VIDIOC_S_DV_PRESET,VIDIOC_S_DV_PRESET parameter was unsuitable. - - - - EBUSY - - The device is busy and therefore can not change the preset. - - - - - - struct <structname>v4l2_dv_preset</structname> - - &cs-str; - - - __u32 - preset - Preset value to represent the digital video timings - - - __u32 - reserved[4] - Reserved fields for future use - - - -
- - - - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-g-dv-timings.xml b/trunk/Documentation/DocBook/v4l/vidioc-g-dv-timings.xml deleted file mode 100644 index ecc19576bb8f..000000000000 --- a/trunk/Documentation/DocBook/v4l/vidioc-g-dv-timings.xml +++ /dev/null @@ -1,224 +0,0 @@ - - - ioctl VIDIOC_G_DV_TIMINGS, VIDIOC_S_DV_TIMINGS - &manvol; - - - - VIDIOC_G_DV_TIMINGS - VIDIOC_S_DV_TIMINGS - Get or set custom DV timings for input or output - - - - - - int ioctl - int fd - int request - &v4l2-dv-timings; -*argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_G_DV_TIMINGS, VIDIOC_S_DV_TIMINGS - - - - argp - - - - - - - - - Description - To set custom DV timings for the input or output, applications use the -VIDIOC_S_DV_TIMINGS ioctl and to get the current custom timings, -applications use the VIDIOC_G_DV_TIMINGS ioctl. The detailed timing -information is filled in using the structure &v4l2-dv-timings;. These ioctls take -a pointer to the &v4l2-dv-timings; structure as argument. If the ioctl is not supported -or the timing values are not correct, the driver returns &EINVAL;. - - - - &return-value; - - - - EINVAL - - This ioctl is not supported, or the -VIDIOC_S_DV_TIMINGS parameter was unsuitable. - - - - EBUSY - - The device is busy and therefore can not change the timings. - - - - - - struct <structname>v4l2_bt_timings</structname> - - &cs-str; - - - __u32 - width - Width of the active video in pixels - - - __u32 - height - Height of the active video in lines - - - __u32 - interlaced - Progressive (0) or interlaced (1) - - - __u32 - polarities - This is a bit mask that defines polarities of sync signals. -bit 0 (V4L2_DV_VSYNC_POS_POL) is for vertical sync polarity and bit 1 (V4L2_DV_HSYNC_POS_POL) is for horizontal sync polarity. If the bit is set -(1) it is positive polarity and if is cleared (0), it is negative polarity. - - - __u64 - pixelclock - Pixel clock in Hz. Ex. 74.25MHz->74250000 - - - __u32 - hfrontporch - Horizontal front porch in pixels - - - __u32 - hsync - Horizontal sync length in pixels - - - __u32 - hbackporch - Horizontal back porch in pixels - - - __u32 - vfrontporch - Vertical front porch in lines - - - __u32 - vsync - Vertical sync length in lines - - - __u32 - vbackporch - Vertical back porch in lines - - - __u32 - il_vfrontporch - Vertical front porch in lines for bottom field of interlaced field formats - - - __u32 - il_vsync - Vertical sync length in lines for bottom field of interlaced field formats - - - __u32 - il_vbackporch - Vertical back porch in lines for bottom field of interlaced field formats - - - -
- - - struct <structname>v4l2_dv_timings</structname> - - &cs-str; - - - __u32 - type - - Type of DV timings as listed in . - - - union - - - - - - &v4l2-bt-timings; - bt - Timings defined by BT.656/1120 specifications - - - - __u32 - reserved[32] - - - - -
- - - DV Timing types - - &cs-str; - - - Timing type - value - Description - - - - - - - - V4L2_DV_BT_656_1120 - 0 - BT.656/1120 timings - - - -
- - - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-g-std.xml b/trunk/Documentation/DocBook/v4l/vidioc-g-std.xml index 912f8513e5da..b6f5d267e856 100644 --- a/trunk/Documentation/DocBook/v4l/vidioc-g-std.xml +++ b/trunk/Documentation/DocBook/v4l/vidioc-g-std.xml @@ -86,12 +86,6 @@ standards. VIDIOC_S_STD parameter was unsuitable. - - EBUSY - - The device is busy and therefore can not change the standard - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-query-dv-preset.xml b/trunk/Documentation/DocBook/v4l/vidioc-query-dv-preset.xml deleted file mode 100644 index 87e4f0f6151c..000000000000 --- a/trunk/Documentation/DocBook/v4l/vidioc-query-dv-preset.xml +++ /dev/null @@ -1,85 +0,0 @@ - - - ioctl VIDIOC_QUERY_DV_PRESET - &manvol; - - - - VIDIOC_QUERY_DV_PRESET - Sense the DV preset received by the current -input - - - - - - int ioctl - int fd - int request - &v4l2-dv-preset; *argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_QUERY_DV_PRESET - - - - argp - - - - - - - - - Description - - The hardware may be able to detect the current DV preset -automatically, similar to sensing the video standard. To do so, applications -call VIDIOC_QUERY_DV_PRESET with a pointer to a -&v4l2-dv-preset; type. Once the hardware detects a preset, that preset is -returned in the preset field of &v4l2-dv-preset;. When detection is not -possible or fails, the value V4L2_DV_INVALID is returned. - - - - &return-value; - - - EINVAL - - This ioctl is not supported. - - - - EBUSY - - The device is busy and therefore can not sense the preset - - - - - - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-querystd.xml b/trunk/Documentation/DocBook/v4l/vidioc-querystd.xml index 1a9e60393091..b5a7ff934486 100644 --- a/trunk/Documentation/DocBook/v4l/vidioc-querystd.xml +++ b/trunk/Documentation/DocBook/v4l/vidioc-querystd.xml @@ -70,12 +70,6 @@ current video input or output. This ioctl is not supported. - - EBUSY - - The device is busy and therefore can not detect the standard - - diff --git a/trunk/Documentation/SubmitChecklist b/trunk/Documentation/SubmitChecklist index 1053a56be3b1..78a9168ff377 100644 --- a/trunk/Documentation/SubmitChecklist +++ b/trunk/Documentation/SubmitChecklist @@ -15,7 +15,7 @@ kernel patches. 2: Passes allnoconfig, allmodconfig 3: Builds on multiple CPU architectures by using local cross-compile tools - or some other build farm. + or something like PLM at OSDL. 4: ppc64 is a good architecture for cross-compilation checking because it tends to use `unsigned long' for 64-bit quantities. @@ -88,6 +88,3 @@ kernel patches. 24: All memory barriers {e.g., barrier(), rmb(), wmb()} need a comment in the source code that explains the logic of what they are doing and why. - -25: If any ioctl's are added by the patch, then also update - Documentation/ioctl/ioctl-number.txt. diff --git a/trunk/Documentation/acpi/method-customizing.txt b/trunk/Documentation/acpi/method-customizing.txt deleted file mode 100644 index e628cd23ca80..000000000000 --- a/trunk/Documentation/acpi/method-customizing.txt +++ /dev/null @@ -1,66 +0,0 @@ -Linux ACPI Custom Control Method How To -======================================= - -Written by Zhang Rui - - -Linux supports customizing ACPI control methods at runtime. - -Users can use this to -1. override an existing method which may not work correctly, - or just for debugging purposes. -2. insert a completely new method in order to create a missing - method such as _OFF, _ON, _STA, _INI, etc. -For these cases, it is far simpler to dynamically install a single -control method rather than override the entire DSDT, because kernel -rebuild/reboot is not needed and test result can be got in minutes. - -Note: Only ACPI METHOD can be overridden, any other object types like - "Device", "OperationRegion", are not recognized. -Note: The same ACPI control method can be overridden for many times, - and it's always the latest one that used by Linux/kernel. - -1. override an existing method - a) get the ACPI table via ACPI sysfs I/F. e.g. to get the DSDT, - just run "cat /sys/firmware/acpi/tables/DSDT > /tmp/dsdt.dat" - b) disassemble the table by running "iasl -d dsdt.dat". - c) rewrite the ASL code of the method and save it in a new file, - d) package the new file (psr.asl) to an ACPI table format. - Here is an example of a customized \_SB._AC._PSR method, - - DefinitionBlock ("", "SSDT", 1, "", "", 0x20080715) - { - External (ACON) - - Method (\_SB_.AC._PSR, 0, NotSerialized) - { - Store ("In AC _PSR", Debug) - Return (ACON) - } - } - Note that the full pathname of the method in ACPI namespace - should be used. - And remember to use "External" to declare external objects. - e) assemble the file to generate the AML code of the method. - e.g. "iasl psr.asl" (psr.aml is generated as a result) - f) mount debugfs by "mount -t debugfs none /sys/kernel/debug" - g) override the old method via the debugfs by running - "cat /tmp/psr.aml > /sys/kernel/debug/acpi/custom_method" - -2. insert a new method - This is easier than overriding an existing method. - We just need to create the ASL code of the method we want to - insert and then follow the step c) ~ g) in section 1. - -3. undo your changes - The "undo" operation is not supported for a new inserted method - right now, i.e. we can not remove a method currently. - For an overrided method, in order to undo your changes, please - save a copy of the method original ASL code in step c) section 1, - and redo step c) ~ g) to override the method with the original one. - - -Note: We can use a kernel with multiple custom ACPI method running, - But each individual write to debugfs can implement a SINGLE - method override. i.e. if we want to insert/override multiple - ACPI methods, we need to redo step c) ~ g) for multiple times. diff --git a/trunk/Documentation/blackfin/00-INDEX b/trunk/Documentation/blackfin/00-INDEX index c34e12440fec..d6840a91e1e1 100644 --- a/trunk/Documentation/blackfin/00-INDEX +++ b/trunk/Documentation/blackfin/00-INDEX @@ -1,6 +1,9 @@ 00-INDEX - This file +cache-lock.txt + - HOWTO for blackfin cache locking. + cachefeatures.txt - Supported cache features. diff --git a/trunk/Documentation/blackfin/Makefile b/trunk/Documentation/blackfin/Makefile deleted file mode 100644 index 773dbb103f1c..000000000000 --- a/trunk/Documentation/blackfin/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -obj-m := gptimers-example.o - -all: modules - -modules clean: - $(MAKE) -C ../.. SUBDIRS=$(PWD) $@ diff --git a/trunk/Documentation/blackfin/cache-lock.txt b/trunk/Documentation/blackfin/cache-lock.txt new file mode 100644 index 000000000000..88ba1e6c31c3 --- /dev/null +++ b/trunk/Documentation/blackfin/cache-lock.txt @@ -0,0 +1,48 @@ +/* + * File: Documentation/blackfin/cache-lock.txt + * Based on: + * Author: + * + * Created: + * Description: This file contains the simple DMA Implementation for Blackfin + * + * Rev: $Id: cache-lock.txt 2384 2006-11-01 04:12:43Z magicyang $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + */ + +How to lock your code in cache in uClinux/blackfin +-------------------------------------------------- + +There are only a few steps required to lock your code into the cache. +Currently you can lock the code by Way. + +Below are the interface provided for locking the cache. + + +1. cache_grab_lock(int Ways); + +This function grab the lock for locking your code into the cache specified +by Ways. + + +2. cache_lock(int Ways); + +This function should be called after your critical code has been executed. +Once the critical code exits, the code is now loaded into the cache. This +function locks the code into the cache. + + +So, the example sequence will be: + + cache_grab_lock(WAY0_L); /* Grab the lock */ + + critical_code(); /* Execute the code of interest */ + + cache_lock(WAY0_L); /* Lock the cache */ + +Where WAY0_L signifies WAY0 locking. diff --git a/trunk/Documentation/blackfin/cachefeatures.txt b/trunk/Documentation/blackfin/cachefeatures.txt index 75de51f94515..0fbec23becb5 100644 --- a/trunk/Documentation/blackfin/cachefeatures.txt +++ b/trunk/Documentation/blackfin/cachefeatures.txt @@ -41,6 +41,16 @@ icplb_flush(); dcplb_flush(); + - Locking the cache. + + cache_grab_lock(); + cache_lock(); + + Please refer linux-2.6.x/Documentation/blackfin/cache-lock.txt for how to + lock the cache. + + Locking the cache is optional feature. + - Miscellaneous cache functions. flush_cache_all(); diff --git a/trunk/Documentation/blackfin/gptimers-example.c b/trunk/Documentation/blackfin/gptimers-example.c deleted file mode 100644 index b1bd6340e748..000000000000 --- a/trunk/Documentation/blackfin/gptimers-example.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Simple gptimers example - * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:gptimers - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#include -#include - -/* ... random driver includes ... */ - -#define DRIVER_NAME "gptimer_example" - -struct gptimer_data { - uint32_t period, width; -}; -static struct gptimer_data data; - -/* ... random driver state ... */ - -static irqreturn_t gptimer_example_irq(int irq, void *dev_id) -{ - struct gptimer_data *data = dev_id; - - /* make sure it was our timer which caused the interrupt */ - if (!get_gptimer_intr(TIMER5_id)) - return IRQ_NONE; - - /* read the width/period values that were captured for the waveform */ - data->width = get_gptimer_pwidth(TIMER5_id); - data->period = get_gptimer_period(TIMER5_id); - - /* acknowledge the interrupt */ - clear_gptimer_intr(TIMER5_id); - - /* tell the upper layers we took care of things */ - return IRQ_HANDLED; -} - -/* ... random driver code ... */ - -static int __init gptimer_example_init(void) -{ - int ret; - - /* grab the peripheral pins */ - ret = peripheral_request(P_TMR5, DRIVER_NAME); - if (ret) { - printk(KERN_NOTICE DRIVER_NAME ": peripheral request failed\n"); - return ret; - } - - /* grab the IRQ for the timer */ - ret = request_irq(IRQ_TIMER5, gptimer_example_irq, IRQF_SHARED, DRIVER_NAME, &data); - if (ret) { - printk(KERN_NOTICE DRIVER_NAME ": IRQ request failed\n"); - peripheral_free(P_TMR5); - return ret; - } - - /* setup the timer and enable it */ - set_gptimer_config(TIMER5_id, WDTH_CAP | PULSE_HI | PERIOD_CNT | IRQ_ENA); - enable_gptimers(TIMER5bit); - - return 0; -} -module_init(gptimer_example_init); - -static void __exit gptimer_example_exit(void) -{ - disable_gptimers(TIMER5bit); - free_irq(IRQ_TIMER5, &data); - peripheral_free(P_TMR5); -} -module_exit(gptimer_example_exit); - -MODULE_LICENSE("BSD"); diff --git a/trunk/Documentation/dontdiff b/trunk/Documentation/dontdiff index 3ad6acead949..e151b2a36267 100644 --- a/trunk/Documentation/dontdiff +++ b/trunk/Documentation/dontdiff @@ -103,7 +103,6 @@ gconf gen-devlist gen_crc32table gen_init_cpio -generated genheaders genksyms *_gray256.c diff --git a/trunk/Documentation/fb/viafb.txt b/trunk/Documentation/fb/viafb.txt index f3e046a6a987..67dbf442b0b6 100644 --- a/trunk/Documentation/fb/viafb.txt +++ b/trunk/Documentation/fb/viafb.txt @@ -7,7 +7,7 @@ VIA UniChrome Family(CLE266, PM800 / CN400 / CN300, P4M800CE / P4M800Pro / CN700 / VN800, CX700 / VX700, K8M890, P4M890, - CN896 / P4M900, VX800, VX855) + CN896 / P4M900, VX800) [Driver features] ------------------------ @@ -154,6 +154,13 @@ 0 : No Dual Edge Panel (default) 1 : Dual Edge Panel + viafb_video_dev: + This option is used to specify video output devices(CRT, DVI, LCD) for + duoview case. + For example: + To output video on DVI, we should use: + modprobe viafb viafb_video_dev=DVI... + viafb_lcd_port: This option is used to specify LCD output port, available values are "DVP0" "DVP1" "DFP_HIGHLOW" "DFP_HIGH" "DFP_LOW". @@ -174,6 +181,9 @@ Notes: and bpp, need to call VIAFB specified ioctl interface VIAFB_SET_DEVICE instead of calling common ioctl function FBIOPUT_VSCREENINFO since viafb doesn't support multi-head well, or it will cause screen crush. + 4. VX800 2D accelerator hasn't been supported in this driver yet. When + using driver on VX800, the driver will disable the acceleration + function as default. [Configure viafb with "fbset" tool] diff --git a/trunk/Documentation/feature-removal-schedule.txt b/trunk/Documentation/feature-removal-schedule.txt index 870d190fe617..21ab9357326d 100644 --- a/trunk/Documentation/feature-removal-schedule.txt +++ b/trunk/Documentation/feature-removal-schedule.txt @@ -474,22 +474,3 @@ Why: Obsoleted by the adt7475 driver. Who: Jean Delvare --------------------------- -What: Support for lcd_switch and display_get in asus-laptop driver -When: March 2010 -Why: These two features use non-standard interfaces. There are the - only features that really need multiple path to guess what's - the right method name on a specific laptop. - - Removing them will allow to remove a lot of code an significantly - clean the drivers. - - This will affect the backlight code which won't be able to know - if the backlight is on or off. The platform display file will also be - write only (like the one in eeepc-laptop). - - This should'nt affect a lot of user because they usually know - when their display is on or off. - -Who: Corentin Chary - ----------------------------- diff --git a/trunk/Documentation/filesystems/00-INDEX b/trunk/Documentation/filesystems/00-INDEX index 875d49696b6e..7001782ab932 100644 --- a/trunk/Documentation/filesystems/00-INDEX +++ b/trunk/Documentation/filesystems/00-INDEX @@ -1,5 +1,7 @@ 00-INDEX - this file (info on some of the filesystems supported by linux). +Exporting + - explanation of how to make filesystems exportable. Locking - info on locking rules as they pertain to Linux VFS. 9p.txt @@ -66,8 +68,12 @@ mandatory-locking.txt - info on the Linux implementation of Sys V mandatory file locking. ncpfs.txt - info on Novell Netware(tm) filesystem using NCP protocol. -nfs/ - - nfs-related documentation. +nfs41-server.txt + - info on the Linux server implementation of NFSv4 minor version 1. +nfs-rdma.txt + - how to install and setup the Linux NFS/RDMA client and server software. +nfsroot.txt + - short guide on setting up a diskless box with NFS root filesystem. nilfs2.txt - info and mount options for the NILFS2 filesystem. ntfs.txt @@ -86,6 +92,8 @@ relay.txt - info on relay, for efficient streaming from kernel to user space. romfs.txt - description of the ROMFS filesystem. +rpc-cache.txt + - introduction to the caching mechanisms in the sunrpc layer. seq_file.txt - how to use the seq_file API sharedsubtree.txt diff --git a/trunk/Documentation/filesystems/nfs/Exporting b/trunk/Documentation/filesystems/Exporting similarity index 100% rename from trunk/Documentation/filesystems/nfs/Exporting rename to trunk/Documentation/filesystems/Exporting diff --git a/trunk/Documentation/filesystems/nfs/knfsd-stats.txt b/trunk/Documentation/filesystems/knfsd-stats.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/knfsd-stats.txt rename to trunk/Documentation/filesystems/knfsd-stats.txt diff --git a/trunk/Documentation/filesystems/nfs/nfs-rdma.txt b/trunk/Documentation/filesystems/nfs-rdma.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/nfs-rdma.txt rename to trunk/Documentation/filesystems/nfs-rdma.txt diff --git a/trunk/Documentation/filesystems/nfs/nfs.txt b/trunk/Documentation/filesystems/nfs.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/nfs.txt rename to trunk/Documentation/filesystems/nfs.txt diff --git a/trunk/Documentation/filesystems/nfs/00-INDEX b/trunk/Documentation/filesystems/nfs/00-INDEX deleted file mode 100644 index 2f68cd688769..000000000000 --- a/trunk/Documentation/filesystems/nfs/00-INDEX +++ /dev/null @@ -1,16 +0,0 @@ -00-INDEX - - this file (nfs-related documentation). -Exporting - - explanation of how to make filesystems exportable. -knfsd-stats.txt - - statistics which the NFS server makes available to user space. -nfs.txt - - nfs client, and DNS resolution for fs_locations. -nfs41-server.txt - - info on the Linux server implementation of NFSv4 minor version 1. -nfs-rdma.txt - - how to install and setup the Linux NFS/RDMA client and server software -nfsroot.txt - - short guide on setting up a diskless box with NFS root filesystem. -rpc-cache.txt - - introduction to the caching mechanisms in the sunrpc layer. diff --git a/trunk/Documentation/filesystems/nfs/nfs41-server.txt b/trunk/Documentation/filesystems/nfs41-server.txt similarity index 96% rename from trunk/Documentation/filesystems/nfs/nfs41-server.txt rename to trunk/Documentation/filesystems/nfs41-server.txt index 1bd0d0c05171..5920fe26e6ff 100644 --- a/trunk/Documentation/filesystems/nfs/nfs41-server.txt +++ b/trunk/Documentation/filesystems/nfs41-server.txt @@ -41,7 +41,7 @@ interoperability problems with future clients. Known issues: conformant with the spec (for example, we don't use kerberos on the backchannel correctly). - no trunking support: no clients currently take advantage of - trunking, but this is a mandatory feature, and its use is + trunking, but this is a mandatory failure, and its use is recommended to clients in a number of places. (E.g. to ensure timely renewal in case an existing connection's retry timeouts have gotten too long; see section 8.3 of the draft.) @@ -213,10 +213,3 @@ The following cases aren't supported yet: DESTROY_CLIENTID, DESTROY_SESSION, EXCHANGE_ID. * DESTROY_SESSION MUST be the final operation in the COMPOUND request. -Nonstandard compound limitations: -* No support for a sessions fore channel RPC compound that requires both a - ca_maxrequestsize request and a ca_maxresponsesize reply, so we may - fail to live up to the promise we made in CREATE_SESSION fore channel - negotiation. -* No more than one IO operation (read, write, readdir) allowed per - compound. diff --git a/trunk/Documentation/filesystems/nfs/nfsroot.txt b/trunk/Documentation/filesystems/nfsroot.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/nfsroot.txt rename to trunk/Documentation/filesystems/nfsroot.txt diff --git a/trunk/Documentation/filesystems/porting b/trunk/Documentation/filesystems/porting index a7e9746ee7ea..92b888d540a6 100644 --- a/trunk/Documentation/filesystems/porting +++ b/trunk/Documentation/filesystems/porting @@ -140,7 +140,7 @@ Callers of notify_change() need ->i_mutex now. New super_block field "struct export_operations *s_export_op" for explicit support for exporting, e.g. via NFS. The structure is fully documented at its declaration in include/linux/fs.h, and in -Documentation/filesystems/nfs/Exporting. +Documentation/filesystems/Exporting. Briefly it allows for the definition of decode_fh and encode_fh operations to encode and decode filehandles, and allows the filesystem to use diff --git a/trunk/Documentation/filesystems/nfs/rpc-cache.txt b/trunk/Documentation/filesystems/rpc-cache.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/rpc-cache.txt rename to trunk/Documentation/filesystems/rpc-cache.txt diff --git a/trunk/Documentation/filesystems/seq_file.txt b/trunk/Documentation/filesystems/seq_file.txt index a1e2e0dda907..0d15ebccf5b0 100644 --- a/trunk/Documentation/filesystems/seq_file.txt +++ b/trunk/Documentation/filesystems/seq_file.txt @@ -248,7 +248,9 @@ code, that is done in the initialization code in the usual way: { struct proc_dir_entry *entry; - proc_create("sequence", 0, NULL, &ct_file_ops); + entry = create_proc_entry("sequence", 0, NULL); + if (entry) + entry->proc_fops = &ct_file_ops; return 0; } diff --git a/trunk/Documentation/gpio.txt b/trunk/Documentation/gpio.txt index 1866c27eec69..e4e7daed2ba8 100644 --- a/trunk/Documentation/gpio.txt +++ b/trunk/Documentation/gpio.txt @@ -531,13 +531,6 @@ and have the following read/write attributes: This file exists only if the pin can be configured as an interrupt generating input pin. - "active_low" ... reads as either 0 (false) or 1 (true). Write - any nonzero value to invert the value attribute both - for reading and writing. Existing and subsequent - poll(2) support configuration via the edge attribute - for "rising" and "falling" edges will follow this - setting. - GPIO controllers have paths like /sys/class/gpio/gpiochip42/ (for the controller implementing GPIOs starting at #42) and have the following read-only attributes: @@ -573,8 +566,6 @@ requested using gpio_request(): int gpio_export_link(struct device *dev, const char *name, unsigned gpio) - /* change the polarity of a GPIO node in sysfs */ - int gpio_sysfs_set_active_low(unsigned gpio, int value); After a kernel driver requests a GPIO, it may only be made available in the sysfs interface by gpio_export(). The driver can control whether the @@ -589,9 +580,3 @@ After the GPIO has been exported, gpio_export_link() allows creating symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can use this to provide the interface under their own device in sysfs with a descriptive name. - -Drivers can use gpio_sysfs_set_active_low() to hide GPIO line polarity -differences between boards from user space. This only affects the -sysfs interface. Polarity change can be done both before and after -gpio_export(), and previously enabled poll(2) support for either -rising or falling edge will be reconfigured to follow this setting. diff --git a/trunk/Documentation/hwmon/k10temp b/trunk/Documentation/hwmon/k10temp deleted file mode 100644 index a7a18d453a51..000000000000 --- a/trunk/Documentation/hwmon/k10temp +++ /dev/null @@ -1,60 +0,0 @@ -Kernel driver k10temp -===================== - -Supported chips: -* AMD Family 10h processors: - Socket F: Quad-Core/Six-Core/Embedded Opteron - Socket AM2+: Opteron, Phenom (II) X3/X4 - Socket AM3: Quad-Core Opteron, Athlon/Phenom II X2/X3/X4, Sempron II - Socket S1G3: Athlon II, Sempron, Turion II -* AMD Family 11h processors: - Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra) - - Prefix: 'k10temp' - Addresses scanned: PCI space - Datasheets: - BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors: - http://support.amd.com/us/Processor_TechDocs/31116.pdf - BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors: - http://support.amd.com/us/Processor_TechDocs/41256.pdf - Revision Guide for AMD Family 10h Processors: - http://support.amd.com/us/Processor_TechDocs/41322.pdf - Revision Guide for AMD Family 11h Processors: - http://support.amd.com/us/Processor_TechDocs/41788.pdf - AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks: - http://support.amd.com/us/Processor_TechDocs/43373.pdf - AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet: - http://support.amd.com/us/Processor_TechDocs/43374.pdf - AMD Family 10h Desktop Processor Power and Thermal Data Sheet: - http://support.amd.com/us/Processor_TechDocs/43375.pdf - -Author: Clemens Ladisch - -Description ------------ - -This driver permits reading of the internal temperature sensor of AMD -Family 10h and 11h processors. - -All these processors have a sensor, but on older revisions of Family 10h -processors, the sensor may return inconsistent values (erratum 319). The -driver will refuse to load on these revisions unless you specify the -"force=1" module parameter. - -There is one temperature measurement value, available as temp1_input in -sysfs. It is measured in degrees Celsius with a resolution of 1/8th degree. -Please note that it is defined as a relative value; to quote the AMD manual: - - Tctl is the processor temperature control value, used by the platform to - control cooling systems. Tctl is a non-physical temperature on an - arbitrary scale measured in degrees. It does _not_ represent an actual - physical temperature like die or case temperature. Instead, it specifies - the processor temperature relative to the point at which the system must - supply the maximum cooling for the processor's specified maximum case - temperature and maximum thermal power dissipation. - -The maximum value for Tctl is available in the file temp1_max. - -If the BIOS has enabled hardware temperature control, the threshold at -which the processor will throttle itself to avoid damage is available in -temp1_crit and temp1_crit_hyst. diff --git a/trunk/Documentation/infiniband/ipoib.txt b/trunk/Documentation/infiniband/ipoib.txt index 64eeb55d0c09..6d40f00b358c 100644 --- a/trunk/Documentation/infiniband/ipoib.txt +++ b/trunk/Documentation/infiniband/ipoib.txt @@ -36,11 +36,11 @@ Datagram vs Connected modes fabric with a 2K MTU, the IPoIB MTU will be 2048 - 4 = 2044 bytes. In connected mode, the IB RC (Reliable Connected) transport is used. - Connected mode takes advantage of the connected nature of the IB - transport and allows an MTU up to the maximal IP packet size of 64K, - which reduces the number of IP packets needed for handling large UDP - datagrams, TCP segments, etc and increases the performance for large - messages. + Connected mode is to takes advantage of the connected nature of the + IB transport and allows an MTU up to the maximal IP packet size of + 64K, which reduces the number of IP packets needed for handling + large UDP datagrams, TCP segments, etc and increases the performance + for large messages. In connected mode, the interface's UD QP is still used for multicast and communication with peers that don't support connected mode. In diff --git a/trunk/Documentation/kbuild/kbuild.txt b/trunk/Documentation/kbuild/kbuild.txt index 6f8c1cabbc5d..bb3bf38f03da 100644 --- a/trunk/Documentation/kbuild/kbuild.txt +++ b/trunk/Documentation/kbuild/kbuild.txt @@ -1,17 +1,3 @@ -Output files - -modules.order --------------------------------------------------- -This file records the order in which modules appear in Makefiles. This -is used by modprobe to deterministically resolve aliases that match -multiple modules. - -modules.builtin --------------------------------------------------- -This file lists all modules that are built into the kernel. This is used -by modprobe to not fail when trying to load something builtin. - - Environment variables KCPPFLAGS diff --git a/trunk/Documentation/kbuild/kconfig.txt b/trunk/Documentation/kbuild/kconfig.txt index 49efae703979..849b5e56d06f 100644 --- a/trunk/Documentation/kbuild/kconfig.txt +++ b/trunk/Documentation/kbuild/kconfig.txt @@ -103,16 +103,10 @@ KCONFIG_AUTOCONFIG This environment variable can be set to specify the path & name of the "auto.conf" file. Its default value is "include/config/auto.conf". -KCONFIG_TRISTATE --------------------------------------------------- -This environment variable can be set to specify the path & name of the -"tristate.conf" file. Its default value is "include/config/tristate.conf". - KCONFIG_AUTOHEADER -------------------------------------------------- This environment variable can be set to specify the path & name of the -"autoconf.h" (header) file. -Its default value is "include/generated/autoconf.h". +"autoconf.h" (header) file. Its default value is "include/linux/autoconf.h". ====================================================================== diff --git a/trunk/Documentation/kernel-parameters.txt b/trunk/Documentation/kernel-parameters.txt index 5ba4d9dff113..ab95d3ada5c7 100644 --- a/trunk/Documentation/kernel-parameters.txt +++ b/trunk/Documentation/kernel-parameters.txt @@ -1032,7 +1032,7 @@ and is between 256 and 4096 characters. It is defined in the file No delay ip= [IP_PNP] - See Documentation/filesystems/nfs/nfsroot.txt. + See Documentation/filesystems/nfsroot.txt. ip2= [HW] Set IO/IRQ pairs for up to 4 IntelliPort boards See comment before ip2_setup() in @@ -1553,10 +1553,10 @@ and is between 256 and 4096 characters. It is defined in the file going to be removed in 2.6.29. nfsaddrs= [NFS] - See Documentation/filesystems/nfs/nfsroot.txt. + See Documentation/filesystems/nfsroot.txt. nfsroot= [NFS] nfs root filesystem for disk-less boxes. - See Documentation/filesystems/nfs/nfsroot.txt. + See Documentation/filesystems/nfsroot.txt. nfs.callback_tcpport= [NFS] set the TCP port on which the NFSv4 callback @@ -2729,11 +2729,6 @@ and is between 256 and 4096 characters. It is defined in the file vmpoff= [KNL,S390] Perform z/VM CP command after power off. Format: - vt.cur_default= [VT] Default cursor shape. - Format: 0xCCBBAA, where AA, BB, and CC are the same as - the parameters of the [?A;B;Cc escape sequence; - see VGA-softcursor.txt. Default: 2 = underline. - vt.default_blu= [VT] Format: ,,,..., Change the default blue palette of the console. diff --git a/trunk/Documentation/laptops/thinkpad-acpi.txt b/trunk/Documentation/laptops/thinkpad-acpi.txt index 169091f75e6d..aafcaa634191 100644 --- a/trunk/Documentation/laptops/thinkpad-acpi.txt +++ b/trunk/Documentation/laptops/thinkpad-acpi.txt @@ -1,7 +1,7 @@ ThinkPad ACPI Extras Driver - Version 0.24 - December 11th, 2009 + Version 0.23 + April 10th, 2009 Borislav Deianov Henrique de Moraes Holschuh @@ -460,8 +460,6 @@ event code Key Notes For Lenovo ThinkPads with a new BIOS, it has to be handled either by the ACPI OSI, or by userspace. - The driver does the right thing, - never mess with this. 0x1011 0x10 FN+END Brightness down. See brightness up for details. @@ -584,15 +582,46 @@ with hotkey_report_mode. Brightness hotkey notes: -Don't mess with the brightness hotkeys in a Thinkpad. If you want -notifications for OSD, use the sysfs backlight class event support. +These are the current sane choices for brightness key mapping in +thinkpad-acpi: -The driver will issue KEY_BRIGHTNESS_UP and KEY_BRIGHTNESS_DOWN events -automatically for the cases were userspace has to do something to -implement brightness changes. When you override these events, you will -either fail to handle properly the ThinkPads that require explicit -action to change backlight brightness, or the ThinkPads that require -that no action be taken to work properly. +For IBM and Lenovo models *without* ACPI backlight control (the ones on +which thinkpad-acpi will autoload its backlight interface by default, +and on which ACPI video does not export a backlight interface): + +1. Don't enable or map the brightness hotkeys in thinkpad-acpi, as + these older firmware versions unfortunately won't respect the hotkey + mask for brightness keys anyway, and always reacts to them. This + usually work fine, unless X.org drivers are doing something to block + the BIOS. In that case, use (3) below. This is the default mode of + operation. + +2. Enable the hotkeys, but map them to something else that is NOT + KEY_BRIGHTNESS_UP/DOWN or any other keycode that would cause + userspace to try to change the backlight level, and use that as an + on-screen-display hint. + +3. IF AND ONLY IF X.org drivers find a way to block the firmware from + automatically changing the brightness, enable the hotkeys and map + them to KEY_BRIGHTNESS_UP and KEY_BRIGHTNESS_DOWN, and feed that to + something that calls xbacklight. thinkpad-acpi will not be able to + change brightness in that case either, so you should disable its + backlight interface. + +For Lenovo models *with* ACPI backlight control: + +1. Load up ACPI video and use that. ACPI video will report ACPI + events for brightness change keys. Do not mess with thinkpad-acpi + defaults in this case. thinkpad-acpi should not have anything to do + with backlight events in a scenario where ACPI video is loaded: + brightness hotkeys must be disabled, and the backlight interface is + to be kept disabled as well. This is the default mode of operation. + +2. Do *NOT* load up ACPI video, enable the hotkeys in thinkpad-acpi, + and map them to KEY_BRIGHTNESS_UP and KEY_BRIGHTNESS_DOWN. Process + these keys on userspace somehow (e.g. by calling xbacklight). + The driver will do this automatically if it detects that ACPI video + has been disabled. Bluetooth @@ -1092,61 +1121,25 @@ WARNING: its level up and down at every change. -Volume control --------------- - -procfs: /proc/acpi/ibm/volume -ALSA: "ThinkPad Console Audio Control", default ID: "ThinkPadEC" - -NOTE: by default, the volume control interface operates in read-only -mode, as it is supposed to be used for on-screen-display purposes. -The read/write mode can be enabled through the use of the -"volume_control=1" module parameter. +Volume control -- /proc/acpi/ibm/volume +--------------------------------------- -NOTE: distros are urged to not enable volume_control by default, this -should be done by the local admin only. The ThinkPad UI is for the -console audio control to be done through the volume keys only, and for -the desktop environment to just provide on-screen-display feedback. -Software volume control should be done only in the main AC97/HDA -mixer. - -This feature allows volume control on ThinkPad models with a digital -volume knob (when available, not all models have it), as well as -mute/unmute control. The available commands are: +This feature allows volume control on ThinkPad models which don't have +a hardware volume knob. The available commands are: echo up >/proc/acpi/ibm/volume echo down >/proc/acpi/ibm/volume echo mute >/proc/acpi/ibm/volume - echo unmute >/proc/acpi/ibm/volume echo 'level ' >/proc/acpi/ibm/volume -The number range is 0 to 14 although not all of them may be +The number range is 0 to 15 although not all of them may be distinct. The unmute the volume after the mute command, use either the -up or down command (the level command will not unmute the volume), or -the unmute command. - +up or down command (the level command will not unmute the volume). The current volume level and mute state is shown in the file. -You can use the volume_capabilities parameter to tell the driver -whether your thinkpad has volume control or mute-only control: -volume_capabilities=1 for mixers with mute and volume control, -volume_capabilities=2 for mixers with only mute control. - -If the driver misdetects the capabilities for your ThinkPad model, -please report this to ibm-acpi-devel@lists.sourceforge.net, so that we -can update the driver. - -There are two strategies for volume control. To select which one -should be used, use the volume_mode module parameter: volume_mode=1 -selects EC mode, and volume_mode=3 selects EC mode with NVRAM backing -(so that volume/mute changes are remembered across shutdown/reboot). - -The driver will operate in volume_mode=3 by default. If that does not -work well on your ThinkPad model, please report this to -ibm-acpi-devel@lists.sourceforge.net. - -The driver supports the standard ALSA module parameters. If the ALSA -mixer is disabled, the driver will disable all volume functionality. +The ALSA mixer interface to this feature is still missing, but patches +to add it exist. That problem should be addressed in the not so +distant future. Fan control and monitoring: fan speed, fan enable/disable @@ -1412,7 +1405,6 @@ to enable more than one output class, just add their values. 0x0008 HKEY event interface, hotkeys 0x0010 Fan control 0x0020 Backlight brightness - 0x0040 Audio mixer/volume control There is also a kernel build option to enable more debugging information, which may be necessary to debug driver problems. @@ -1473,9 +1465,3 @@ Sysfs interface changelog: and it is always able to disable hot keys. Very old thinkpads are properly supported. hotkey_bios_mask is deprecated and marked for removal. - -0x020600: Marker for backlight change event support. - -0x020700: Support for mute-only mixers. - Volume control in read-only mode by default. - Marker for ALSA mixer support. diff --git a/trunk/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt b/trunk/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt deleted file mode 100644 index 515ebcf1b97d..000000000000 --- a/trunk/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt +++ /dev/null @@ -1,93 +0,0 @@ -PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator) - -Device nodes needed for operation of the ppc440spe-adma driver -are specified hereby. These are I2O/DMA, DMA and XOR nodes -for DMA engines and Memory Queue Module node. The latter is used -by ADMA driver for configuration of RAID-6 H/W capabilities of -the PPC440SPe. In addition to the nodes and properties described -below, the ranges property of PLB node must specify ranges for -DMA devices. - - i) The I2O node - - Required properties: - - - compatible : "ibm,i2o-440spe"; - - reg : - - dcr-reg : - - Example: - - I2O: i2o@400100000 { - compatible = "ibm,i2o-440spe"; - reg = <0x00000004 0x00100000 0x100>; - dcr-reg = <0x060 0x020>; - }; - - - ii) The DMA node - - Required properties: - - - compatible : "ibm,dma-440spe"; - - cell-index : 1 cell, hardware index of the DMA engine - (typically 0x0 and 0x1 for DMA0 and DMA1) - - reg : - - dcr-reg : - - interrupts : . - - interrupt-parent : needed for interrupt mapping - - Example: - - DMA0: dma0@400100100 { - compatible = "ibm,dma-440spe"; - cell-index = <0>; - reg = <0x00000004 0x00100100 0x100>; - dcr-reg = <0x060 0x020>; - interrupt-parent = <&DMA0>; - interrupts = <0 1>; - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = < - 0 &UIC0 0x14 4 - 1 &UIC1 0x16 4>; - }; - - - iii) XOR Accelerator node - - Required properties: - - - compatible : "amcc,xor-accelerator"; - - reg : - - interrupts : - - interrupt-parent : for interrupt mapping - - Example: - - xor-accel@400200000 { - compatible = "amcc,xor-accelerator"; - reg = <0x00000004 0x00200000 0x400>; - interrupt-parent = <&UIC1>; - interrupts = <0x1f 4>; - }; - - - iv) Memory Queue Module node - - Required properties: - - - compatible : "ibm,mq-440spe"; - - dcr-reg : - - Example: - - MQ0: mq { - compatible = "ibm,mq-440spe"; - dcr-reg = <0x040 0x020>; - }; - diff --git a/trunk/Documentation/powerpc/dts-bindings/nintendo/gamecube.txt b/trunk/Documentation/powerpc/dts-bindings/nintendo/gamecube.txt deleted file mode 100644 index b558585b1aaf..000000000000 --- a/trunk/Documentation/powerpc/dts-bindings/nintendo/gamecube.txt +++ /dev/null @@ -1,109 +0,0 @@ - -Nintendo GameCube device tree -============================= - -1) The "flipper" node - - This node represents the multi-function "Flipper" chip, which packages - many of the devices found in the Nintendo GameCube. - - Required properties: - - - compatible : Should be "nintendo,flipper" - -1.a) The Video Interface (VI) node - - Represents the interface between the graphics processor and a external - video encoder. - - Required properties: - - - compatible : should be "nintendo,flipper-vi" - - reg : should contain the VI registers location and length - - interrupts : should contain the VI interrupt - -1.b) The Processor Interface (PI) node - - Represents the data and control interface between the main processor - and graphics and audio processor. - - Required properties: - - - compatible : should be "nintendo,flipper-pi" - - reg : should contain the PI registers location and length - -1.b.i) The "Flipper" interrupt controller node - - Represents the interrupt controller within the "Flipper" chip. - The node for the "Flipper" interrupt controller must be placed under - the PI node. - - Required properties: - - - compatible : should be "nintendo,flipper-pic" - -1.c) The Digital Signal Procesor (DSP) node - - Represents the digital signal processor interface, designed to offload - audio related tasks. - - Required properties: - - - compatible : should be "nintendo,flipper-dsp" - - reg : should contain the DSP registers location and length - - interrupts : should contain the DSP interrupt - -1.c.i) The Auxiliary RAM (ARAM) node - - Represents the non cpu-addressable ram designed mainly to store audio - related information. - The ARAM node must be placed under the DSP node. - - Required properties: - - - compatible : should be "nintendo,flipper-aram" - - reg : should contain the ARAM start (zero-based) and length - -1.d) The Disk Interface (DI) node - - Represents the interface used to communicate with mass storage devices. - - Required properties: - - - compatible : should be "nintendo,flipper-di" - - reg : should contain the DI registers location and length - - interrupts : should contain the DI interrupt - -1.e) The Audio Interface (AI) node - - Represents the interface to the external 16-bit stereo digital-to-analog - converter. - - Required properties: - - - compatible : should be "nintendo,flipper-ai" - - reg : should contain the AI registers location and length - - interrupts : should contain the AI interrupt - -1.f) The Serial Interface (SI) node - - Represents the interface to the four single bit serial interfaces. - The SI is a proprietary serial interface used normally to control gamepads. - It's NOT a RS232-type interface. - - Required properties: - - - compatible : should be "nintendo,flipper-si" - - reg : should contain the SI registers location and length - - interrupts : should contain the SI interrupt - -1.g) The External Interface (EXI) node - - Represents the multi-channel SPI-like interface. - - Required properties: - - - compatible : should be "nintendo,flipper-exi" - - reg : should contain the EXI registers location and length - - interrupts : should contain the EXI interrupt - diff --git a/trunk/Documentation/powerpc/dts-bindings/nintendo/wii.txt b/trunk/Documentation/powerpc/dts-bindings/nintendo/wii.txt deleted file mode 100644 index a7e155a023b8..000000000000 --- a/trunk/Documentation/powerpc/dts-bindings/nintendo/wii.txt +++ /dev/null @@ -1,184 +0,0 @@ - -Nintendo Wii device tree -======================== - -0) The root node - - This node represents the Nintendo Wii video game console. - - Required properties: - - - model : Should be "nintendo,wii" - - compatible : Should be "nintendo,wii" - -1) The "hollywood" node - - This node represents the multi-function "Hollywood" chip, which packages - many of the devices found in the Nintendo Wii. - - Required properties: - - - compatible : Should be "nintendo,hollywood" - -1.a) The Video Interface (VI) node - - Represents the interface between the graphics processor and a external - video encoder. - - Required properties: - - - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi" - - reg : should contain the VI registers location and length - - interrupts : should contain the VI interrupt - -1.b) The Processor Interface (PI) node - - Represents the data and control interface between the main processor - and graphics and audio processor. - - Required properties: - - - compatible : should be "nintendo,hollywood-pi","nintendo,flipper-pi" - - reg : should contain the PI registers location and length - -1.b.i) The "Flipper" interrupt controller node - - Represents the "Flipper" interrupt controller within the "Hollywood" chip. - The node for the "Flipper" interrupt controller must be placed under - the PI node. - - Required properties: - - - #interrupt-cells : <1> - - compatible : should be "nintendo,flipper-pic" - - interrupt-controller - -1.c) The Digital Signal Procesor (DSP) node - - Represents the digital signal processor interface, designed to offload - audio related tasks. - - Required properties: - - - compatible : should be "nintendo,hollywood-dsp","nintendo,flipper-dsp" - - reg : should contain the DSP registers location and length - - interrupts : should contain the DSP interrupt - -1.d) The Serial Interface (SI) node - - Represents the interface to the four single bit serial interfaces. - The SI is a proprietary serial interface used normally to control gamepads. - It's NOT a RS232-type interface. - - Required properties: - - - compatible : should be "nintendo,hollywood-si","nintendo,flipper-si" - - reg : should contain the SI registers location and length - - interrupts : should contain the SI interrupt - -1.e) The Audio Interface (AI) node - - Represents the interface to the external 16-bit stereo digital-to-analog - converter. - - Required properties: - - - compatible : should be "nintendo,hollywood-ai","nintendo,flipper-ai" - - reg : should contain the AI registers location and length - - interrupts : should contain the AI interrupt - -1.f) The External Interface (EXI) node - - Represents the multi-channel SPI-like interface. - - Required properties: - - - compatible : should be "nintendo,hollywood-exi","nintendo,flipper-exi" - - reg : should contain the EXI registers location and length - - interrupts : should contain the EXI interrupt - -1.g) The Open Host Controller Interface (OHCI) nodes - - Represent the USB 1.x Open Host Controller Interfaces. - - Required properties: - - - compatible : should be "nintendo,hollywood-usb-ohci","usb-ohci" - - reg : should contain the OHCI registers location and length - - interrupts : should contain the OHCI interrupt - -1.h) The Enhanced Host Controller Interface (EHCI) node - - Represents the USB 2.0 Enhanced Host Controller Interface. - - Required properties: - - - compatible : should be "nintendo,hollywood-usb-ehci","usb-ehci" - - reg : should contain the EHCI registers location and length - - interrupts : should contain the EHCI interrupt - -1.i) The Secure Digital Host Controller Interface (SDHCI) nodes - - Represent the Secure Digital Host Controller Interfaces. - - Required properties: - - - compatible : should be "nintendo,hollywood-sdhci","sdhci" - - reg : should contain the SDHCI registers location and length - - interrupts : should contain the SDHCI interrupt - -1.j) The Inter-Processsor Communication (IPC) node - - Represent the Inter-Processor Communication interface. This interface - enables communications between the Broadway and the Starlet processors. - - - compatible : should be "nintendo,hollywood-ipc" - - reg : should contain the IPC registers location and length - - interrupts : should contain the IPC interrupt - -1.k) The "Hollywood" interrupt controller node - - Represents the "Hollywood" interrupt controller within the - "Hollywood" chip. - - Required properties: - - - #interrupt-cells : <1> - - compatible : should be "nintendo,hollywood-pic" - - reg : should contain the controller registers location and length - - interrupt-controller - - interrupts : should contain the cascade interrupt of the "flipper" pic - - interrupt-parent: should contain the phandle of the "flipper" pic - -1.l) The General Purpose I/O (GPIO) controller node - - Represents the dual access 32 GPIO controller interface. - - Required properties: - - - #gpio-cells : <2> - - compatible : should be "nintendo,hollywood-gpio" - - reg : should contain the IPC registers location and length - - gpio-controller - -1.m) The control node - - Represents the control interface used to setup several miscellaneous - settings of the "Hollywood" chip like boot memory mappings, resets, - disk interface mode, etc. - - Required properties: - - - compatible : should be "nintendo,hollywood-control" - - reg : should contain the control registers location and length - -1.n) The Disk Interface (DI) node - - Represents the interface used to communicate with mass storage devices. - - Required properties: - - - compatible : should be "nintendo,hollywood-di" - - reg : should contain the DI registers location and length - - interrupts : should contain the DI interrupt - diff --git a/trunk/Documentation/thermal/sysfs-api.txt b/trunk/Documentation/thermal/sysfs-api.txt index cb3d15bc1aeb..a87dc277a5ca 100644 --- a/trunk/Documentation/thermal/sysfs-api.txt +++ b/trunk/Documentation/thermal/sysfs-api.txt @@ -206,7 +206,6 @@ passive passive trip point for the zone. Activation is done by polling with an interval of 1 second. Unit: millidegrees Celsius - Valid values: 0 (disabled) or greater than 1000 RW, Optional ***************************** diff --git a/trunk/Documentation/video4linux/gspca.txt b/trunk/Documentation/video4linux/gspca.txt index 1800a62cf135..319d9838e87e 100644 --- a/trunk/Documentation/video4linux/gspca.txt +++ b/trunk/Documentation/video4linux/gspca.txt @@ -12,7 +12,6 @@ m5602 0402:5602 ALi Video Camera Controller spca501 040a:0002 Kodak DVC-325 spca500 040a:0300 Kodak EZ200 zc3xx 041e:041e Creative WebCam Live! -ov519 041e:4003 Video Blaster WebCam Go Plus spca500 041e:400a Creative PC-CAM 300 sunplus 041e:400b Creative PC-CAM 600 sunplus 041e:4012 PC-Cam350 @@ -169,14 +168,10 @@ sunplus 055f:c650 Mustek MDC5500Z zc3xx 055f:d003 Mustek WCam300A zc3xx 055f:d004 Mustek WCam300 AN conex 0572:0041 Creative Notebook cx11646 -ov519 05a9:0511 Video Blaster WebCam 3/WebCam Plus, D-Link USB Digital Video Camera -ov519 05a9:0518 Creative WebCam ov519 05a9:0519 OV519 Microphone ov519 05a9:0530 OmniVision -ov519 05a9:2800 OmniVision SuperCAM ov519 05a9:4519 Webcam Classic ov519 05a9:8519 OmniVision -ov519 05a9:a511 D-Link USB Digital Video Camera ov519 05a9:a518 D-Link DSB-C310 Webcam sunplus 05da:1018 Digital Dream Enigma 1.3 stk014 05e1:0893 Syntek DV4000 @@ -192,7 +187,7 @@ ov534 06f8:3002 Hercules Blog Webcam ov534 06f8:3003 Hercules Dualpix HD Weblog sonixj 06f8:3004 Hercules Classic Silver sonixj 06f8:3008 Hercules Deluxe Optical Glass -pac7302 06f8:3009 Hercules Classic Link +pac7311 06f8:3009 Hercules Classic Link spca508 0733:0110 ViewQuest VQ110 spca501 0733:0401 Intel Create and Share spca501 0733:0402 ViewQuest M318B @@ -204,7 +199,6 @@ sunplus 0733:2221 Mercury Digital Pro 3.1p sunplus 0733:3261 Concord 3045 spca536a sunplus 0733:3281 Cyberpix S550V spca506 0734:043b 3DeMon USB Capture aka -ov519 0813:0002 Dual Mode USB Camera Plus spca500 084d:0003 D-Link DSC-350 spca500 08ca:0103 Aiptek PocketDV sunplus 08ca:0104 Aiptek PocketDVII 1.3 @@ -242,15 +236,15 @@ pac7311 093a:2603 Philips SPC 500 NC pac7311 093a:2608 Trust WB-3300p pac7311 093a:260e Gigaware VGA PC Camera, Trust WB-3350p, SIGMA cam 2350 pac7311 093a:260f SnakeCam -pac7302 093a:2620 Apollo AC-905 -pac7302 093a:2621 PAC731x -pac7302 093a:2622 Genius Eye 312 -pac7302 093a:2624 PAC7302 -pac7302 093a:2626 Labtec 2200 -pac7302 093a:2628 Genius iLook 300 -pac7302 093a:2629 Genious iSlim 300 -pac7302 093a:262a Webcam 300k -pac7302 093a:262c Philips SPC 230 NC +pac7311 093a:2620 Apollo AC-905 +pac7311 093a:2621 PAC731x +pac7311 093a:2622 Genius Eye 312 +pac7311 093a:2624 PAC7302 +pac7311 093a:2626 Labtec 2200 +pac7311 093a:2628 Genius iLook 300 +pac7311 093a:2629 Genious iSlim 300 +pac7311 093a:262a Webcam 300k +pac7311 093a:262c Philips SPC 230 NC jeilinj 0979:0280 Sakar 57379 zc3xx 0ac8:0302 Z-star Vimicro zc0302 vc032x 0ac8:0321 Vimicro generic vc0321 @@ -265,7 +259,6 @@ vc032x 0ac8:c002 Sony embedded vimicro vc032x 0ac8:c301 Samsung Q1 Ultra Premium spca508 0af9:0010 Hama USB Sightcam 100 spca508 0af9:0011 Hama USB Sightcam 100 -ov519 0b62:0059 iBOT2 Webcam sonixb 0c45:6001 Genius VideoCAM NB sonixb 0c45:6005 Microdia Sweex Mini Webcam sonixb 0c45:6007 Sonix sn9c101 + Tas5110D @@ -325,10 +318,8 @@ sn9c20x 0c45:62b3 PC Camera (SN9C202 + OV9655) sn9c20x 0c45:62bb PC Camera (SN9C202 + OV7660) sn9c20x 0c45:62bc PC Camera (SN9C202 + HV7131R) sunplus 0d64:0303 Sunplus FashionCam DXG -ov519 0e96:c001 TRUST 380 USB2 SPACEC@M etoms 102c:6151 Qcam Sangha CIF etoms 102c:6251 Qcam xxxxxx VGA -ov519 1046:9967 W9967CF/W9968CF WebCam IC, Video Blaster WebCam Go zc3xx 10fd:0128 Typhoon Webshot II USB 300k 0x0128 spca561 10fd:7e50 FlyCam Usb 100 zc3xx 10fd:8050 Typhoon Webshot II USB 300k @@ -341,12 +332,7 @@ spca501 1776:501c Arowana 300K CMOS Camera t613 17a1:0128 TASCORP JPEG Webcam, NGS Cyclops vc032x 17ef:4802 Lenovo Vc0323+MI1310_SOC pac207 2001:f115 D-Link DSB-C120 -sq905c 2770:9050 sq905c -sq905c 2770:905c DualCamera -sq905 2770:9120 Argus Digital Camera DC1512 -sq905c 2770:913d sq905c spca500 2899:012c Toptro Industrial -ov519 8020:ef04 ov519 spca508 8086:0110 Intel Easy PC Camera spca500 8086:0630 Intel Pocket PC Camera spca506 99fa:8988 Grandtec V.cap diff --git a/trunk/Documentation/video4linux/sh_mobile_ceu_camera.txt b/trunk/Documentation/video4linux/sh_mobile_ceu_camera.txt deleted file mode 100644 index 2ae16349a78d..000000000000 --- a/trunk/Documentation/video4linux/sh_mobile_ceu_camera.txt +++ /dev/null @@ -1,157 +0,0 @@ - Cropping and Scaling algorithm, used in the sh_mobile_ceu_camera driver - ======================================================================= - -Terminology ------------ - -sensor scales: horizontal and vertical scales, configured by the sensor driver -host scales: -"- host driver -combined scales: sensor_scale * host_scale - - -Generic scaling / cropping scheme ---------------------------------- - --1-- -| --2-- -\ -| --\ -| --\ -+-5-- -\ -- -3-- -| ---\ -| --- -4-- -\ -| -\ -| - -6-- -| -| - -6'- -| -/ -| --- -4'- -/ -| ---/ -+-5'- -/ -| -- -3'- -| --/ -| --/ --2'- -/ -| -| --1'- - -Produced by user requests: - -S_CROP(left / top = (5) - (1), width / height = (5') - (5)) -S_FMT(width / height = (6') - (6)) - -Here: - -(1) to (1') - whole max width or height -(1) to (2) - sensor cropped left or top -(2) to (2') - sensor cropped width or height -(3) to (3') - sensor scale -(3) to (4) - CEU cropped left or top -(4) to (4') - CEU cropped width or height -(5) to (5') - reverse sensor scale applied to CEU cropped width or height -(2) to (5) - reverse sensor scale applied to CEU cropped left or top -(6) to (6') - CEU scale - user window - - -S_FMT ------ - -Do not touch input rectangle - it is already optimal. - -1. Calculate current sensor scales: - - scale_s = ((3') - (3)) / ((2') - (2)) - -2. Calculate "effective" input crop (sensor subwindow) - CEU crop scaled back at -current sensor scales onto input window - this is user S_CROP: - - width_u = (5') - (5) = ((4') - (4)) * scale_s - -3. Calculate new combined scales from "effective" input window to requested user -window: - - scale_comb = width_u / ((6') - (6)) - -4. Calculate sensor output window by applying combined scales to real input -window: - - width_s_out = ((2') - (2)) / scale_comb - -5. Apply iterative sensor S_FMT for sensor output window. - - subdev->video_ops->s_fmt(.width = width_s_out) - -6. Retrieve sensor output window (g_fmt) - -7. Calculate new sensor scales: - - scale_s_new = ((3')_new - (3)_new) / ((2') - (2)) - -8. Calculate new CEU crop - apply sensor scales to previously calculated -"effective" crop: - - width_ceu = (4')_new - (4)_new = width_u / scale_s_new - left_ceu = (4)_new - (3)_new = ((5) - (2)) / scale_s_new - -9. Use CEU cropping to crop to the new window: - - ceu_crop(.width = width_ceu, .left = left_ceu) - -10. Use CEU scaling to scale to the requested user window: - - scale_ceu = width_ceu / width - - -S_CROP ------- - -If old scale applied to new crop is invalid produce nearest new scale possible - -1. Calculate current combined scales. - - scale_comb = (((4') - (4)) / ((6') - (6))) * (((2') - (2)) / ((3') - (3))) - -2. Apply iterative sensor S_CROP for new input window. - -3. If old combined scales applied to new crop produce an impossible user window, -adjust scales to produce nearest possible window. - - width_u_out = ((5') - (5)) / scale_comb - - if (width_u_out > max) - scale_comb = ((5') - (5)) / max; - else if (width_u_out < min) - scale_comb = ((5') - (5)) / min; - -4. Issue G_CROP to retrieve actual input window. - -5. Using actual input window and calculated combined scales calculate sensor -target output window. - - width_s_out = ((3') - (3)) = ((2') - (2)) / scale_comb - -6. Apply iterative S_FMT for new sensor target output window. - -7. Issue G_FMT to retrieve the actual sensor output window. - -8. Calculate sensor scales. - - scale_s = ((3') - (3)) / ((2') - (2)) - -9. Calculate sensor output subwindow to be cropped on CEU by applying sensor -scales to the requested window. - - width_ceu = ((5') - (5)) / scale_s - -10. Use CEU cropping for above calculated window. - -11. Calculate CEU scales from sensor scales from results of (10) and user window -from (3) - - scale_ceu = calc_scale(((5') - (5)), &width_u_out) - -12. Apply CEU scales. - --- -Author: Guennadi Liakhovetski diff --git a/trunk/Documentation/video4linux/v4l2-framework.txt b/trunk/Documentation/video4linux/v4l2-framework.txt index 74d677c8b036..b806edaf3e75 100644 --- a/trunk/Documentation/video4linux/v4l2-framework.txt +++ b/trunk/Documentation/video4linux/v4l2-framework.txt @@ -561,8 +561,6 @@ video_device helper functions There are a few useful helper functions: -- file/video_device private data - You can set/get driver private data in the video_device struct using: void *video_get_drvdata(struct video_device *vdev); @@ -577,7 +575,8 @@ struct video_device *video_devdata(struct file *file); returns the video_device belonging to the file struct. -The video_drvdata function combines video_get_drvdata with video_devdata: +The final helper function combines video_get_drvdata with +video_devdata: void *video_drvdata(struct file *file); @@ -585,17 +584,6 @@ You can go from a video_device struct to the v4l2_device struct using: struct v4l2_device *v4l2_dev = vdev->v4l2_dev; -- Device node name - -The video_device node kernel name can be retrieved using - -const char *video_device_node_name(struct video_device *vdev); - -The name is used as a hint by userspace tools such as udev. The function -should be used where possible instead of accessing the video_device::num and -video_device::minor fields. - - video buffer helper functions ----------------------------- diff --git a/trunk/Documentation/vm/hwpoison.txt b/trunk/Documentation/vm/hwpoison.txt index 12f9ba20ccb7..3ffadf8da61f 100644 --- a/trunk/Documentation/vm/hwpoison.txt +++ b/trunk/Documentation/vm/hwpoison.txt @@ -92,62 +92,16 @@ PR_MCE_KILL_GET Testing: -madvise(MADV_HWPOISON, ....) +madvise(MADV_POISON, ....) (as root) Poison a page in the process for testing hwpoison-inject module through debugfs + /sys/debug/hwpoison/corrupt-pfn -/sys/debug/hwpoison/ +Inject hwpoison fault at PFN echoed into this file -corrupt-pfn - -Inject hwpoison fault at PFN echoed into this file. This does -some early filtering to avoid corrupted unintended pages in test suites. - -unpoison-pfn - -Software-unpoison page at PFN echoed into this file. This -way a page can be reused again. -This only works for Linux injected failures, not for real -memory failures. - -Note these injection interfaces are not stable and might change between -kernel versions - -corrupt-filter-dev-major -corrupt-filter-dev-minor - -Only handle memory failures to pages associated with the file system defined -by block device major/minor. -1U is the wildcard value. -This should be only used for testing with artificial injection. - -corrupt-filter-memcg - -Limit injection to pages owned by memgroup. Specified by inode number -of the memcg. - -Example: - mkdir /cgroup/hwpoison - - usemem -m 100 -s 1000 & - echo `jobs -p` > /cgroup/hwpoison/tasks - - memcg_ino=$(ls -id /cgroup/hwpoison | cut -f1 -d' ') - echo $memcg_ino > /debug/hwpoison/corrupt-filter-memcg - - page-types -p `pidof init` --hwpoison # shall do nothing - page-types -p `pidof usemem` --hwpoison # poison its pages - -corrupt-filter-flags-mask -corrupt-filter-flags-value - -When specified, only poison pages if ((page_flags & mask) == value). -This allows stress testing of many kinds of pages. The page_flags -are the same as in /proc/kpageflags. The flag bits are defined in -include/linux/kernel-page-flags.h and documented in -Documentation/vm/pagemap.txt Architecture specific MCE injector diff --git a/trunk/Documentation/vm/page-types.c b/trunk/Documentation/vm/page-types.c index 66e9358e2144..7a7d9bab32ef 100644 --- a/trunk/Documentation/vm/page-types.c +++ b/trunk/Documentation/vm/page-types.c @@ -1,22 +1,11 @@ /* * page-types: Tool for querying page flags * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; version 2. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should find a copy of v2 of the GNU General Public License somewhere on - * your Linux system; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place, Suite 330, Boston, MA 02111-1307 USA. - * * Copyright (C) 2009 Intel corporation * * Authors: Wu Fengguang + * + * Released under the General Public License (GPL). */ #define _LARGEFILE64_SOURCE diff --git a/trunk/Kbuild b/trunk/Kbuild index e3737ad72b5a..f056b4feee51 100644 --- a/trunk/Kbuild +++ b/trunk/Kbuild @@ -8,7 +8,7 @@ ##### # 1) Generate bounds.h -bounds-file := include/generated/bounds.h +bounds-file := include/linux/bounds.h always := $(bounds-file) targets := $(bounds-file) kernel/bounds.s @@ -43,7 +43,7 @@ $(obj)/$(bounds-file): kernel/bounds.s Kbuild # 2) Generate asm-offsets.h # -offsets-file := include/generated/asm-offsets.h +offsets-file := include/asm/asm-offsets.h always += $(offsets-file) targets += $(offsets-file) diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index efd2ef2c2660..0a32c3ec6b1c 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -2377,15 +2377,6 @@ W: http://www.kernel.org/pub/linux/kernel/people/fseidel/hdaps/ S: Maintained F: drivers/hwmon/hdaps.c -HWPOISON MEMORY FAILURE HANDLING -M: Andi Kleen -L: linux-mm@kvack.org -L: linux-kernel@vger.kernel.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/ak/linux-mce-2.6.git hwpoison -S: Maintained -F: mm/memory-failure.c -F: mm/hwpoison-inject.c - HYPERVISOR VIRTUAL CONSOLE DRIVER L: linuxppc-dev@ozlabs.org S: Odd Fixes @@ -5434,12 +5425,6 @@ F: drivers/uwb/* F: include/linux/uwb.h F: include/linux/uwb/ -UNIFDEF -M: Tony Finch -W: http://dotat.at/prog/unifdef -S: Maintained -F: scripts/unifdef.c - UNIFORM CDROM DRIVER M: Jens Axboe W: http://www.kernel.dk @@ -6006,9 +5991,9 @@ F: sound/soc/codecs/wm8350.* F: sound/soc/codecs/wm8400.* X.25 NETWORK LAYER -M: Andrew Hendry +M: Henner Eisen L: linux-x25@vger.kernel.org -S: Odd Fixes +S: Maintained F: Documentation/networking/x25* F: include/net/x25* F: net/x25/ diff --git a/trunk/Makefile b/trunk/Makefile index 8491b21b5537..33d4732a6c4a 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -334,9 +334,10 @@ CFLAGS_GCOV = -fprofile-arcs -ftest-coverage # Use LINUXINCLUDE when you must reference the include/ directory. # Needed to be compatible with the O= option -LINUXINCLUDE := -I$(srctree)/arch/$(hdr-arch)/include -Iinclude \ - $(if $(KBUILD_SRC), -I$(srctree)/include) \ - -include include/generated/autoconf.h +LINUXINCLUDE := -Iinclude \ + $(if $(KBUILD_SRC),-Iinclude2 -I$(srctree)/include) \ + -I$(srctree)/arch/$(hdr-arch)/include \ + -include include/linux/autoconf.h KBUILD_CPPFLAGS := -D__KERNEL__ @@ -464,7 +465,7 @@ ifeq ($(KBUILD_EXTMOD),) # Carefully list dependencies so we do not try to build scripts twice # in parallel PHONY += scripts -scripts: scripts_basic include/config/auto.conf include/config/tristate.conf +scripts: scripts_basic include/config/auto.conf $(Q)$(MAKE) $(build)=$(@) # Objects we will link into vmlinux / subdirs we need to visit @@ -491,18 +492,18 @@ $(KCONFIG_CONFIG) include/config/auto.conf.cmd: ; # with it and forgot to run make oldconfig. # if auto.conf.cmd is missing then we are probably in a cleaned tree so # we execute the config step to be sure to catch updated Kconfig files -include/config/%.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd +include/config/auto.conf: $(KCONFIG_CONFIG) include/config/auto.conf.cmd $(Q)$(MAKE) -f $(srctree)/Makefile silentoldconfig else -# external modules needs include/generated/autoconf.h and include/config/auto.conf +# external modules needs include/linux/autoconf.h and include/config/auto.conf # but do not care if they are up-to-date. Use auto.conf to trigger the test PHONY += include/config/auto.conf include/config/auto.conf: - $(Q)test -e include/generated/autoconf.h -a -e $@ || ( \ + $(Q)test -e include/linux/autoconf.h -a -e $@ || ( \ echo; \ echo " ERROR: Kernel configuration is invalid."; \ - echo " include/generated/autoconf.h or $@ are missing.";\ + echo " include/linux/autoconf.h or $@ are missing."; \ echo " Run 'make oldconfig && make prepare' on kernel src to fix it."; \ echo; \ /bin/false) @@ -876,9 +877,6 @@ $(sort $(vmlinux-init) $(vmlinux-main)) $(vmlinux-lds): $(vmlinux-dirs) ; PHONY += $(vmlinux-dirs) $(vmlinux-dirs): prepare scripts $(Q)$(MAKE) $(build)=$@ -ifdef CONFIG_MODULES - $(Q)$(MAKE) $(modbuiltin)=$@ -endif # Build the kernel release string # @@ -957,6 +955,7 @@ PHONY += prepare archprepare prepare0 prepare1 prepare2 prepare3 # prepare3 is used to check if we are building in a separate output directory, # and if so do: # 1) Check that make has not been executed in the kernel src $(srctree) +# 2) Create the include2 directory, used for the second asm symlink prepare3: include/config/kernel.release ifneq ($(KBUILD_SRC),) @$(kecho) ' Using $(srctree) as source for kernel' @@ -965,13 +964,17 @@ ifneq ($(KBUILD_SRC),) echo " in the '$(srctree)' directory.";\ /bin/false; \ fi; + $(Q)if [ ! -d include2 ]; then \ + mkdir -p include2; \ + ln -fsn $(srctree)/include/asm-$(SRCARCH) include2/asm; \ + fi endif # prepare2 creates a makefile if using a separate output directory prepare2: prepare3 outputmakefile -prepare1: prepare2 include/linux/version.h include/generated/utsrelease.h \ - include/config/auto.conf +prepare1: prepare2 include/linux/version.h include/linux/utsrelease.h \ + include/asm include/config/auto.conf $(cmd_crmodverdir) archprepare: prepare1 scripts_basic @@ -983,6 +986,42 @@ prepare0: archprepare FORCE # All the preparing.. prepare: prepare0 +# The asm symlink changes when $(ARCH) changes. +# Detect this and ask user to run make mrproper +# If asm is a stale symlink (point to dir that does not exist) remove it +define check-symlink + set -e; \ + if [ -L include/asm ]; then \ + asmlink=`readlink include/asm | cut -d '-' -f 2`; \ + if [ "$$asmlink" != "$(SRCARCH)" ]; then \ + echo "ERROR: the symlink $@ points to asm-$$asmlink but asm-$(SRCARCH) was expected"; \ + echo " set ARCH or save .config and run 'make mrproper' to fix it"; \ + exit 1; \ + fi; \ + test -e $$asmlink || rm include/asm; \ + elif [ -d include/asm ]; then \ + echo "ERROR: $@ is a directory but a symlink was expected";\ + exit 1; \ + fi +endef + +# We create the target directory of the symlink if it does +# not exist so the test in check-symlink works and we have a +# directory for generated filesas used by some architectures. +define create-symlink + if [ ! -L include/asm ]; then \ + $(kecho) ' SYMLINK $@ -> include/asm-$(SRCARCH)'; \ + if [ ! -d include/asm-$(SRCARCH) ]; then \ + mkdir -p include/asm-$(SRCARCH); \ + fi; \ + ln -fsn asm-$(SRCARCH) $@; \ + fi +endef + +include/asm: FORCE + $(Q)$(check-symlink) + $(Q)$(create-symlink) + # Generate some files # --------------------------------------------------------------------------- @@ -1007,7 +1046,7 @@ endef include/linux/version.h: $(srctree)/Makefile FORCE $(call filechk,version.h) -include/generated/utsrelease.h: include/config/kernel.release FORCE +include/linux/utsrelease.h: include/config/kernel.release FORCE $(call filechk,utsrelease.h) PHONY += headerdep @@ -1037,6 +1076,11 @@ firmware_install: FORCE export INSTALL_HDR_PATH = $(objtree)/usr hdr-inst := -rR -f $(srctree)/scripts/Makefile.headersinst obj +# Find out where the Kbuild file is located to support +# arch/$(ARCH)/include/asm +hdr-dir = $(strip \ + $(if $(wildcard $(srctree)/arch/$(hdr-arch)/include/asm/Kbuild), \ + arch/$(hdr-arch)/include/asm, include/asm-$(hdr-arch))) # If we do an all arch process set dst to asm-$(hdr-arch) hdr-dst = $(if $(KBUILD_HEADERS), dst=include/asm-$(hdr-arch), dst=include/asm) @@ -1051,10 +1095,10 @@ headers_install_all: PHONY += headers_install headers_install: __headers - $(if $(wildcard $(srctree)/arch/$(hdr-arch)/include/asm/Kbuild),, \ + $(if $(wildcard $(srctree)/$(hdr-dir)/Kbuild),, \ $(error Headers not exportable for the $(SRCARCH) architecture)) $(Q)$(MAKE) $(hdr-inst)=include - $(Q)$(MAKE) $(hdr-inst)=arch/$(hdr-arch)/include/asm $(hdr-dst) + $(Q)$(MAKE) $(hdr-inst)=$(hdr-dir) $(hdr-dst) PHONY += headers_check_all headers_check_all: headers_install_all @@ -1063,7 +1107,7 @@ headers_check_all: headers_install_all PHONY += headers_check headers_check: headers_install $(Q)$(MAKE) $(hdr-inst)=include HDRCHECK=1 - $(Q)$(MAKE) $(hdr-inst)=arch/$(hdr-arch)/include/asm $(hdr-dst) HDRCHECK=1 + $(Q)$(MAKE) $(hdr-inst)=$(hdr-dir) $(hdr-dst) HDRCHECK=1 # --------------------------------------------------------------------------- # Modules @@ -1083,7 +1127,6 @@ all: modules PHONY += modules modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) $(Q)$(AWK) '!x[$$0]++' $(vmlinux-dirs:%=$(objtree)/%/modules.order) > $(objtree)/modules.order - $(Q)$(AWK) '!x[$$0]++' $(vmlinux-dirs:%=$(objtree)/%/modules.builtin) > $(objtree)/modules.builtin @$(kecho) ' Building modules, stage 2.'; $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.fwinst obj=firmware __fw_modbuild @@ -1113,7 +1156,6 @@ _modinst_: ln -s $(objtree) $(MODLIB)/build ; \ fi @cp -f $(objtree)/modules.order $(MODLIB)/ - @cp -f $(objtree)/modules.builtin $(MODLIB)/ $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modinst # This depmod is only for convenience to give the initial @@ -1152,10 +1194,12 @@ CLEAN_FILES += vmlinux System.map \ .tmp_kallsyms* .tmp_version .tmp_vmlinux* .tmp_System.map # Directories & files removed with 'make mrproper' -MRPROPER_DIRS += include/config usr/include include/generated -MRPROPER_FILES += .config .config.old .version .old_version \ - include/linux/version.h \ - Module.symvers tags TAGS cscope* +MRPROPER_DIRS += include/config include2 usr/include include/generated +MRPROPER_FILES += .config .config.old include/asm .version .old_version \ + include/linux/autoconf.h include/linux/version.h \ + include/linux/utsrelease.h \ + include/linux/bounds.h include/asm*/asm-offsets.h \ + Module.symvers Module.markers tags TAGS cscope* # clean - Delete most, but leave enough to build external modules # @@ -1174,7 +1218,7 @@ clean: archclean $(clean-dirs) \( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ -o -name '*.symtypes' -o -name 'modules.order' \ - -o -name modules.builtin -o -name '.tmp_*.o.*' \ + -o -name 'Module.markers' -o -name '.tmp_*.o.*' \ -o -name '*.gcno' \) -type f -print | xargs rm -f # mrproper - Delete all generated files, including .config @@ -1372,8 +1416,8 @@ $(clean-dirs): clean: rm-dirs := $(MODVERDIR) clean: rm-files := $(KBUILD_EXTMOD)/Module.symvers \ - $(KBUILD_EXTMOD)/modules.order \ - $(KBUILD_EXTMOD)/modules.builtin + $(KBUILD_EXTMOD)/Module.markers \ + $(KBUILD_EXTMOD)/modules.order clean: $(clean-dirs) $(call cmd,rmdirs) $(call cmd,rmfiles) diff --git a/trunk/arch/alpha/boot/bootp.c b/trunk/arch/alpha/boot/bootp.c index 3c8d1b25c661..3af21c789339 100644 --- a/trunk/arch/alpha/boot/bootp.c +++ b/trunk/arch/alpha/boot/bootp.c @@ -9,7 +9,7 @@ */ #include #include -#include +#include #include #include diff --git a/trunk/arch/alpha/boot/bootpz.c b/trunk/arch/alpha/boot/bootpz.c index ade3f129dc27..1036b515e20c 100644 --- a/trunk/arch/alpha/boot/bootpz.c +++ b/trunk/arch/alpha/boot/bootpz.c @@ -11,7 +11,7 @@ */ #include #include -#include +#include #include #include diff --git a/trunk/arch/alpha/boot/main.c b/trunk/arch/alpha/boot/main.c index 644b7db55438..89f3be071ae5 100644 --- a/trunk/arch/alpha/boot/main.c +++ b/trunk/arch/alpha/boot/main.c @@ -7,7 +7,7 @@ */ #include #include -#include +#include #include #include diff --git a/trunk/arch/alpha/include/asm/asm-offsets.h b/trunk/arch/alpha/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/alpha/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/alpha/include/asm/elf.h b/trunk/arch/alpha/include/asm/elf.h index 9baae8afe8a3..5c75c1b2352a 100644 --- a/trunk/arch/alpha/include/asm/elf.h +++ b/trunk/arch/alpha/include/asm/elf.h @@ -81,6 +81,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_ALPHA +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 8192 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/alpha/include/asm/fcntl.h b/trunk/arch/alpha/include/asm/fcntl.h index 70145cbb21cb..21b1117a0c61 100644 --- a/trunk/arch/alpha/include/asm/fcntl.h +++ b/trunk/arch/alpha/include/asm/fcntl.h @@ -16,7 +16,7 @@ #define O_NOATIME 04000000 #define O_CLOEXEC 010000000 /* set close_on_exec */ /* - * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using + * Before Linux 2.6.32 only O_DSYNC semantics were implemented, but using * the O_SYNC flag. We continue to use the existing numerical value * for O_DSYNC semantics now, but using the correct symbolic name for it. * This new value is used to request true Posix O_SYNC semantics. It is diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index e9da08483b3c..fa0cdab2e1d3 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -242,8 +242,15 @@ all: $(KBUILD_IMAGE) boot := arch/arm/boot -archprepare: - $(Q)$(MAKE) $(build)=arch/arm/tools include/generated/mach-types.h +# Update machine arch and proc symlinks if something which affects +# them changed. We use .arch to indicate when they were updated +# last, otherwise make uses the target directory mtime. + +archprepare: maketools + +PHONY += maketools FORCE +maketools: include/linux/version.h FORCE + $(Q)$(MAKE) $(build)=arch/arm/tools include/asm-arm/mach-types.h # Convert bzImage to zImage bzImage: zImage @@ -254,6 +261,9 @@ zImage Image xipImage bootpImage uImage: vmlinux zinstall install: vmlinux $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@ +CLEAN_FILES += include/asm-arm/mach-types.h \ + include/asm-arm/arch include/asm-arm/.arch + # We use MRPROPER_FILES and CLEAN_FILES now archclean: $(Q)$(MAKE) $(clean)=$(boot) diff --git a/trunk/arch/arm/common/dmabounce.c b/trunk/arch/arm/common/dmabounce.c index bc90364a96c7..5a375e5fef21 100644 --- a/trunk/arch/arm/common/dmabounce.c +++ b/trunk/arch/arm/common/dmabounce.c @@ -308,11 +308,15 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr, memcpy(ptr, buf->safe, size); /* - * Since we may have written to a page cache page, - * we need to ensure that the data will be coherent - * with user mappings. + * DMA buffers must have the same cache properties + * as if they were really used for DMA - which means + * data must be written back to RAM. Note that + * we don't use dmac_flush_range() here for the + * bidirectional case because we know the cache + * lines will be coherent with the data written. */ - __cpuc_flush_kernel_dcache_area(ptr, size); + dmac_clean_range(ptr, ptr + size); + outer_clean_range(__pa(ptr), __pa(ptr) + size); } free_safe_buffer(dev->archdata.dmabounce, buf); } diff --git a/trunk/arch/arm/include/asm/asm-offsets.h b/trunk/arch/arm/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/arm/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/arm/include/asm/cacheflush.h b/trunk/arch/arm/include/asm/cacheflush.h index 730aefcfbee3..73eceb87e588 100644 --- a/trunk/arch/arm/include/asm/cacheflush.h +++ b/trunk/arch/arm/include/asm/cacheflush.h @@ -211,7 +211,7 @@ struct cpu_cache_fns { void (*coherent_kern_range)(unsigned long, unsigned long); void (*coherent_user_range)(unsigned long, unsigned long); - void (*flush_kern_dcache_area)(void *, size_t); + void (*flush_kern_dcache_page)(void *); void (*dma_inv_range)(const void *, const void *); void (*dma_clean_range)(const void *, const void *); @@ -236,7 +236,7 @@ extern struct cpu_cache_fns cpu_cache; #define __cpuc_flush_user_range cpu_cache.flush_user_range #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range #define __cpuc_coherent_user_range cpu_cache.coherent_user_range -#define __cpuc_flush_dcache_area cpu_cache.flush_kern_dcache_area +#define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page /* * These are private to the dma-mapping API. Do not use directly. @@ -255,14 +255,14 @@ extern struct cpu_cache_fns cpu_cache; #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) -#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) +#define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page) extern void __cpuc_flush_kern_all(void); extern void __cpuc_flush_user_all(void); extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); extern void __cpuc_coherent_user_range(unsigned long, unsigned long); -extern void __cpuc_flush_dcache_area(void *, size_t); +extern void __cpuc_flush_dcache_page(void *); /* * These are private to the dma-mapping API. Do not use directly. @@ -448,7 +448,7 @@ static inline void flush_kernel_dcache_page(struct page *page) { /* highmem pages are always flushed upon kunmap already */ if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page)) - __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); + __cpuc_flush_dcache_page(page_address(page)); } #define flush_dcache_mmap_lock(mapping) \ @@ -465,6 +465,13 @@ static inline void flush_kernel_dcache_page(struct page *page) */ #define flush_icache_page(vma,page) do { } while (0) +static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, + unsigned offset, size_t size) +{ + const void *start = (void __force *)virt + offset; + dmac_inv_range(start, start + size); +} + /* * flush_cache_vmap() is used when creating mappings (eg, via vmap, * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT diff --git a/trunk/arch/arm/include/asm/elf.h b/trunk/arch/arm/include/asm/elf.h index a399bb5730f1..6aac3f5bb2f3 100644 --- a/trunk/arch/arm/include/asm/elf.h +++ b/trunk/arch/arm/include/asm/elf.h @@ -101,6 +101,7 @@ extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define ELF_CORE_COPY_TASK_REGS dump_task_regs +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/arm/include/asm/mach-types.h b/trunk/arch/arm/include/asm/mach-types.h deleted file mode 100644 index 948178cc6ba8..000000000000 --- a/trunk/arch/arm/include/asm/mach-types.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/arm/kernel/armksyms.c b/trunk/arch/arm/kernel/armksyms.c index 8214bfebfaca..0e627705f746 100644 --- a/trunk/arch/arm/kernel/armksyms.c +++ b/trunk/arch/arm/kernel/armksyms.c @@ -48,7 +48,27 @@ extern void __aeabi_uidivmod(void); extern void __aeabi_ulcmp(void); extern void fpundefinstr(void); +extern void fp_enter(void); +/* + * This has a special calling convention; it doesn't + * modify any of the usual registers, except for LR. + */ +#define EXPORT_CRC_ALIAS(sym) __CRC_SYMBOL(sym, "") + +#define EXPORT_SYMBOL_ALIAS(sym,orig) \ + EXPORT_CRC_ALIAS(sym) \ + static const struct kernel_symbol __ksymtab_##sym \ + __used __attribute__((section("__ksymtab"))) = \ + { (unsigned long)&orig, #sym }; + +/* + * floating point math emulator support. + * These symbols will never change their calling convention... + */ +EXPORT_SYMBOL_ALIAS(kern_fp_enter,fp_enter); +EXPORT_SYMBOL_ALIAS(fp_printk,printk); +EXPORT_SYMBOL_ALIAS(fp_send_sig,send_sig); EXPORT_SYMBOL(__backtrace); diff --git a/trunk/arch/arm/kernel/vmlinux.lds.S b/trunk/arch/arm/kernel/vmlinux.lds.S index 4957e13ef55b..71151bd87a36 100644 --- a/trunk/arch/arm/kernel/vmlinux.lds.S +++ b/trunk/arch/arm/kernel/vmlinux.lds.S @@ -65,11 +65,11 @@ SECTIONS __init_end = .; #endif - /* - * unwind exit sections must be discarded before the rest of the - * unwind sections get included. - */ - /DISCARD/ : { + /DISCARD/ : { /* Exit code and data */ + EXIT_TEXT + EXIT_DATA + *(.exitcall.exit) + *(.discard) *(.ARM.exidx.exit.text) *(.ARM.extab.exit.text) #ifndef CONFIG_HOTPLUG_CPU @@ -238,9 +238,6 @@ SECTIONS STABS_DEBUG .comment 0 : { *(.comment) } - - /* Default discards */ - DISCARDS } /* diff --git a/trunk/arch/arm/mach-bcmring/arch.c b/trunk/arch/arm/mach-bcmring/arch.c index 53dd2a9eecf9..fbe6fa02c882 100644 --- a/trunk/arch/arm/mach-bcmring/arch.c +++ b/trunk/arch/arm/mach-bcmring/arch.c @@ -70,19 +70,9 @@ static struct ctl_table bcmring_sysctl_reboot[] = { {} }; -static struct resource nand_resource[] = { - [0] = { - .start = MM_ADDR_IO_NAND, - .end = MM_ADDR_IO_NAND + 0x1000 - 1, - .flags = IORESOURCE_MEM, - }, -}; - static struct platform_device nand_device = { .name = "bcm-nand", .id = -1, - .resource = nand_resource, - .num_resources = ARRAY_SIZE(nand_resource), }; static struct platform_device *devices[] __initdata = { diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h deleted file mode 100644 index 387376ffb56b..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************** -* Copyright 2001 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* -* -***************************************************************************** -* -* REG_NAND.h -* -* PURPOSE: -* -* This file contains definitions for the nand registers: -* -* NOTES: -* -*****************************************************************************/ - -#if !defined(__ASM_ARCH_REG_NAND_H) -#define __ASM_ARCH_REG_NAND_H - -/* ---- Include Files ---------------------------------------------------- */ -#include -#include - -/* ---- Constants and Types ---------------------------------------------- */ - -#define HW_NAND_BASE MM_IO_BASE_NAND /* NAND Flash */ - -/* DMA accesses by the bootstrap need hard nonvirtual addresses */ -#define REG_NAND_CMD __REG16(HW_NAND_BASE + 0) -#define REG_NAND_ADDR __REG16(HW_NAND_BASE + 4) - -#define REG_NAND_PHYS_DATA16 (HW_NAND_BASE + 8) -#define REG_NAND_PHYS_DATA8 (HW_NAND_BASE + 8) -#define REG_NAND_DATA16 __REG16(REG_NAND_PHYS_DATA16) -#define REG_NAND_DATA8 __REG8(REG_NAND_PHYS_DATA8) - -/* use appropriate offset to make sure it start at the 1K boundary */ -#define REG_NAND_PHYS_DATA_DMA (HW_NAND_BASE + 0x400) -#define REG_NAND_DATA_DMA __REG32(REG_NAND_PHYS_DATA_DMA) - -/* Linux DMA requires physical address of the data register */ -#define REG_NAND_DATA16_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16) -#define REG_NAND_DATA8_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8) -#define REG_NAND_DATA_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA) - -#define NAND_BUS_16BIT() (0) -#define NAND_BUS_8BIT() (!NAND_BUS_16BIT()) - -/* Register offsets */ -#define REG_NAND_CMD_OFFSET (0) -#define REG_NAND_ADDR_OFFSET (4) -#define REG_NAND_DATA8_OFFSET (8) - -#endif diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h deleted file mode 100644 index 06a355481ea6..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ /dev/null @@ -1,237 +0,0 @@ -/***************************************************************************** -* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* -* -***************************************************************************** -* -* REG_UMI.h -* -* PURPOSE: -* -* This file contains definitions for the nand registers: -* -* NOTES: -* -*****************************************************************************/ - -#if !defined(__ASM_ARCH_REG_UMI_H) -#define __ASM_ARCH_REG_UMI_H - -/* ---- Include Files ---------------------------------------------------- */ -#include -#include - -/* ---- Constants and Types ---------------------------------------------- */ - -/* Unified Memory Interface Ctrl Register */ -#define HW_UMI_BASE MM_IO_BASE_UMI - -/* Flash bank 0 timing and control register */ -#define REG_UMI_FLASH0_TCR __REG32(HW_UMI_BASE + 0x00) -/* Flash bank 1 timing and control register */ -#define REG_UMI_FLASH1_TCR __REG32(HW_UMI_BASE + 0x04) -/* Flash bank 2 timing and control register */ -#define REG_UMI_FLASH2_TCR __REG32(HW_UMI_BASE + 0x08) -/* MMD interface and control register */ -#define REG_UMI_MMD_ICR __REG32(HW_UMI_BASE + 0x0c) -/* NAND timing and control register */ -#define REG_UMI_NAND_TCR __REG32(HW_UMI_BASE + 0x18) -/* NAND ready/chip select register */ -#define REG_UMI_NAND_RCSR __REG32(HW_UMI_BASE + 0x1c) -/* NAND ECC control & status register */ -#define REG_UMI_NAND_ECC_CSR __REG32(HW_UMI_BASE + 0x20) -/* NAND ECC data register XXB2B1B0 */ -#define REG_UMI_NAND_ECC_DATA __REG32(HW_UMI_BASE + 0x24) -/* BCH ECC Parameter N */ -#define REG_UMI_BCH_N __REG32(HW_UMI_BASE + 0x40) -/* BCH ECC Parameter T */ -#define REG_UMI_BCH_K __REG32(HW_UMI_BASE + 0x44) -/* BCH ECC Parameter K */ -#define REG_UMI_BCH_T __REG32(HW_UMI_BASE + 0x48) -/* BCH ECC Contro Status */ -#define REG_UMI_BCH_CTRL_STATUS __REG32(HW_UMI_BASE + 0x4C) -/* BCH WR ECC 31:0 */ -#define REG_UMI_BCH_WR_ECC_0 __REG32(HW_UMI_BASE + 0x50) -/* BCH WR ECC 63:32 */ -#define REG_UMI_BCH_WR_ECC_1 __REG32(HW_UMI_BASE + 0x54) -/* BCH WR ECC 95:64 */ -#define REG_UMI_BCH_WR_ECC_2 __REG32(HW_UMI_BASE + 0x58) -/* BCH WR ECC 127:96 */ -#define REG_UMI_BCH_WR_ECC_3 __REG32(HW_UMI_BASE + 0x5c) -/* BCH WR ECC 155:128 */ -#define REG_UMI_BCH_WR_ECC_4 __REG32(HW_UMI_BASE + 0x60) -/* BCH Read Error Location 1,0 */ -#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE + 0x64) -/* BCH Read Error Location 3,2 */ -#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE + 0x68) -/* BCH Read Error Location 5,4 */ -#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE + 0x6c) -/* BCH Read Error Location 7,6 */ -#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE + 0x70) -/* BCH Read Error Location 9,8 */ -#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE + 0x74) -/* BCH Read Error Location 11,10 */ -#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE + 0x78) - -/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */ -/* Enable wait pin during burst write or read */ -#define REG_UMI_TCR_WAITEN 0x80000000 -/* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */ -#define REG_UMI_TCR_LOWFREQ 0x40000000 -/* 1=synch write, 0=async write */ -#define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000 -/* 1=synch read, 0=async read */ -#define REG_UMI_TCR_MEMTYPE_SYNCREAD 0x10000000 -/* 1=page mode read, 0=normal mode read */ -#define REG_UMI_TCR_MEMTYPE_PAGEREAD 0x08000000 -/* page size/burst size (wrap only) */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK 0x07000000 -/* 4 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_4 0x00000000 -/* 8 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_8 0x01000000 -/* 16 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_16 0x02000000 -/* 32 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_32 0x03000000 -/* 64 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_64 0x04000000 -/* 128 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_128 0x05000000 -/* 256 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_256 0x06000000 -/* 512 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_512 0x07000000 -/* Page read access cycle / Burst write latency (n+2 / n+1) */ -#define REG_UMI_TCR_TPRC_TWLC_MASK 0x00f80000 -/* Bus turnaround cycle (n) */ -#define REG_UMI_TCR_TBTA_MASK 0x00070000 -/* Write pulse width cycle (n+1) */ -#define REG_UMI_TCR_TWP_MASK 0x0000f800 -/* Write recovery cycle (n+1) */ -#define REG_UMI_TCR_TWR_MASK 0x00000600 -/* Write address setup cycle (n+1) */ -#define REG_UMI_TCR_TAS_MASK 0x00000180 -/* Output enable delay cycle (n) */ -#define REG_UMI_TCR_TOE_MASK 0x00000060 -/* Read access cycle / Burst read latency (n+2 / n+1) */ -#define REG_UMI_TCR_TRC_TLC_MASK 0x0000001f - -/* REG_UMI_MMD_ICR bits */ -/* Flash write protection pin control */ -#define REG_UMI_MMD_ICR_FLASH_WP 0x8000 -/* Extend hold time for sram0, sram1 csn (39 MHz operation) */ -#define REG_UMI_MMD_ICR_XHCS 0x4000 -/* Enable SDRAM 2 interface control */ -#define REG_UMI_MMD_ICR_SDRAM2EN 0x2000 -/* Enable merge of flash banks 0/1 to 512 MBit bank */ -#define REG_UMI_MMD_ICR_INST512 0x1000 -/* Enable merge of flash banks 1/2 to 512 MBit bank */ -#define REG_UMI_MMD_ICR_DATA512 0x0800 -/* Enable SDRAM interface control */ -#define REG_UMI_MMD_ICR_SDRAMEN 0x0400 -/* Polarity of busy state of Burst Wait Signal */ -#define REG_UMI_MMD_ICR_WAITPOL 0x0200 -/* Enable burst clock stopped when not accessing external burst flash/sram */ -#define REG_UMI_MMD_ICR_BCLKSTOP 0x0100 -/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */ -#define REG_UMI_MMD_ICR_PERI1EN 0x0080 -/* Enable the peri2_csn to replace sdram_csn */ -#define REG_UMI_MMD_ICR_PERI2EN 0x0040 -/* Enable the peri3_csn to replace sdram2_csn */ -#define REG_UMI_MMD_ICR_PERI3EN 0x0020 -/* Enable sram bank1 for H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSB1 0x0010 -/* Enable sram bank0 for H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSB0 0x0008 -/* Polarity for assert3ed state of H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSPOL 0x0004 -/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */ -/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */ -#define REG_UMI_MMD_ICR_MRSMODE 0x0002 -/* MRS state for S/W controlled mode */ -#define REG_UMI_MMD_ICR_MRSSTATE 0x0001 - -/* REG_UMI_NAND_TCR bits */ -/* Enable software to control CS */ -#define REG_UMI_NAND_TCR_CS_SWCTRL 0x80000000 -/* 16-bit nand wordsize if set */ -#define REG_UMI_NAND_TCR_WORD16 0x40000000 -/* Bus turnaround cycle (n) */ -#define REG_UMI_NAND_TCR_TBTA_MASK 0x00070000 -/* Write pulse width cycle (n+1) */ -#define REG_UMI_NAND_TCR_TWP_MASK 0x0000f800 -/* Write recovery cycle (n+1) */ -#define REG_UMI_NAND_TCR_TWR_MASK 0x00000600 -/* Write address setup cycle (n+1) */ -#define REG_UMI_NAND_TCR_TAS_MASK 0x00000180 -/* Output enable delay cycle (n) */ -#define REG_UMI_NAND_TCR_TOE_MASK 0x00000060 -/* Read access cycle (n+2) */ -#define REG_UMI_NAND_TCR_TRC_TLC_MASK 0x0000001f - -/* REG_UMI_NAND_RCSR bits */ -/* Status: Ready=1, Busy=0 */ -#define REG_UMI_NAND_RCSR_RDY 0x02 -/* Keep CS asserted during operation */ -#define REG_UMI_NAND_RCSR_CS_ASSERTED 0x01 - -/* REG_UMI_NAND_ECC_CSR bits */ -/* Interrupt status - read-only */ -#define REG_UMI_NAND_ECC_CSR_NANDINT 0x80000000 -/* Read: Status of ECC done, Write: clear ECC interrupt */ -#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW 0x00800000 -/* Read: Status of R/B, Write: clear R/B interrupt */ -#define REG_UMI_NAND_ECC_CSR_RBINT_RAW 0x00400000 -/* 1 = Enable ECC Interrupt */ -#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE 0x00008000 -/* 1 = Assert interrupt at rising edge of R/B_ */ -#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE 0x00004000 -/* Calculate ECC by 0=512 bytes, 1=256 bytes */ -#define REG_UMI_NAND_ECC_CSR_256BYTE 0x00000080 -/* Enable ECC in hardware */ -#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE 0x00000001 - -/* REG_UMI_BCH_CTRL_STATUS bits */ -/* Shift to Indicate Number of correctable errors detected */ -#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20 -/* Indicate Number of correctable errors detected */ -#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000 -/* Indicate Errors detected during read but uncorrectable */ -#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR 0x00080000 -/* Indicate Errors detected during read and are correctable */ -#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR 0x00040000 -/* Flag indicates BCH's ECC status of read process are valid */ -#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID 0x00020000 -/* Flag indicates BCH's ECC status of write process are valid */ -#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID 0x00010000 -/* Pause ECC calculation */ -#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010 -/* Enable Interrupt */ -#define REG_UMI_BCH_CTRL_STATUS_INT_EN 0x00000004 -/* Enable ECC during read */ -#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN 0x00000002 -/* Enable ECC during write */ -#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN 0x00000001 -/* Mask for location */ -#define REG_UMI_BCH_ERR_LOC_MASK 0x00001FFF -/* location within a byte */ -#define REG_UMI_BCH_ERR_LOC_BYTE 0x00000007 -/* location within a word */ -#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 -/* location within a page (512 byte) */ -#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 -#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) -#endif diff --git a/trunk/arch/arm/mach-davinci/board-da850-evm.c b/trunk/arch/arm/mach-davinci/board-da850-evm.c index 07de8db14581..62b98bffc158 100644 --- a/trunk/arch/arm/mach-davinci/board-da850-evm.c +++ b/trunk/arch/arm/mach-davinci/board-da850-evm.c @@ -339,15 +339,6 @@ static struct davinci_mmc_config da850_mmc_config = { .version = MMC_CTLR_VERSION_2, }; -static void da850_panel_power_ctrl(int val) -{ - /* lcd backlight */ - gpio_set_value(DA850_LCD_BL_PIN, val); - - /* lcd power */ - gpio_set_value(DA850_LCD_PWR_PIN, val); -} - static int da850_lcd_hw_init(void) { int status; @@ -365,11 +356,17 @@ static int da850_lcd_hw_init(void) gpio_direction_output(DA850_LCD_BL_PIN, 0); gpio_direction_output(DA850_LCD_PWR_PIN, 0); - /* Switch off panel power and backlight */ - da850_panel_power_ctrl(0); + /* disable lcd backlight */ + gpio_set_value(DA850_LCD_BL_PIN, 0); + + /* disable lcd power */ + gpio_set_value(DA850_LCD_PWR_PIN, 0); + + /* enable lcd power */ + gpio_set_value(DA850_LCD_PWR_PIN, 1); - /* Switch on panel power and backlight */ - da850_panel_power_ctrl(1); + /* enable lcd backlight */ + gpio_set_value(DA850_LCD_BL_PIN, 1); return 0; } @@ -677,7 +674,6 @@ static __init void da850_evm_init(void) pr_warning("da850_evm_init: lcd initialization failed: %d\n", ret); - sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl, ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata); if (ret) pr_warning("da850_evm_init: lcdc registration failed: %d\n", diff --git a/trunk/arch/arm/mach-davinci/include/mach/nand.h b/trunk/arch/arm/mach-davinci/include/mach/nand.h index b2ad8090bd10..b520c4b5678a 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/nand.h +++ b/trunk/arch/arm/mach-davinci/include/mach/nand.h @@ -79,10 +79,6 @@ struct davinci_nand_pdata { /* platform_data */ /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ unsigned options; - - /* Main and mirror bbt descriptor overrides */ - struct nand_bbt_descr *bbt_td; - struct nand_bbt_descr *bbt_md; }; #endif /* __ARCH_ARM_DAVINCI_NAND_H */ diff --git a/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h b/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h index 62d17421e48c..83f31cd0a274 100644 --- a/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h +++ b/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h @@ -5,6 +5,9 @@ #ifndef __ASM_ARCH_EP93XX_KEYPAD_H #define __ASM_ARCH_EP93XX_KEYPAD_H +#define MAX_MATRIX_KEY_ROWS (8) +#define MAX_MATRIX_KEY_COLS (8) + /* flags for the ep93xx_keypad driver */ #define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */ #define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */ @@ -15,6 +18,8 @@ /** * struct ep93xx_keypad_platform_data - platform specific device structure + * @matrix_key_rows: number of rows in the keypad matrix + * @matrix_key_cols: number of columns in the keypad matrix * @matrix_key_map: array of keycodes defining the keypad matrix * @matrix_key_map_size: ARRAY_SIZE(matrix_key_map) * @debounce: debounce start count; terminal count is 0xff @@ -22,6 +27,8 @@ * @flags: see above */ struct ep93xx_keypad_platform_data { + unsigned int matrix_key_rows; + unsigned int matrix_key_cols; unsigned int *matrix_key_map; int matrix_key_map_size; unsigned int debounce; @@ -29,7 +36,7 @@ struct ep93xx_keypad_platform_data { unsigned int flags; }; -#define EP93XX_MATRIX_ROWS (8) -#define EP93XX_MATRIX_COLS (8) +/* macro for creating the matrix_key_map table */ +#define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) #endif /* __ASM_ARCH_EP93XX_KEYPAD_H */ diff --git a/trunk/arch/arm/mach-kirkwood/Kconfig b/trunk/arch/arm/mach-kirkwood/Kconfig index f6c6196a51fa..8bf09ae5b347 100644 --- a/trunk/arch/arm/mach-kirkwood/Kconfig +++ b/trunk/arch/arm/mach-kirkwood/Kconfig @@ -52,12 +52,6 @@ config MACH_OPENRD_BASE Say 'Y' here if you want your kernel to support the Marvell OpenRD Base Board. -config MACH_NETSPACE_V2 - bool "LaCie Network Space v2 NAS Board" - help - Say 'Y' here if you want your kernel to support the - LaCie Network Space v2 NAS. - endmenu endif diff --git a/trunk/arch/arm/mach-kirkwood/Makefile b/trunk/arch/arm/mach-kirkwood/Makefile index d4d7f53b0fb9..9f2f67b2b63d 100644 --- a/trunk/arch/arm/mach-kirkwood/Makefile +++ b/trunk/arch/arm/mach-kirkwood/Makefile @@ -8,6 +8,5 @@ obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o -obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c b/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c deleted file mode 100644 index 9a064065bebe..000000000000 --- a/trunk/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * arch/arm/mach-kirkwood/netspace_v2-setup.c - * - * LaCie Network Space v2 board setup - * - * Copyright (C) 2009 Simon Guinot - * Copyright (C) 2009 Benoît Canet - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" - -/***************************************************************************** - * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005) - ****************************************************************************/ - -static struct mtd_partition netspace_v2_flash_parts[] = { - { - .name = "u-boot", - .size = MTDPART_SIZ_FULL, - .offset = 0, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, -}; - -static const struct flash_platform_data netspace_v2_flash = { - .type = "mx25l4005a", - .name = "spi_flash", - .parts = netspace_v2_flash_parts, - .nr_parts = ARRAY_SIZE(netspace_v2_flash_parts), -}; - -static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &netspace_v2_flash, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data netspace_v2_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * I2C devices - ****************************************************************************/ - -static struct at24_platform_data at24c04 = { - .byte_len = SZ_4K / 8, - .page_size = 16, -}; - -/* - * i2c addr | chip | description - * 0x50 | HT24LC04 | eeprom (512B) - */ - -static struct i2c_board_info __initdata netspace_v2_i2c_info[] = { - { - I2C_BOARD_INFO("24c04", 0x50), - .platform_data = &at24c04, - } -}; - -/***************************************************************************** - * SATA - ****************************************************************************/ - -static struct mv_sata_platform_data netspace_v2_sata_data = { - .n_ports = 2, -}; - -#define NETSPACE_V2_GPIO_SATA0_POWER 16 -#define NETSPACE_V2_GPIO_SATA1_POWER 17 - -static void __init netspace_v2_sata_power_init(void) -{ - int err; - - err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power"); - if (err == 0) { - err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1); - if (err) - gpio_free(NETSPACE_V2_GPIO_SATA0_POWER); - } - if (err) - pr_err("netspace_v2: failed to setup SATA0 power\n"); -} - -/***************************************************************************** - * GPIO keys - ****************************************************************************/ - -#define NETSPACE_V2_PUSH_BUTTON 32 - -static struct gpio_keys_button netspace_v2_buttons[] = { - [0] = { - .code = KEY_POWER, - .gpio = NETSPACE_V2_PUSH_BUTTON, - .desc = "Power push button", - .active_low = 0, - }, -}; - -static struct gpio_keys_platform_data netspace_v2_button_data = { - .buttons = netspace_v2_buttons, - .nbuttons = ARRAY_SIZE(netspace_v2_buttons), -}; - -static struct platform_device netspace_v2_gpio_buttons = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &netspace_v2_button_data, - }, -}; - -/***************************************************************************** - * GPIO LEDs - ****************************************************************************/ - -/* - * The blue front LED is wired to a CPLD and can blink in relation with the - * SATA activity. - * - * The following array detail the different LED registers and the combination - * of their possible values: - * - * cmd_led | slow_led | /SATA active | LED state - * | | | - * 1 | 0 | x | off - * - | 1 | x | on - * 0 | 0 | 1 | on - * 0 | 0 | 0 | blink (rate 300ms) - */ - -#define NETSPACE_V2_GPIO_RED_LED 12 -#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29 -#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30 - - -static struct gpio_led netspace_v2_gpio_led_pins[] = { - { - .name = "ns_v2:red:fail", - .gpio = NETSPACE_V2_GPIO_RED_LED, - }, -}; - -static struct gpio_led_platform_data netspace_v2_gpio_leds_data = { - .num_leds = ARRAY_SIZE(netspace_v2_gpio_led_pins), - .leds = netspace_v2_gpio_led_pins, -}; - -static struct platform_device netspace_v2_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &netspace_v2_gpio_leds_data, - }, -}; - -static void __init netspace_v2_gpio_leds_init(void) -{ - platform_device_register(&netspace_v2_gpio_leds); - - /* - * Configure the front blue LED to blink in relation with the SATA - * activity. - */ - if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, - "SATA blue LED slow") != 0) - return; - if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0) != 0) - goto err_free_1; - if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_CMD, - "SATA blue LED command") != 0) - goto err_free_1; - if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_CMD, 0) != 0) - goto err_free_2; - - return; - -err_free_2: - gpio_free(NETSPACE_V2_GPIO_BLUE_LED_CMD); -err_free_1: - gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW); - pr_err("netspace_v2: failed to configure SATA blue LED\n"); -} - -/***************************************************************************** - * Timer - ****************************************************************************/ - -static void netspace_v2_timer_init(void) -{ - kirkwood_tclk = 166666667; - orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); -} - -struct sys_timer netspace_v2_timer = { - .init = netspace_v2_timer_init, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -static unsigned int netspace_v2_mpp_config[] __initdata = { - MPP0_SPI_SCn, - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP8_TW_SDA, - MPP9_TW_SCK, - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, /* Red led */ - MPP14_GPIO, /* USB fuse */ - MPP16_GPIO, /* SATA 0 power */ - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_SATA1_ACTn, - MPP21_SATA0_ACTn, - MPP24_GPIO, /* USB mode select */ - MPP25_GPIO, /* Fan rotation fail */ - MPP26_GPIO, /* USB device vbus */ - MPP28_GPIO, /* USB enable host vbus */ - MPP29_GPIO, /* Blue led (slow register) */ - MPP30_GPIO, /* Blue led (command register) */ - MPP31_GPIO, /* Board power off */ - MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */ - 0 -}; - -#define NETSPACE_V2_GPIO_POWER_OFF 31 - -static void netspace_v2_power_off(void) -{ - gpio_set_value(NETSPACE_V2_GPIO_POWER_OFF, 1); -} - -static void __init netspace_v2_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(netspace_v2_mpp_config); - - netspace_v2_sata_power_init(); - - kirkwood_ehci_init(); - kirkwood_ge00_init(&netspace_v2_ge00_data); - kirkwood_sata_init(&netspace_v2_sata_data); - kirkwood_uart0_init(); - spi_register_board_info(netspace_v2_spi_slave_info, - ARRAY_SIZE(netspace_v2_spi_slave_info)); - kirkwood_spi_init(); - kirkwood_i2c_init(); - i2c_register_board_info(0, netspace_v2_i2c_info, - ARRAY_SIZE(netspace_v2_i2c_info)); - - netspace_v2_gpio_leds_init(); - platform_device_register(&netspace_v2_gpio_buttons); - - if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 && - gpio_direction_output(NETSPACE_V2_GPIO_POWER_OFF, 0) == 0) - pm_power_off = netspace_v2_power_off; - else - pr_err("netspace_v2: failed to configure power-off GPIO\n"); -} - -MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = netspace_v2_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &netspace_v2_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-nomadik/board-nhk8815.c b/trunk/arch/arm/mach-nomadik/board-nhk8815.c index 9438bf6613a3..116394484e71 100644 --- a/trunk/arch/arm/mach-nomadik/board-nhk8815.c +++ b/trunk/arch/arm/mach-nomadik/board-nhk8815.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -150,7 +149,7 @@ static struct mtd_partition nhk8815_onenand_partitions[] = { } }; -static struct onenand_platform_data nhk8815_onenand_data = { +static struct flash_platform_data nhk8815_onenand_data = { .parts = nhk8815_onenand_partitions, .nr_parts = ARRAY_SIZE(nhk8815_onenand_partitions), }; @@ -164,7 +163,7 @@ static struct resource nhk8815_onenand_resource[] = { }; static struct platform_device nhk8815_onenand_device = { - .name = "onenand-flash", + .name = "onenand", .id = -1, .dev = { .platform_data = &nhk8815_onenand_data, @@ -175,10 +174,10 @@ static struct platform_device nhk8815_onenand_device = { static void __init nhk8815_onenand_init(void) { -#ifdef CONFIG_MTD_ONENAND +#ifdef CONFIG_ONENAND /* Set up SMCS0 for OneNand */ - writel(0x000030db, FSMC_BCR(0)); - writel(0x02100551, FSMC_BTR(0)); + writel(0x000030db, FSMC_BCR0); + writel(0x02100551, FSMC_BTR0); #endif } diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index 76c11ee113e9..10eafa70a909 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -18,6 +18,7 @@ config ARCH_OMAP2430 config ARCH_OMAP34XX bool "OMAP34xx Based System" depends on ARCH_OMAP3 + select USB_ARCH_HAS_EHCI config ARCH_OMAP3430 bool "OMAP3430 support" diff --git a/trunk/arch/arm/mach-pxa/Kconfig b/trunk/arch/arm/mach-pxa/Kconfig index 8a0837ea0294..e6d8e10ae5d1 100644 --- a/trunk/arch/arm/mach-pxa/Kconfig +++ b/trunk/arch/arm/mach-pxa/Kconfig @@ -110,8 +110,6 @@ config MACH_CM_X300 bool "CompuLab CM-X300 modules" select PXA3xx select CPU_PXA300 - select CPU_PXA310 - select HAVE_PWM config ARCH_GUMSTIX bool "Gumstix XScale 255 boards" @@ -242,6 +240,7 @@ config MACH_COLIBRI300 select PXA3xx select CPU_PXA300 select CPU_PXA310 + select HAVE_PWM config MACH_COLIBRI320 bool "Toradex Colibri PXA320" diff --git a/trunk/arch/arm/mach-pxa/devices.c b/trunk/arch/arm/mach-pxa/devices.c index 8e10db148f1b..3395463bb5a6 100644 --- a/trunk/arch/arm/mach-pxa/devices.c +++ b/trunk/arch/arm/mach-pxa/devices.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -13,7 +14,6 @@ #include #include #include -#include #include #include diff --git a/trunk/arch/arm/mach-s3c2410/include/mach/spi.h b/trunk/arch/arm/mach-s3c2410/include/mach/spi.h index 4d9588373aa5..193b39d654ed 100644 --- a/trunk/arch/arm/mach-s3c2410/include/mach/spi.h +++ b/trunk/arch/arm/mach-s3c2410/include/mach/spi.h @@ -18,8 +18,6 @@ struct s3c2410_spi_info { unsigned int num_cs; /* total chipselects */ int bus_num; /* bus number to use. */ - unsigned int use_fiq:1; /* use fiq */ - void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable); void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); }; diff --git a/trunk/arch/arm/mach-u300/include/mach/coh901318.h b/trunk/arch/arm/mach-u300/include/mach/coh901318.h deleted file mode 100644 index f4cfee9c7d28..000000000000 --- a/trunk/arch/arm/mach-u300/include/mach/coh901318.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * - * include/linux/coh901318.h - * - * - * Copyright (C) 2007-2009 ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - * DMA driver for COH 901 318 - * Author: Per Friden - */ - -#ifndef COH901318_H -#define COH901318_H - -#include -#include - -#define MAX_DMA_PACKET_SIZE_SHIFT 11 -#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT) - -/** - * struct coh901318_lli - linked list item for DMAC - * @control: control settings for DMAC - * @src_addr: transfer source address - * @dst_addr: transfer destination address - * @link_addr: physical address to next lli - * @virt_link_addr: virtual addres of next lli (only used by pool_free) - * @phy_this: physical address of current lli (only used by pool_free) - */ -struct coh901318_lli { - u32 control; - dma_addr_t src_addr; - dma_addr_t dst_addr; - dma_addr_t link_addr; - - void *virt_link_addr; - dma_addr_t phy_this; -}; -/** - * struct coh901318_params - parameters for DMAC configuration - * @config: DMA config register - * @ctrl_lli_last: DMA control register for the last lli in the list - * @ctrl_lli: DMA control register for an lli - * @ctrl_lli_chained: DMA control register for a chained lli - */ -struct coh901318_params { - u32 config; - u32 ctrl_lli_last; - u32 ctrl_lli; - u32 ctrl_lli_chained; -}; -/** - * struct coh_dma_channel - dma channel base - * @name: ascii name of dma channel - * @number: channel id number - * @desc_nbr_max: number of preallocated descriptortors - * @priority_high: prio of channel, 0 low otherwise high. - * @param: configuration parameters - * @dev_addr: physical address of periphal connected to channel - */ -struct coh_dma_channel { - const char name[32]; - const int number; - const int desc_nbr_max; - const int priority_high; - const struct coh901318_params param; - const dma_addr_t dev_addr; -}; - -/** - * dma_access_memory_state_t - register dma for memory access - * - * @dev: The dma device - * @active: 1 means dma intends to access memory - * 0 means dma wont access memory - */ -typedef void (*dma_access_memory_state_t)(struct device *dev, - bool active); - -/** - * struct powersave - DMA power save structure - * @lock: lock protecting data in this struct - * @started_channels: bit mask indicating active dma channels - */ -struct powersave { - spinlock_t lock; - u64 started_channels; -}; -/** - * struct coh901318_platform - platform arch structure - * @chans_slave: specifying dma slave channels - * @chans_memcpy: specifying dma memcpy channels - * @access_memory_state: requesting DMA memeory access (on / off) - * @chan_conf: dma channel configurations - * @max_channels: max number of dma chanenls - */ -struct coh901318_platform { - const int *chans_slave; - const int *chans_memcpy; - const dma_access_memory_state_t access_memory_state; - const struct coh_dma_channel *chan_conf; - const int max_channels; -}; - -/** - * coh901318_get_bytes_left() - Get number of bytes left on a current transfer - * @chan: dma channel handle - * return number of bytes left, or negative on error - */ -u32 coh901318_get_bytes_left(struct dma_chan *chan); - -/** - * coh901318_stop() - Stops dma transfer - * @chan: dma channel handle - * return 0 on success otherwise negative value - */ -void coh901318_stop(struct dma_chan *chan); - -/** - * coh901318_continue() - Resumes a stopped dma transfer - * @chan: dma channel handle - * return 0 on success otherwise negative value - */ -void coh901318_continue(struct dma_chan *chan); - -/** - * coh901318_filter_id() - DMA channel filter function - * @chan: dma channel handle - * @chan_id: id of dma channel to be filter out - * - * In dma_request_channel() it specifies what channel id to be requested - */ -bool coh901318_filter_id(struct dma_chan *chan, void *chan_id); - -/* - * DMA Controller - this access the static mappings of the coh901318 dma. - * - */ - -#define COH901318_MOD32_MASK (0x1F) -#define COH901318_WORD_MASK (0xFFFFFFFF) -/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */ -#define COH901318_INT_STATUS1 (0x0000) -#define COH901318_INT_STATUS2 (0x0004) -/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */ -#define COH901318_TC_INT_STATUS1 (0x0008) -#define COH901318_TC_INT_STATUS2 (0x000C) -/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */ -#define COH901318_TC_INT_CLEAR1 (0x0010) -#define COH901318_TC_INT_CLEAR2 (0x0014) -/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ -#define COH901318_RAW_TC_INT_STATUS1 (0x0018) -#define COH901318_RAW_TC_INT_STATUS2 (0x001C) -/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */ -#define COH901318_BE_INT_STATUS1 (0x0020) -#define COH901318_BE_INT_STATUS2 (0x0024) -/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */ -#define COH901318_BE_INT_CLEAR1 (0x0028) -#define COH901318_BE_INT_CLEAR2 (0x002C) -/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ -#define COH901318_RAW_BE_INT_STATUS1 (0x0030) -#define COH901318_RAW_BE_INT_STATUS2 (0x0034) - -/* - * CX_CFG - Channel Configuration Registers 32bit (R/W) - */ -#define COH901318_CX_CFG (0x0100) -#define COH901318_CX_CFG_SPACING (0x04) -/* Channel enable activates tha dma job */ -#define COH901318_CX_CFG_CH_ENABLE (0x00000001) -#define COH901318_CX_CFG_CH_DISABLE (0x00000000) -/* Request Mode */ -#define COH901318_CX_CFG_RM_MASK (0x00000006) -#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1) -#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1) -#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1) -#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1) -#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1) -/* Linked channel request field. RM must == 11 */ -#define COH901318_CX_CFG_LCRF_SHIFT 3 -#define COH901318_CX_CFG_LCRF_MASK (0x000001F8) -#define COH901318_CX_CFG_LCR_DISABLE (0x00000000) -/* Terminal Counter Interrupt Request Mask */ -#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200) -#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000) -/* Bus Error interrupt Mask */ -#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400) -#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000) - -/* - * CX_STAT - Channel Status Registers 32bit (R/-) - */ -#define COH901318_CX_STAT (0x0200) -#define COH901318_CX_STAT_SPACING (0x04) -#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008) -#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004) -#define COH901318_CX_STAT_ACTIVE (0x00000002) -#define COH901318_CX_STAT_ENABLED (0x00000001) - -/* - * CX_CTRL - Channel Control Registers 32bit (R/W) - */ -#define COH901318_CX_CTRL (0x0400) -#define COH901318_CX_CTRL_SPACING (0x10) -/* Transfer Count Enable */ -#define COH901318_CX_CTRL_TC_ENABLE (0x00001000) -#define COH901318_CX_CTRL_TC_DISABLE (0x00000000) -/* Transfer Count Value 0 - 4095 */ -#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF) -/* Burst count */ -#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000) -#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13) -/* Source bus size */ -#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000) -#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16) -#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16) -#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16) -/* Source address increment */ -#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000) -#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000) -/* Destination Bus Size */ -#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000) -#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19) -#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19) -#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19) -/* Destination address increment */ -#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000) -#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000) -/* Master Mode (Master2 is only connected to MSL) */ -#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000) -#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22) -#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22) -#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22) -#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22) -/* Terminal Count flag to PER enable */ -#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000) -#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000) -/* Terminal Count flags to CPU enable */ -#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000) -#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000) -/* Hand shake to peripheral */ -#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000) -#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000) -#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000) -#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000) -/* DMA mode */ -#define COH901318_CX_CTRL_DDMA_MASK (0x30000000) -#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28) -#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28) -#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28) -/* Primary Request Data Destination */ -#define COH901318_CX_CTRL_PRDD_MASK (0x40000000) -#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30) -#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30) - -/* - * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W) - */ -#define COH901318_CX_SRC_ADDR (0x0404) -#define COH901318_CX_SRC_ADDR_SPACING (0x10) - -/* - * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W - */ -#define COH901318_CX_DST_ADDR (0x0408) -#define COH901318_CX_DST_ADDR_SPACING (0x10) - -/* - * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W) - */ -#define COH901318_CX_LNK_ADDR (0x040C) -#define COH901318_CX_LNK_ADDR_SPACING (0x10) -#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001) -#endif /* COH901318_H */ diff --git a/trunk/arch/arm/mm/cache-fa.S b/trunk/arch/arm/mm/cache-fa.S index a89444a3c016..b63a8f7b95cf 100644 --- a/trunk/arch/arm/mm/cache-fa.S +++ b/trunk/arch/arm/mm/cache-fa.S @@ -127,16 +127,15 @@ ENTRY(fa_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(kaddr) * * Ensure that the data held in the page kaddr is written back * to the page in question. * - * - addr - kernel address - * - size - size of region + * - kaddr - kernel address (guaranteed to be page aligned) */ -ENTRY(fa_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(fa_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -214,7 +213,7 @@ ENTRY(fa_cache_fns) .long fa_flush_user_cache_range .long fa_coherent_kern_range .long fa_coherent_user_range - .long fa_flush_kern_dcache_area + .long fa_flush_kern_dcache_page .long fa_dma_inv_range .long fa_dma_clean_range .long fa_dma_flush_range diff --git a/trunk/arch/arm/mm/cache-l2x0.c b/trunk/arch/arm/mm/cache-l2x0.c index cb8fc6573b1b..747f9a9021bb 100644 --- a/trunk/arch/arm/mm/cache-l2x0.c +++ b/trunk/arch/arm/mm/cache-l2x0.c @@ -28,120 +28,69 @@ static void __iomem *l2x0_base; static DEFINE_SPINLOCK(l2x0_lock); -static inline void cache_wait(void __iomem *reg, unsigned long mask) +static inline void sync_writel(unsigned long val, unsigned long reg, + unsigned long complete_mask) { + unsigned long flags; + + spin_lock_irqsave(&l2x0_lock, flags); + writel(val, l2x0_base + reg); /* wait for the operation to complete */ - while (readl(reg) & mask) + while (readl(l2x0_base + reg) & complete_mask) ; + spin_unlock_irqrestore(&l2x0_lock, flags); } static inline void cache_sync(void) { - void __iomem *base = l2x0_base; - writel(0, base + L2X0_CACHE_SYNC); - cache_wait(base + L2X0_CACHE_SYNC, 1); + sync_writel(0, L2X0_CACHE_SYNC, 1); } static inline void l2x0_inv_all(void) { - unsigned long flags; - /* invalidate all ways */ - spin_lock_irqsave(&l2x0_lock, flags); - writel(0xff, l2x0_base + L2X0_INV_WAY); - cache_wait(l2x0_base + L2X0_INV_WAY, 0xff); + sync_writel(0xff, L2X0_INV_WAY, 0xff); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_inv_range(unsigned long start, unsigned long end) { - void __iomem *base = l2x0_base; - unsigned long flags; + unsigned long addr; - spin_lock_irqsave(&l2x0_lock, flags); if (start & (CACHE_LINE_SIZE - 1)) { start &= ~(CACHE_LINE_SIZE - 1); - cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); - writel(start, base + L2X0_CLEAN_INV_LINE_PA); + sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1); start += CACHE_LINE_SIZE; } if (end & (CACHE_LINE_SIZE - 1)) { end &= ~(CACHE_LINE_SIZE - 1); - cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); - writel(end, base + L2X0_CLEAN_INV_LINE_PA); + sync_writel(end, L2X0_CLEAN_INV_LINE_PA, 1); } - while (start < end) { - unsigned long blk_end = start + min(end - start, 4096UL); - - while (start < blk_end) { - cache_wait(base + L2X0_INV_LINE_PA, 1); - writel(start, base + L2X0_INV_LINE_PA); - start += CACHE_LINE_SIZE; - } - - if (blk_end < end) { - spin_unlock_irqrestore(&l2x0_lock, flags); - spin_lock_irqsave(&l2x0_lock, flags); - } - } - cache_wait(base + L2X0_INV_LINE_PA, 1); + for (addr = start; addr < end; addr += CACHE_LINE_SIZE) + sync_writel(addr, L2X0_INV_LINE_PA, 1); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_clean_range(unsigned long start, unsigned long end) { - void __iomem *base = l2x0_base; - unsigned long flags; + unsigned long addr; - spin_lock_irqsave(&l2x0_lock, flags); start &= ~(CACHE_LINE_SIZE - 1); - while (start < end) { - unsigned long blk_end = start + min(end - start, 4096UL); - - while (start < blk_end) { - cache_wait(base + L2X0_CLEAN_LINE_PA, 1); - writel(start, base + L2X0_CLEAN_LINE_PA); - start += CACHE_LINE_SIZE; - } - - if (blk_end < end) { - spin_unlock_irqrestore(&l2x0_lock, flags); - spin_lock_irqsave(&l2x0_lock, flags); - } - } - cache_wait(base + L2X0_CLEAN_LINE_PA, 1); + for (addr = start; addr < end; addr += CACHE_LINE_SIZE) + sync_writel(addr, L2X0_CLEAN_LINE_PA, 1); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); } static void l2x0_flush_range(unsigned long start, unsigned long end) { - void __iomem *base = l2x0_base; - unsigned long flags; + unsigned long addr; - spin_lock_irqsave(&l2x0_lock, flags); start &= ~(CACHE_LINE_SIZE - 1); - while (start < end) { - unsigned long blk_end = start + min(end - start, 4096UL); - - while (start < blk_end) { - cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); - writel(start, base + L2X0_CLEAN_INV_LINE_PA); - start += CACHE_LINE_SIZE; - } - - if (blk_end < end) { - spin_unlock_irqrestore(&l2x0_lock, flags); - spin_lock_irqsave(&l2x0_lock, flags); - } - } - cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1); + for (addr = start; addr < end; addr += CACHE_LINE_SIZE) + sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1); cache_sync(); - spin_unlock_irqrestore(&l2x0_lock, flags); } void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) diff --git a/trunk/arch/arm/mm/cache-v3.S b/trunk/arch/arm/mm/cache-v3.S index 2a482731ea36..8a4abebc478a 100644 --- a/trunk/arch/arm/mm/cache-v3.S +++ b/trunk/arch/arm/mm/cache-v3.S @@ -72,15 +72,14 @@ ENTRY(v3_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *page, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(v3_flush_kern_dcache_area) +ENTRY(v3_flush_kern_dcache_page) /* FALLTHROUGH */ /* @@ -130,7 +129,7 @@ ENTRY(v3_cache_fns) .long v3_flush_user_cache_range .long v3_coherent_kern_range .long v3_coherent_user_range - .long v3_flush_kern_dcache_area + .long v3_flush_kern_dcache_page .long v3_dma_inv_range .long v3_dma_clean_range .long v3_dma_flush_range diff --git a/trunk/arch/arm/mm/cache-v4.S b/trunk/arch/arm/mm/cache-v4.S index 5c7da3e372e9..3668611cb400 100644 --- a/trunk/arch/arm/mm/cache-v4.S +++ b/trunk/arch/arm/mm/cache-v4.S @@ -82,15 +82,14 @@ ENTRY(v4_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(v4_flush_kern_dcache_area) +ENTRY(v4_flush_kern_dcache_page) /* FALLTHROUGH */ /* @@ -142,7 +141,7 @@ ENTRY(v4_cache_fns) .long v4_flush_user_cache_range .long v4_coherent_kern_range .long v4_coherent_user_range - .long v4_flush_kern_dcache_area + .long v4_flush_kern_dcache_page .long v4_dma_inv_range .long v4_dma_clean_range .long v4_dma_flush_range diff --git a/trunk/arch/arm/mm/cache-v4wb.S b/trunk/arch/arm/mm/cache-v4wb.S index 3dbedf1ec0e7..2ebc1b3bf856 100644 --- a/trunk/arch/arm/mm/cache-v4wb.S +++ b/trunk/arch/arm/mm/cache-v4wb.S @@ -114,16 +114,15 @@ ENTRY(v4wb_flush_user_cache_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(v4wb_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(v4wb_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ /* fall through */ /* @@ -225,7 +224,7 @@ ENTRY(v4wb_cache_fns) .long v4wb_flush_user_cache_range .long v4wb_coherent_kern_range .long v4wb_coherent_user_range - .long v4wb_flush_kern_dcache_area + .long v4wb_flush_kern_dcache_page .long v4wb_dma_inv_range .long v4wb_dma_clean_range .long v4wb_dma_flush_range diff --git a/trunk/arch/arm/mm/cache-v4wt.S b/trunk/arch/arm/mm/cache-v4wt.S index b3b7410270b4..c54fa2cc40e6 100644 --- a/trunk/arch/arm/mm/cache-v4wt.S +++ b/trunk/arch/arm/mm/cache-v4wt.S @@ -117,18 +117,17 @@ ENTRY(v4wt_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(v4wt_flush_kern_dcache_area) +ENTRY(v4wt_flush_kern_dcache_page) mov r2, #0 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache - add r1, r0, r1 + add r1, r0, #PAGE_SZ /* fallthrough */ /* @@ -181,7 +180,7 @@ ENTRY(v4wt_cache_fns) .long v4wt_flush_user_cache_range .long v4wt_coherent_kern_range .long v4wt_coherent_user_range - .long v4wt_flush_kern_dcache_area + .long v4wt_flush_kern_dcache_page .long v4wt_dma_inv_range .long v4wt_dma_clean_range .long v4wt_dma_flush_range diff --git a/trunk/arch/arm/mm/cache-v6.S b/trunk/arch/arm/mm/cache-v6.S index 4ba0a24ce6f5..295e25dd6381 100644 --- a/trunk/arch/arm/mm/cache-v6.S +++ b/trunk/arch/arm/mm/cache-v6.S @@ -159,16 +159,15 @@ ENDPROC(v6_coherent_user_range) ENDPROC(v6_coherent_kern_range) /* - * v6_flush_kern_dcache_area(void *addr, size_t size) + * v6_flush_kern_dcache_page(kaddr) * * Ensure that the data held in the page kaddr is written back * to the page in question. * - * - addr - kernel address - * - size - region size + * - kaddr - kernel address (guaranteed to be page aligned) */ -ENTRY(v6_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(v6_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: #ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line @@ -272,7 +271,7 @@ ENTRY(v6_cache_fns) .long v6_flush_user_cache_range .long v6_coherent_kern_range .long v6_coherent_user_range - .long v6_flush_kern_dcache_area + .long v6_flush_kern_dcache_page .long v6_dma_inv_range .long v6_dma_clean_range .long v6_dma_flush_range diff --git a/trunk/arch/arm/mm/cache-v7.S b/trunk/arch/arm/mm/cache-v7.S index 9073db849fb4..e1bd9759617f 100644 --- a/trunk/arch/arm/mm/cache-v7.S +++ b/trunk/arch/arm/mm/cache-v7.S @@ -186,17 +186,16 @@ ENDPROC(v7_coherent_kern_range) ENDPROC(v7_coherent_user_range) /* - * v7_flush_kern_dcache_area(void *addr, size_t size) + * v7_flush_kern_dcache_page(kaddr) * * Ensure that the data held in the page kaddr is written back * to the page in question. * - * - addr - kernel address - * - size - region size + * - kaddr - kernel address (guaranteed to be page aligned) */ -ENTRY(v7_flush_kern_dcache_area) +ENTRY(v7_flush_kern_dcache_page) dcache_line_size r2, r3 - add r1, r0, r1 + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line add r0, r0, r2 @@ -204,7 +203,7 @@ ENTRY(v7_flush_kern_dcache_area) blo 1b dsb mov pc, lr -ENDPROC(v7_flush_kern_dcache_area) +ENDPROC(v7_flush_kern_dcache_page) /* * v7_dma_inv_range(start,end) @@ -280,7 +279,7 @@ ENTRY(v7_cache_fns) .long v7_flush_user_cache_range .long v7_coherent_kern_range .long v7_coherent_user_range - .long v7_flush_kern_dcache_area + .long v7_flush_kern_dcache_page .long v7_dma_inv_range .long v7_dma_clean_range .long v7_dma_flush_range diff --git a/trunk/arch/arm/mm/flush.c b/trunk/arch/arm/mm/flush.c index 6f3a4b7a3b82..329594e760cd 100644 --- a/trunk/arch/arm/mm/flush.c +++ b/trunk/arch/arm/mm/flush.c @@ -131,7 +131,7 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page) */ if (addr) #endif - __cpuc_flush_dcache_area(addr, PAGE_SIZE); + __cpuc_flush_dcache_page(addr); /* * If this is a page cache page, and we have an aliasing VIPT cache, @@ -258,5 +258,5 @@ void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned l * in this mapping of the page. FIXME: this is overkill * since we actually ask for a write-back and invalidate. */ - __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); + __cpuc_flush_dcache_page(page_address(page)); } diff --git a/trunk/arch/arm/mm/highmem.c b/trunk/arch/arm/mm/highmem.c index 2be1ec7c1b41..30f82fb5918c 100644 --- a/trunk/arch/arm/mm/highmem.c +++ b/trunk/arch/arm/mm/highmem.c @@ -79,7 +79,7 @@ void kunmap_atomic(void *kvaddr, enum km_type type) unsigned int idx = type + KM_TYPE_NR * smp_processor_id(); if (kvaddr >= (void *)FIXADDR_START) { - __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE); + __cpuc_flush_dcache_page((void *)vaddr); #ifdef CONFIG_DEBUG_HIGHMEM BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); set_pte_ext(TOP_PTE(vaddr), __pte(0), 0); diff --git a/trunk/arch/arm/mm/nommu.c b/trunk/arch/arm/mm/nommu.c index 374a8311bc84..900811cc9130 100644 --- a/trunk/arch/arm/mm/nommu.c +++ b/trunk/arch/arm/mm/nommu.c @@ -61,7 +61,7 @@ void setup_mm_for_reboot(char mode) void flush_dcache_page(struct page *page) { - __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); + __cpuc_flush_dcache_page(page_address(page)); } EXPORT_SYMBOL(flush_dcache_page); diff --git a/trunk/arch/arm/mm/proc-arm1020.S b/trunk/arch/arm/mm/proc-arm1020.S index 8012e24282b2..d9fb4b98c49f 100644 --- a/trunk/arch/arm/mm/proc-arm1020.S +++ b/trunk/arch/arm/mm/proc-arm1020.S @@ -231,18 +231,17 @@ ENTRY(arm1020_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - page - page aligned address */ -ENTRY(arm1020_flush_kern_dcache_area) +ENTRY(arm1020_flush_kern_dcache_page) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE - add r1, r0, r1 + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry mcr p15, 0, ip, c7, c10, 4 @ drain WB add r0, r0, #CACHE_DLINESIZE @@ -336,7 +335,7 @@ ENTRY(arm1020_cache_fns) .long arm1020_flush_user_cache_range .long arm1020_coherent_kern_range .long arm1020_coherent_user_range - .long arm1020_flush_kern_dcache_area + .long arm1020_flush_kern_dcache_page .long arm1020_dma_inv_range .long arm1020_dma_clean_range .long arm1020_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm1020e.S b/trunk/arch/arm/mm/proc-arm1020e.S index 41fe25d234f5..7453b75dcea5 100644 --- a/trunk/arch/arm/mm/proc-arm1020e.S +++ b/trunk/arch/arm/mm/proc-arm1020e.S @@ -225,18 +225,17 @@ ENTRY(arm1020e_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - page - page aligned address */ -ENTRY(arm1020e_flush_kern_dcache_area) +ENTRY(arm1020e_flush_kern_dcache_page) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE - add r1, r0, r1 + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -322,7 +321,7 @@ ENTRY(arm1020e_cache_fns) .long arm1020e_flush_user_cache_range .long arm1020e_coherent_kern_range .long arm1020e_coherent_user_range - .long arm1020e_flush_kern_dcache_area + .long arm1020e_flush_kern_dcache_page .long arm1020e_dma_inv_range .long arm1020e_dma_clean_range .long arm1020e_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm1022.S b/trunk/arch/arm/mm/proc-arm1022.S index 20a5b1b31a70..8eb72d75a8b6 100644 --- a/trunk/arch/arm/mm/proc-arm1022.S +++ b/trunk/arch/arm/mm/proc-arm1022.S @@ -214,18 +214,17 @@ ENTRY(arm1022_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - page - page aligned address */ -ENTRY(arm1022_flush_kern_dcache_area) +ENTRY(arm1022_flush_kern_dcache_page) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE - add r1, r0, r1 + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -311,7 +310,7 @@ ENTRY(arm1022_cache_fns) .long arm1022_flush_user_cache_range .long arm1022_coherent_kern_range .long arm1022_coherent_user_range - .long arm1022_flush_kern_dcache_area + .long arm1022_flush_kern_dcache_page .long arm1022_dma_inv_range .long arm1022_dma_clean_range .long arm1022_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm1026.S b/trunk/arch/arm/mm/proc-arm1026.S index 96aedb10fcc4..3b59f0d67139 100644 --- a/trunk/arch/arm/mm/proc-arm1026.S +++ b/trunk/arch/arm/mm/proc-arm1026.S @@ -208,18 +208,17 @@ ENTRY(arm1026_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - page - page aligned address */ -ENTRY(arm1026_flush_kern_dcache_area) +ENTRY(arm1026_flush_kern_dcache_page) mov ip, #0 #ifndef CONFIG_CPU_DCACHE_DISABLE - add r1, r0, r1 + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -305,7 +304,7 @@ ENTRY(arm1026_cache_fns) .long arm1026_flush_user_cache_range .long arm1026_coherent_kern_range .long arm1026_coherent_user_range - .long arm1026_flush_kern_dcache_area + .long arm1026_flush_kern_dcache_page .long arm1026_dma_inv_range .long arm1026_dma_clean_range .long arm1026_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm920.S b/trunk/arch/arm/mm/proc-arm920.S index 471669e2d7cb..2b7c197cc58d 100644 --- a/trunk/arch/arm/mm/proc-arm920.S +++ b/trunk/arch/arm/mm/proc-arm920.S @@ -207,16 +207,15 @@ ENTRY(arm920_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(arm920_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(arm920_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -294,7 +293,7 @@ ENTRY(arm920_cache_fns) .long arm920_flush_user_cache_range .long arm920_coherent_kern_range .long arm920_coherent_user_range - .long arm920_flush_kern_dcache_area + .long arm920_flush_kern_dcache_page .long arm920_dma_inv_range .long arm920_dma_clean_range .long arm920_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm922.S b/trunk/arch/arm/mm/proc-arm922.S index ee111b00fa41..06a1aa4e3398 100644 --- a/trunk/arch/arm/mm/proc-arm922.S +++ b/trunk/arch/arm/mm/proc-arm922.S @@ -209,16 +209,15 @@ ENTRY(arm922_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(arm922_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(arm922_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -296,7 +295,7 @@ ENTRY(arm922_cache_fns) .long arm922_flush_user_cache_range .long arm922_coherent_kern_range .long arm922_coherent_user_range - .long arm922_flush_kern_dcache_area + .long arm922_flush_kern_dcache_page .long arm922_dma_inv_range .long arm922_dma_clean_range .long arm922_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm925.S b/trunk/arch/arm/mm/proc-arm925.S index 8deb5bde58e4..cb53435a85ae 100644 --- a/trunk/arch/arm/mm/proc-arm925.S +++ b/trunk/arch/arm/mm/proc-arm925.S @@ -251,16 +251,15 @@ ENTRY(arm925_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(arm925_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(arm925_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -347,7 +346,7 @@ ENTRY(arm925_cache_fns) .long arm925_flush_user_cache_range .long arm925_coherent_kern_range .long arm925_coherent_user_range - .long arm925_flush_kern_dcache_area + .long arm925_flush_kern_dcache_page .long arm925_dma_inv_range .long arm925_dma_clean_range .long arm925_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm926.S b/trunk/arch/arm/mm/proc-arm926.S index 64db6e275a44..1c4848704bb3 100644 --- a/trunk/arch/arm/mm/proc-arm926.S +++ b/trunk/arch/arm/mm/proc-arm926.S @@ -214,16 +214,15 @@ ENTRY(arm926_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(arm926_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(arm926_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -310,7 +309,7 @@ ENTRY(arm926_cache_fns) .long arm926_flush_user_cache_range .long arm926_coherent_kern_range .long arm926_coherent_user_range - .long arm926_flush_kern_dcache_area + .long arm926_flush_kern_dcache_page .long arm926_dma_inv_range .long arm926_dma_clean_range .long arm926_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm940.S b/trunk/arch/arm/mm/proc-arm940.S index 8196b9f401fb..5b0f8464c8f2 100644 --- a/trunk/arch/arm/mm/proc-arm940.S +++ b/trunk/arch/arm/mm/proc-arm940.S @@ -141,15 +141,14 @@ ENTRY(arm940_coherent_user_range) /* FALLTHROUGH */ /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(arm940_flush_kern_dcache_area) +ENTRY(arm940_flush_kern_dcache_page) mov ip, #0 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries @@ -239,7 +238,7 @@ ENTRY(arm940_cache_fns) .long arm940_flush_user_cache_range .long arm940_coherent_kern_range .long arm940_coherent_user_range - .long arm940_flush_kern_dcache_area + .long arm940_flush_kern_dcache_page .long arm940_dma_inv_range .long arm940_dma_clean_range .long arm940_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-arm946.S b/trunk/arch/arm/mm/proc-arm946.S index 9a951239c86c..40c0449a139b 100644 --- a/trunk/arch/arm/mm/proc-arm946.S +++ b/trunk/arch/arm/mm/proc-arm946.S @@ -183,17 +183,16 @@ ENTRY(arm946_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address * (same as arm926) */ -ENTRY(arm946_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(arm946_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -281,7 +280,7 @@ ENTRY(arm946_cache_fns) .long arm946_flush_user_cache_range .long arm946_coherent_kern_range .long arm946_coherent_user_range - .long arm946_flush_kern_dcache_area + .long arm946_flush_kern_dcache_page .long arm946_dma_inv_range .long arm946_dma_clean_range .long arm946_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-feroceon.S b/trunk/arch/arm/mm/proc-feroceon.S index dbc39383e66a..d0d7795200fc 100644 --- a/trunk/arch/arm/mm/proc-feroceon.S +++ b/trunk/arch/arm/mm/proc-feroceon.S @@ -226,17 +226,16 @@ ENTRY(feroceon_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ .align 5 -ENTRY(feroceon_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(feroceon_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -247,7 +246,7 @@ ENTRY(feroceon_flush_kern_dcache_area) mov pc, lr .align 5 -ENTRY(feroceon_range_flush_kern_dcache_area) +ENTRY(feroceon_range_flush_kern_dcache_page) mrs r2, cpsr add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive orr r3, r2, #PSR_I_BIT @@ -373,7 +372,7 @@ ENTRY(feroceon_cache_fns) .long feroceon_flush_user_cache_range .long feroceon_coherent_kern_range .long feroceon_coherent_user_range - .long feroceon_flush_kern_dcache_area + .long feroceon_flush_kern_dcache_page .long feroceon_dma_inv_range .long feroceon_dma_clean_range .long feroceon_dma_flush_range @@ -384,7 +383,7 @@ ENTRY(feroceon_range_cache_fns) .long feroceon_flush_user_cache_range .long feroceon_coherent_kern_range .long feroceon_coherent_user_range - .long feroceon_range_flush_kern_dcache_area + .long feroceon_range_flush_kern_dcache_page .long feroceon_range_dma_inv_range .long feroceon_range_dma_clean_range .long feroceon_range_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-mohawk.S b/trunk/arch/arm/mm/proc-mohawk.S index 9674d36cc97d..52b5fd74fbb3 100644 --- a/trunk/arch/arm/mm/proc-mohawk.S +++ b/trunk/arch/arm/mm/proc-mohawk.S @@ -186,16 +186,15 @@ ENTRY(mohawk_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(mohawk_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(mohawk_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry add r0, r0, #CACHE_DLINESIZE cmp r0, r1 @@ -274,7 +273,7 @@ ENTRY(mohawk_cache_fns) .long mohawk_flush_user_cache_range .long mohawk_coherent_kern_range .long mohawk_coherent_user_range - .long mohawk_flush_kern_dcache_area + .long mohawk_flush_kern_dcache_page .long mohawk_dma_inv_range .long mohawk_dma_clean_range .long mohawk_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-syms.c b/trunk/arch/arm/mm/proc-syms.c index 3e6210b4d6d4..ac5c80062b70 100644 --- a/trunk/arch/arm/mm/proc-syms.c +++ b/trunk/arch/arm/mm/proc-syms.c @@ -27,7 +27,8 @@ EXPORT_SYMBOL(__cpuc_flush_kern_all); EXPORT_SYMBOL(__cpuc_flush_user_all); EXPORT_SYMBOL(__cpuc_flush_user_range); EXPORT_SYMBOL(__cpuc_coherent_kern_range); -EXPORT_SYMBOL(__cpuc_flush_dcache_area); +EXPORT_SYMBOL(__cpuc_flush_dcache_page); +EXPORT_SYMBOL(dmac_inv_range); /* because of flush_ioremap_region() */ #else EXPORT_SYMBOL(cpu_cache); #endif diff --git a/trunk/arch/arm/mm/proc-v6.S b/trunk/arch/arm/mm/proc-v6.S index 395cc90c6613..5485c821101c 100644 --- a/trunk/arch/arm/mm/proc-v6.S +++ b/trunk/arch/arm/mm/proc-v6.S @@ -254,9 +254,10 @@ __pj4_v6_proc_info: .long 0x560f5810 .long 0xff0ffff0 .long PMD_TYPE_SECT | \ + PMD_SECT_BUFFERABLE | \ + PMD_SECT_CACHEABLE | \ PMD_SECT_AP_WRITE | \ - PMD_SECT_AP_READ | \ - PMD_FLAGS + PMD_SECT_AP_READ .long PMD_TYPE_SECT | \ PMD_SECT_XN | \ PMD_SECT_AP_WRITE | \ diff --git a/trunk/arch/arm/mm/proc-xsc3.S b/trunk/arch/arm/mm/proc-xsc3.S index 96456f548798..fab134e29826 100644 --- a/trunk/arch/arm/mm/proc-xsc3.S +++ b/trunk/arch/arm/mm/proc-xsc3.S @@ -226,16 +226,15 @@ ENTRY(xsc3_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache. * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(xsc3_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(xsc3_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line add r0, r0, #CACHELINESIZE cmp r0, r1 @@ -310,7 +309,7 @@ ENTRY(xsc3_cache_fns) .long xsc3_flush_user_cache_range .long xsc3_coherent_kern_range .long xsc3_coherent_user_range - .long xsc3_flush_kern_dcache_area + .long xsc3_flush_kern_dcache_page .long xsc3_dma_inv_range .long xsc3_dma_clean_range .long xsc3_dma_flush_range diff --git a/trunk/arch/arm/mm/proc-xscale.S b/trunk/arch/arm/mm/proc-xscale.S index 93df47265f2d..f056c283682d 100644 --- a/trunk/arch/arm/mm/proc-xscale.S +++ b/trunk/arch/arm/mm/proc-xscale.S @@ -284,16 +284,15 @@ ENTRY(xscale_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_area(void *addr, size_t size) + * flush_kern_dcache_page(void *page) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - kernel address - * - size - region size + * - addr - page aligned address */ -ENTRY(xscale_flush_kern_dcache_area) - add r1, r0, r1 +ENTRY(xscale_flush_kern_dcache_page) + add r1, r0, #PAGE_SZ 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry add r0, r0, #CACHELINESIZE @@ -369,7 +368,7 @@ ENTRY(xscale_cache_fns) .long xscale_flush_user_cache_range .long xscale_coherent_kern_range .long xscale_coherent_user_range - .long xscale_flush_kern_dcache_area + .long xscale_flush_kern_dcache_page .long xscale_dma_inv_range .long xscale_dma_clean_range .long xscale_dma_flush_range @@ -393,7 +392,7 @@ ENTRY(xscale_80200_A0_A1_cache_fns) .long xscale_flush_user_cache_range .long xscale_coherent_kern_range .long xscale_coherent_user_range - .long xscale_flush_kern_dcache_area + .long xscale_flush_kern_dcache_page .long xscale_dma_flush_range .long xscale_dma_clean_range .long xscale_dma_flush_range diff --git a/trunk/arch/arm/plat-mxc/include/mach/mxc_nand.h b/trunk/arch/arm/plat-mxc/include/mach/mxc_nand.h index 5d2d21d414e0..2b972df22d12 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mxc_nand.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mxc_nand.h @@ -22,7 +22,6 @@ struct mxc_nand_platform_data { int width; /* data bus width in bytes */ - int hw_ecc:1; /* 0 if supress hardware ECC */ - int flash_bbt:1; /* set to 1 to use a flash based bbt */ + int hw_ecc; /* 0 if supress hardware ECC */ }; #endif /* __ASM_ARCH_NAND_H */ diff --git a/trunk/arch/arm/plat-s3c/include/plat/nand.h b/trunk/arch/arm/plat-s3c/include/plat/nand.h index 226147b7e026..065985978413 100644 --- a/trunk/arch/arm/plat-s3c/include/plat/nand.h +++ b/trunk/arch/arm/plat-s3c/include/plat/nand.h @@ -17,7 +17,6 @@ * Setting this flag will allow the kernel to * look for it at boot time and also skip the NAND * scan. - * @options: Default value to set into 'struct nand_chip' options. * @nr_chips: Number of chips in this set * @nr_partitions: Number of partitions pointed to by @partitions * @name: Name of set (optional) @@ -32,7 +31,6 @@ struct s3c2410_nand_set { unsigned int disable_ecc:1; unsigned int flash_bbt:1; - unsigned int options; int nr_chips; int nr_partitions; char *name; diff --git a/trunk/arch/arm/tools/Makefile b/trunk/arch/arm/tools/Makefile index 635cb1865e4d..1dbaa29ac4d7 100644 --- a/trunk/arch/arm/tools/Makefile +++ b/trunk/arch/arm/tools/Makefile @@ -4,7 +4,7 @@ # Copyright (C) 2001 Russell King # -include/generated/mach-types.h: $(src)/gen-mach-types $(src)/mach-types +include/asm-arm/mach-types.h: $(src)/gen-mach-types $(src)/mach-types @echo ' Generating $@' @mkdir -p $(dir $@) $(Q)$(AWK) -f $^ > $@ || { rm -f $@; /bin/false; } diff --git a/trunk/arch/arm/tools/gen-mach-types b/trunk/arch/arm/tools/gen-mach-types index 04fef71d7be9..ce319ef64bc1 100644 --- a/trunk/arch/arm/tools/gen-mach-types +++ b/trunk/arch/arm/tools/gen-mach-types @@ -1,6 +1,6 @@ #!/bin/awk # -# Awk script to generate include/generated/mach-types.h +# Awk script to generate include/asm-arm/mach-types.h # BEGIN { nr = 0 } /^#/ { next } diff --git a/trunk/arch/arm/tools/mach-types b/trunk/arch/arm/tools/mach-types index c3a74ce24ef6..07b976da6174 100644 --- a/trunk/arch/arm/tools/mach-types +++ b/trunk/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Wed Dec 16 20:06:34 2009 +# Last update: Wed Nov 25 22:14:58 2009 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -1776,7 +1776,6 @@ cybook3 MACH_CYBOOK3 CYBOOK3 1784 wdg002 MACH_WDG002 WDG002 1785 sg560adsl MACH_SG560ADSL SG560ADSL 1786 nextio_n2800_ica MACH_NEXTIO_N2800_ICA NEXTIO_N2800_ICA 1787 -dove_db MACH_DOVE_DB DOVE_DB 1788 marvell_newdb MACH_MARVELL_NEWDB MARVELL_NEWDB 1789 vandihud MACH_VANDIHUD VANDIHUD 1790 magx_e8 MACH_MAGX_E8 MAGX_E8 1791 @@ -2537,44 +2536,3 @@ c3ax03 MACH_C3AX03 C3AX03 2549 mxt_td60 MACH_MXT_TD60 MXT_TD60 2550 esyx MACH_ESYX ESYX 2551 bulldog MACH_BULLDOG BULLDOG 2553 -derell_me2000 MACH_DERELL_ME2000 DERELL_ME2000 2554 -bcmring_base MACH_BCMRING_BASE BCMRING_BASE 2555 -bcmring_evm MACH_BCMRING_EVM BCMRING_EVM 2556 -bcmring_evm_jazz MACH_BCMRING_EVM_JAZZ BCMRING_EVM_JAZZ 2557 -bcmring_sp MACH_BCMRING_SP BCMRING_SP 2558 -bcmring_sv MACH_BCMRING_SV BCMRING_SV 2559 -bcmring_sv_jazz MACH_BCMRING_SV_JAZZ BCMRING_SV_JAZZ 2560 -bcmring_tablet MACH_BCMRING_TABLET BCMRING_TABLET 2561 -bcmring_vp MACH_BCMRING_VP BCMRING_VP 2562 -bcmring_evm_seikor MACH_BCMRING_EVM_SEIKOR BCMRING_EVM_SEIKOR 2563 -bcmring_sp_wqvga MACH_BCMRING_SP_WQVGA BCMRING_SP_WQVGA 2564 -bcmring_custom MACH_BCMRING_CUSTOM BCMRING_CUSTOM 2565 -acer_s200 MACH_ACER_S200 ACER_S200 2566 -bt270 MACH_BT270 BT270 2567 -iseo MACH_ISEO ISEO 2568 -cezanne MACH_CEZANNE CEZANNE 2569 -lucca MACH_LUCCA LUCCA 2570 -supersmart MACH_SUPERSMART SUPERSMART 2571 -magnolia2 MACH_MAGNOLIA2 MAGNOLIA2 2573 -emxx MACH_EMXX EMXX 2574 -outlaw MACH_OUTLAW OUTLAW 2575 -riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576 -riot_vox MACH_RIOT_VOX RIOT_VOX 2577 -riot_x37 MACH_RIOT_X37 RIOT_X37 2578 -mega25mx MACH_MEGA25MX MEGA25MX 2579 -benzina2 MACH_BENZINA2 BENZINA2 2580 -ignite MACH_IGNITE IGNITE 2581 -foggia MACH_FOGGIA FOGGIA 2582 -arezzo MACH_AREZZO AREZZO 2583 -leica_skywalker MACH_LEICA_SKYWALKER LEICA_SKYWALKER 2584 -jacinto2_jamr MACH_JACINTO2_JAMR JACINTO2_JAMR 2585 -gts_nova MACH_GTS_NOVA GTS_NOVA 2586 -p3600 MACH_P3600 P3600 2587 -dlt2 MACH_DLT2 DLT2 2588 -df3120 MACH_DF3120 DF3120 2589 -ecucore_9g20 MACH_ECUCORE_9G20 ECUCORE_9G20 2590 -nautel_lpc3240 MACH_NAUTEL_LPC3240 NAUTEL_LPC3240 2591 -glacier MACH_GLACIER GLACIER 2592 -phrazer_bulldog MACH_PHRAZER_BULLDOG PHRAZER_BULLDOG 2593 -omap3_bulldog MACH_OMAP3_BULLDOG OMAP3_BULLDOG 2594 -pca101 MACH_PCA101 PCA101 2595 diff --git a/trunk/arch/avr32/include/asm/asm-offsets.h b/trunk/arch/avr32/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/avr32/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/avr32/include/asm/elf.h b/trunk/arch/avr32/include/asm/elf.h index 3b3159b710d4..d5d1d41c600a 100644 --- a/trunk/arch/avr32/include/asm/elf.h +++ b/trunk/arch/avr32/include/asm/elf.h @@ -77,6 +77,7 @@ typedef struct user_fpu_struct elf_fpregset_t; #endif #define ELF_ARCH EM_AVR32 +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/blackfin/Kconfig b/trunk/arch/blackfin/Kconfig index 53c1e1d45c68..ae6a60f10120 100644 --- a/trunk/arch/blackfin/Kconfig +++ b/trunk/arch/blackfin/Kconfig @@ -5,10 +5,6 @@ mainmenu "Blackfin Kernel Configuration" -config SYMBOL_PREFIX - string - default "_" - config MMU def_bool n @@ -32,9 +28,6 @@ config BLACKFIN select HAVE_OPROFILE select ARCH_WANT_OPTIONAL_GPIOLIB -config GENERIC_CSUM - def_bool y - config GENERIC_BUG def_bool y depends on BUG @@ -180,7 +173,7 @@ config BF539 help BF539 Processor Support. -config BF542_std +config BF542 bool "BF542" help BF542 Processor Support. @@ -190,7 +183,7 @@ config BF542M help BF542 Processor Support. -config BF544_std +config BF544 bool "BF544" help BF544 Processor Support. @@ -200,7 +193,7 @@ config BF544M help BF544 Processor Support. -config BF547_std +config BF547 bool "BF547" help BF547 Processor Support. @@ -210,7 +203,7 @@ config BF547M help BF547 Processor Support. -config BF548_std +config BF548 bool "BF548" help BF548 Processor Support. @@ -220,7 +213,7 @@ config BF548M help BF548 Processor Support. -config BF549_std +config BF549 bool "BF549" help BF549 Processor Support. @@ -314,11 +307,31 @@ config BF_REV_NONE endchoice +config BF51x + bool + depends on (BF512 || BF514 || BF516 || BF518) + default y + +config BF52x + bool + depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) + default y + config BF53x bool depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) default y +config BF54xM + bool + depends on (BF542M || BF544M || BF547M || BF548M || BF549M) + default y + +config BF54x + bool + depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM) + default y + config MEM_GENERIC_BOARD bool depends on GENERIC_BOARD @@ -900,12 +913,6 @@ config DMA_UNCACHED_2M bool "Enable 2M DMA region" config DMA_UNCACHED_1M bool "Enable 1M DMA region" -config DMA_UNCACHED_512K - bool "Enable 512K DMA region" -config DMA_UNCACHED_256K - bool "Enable 256K DMA region" -config DMA_UNCACHED_128K - bool "Enable 128K DMA region" config DMA_UNCACHED_NONE bool "Disable DMA region" endchoice @@ -1267,8 +1274,6 @@ source "net/Kconfig" source "drivers/Kconfig" -source "drivers/firmware/Kconfig" - source "fs/Kconfig" source "arch/blackfin/Kconfig.debug" diff --git a/trunk/arch/blackfin/Makefile b/trunk/arch/blackfin/Makefile index d4c7177e7656..f063b772934b 100644 --- a/trunk/arch/blackfin/Makefile +++ b/trunk/arch/blackfin/Makefile @@ -16,7 +16,6 @@ GZFLAGS := -9 KBUILD_CFLAGS += $(call cc-option,-mno-fdpic) KBUILD_AFLAGS += $(call cc-option,-mno-fdpic) CFLAGS_MODULE += -mlong-calls -LDFLAGS_MODULE += -m elf32bfin KALLSYMS += --symbol-prefix=_ KBUILD_DEFCONFIG := BF537-STAMP_defconfig @@ -138,7 +137,7 @@ archclean: INSTALL_PATH ?= /tftpboot boot := arch/$(ARCH)/boot -BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma +BOOT_TARGETS = vmImage vmImage.bz2 vmImage.gz vmImage.lzma PHONY += $(BOOT_TARGETS) install KBUILD_IMAGE := $(boot)/vmImage @@ -152,7 +151,6 @@ install: define archhelp echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)' - echo ' vmImage.bin - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)' echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)' echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)' echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)' diff --git a/trunk/arch/blackfin/boot/Makefile b/trunk/arch/blackfin/boot/Makefile index e9c48c6f8c1f..fd9ccc5fea10 100644 --- a/trunk/arch/blackfin/boot/Makefile +++ b/trunk/arch/blackfin/boot/Makefile @@ -8,7 +8,7 @@ MKIMAGE := $(srctree)/scripts/mkuboot.sh -targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma +targets := vmImage vmImage.bz2 vmImage.gz vmImage.lzma extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma quiet_cmd_uimage = UIMAGE $@ @@ -29,9 +29,6 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE $(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE $(call if_changed,lzma) -$(obj)/vmImage.bin: $(obj)/vmlinux.bin - $(call if_changed,uimage,none) - $(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2 $(call if_changed,uimage,bzip2) @@ -41,7 +38,6 @@ $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz $(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma $(call if_changed,uimage,lzma) -suffix-y := bin suffix-$(CONFIG_KERNEL_GZIP) := gz suffix-$(CONFIG_KERNEL_BZIP2) := bz2 suffix-$(CONFIG_KERNEL_LZMA) := lzma diff --git a/trunk/arch/blackfin/configs/BF518F-EZBRD_defconfig b/trunk/arch/blackfin/configs/BF518F-EZBRD_defconfig index e31559419817..9905b26009e5 100644 --- a/trunk/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/trunk/arch/blackfin/configs/BF518F-EZBRD_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -317,7 +316,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -440,7 +438,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set +CONFIG_NET_DSA=y +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_DSA_TAG_TRAILER is not set +CONFIG_NET_DSA_TAG_STPID=y +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_NET_DSA_KSZ8893M=y # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set diff --git a/trunk/arch/blackfin/configs/BF526-EZBRD_defconfig b/trunk/arch/blackfin/configs/BF526-EZBRD_defconfig index 075e0fdcb399..9dc682088023 100644 --- a/trunk/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/trunk/arch/blackfin/configs/BF526-EZBRD_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -322,7 +321,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF527-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF527-EZKIT_defconfig index 6d1a623fb149..77e35d4baf53 100644 --- a/trunk/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -322,7 +321,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF533-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF533-EZKIT_defconfig index 50f9a23ccdbd..4c044805cb5c 100644 --- a/trunk/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -284,7 +283,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF533-STAMP_defconfig b/trunk/arch/blackfin/configs/BF533-STAMP_defconfig index 6c60c8286318..c99bbcd09a68 100644 --- a/trunk/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/trunk/arch/blackfin/configs/BF533-STAMP_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -284,7 +283,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF537-STAMP_defconfig b/trunk/arch/blackfin/configs/BF537-STAMP_defconfig index 2908595b67c5..092ffda80e68 100644 --- a/trunk/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/trunk/arch/blackfin/configs/BF537-STAMP_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -291,7 +290,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -706,7 +704,10 @@ CONFIG_CONFIG_INPUT_PCF8574=m # # Hardware I/O ports # -# CONFIG_SERIO is not set +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set # CONFIG_GAMEPORT is not set # diff --git a/trunk/arch/blackfin/configs/BF538-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF538-EZKIT_defconfig index 09ea2499555e..fa698a89f6fe 100644 --- a/trunk/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF538-EZKIT_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -302,7 +301,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF548-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF548-EZKIT_defconfig index eb3e98b6f3f0..f773ad1155d4 100644 --- a/trunk/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -1,29 +1,22 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.31.5 -# Mon Nov 2 22:02:56 2009 +# Linux kernel version: 2.6.28.10 +# Thu May 21 05:50:01 2009 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y # # General setup @@ -33,40 +26,22 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -87,28 +62,17 @@ CONFIG_EPOLL=y # CONFIG_TIMERFD is not set # CONFIG_EVENTFD is not set # CONFIG_AIO is not set - -# -# Performance Counters -# CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -116,8 +80,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y -# CONFIG_LBDAF is not set +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -127,12 +94,13 @@ CONFIG_BLOCK=y CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y # CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -169,7 +137,7 @@ CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_BF544M is not set # CONFIG_BF547 is not set # CONFIG_BF547M is not set -CONFIG_BF548_std=y +CONFIG_BF548=y # CONFIG_BF548M is not set # CONFIG_BF549 is not set # CONFIG_BF549M is not set @@ -227,7 +195,7 @@ CONFIG_BFIN548_EZKIT=y # # BF548 Specific Configuration # -CONFIG_DEB_DMA_URGENT=y +# CONFIG_DEB_DMA_URGENT is not set # CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set # @@ -384,11 +352,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set CONFIG_DMA_UNCACHED_2M=y @@ -399,13 +366,14 @@ CONFIG_DMA_UNCACHED_2M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y -# CONFIG_BFIN_EXTMEM_WRITEBACK is not set -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set # CONFIG_BFIN_L2_DCACHEABLE is not set # @@ -414,7 +382,7 @@ CONFIG_BFIN_EXTMEM_WRITETHROUGH=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -473,6 +441,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -496,11 +469,13 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -518,10 +493,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -576,10 +548,14 @@ CONFIG_SIR_BFIN_DMA=y # CONFIG_MCS_FIR is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y -CONFIG_LIB80211=m -# CONFIG_WIMAX is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -602,7 +578,6 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set @@ -678,6 +653,7 @@ CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_BFIN is not set CONFIG_MTD_NAND_IDS=y CONFIG_MTD_NAND_BF5XX=y CONFIG_MTD_NAND_BF5XX_HWECC=y @@ -688,11 +664,6 @@ CONFIG_MTD_NAND_BF5XX_HWECC=y # CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -711,20 +682,10 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_ISL29003 is not set -# CONFIG_AD525X_DPOT is not set # CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -748,6 +709,10 @@ CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -764,7 +729,6 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_SATA_PMP=y @@ -780,34 +744,13 @@ CONFIG_NETDEVICES=y # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set +# CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_SMC91X is not set +CONFIG_SMSC911X=y # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -816,8 +759,6 @@ CONFIG_SMSC911X=y # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -830,15 +771,12 @@ CONFIG_LIBERTAS=m # CONFIG_LIBERTAS_USB is not set CONFIG_LIBERTAS_SDIO=m CONFIG_POWEROF2_BLOCKSIZE_ONLY=y -# CONFIG_LIBERTAS_SPI is not set # CONFIG_LIBERTAS_DEBUG is not set # CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_HOSTAP is not set -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - # # USB Network Adapters # @@ -875,31 +813,28 @@ CONFIG_INPUT_EVBUG=m # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_BFIN=y +# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_KEYBOARD_BFIN=y +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set CONFIG_TOUCHSCREEN_AD7877=m # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879_SPI is not set # CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set @@ -909,8 +844,6 @@ CONFIG_TOUCHSCREEN_AD7877=m # CONFIG_TOUCHSCREEN_WM97XX is not set # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_ATI_REMOTE is not set # CONFIG_INPUT_ATI_REMOTE2 is not set @@ -919,11 +852,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_INPUT_BFIN_ROTARY is not set -# CONFIG_INPUT_AD714X is not set -# CONFIG_INPUT_ADXL34X is not set -# CONFIG_INPUT_PCF8574 is not set +# CONFIG_CONFIG_INPUT_PCF8574 is not set # # Hardware I/O ports @@ -934,13 +863,16 @@ CONFIG_INPUT_MISC=y # # Character devices # +# CONFIG_AD9960 is not set CONFIG_BFIN_DMA_INTERFACE=m # CONFIG_BFIN_PPI is not set # CONFIG_BFIN_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set # CONFIG_BFIN_SPI_ADC is not set CONFIG_BFIN_SPORT=m +# CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_BFIN_TWI_LCD is not set +CONFIG_SIMPLE_GPIO=m CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y @@ -958,7 +890,6 @@ CONFIG_BFIN_JTAG_COMM=m # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -972,7 +903,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_OTP=y # CONFIG_BFIN_OTP_WRITE_ENABLE is not set @@ -1021,9 +951,14 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_SENSORS_AD5252 is not set +# CONFIG_EEPROM_LEGACY is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1040,18 +975,13 @@ CONFIG_SPI_BFIN=y # CONFIG_SPI_BFIN_LOCK is not set # CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -1067,7 +997,6 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -1109,19 +1038,28 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set -# CONFIG_UCB1400_CORE is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_PMIC_DA903X is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set # CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set # # Graphics support @@ -1158,7 +1096,6 @@ CONFIG_FB_BF54X_LQ043=y # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -1195,7 +1132,6 @@ CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y -CONFIG_SND_JACK=y # CONFIG_SND_SEQUENCER is not set CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=y @@ -1206,11 +1142,6 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set # CONFIG_SND_MTPAV is not set @@ -1221,6 +1152,7 @@ CONFIG_SND_SPI=y # # ALSA Blackfin devices # +# CONFIG_SND_BLACKFIN_AD1836 is not set # CONFIG_SND_BFIN_AD73322 is not set CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set @@ -1228,17 +1160,15 @@ CONFIG_SND_USB=y CONFIG_SND_SOC=y CONFIG_SND_SOC_AC97_BUS=y # CONFIG_SND_BF5XX_I2S is not set -# CONFIG_SND_BF5XX_TDM is not set CONFIG_SND_BF5XX_AC97=y CONFIG_SND_BF5XX_MMAP_SUPPORT=y # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set -CONFIG_SND_BF5XX_HAVE_COLD_RESET=y -CONFIG_SND_BF5XX_RESET_GPIO_NUM=19 -CONFIG_SND_BF5XX_SOC_AD1980=y CONFIG_SND_BF5XX_SOC_SPORT=y CONFIG_SND_BF5XX_SOC_AC97=y +CONFIG_SND_BF5XX_SOC_AD1980=y CONFIG_SND_BF5XX_SPORT_NUM=0 -CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_BF5XX_HAVE_COLD_RESET=y +CONFIG_SND_BF5XX_RESET_GPIO_NUM=19 # CONFIG_SND_SOC_ALL_CODECS is not set CONFIG_SND_SOC_AD1980=y # CONFIG_SOUND_PRIME is not set @@ -1258,34 +1188,30 @@ CONFIG_USB_HID=y # # Special HID drivers # +CONFIG_HID_COMPAT=y CONFIG_HID_A4TECH=y CONFIG_HID_APPLE=y CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set +CONFIG_HID_DELL=y CONFIG_HID_EZKEY=y -# CONFIG_HID_KYE is not set CONFIG_HID_GYRATION=y -# CONFIG_HID_KENSINGTON is not set CONFIG_HID_LOGITECH=y # CONFIG_LOGITECH_FF is not set # CONFIG_LOGIRUMBLEPAD2_FF is not set CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y -# CONFIG_HID_NTRIG is not set CONFIG_HID_PANTHERLORD=y # CONFIG_PANTHERLORD_FF is not set CONFIG_HID_PETALYNX=y CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set @@ -1311,7 +1237,6 @@ CONFIG_USB_MON=y # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set @@ -1342,17 +1267,18 @@ CONFIG_USB_INVENTRA_DMA=y # CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # -# also be needed; see USB_STORAGE Help for more info +# see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set @@ -1388,6 +1314,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set @@ -1399,13 +1326,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -CONFIG_NOP_USB_XCEIV=y CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set @@ -1460,7 +1380,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers @@ -1492,20 +1411,9 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_BFIN=y # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set -# -# Firmware Drivers -# -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_SIGMA is not set - # # File systems # @@ -1519,11 +1427,9 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1532,11 +1438,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -1566,7 +1467,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1585,8 +1489,17 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +CONFIG_YAFFS_FS=m +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -1595,7 +1508,6 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y @@ -1610,6 +1522,7 @@ CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1683,15 +1596,11 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set @@ -1699,21 +1608,16 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_NOMMU_REGIONS is not set # CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_FRAME_POINTER is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set @@ -1721,16 +1625,17 @@ CONFIG_DEBUG_INFO=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set + +# +# Tracers +# +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_VERBOSE=y @@ -1752,15 +1657,17 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set -# CONFIG_SECURITY is not set +CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_SECURITY_ROOTPLUG is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 CONFIG_CRYPTO=y # @@ -1839,7 +1746,6 @@ CONFIG_CRYPTO=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -1847,13 +1753,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1863,8 +1767,6 @@ CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m -CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/BF561-ACVILON_defconfig b/trunk/arch/blackfin/configs/BF561-ACVILON_defconfig deleted file mode 100644 index b9b0f93d0bd3..000000000000 --- a/trunk/arch/blackfin/configs/BF561-ACVILON_defconfig +++ /dev/null @@ -1,1643 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.31.4 -# Sat Oct 24 12:15:32 2009 -# -# CONFIG_MMU is not set -# CONFIG_FPU is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_BLACKFIN=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_BUG=y -CONFIG_ZONE_DMA=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_GENERIC_GPIO=y -CONFIG_FORCE_MAX_ZONEORDER=14 -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -# CONFIG_FUTEX is not set -CONFIG_EPOLL=y -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set - -# -# Performance Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -CONFIG_LBDAF=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y -# CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set - -# -# Blackfin Processor Options -# - -# -# Processor and Board Settings -# -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set -# CONFIG_BF522 is not set -# CONFIG_BF523 is not set -# CONFIG_BF524 is not set -# CONFIG_BF525 is not set -# CONFIG_BF526 is not set -# CONFIG_BF527 is not set -# CONFIG_BF531 is not set -# CONFIG_BF532 is not set -# CONFIG_BF533 is not set -# CONFIG_BF534 is not set -# CONFIG_BF536 is not set -# CONFIG_BF537 is not set -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set -# CONFIG_BF542 is not set -# CONFIG_BF542M is not set -# CONFIG_BF544 is not set -# CONFIG_BF544M is not set -# CONFIG_BF547 is not set -# CONFIG_BF547M is not set -# CONFIG_BF548 is not set -# CONFIG_BF548M is not set -# CONFIG_BF549 is not set -# CONFIG_BF549M is not set -CONFIG_BF561=y -# CONFIG_SMP is not set -CONFIG_BF_REV_MIN=3 -CONFIG_BF_REV_MAX=5 -# CONFIG_BF_REV_0_0 is not set -# CONFIG_BF_REV_0_1 is not set -# CONFIG_BF_REV_0_2 is not set -# CONFIG_BF_REV_0_3 is not set -# CONFIG_BF_REV_0_4 is not set -CONFIG_BF_REV_0_5=y -# CONFIG_BF_REV_0_6 is not set -# CONFIG_BF_REV_ANY is not set -# CONFIG_BF_REV_NONE is not set -CONFIG_IRQ_PLL_WAKEUP=7 -CONFIG_IRQ_SPORT0_ERROR=7 -CONFIG_IRQ_SPORT1_ERROR=7 -CONFIG_IRQ_TIMER0=10 -CONFIG_IRQ_TIMER1=10 -CONFIG_IRQ_TIMER2=10 -CONFIG_IRQ_TIMER3=10 -CONFIG_IRQ_TIMER4=10 -CONFIG_IRQ_TIMER5=10 -CONFIG_IRQ_TIMER6=10 -CONFIG_IRQ_TIMER7=10 -CONFIG_IRQ_SPI_ERROR=7 -# CONFIG_BFIN561_EZKIT is not set -# CONFIG_BFIN561_TEPLA is not set -# CONFIG_BFIN561_BLUETECHNIX_CM is not set -CONFIG_BFIN561_ACVILON=y - -# -# BF561 Specific Configuration -# - -# -# Core B Support -# -# CONFIG_BF561_COREB is not set - -# -# Interrupt Priority Assignment -# - -# -# Priority -# -CONFIG_IRQ_DMA1_ERROR=7 -CONFIG_IRQ_DMA2_ERROR=7 -CONFIG_IRQ_IMDMA_ERROR=7 -CONFIG_IRQ_PPI0_ERROR=7 -CONFIG_IRQ_PPI1_ERROR=7 -CONFIG_IRQ_UART_ERROR=7 -CONFIG_IRQ_RESERVED_ERROR=7 -CONFIG_IRQ_DMA1_0=8 -CONFIG_IRQ_DMA1_1=8 -CONFIG_IRQ_DMA1_2=8 -CONFIG_IRQ_DMA1_3=8 -CONFIG_IRQ_DMA1_4=8 -CONFIG_IRQ_DMA1_5=8 -CONFIG_IRQ_DMA1_6=8 -CONFIG_IRQ_DMA1_7=8 -CONFIG_IRQ_DMA1_8=8 -CONFIG_IRQ_DMA1_9=8 -CONFIG_IRQ_DMA1_10=8 -CONFIG_IRQ_DMA1_11=8 -CONFIG_IRQ_DMA2_0=9 -CONFIG_IRQ_DMA2_1=9 -CONFIG_IRQ_DMA2_2=9 -CONFIG_IRQ_DMA2_3=9 -CONFIG_IRQ_DMA2_4=9 -CONFIG_IRQ_DMA2_5=9 -CONFIG_IRQ_DMA2_6=9 -CONFIG_IRQ_DMA2_7=9 -CONFIG_IRQ_DMA2_8=9 -CONFIG_IRQ_DMA2_9=9 -CONFIG_IRQ_DMA2_10=9 -CONFIG_IRQ_DMA2_11=9 -CONFIG_IRQ_TIMER8=10 -CONFIG_IRQ_TIMER9=10 -CONFIG_IRQ_TIMER10=10 -CONFIG_IRQ_TIMER11=10 -CONFIG_IRQ_PROG0_INTA=11 -CONFIG_IRQ_PROG0_INTB=11 -CONFIG_IRQ_PROG1_INTA=11 -CONFIG_IRQ_PROG1_INTB=11 -CONFIG_IRQ_PROG2_INTA=11 -CONFIG_IRQ_PROG2_INTB=11 -CONFIG_IRQ_DMA1_WRRD0=8 -CONFIG_IRQ_DMA1_WRRD1=8 -CONFIG_IRQ_DMA2_WRRD0=9 -CONFIG_IRQ_DMA2_WRRD1=9 -CONFIG_IRQ_IMDMA_WRRD0=12 -CONFIG_IRQ_IMDMA_WRRD1=12 -CONFIG_IRQ_WDTIMER=13 - -# -# Board customizations -# -# CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 - -# -# Clock/PLL Setup -# -CONFIG_CLKIN_HZ=12000000 -# CONFIG_BFIN_KERNEL_CLOCK is not set -CONFIG_MAX_VCO_HZ=600000000 -CONFIG_MIN_VCO_HZ=50000000 -CONFIG_MAX_SCLK_HZ=133333333 -CONFIG_MIN_SCLK_HZ=27000000 - -# -# Kernel Timer/Scheduler -# -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_SCHED_HRTICK=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y -CONFIG_CYCLES_CLOCKSOURCE=y -# CONFIG_GPTMR0_CLOCKSOURCE is not set -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y - -# -# Misc -# -CONFIG_BFIN_SCRATCH_REG_RETN=y -# CONFIG_BFIN_SCRATCH_REG_RETE is not set -# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set - -# -# Blackfin Kernel Optimizations -# - -# -# Memory Optimizations -# -CONFIG_I_ENTRY_L1=y -CONFIG_EXCPT_IRQ_SYSC_L1=y -CONFIG_DO_IRQ_L1=y -CONFIG_CORE_TIMER_IRQ_L1=y -CONFIG_IDLE_L1=y -CONFIG_SCHEDULE_L1=y -CONFIG_ARITHMETIC_OPS_L1=y -CONFIG_ACCESS_OK_L1=y -CONFIG_MEMSET_L1=y -CONFIG_MEMCPY_L1=y -CONFIG_SYS_BFIN_SPINLOCK_L1=y -# CONFIG_IP_CHECKSUM_L1 is not set -CONFIG_CACHELINE_ALIGNED_L1=y -# CONFIG_SYSCALL_TAB_L1 is not set -# CONFIG_CPLB_SWITCH_TAB_L1 is not set -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y -CONFIG_RAMKERNEL=y -# CONFIG_ROMKERNEL is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_VIRT_TO_BUS=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=y -CONFIG_DMA_UNCACHED_4M=y -# CONFIG_DMA_UNCACHED_2M is not set -# CONFIG_DMA_UNCACHED_1M is not set -# CONFIG_DMA_UNCACHED_NONE is not set - -# -# Cache Support -# -CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set -CONFIG_BFIN_DCACHE=y -# CONFIG_BFIN_DCACHE_BANKA is not set -CONFIG_BFIN_EXTMEM_DCACHEABLE=y -CONFIG_BFIN_EXTMEM_WRITEBACK=y -# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set -# CONFIG_BFIN_L2_DCACHEABLE is not set - -# -# Memory Protection Unit -# -# CONFIG_MPU is not set - -# -# Asynchronous Memory Configuration -# - -# -# EBIU_AMGCTL Global Control -# -CONFIG_C_AMCKEN=y -CONFIG_C_CDPRIO=y -CONFIG_C_B0PEN=y -CONFIG_C_B1PEN=y -CONFIG_C_B2PEN=y -# CONFIG_C_B3PEN is not set -# CONFIG_C_AMBEN is not set -# CONFIG_C_AMBEN_B0 is not set -# CONFIG_C_AMBEN_B0_B1 is not set -# CONFIG_C_AMBEN_B0_B1_B2 is not set -CONFIG_C_AMBEN_ALL=y - -# -# EBIU_AMBCTL Control -# -CONFIG_BANK_0=0x99b2 -CONFIG_BANK_1=0x3350 -CONFIG_BANK_2=0x7BB0 -CONFIG_BANK_3=0xAAC2 - -# -# Bus options (PCI, PCMCIA, EISA, MCA, ISA) -# -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF_FDPIC=y -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -# CONFIG_BINFMT_SHARED_FLAT is not set -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y - -# -# CPU Frequency scaling -# -# CONFIG_CPU_FREQ is not set -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETLABEL is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_RAM=y -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_UCLINUX is not set -CONFIG_MTD_PLATRAM=y - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SLRAM is not set -CONFIG_MTD_PHRAM=y -# CONFIG_MTD_MTDRAM is not set -CONFIG_MTD_BLOCK2MTD=y - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=2 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_PROC_FS is not set - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=y - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_BFIN_DMA_INTERFACE is not set -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set -CONFIG_BFIN_SIMPLE_TIMER=y -# CONFIG_BFIN_SPI_ADC is not set -# CONFIG_BFIN_SPORT is not set -# CONFIG_BFIN_TWI_LCD is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -# CONFIG_BFIN_JTAG_COMM is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_SERIAL_BFIN_DMA is not set -CONFIG_SERIAL_BFIN_PIO=y -CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_BFIN_UART0_CTSRTS is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_BFIN_SPORT is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# CAN, the car bus and industrial fieldbus -# -# CONFIG_CAN4LINUX is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_ALGOPCA=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -CONFIG_I2C_PCA_PLATFORM=y -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -CONFIG_GPIO_PCF857X=y -# CONFIG_GPIO_ADP5588 is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -CONFIG_SENSORS_LM75=y -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_BFIN_WDT=y - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -# CONFIG_SND_SEQUENCER is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -CONFIG_SND_SPI=y - -# -# ALSA Blackfin devices -# -# CONFIG_SND_BFIN_AD73322 is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=y -CONFIG_SND_BF5XX_I2S=y -# CONFIG_SND_BF5XX_SOC_SSM2602 is not set -# CONFIG_SND_BF5XX_SOC_AD73311 is not set -# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set -# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set -# CONFIG_SND_BF5XX_TDM is not set -# CONFIG_SND_BF5XX_AC97 is not set -CONFIG_SND_BF5XX_SOC_SPORT=y -CONFIG_SND_BF5XX_SPORT_NUM=1 -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=y -# CONFIG_USB_SERIAL_CONSOLE is not set -# CONFIG_USB_EZUSB is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP210X is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -CONFIG_USB_SERIAL_FTDI_SIO=y -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -CONFIG_USB_SERIAL_PL2303=y -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -# CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_DRV_DS1307=y -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# Firmware Drivers -# -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_SIGMA is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=866 -CONFIG_FAT_DEFAULT_IOCHARSET="cp1251" -CONFIG_NTFS_FS=y -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_CONFIGFS_FS=y -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -# CONFIG_JFFS2_ZLIB is not set -CONFIG_JFFS2_LZO=y -# CONFIG_JFFS2_RTIME is not set -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_CRAMFS=y -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -CONFIG_MINIX_FS=y -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="cp1251" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -CONFIG_NLS_CODEPAGE_866=y -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -CONFIG_NLS_CODEPAGE_1251=y -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -CONFIG_NLS_KOI8_R=y -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_NOMMU_REGIONS is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_FRAME_POINTER is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set -# CONFIG_DEBUG_STACKOVERFLOW is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_VERBOSE=y -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_HWERR is not set -# CONFIG_DEBUG_DOUBLEFAULT is not set -CONFIG_DEBUG_HUNT_FOR_ZERO=y -CONFIG_DEBUG_BFIN_HWTRACE_ON=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y -# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set -# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 -# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -# CONFIG_EARLY_PRINTK is not set -CONFIG_CPLB_INFO=y -CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set - -# -# Security options -# -# CONFIG_KEYS is not set -CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_ROOTPLUG is not set -# CONFIG_SECURITY_TOMOYO is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/BF561-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF561-EZKIT_defconfig index e3ecdcc3e76b..0313cd1d9824 100644 --- a/trunk/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -1,29 +1,22 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.31.5 -# Mon Nov 2 21:59:31 2009 +# Linux kernel version: 2.6.28.10 +# Thu May 21 05:50:01 2009 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y # # General setup @@ -33,40 +26,22 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -87,28 +62,17 @@ CONFIG_EPOLL=y # CONFIG_TIMERFD is not set # CONFIG_EVENTFD is not set # CONFIG_AIO is not set - -# -# Performance Counters -# CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -116,8 +80,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y -# CONFIG_LBDAF is not set +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -127,12 +94,13 @@ CONFIG_BLOCK=y CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y # CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -202,7 +170,6 @@ CONFIG_IRQ_SPI_ERROR=7 CONFIG_BFIN561_EZKIT=y # CONFIG_BFIN561_TEPLA is not set # CONFIG_BFIN561_BLUETECHNIX_CM is not set -# CONFIG_BFIN561_ACVILON is not set # # BF561 Specific Configuration @@ -350,11 +317,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -365,13 +331,14 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set # CONFIG_BFIN_L2_DCACHEABLE is not set # @@ -380,7 +347,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -440,6 +407,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -463,11 +435,13 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -485,10 +459,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -532,8 +503,13 @@ CONFIG_IRTTY_SIR=m # # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -554,7 +530,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set @@ -627,11 +602,6 @@ CONFIG_MTD_PHYSMAP=m # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -649,14 +619,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -680,11 +645,9 @@ CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_SMC91X=y +# CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -693,8 +656,6 @@ CONFIG_SMC91X=y # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -703,10 +664,7 @@ CONFIG_SMC91X=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -750,12 +708,15 @@ CONFIG_INPUT_EVDEV=m # # Character devices # +# CONFIG_AD9960 is not set CONFIG_BFIN_DMA_INTERFACE=m # CONFIG_BFIN_PPI is not set # CONFIG_BFIN_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set # CONFIG_BFIN_SPI_ADC is not set # CONFIG_BFIN_SPORT is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +CONFIG_SIMPLE_GPIO=m # CONFIG_VT is not set # CONFIG_DEVKMEM is not set CONFIG_BFIN_JTAG_COMM=m @@ -769,7 +730,6 @@ CONFIG_BFIN_JTAG_COMM=m # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -780,7 +740,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # @@ -804,18 +763,13 @@ CONFIG_SPI_BFIN=y # CONFIG_SPI_BFIN_LOCK is not set # CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -828,6 +782,9 @@ CONFIG_GPIO_SYSFS=y # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set # # PCI GPIO expanders: @@ -865,9 +822,23 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set -# CONFIG_EZX_PCAP is not set # CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set # # Graphics support @@ -891,6 +862,7 @@ CONFIG_HID=m # # Special HID drivers # +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -898,19 +870,9 @@ CONFIG_HID=m # CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set -# -# Firmware Drivers -# -# CONFIG_FIRMWARE_MEMMAP is not set - # # File systems # @@ -920,11 +882,9 @@ CONFIG_HID=m # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -933,11 +893,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -960,7 +915,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -979,8 +937,17 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +CONFIG_YAFFS_FS=m +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -989,7 +956,6 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y @@ -1000,6 +966,7 @@ CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1067,15 +1034,11 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set @@ -1083,21 +1046,16 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_NOMMU_REGIONS is not set # CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_FRAME_POINTER is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set @@ -1105,19 +1063,17 @@ CONFIG_DEBUG_INFO=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_BRANCH_PROFILE_NONE is not set -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_DYNAMIC_DEBUG is not set + +# +# Tracers +# +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_VERBOSE=y @@ -1139,15 +1095,16 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set -# CONFIG_SECURITY is not set +CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 CONFIG_CRYPTO=y # @@ -1226,7 +1183,6 @@ CONFIG_CRYPTO=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -1234,13 +1190,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1250,8 +1204,6 @@ CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m -CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/BlackStamp_defconfig b/trunk/arch/blackfin/configs/BlackStamp_defconfig index 9e65d885ec0b..5d944ffd4ab0 100644 --- a/trunk/arch/blackfin/configs/BlackStamp_defconfig +++ b/trunk/arch/blackfin/configs/BlackStamp_defconfig @@ -66,7 +66,6 @@ CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -276,7 +275,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/CM-BF527_defconfig b/trunk/arch/blackfin/configs/CM-BF527_defconfig index 4432150d89e3..648a31d01bf4 100644 --- a/trunk/arch/blackfin/configs/CM-BF527_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF527_defconfig @@ -1,13 +1,12 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.28 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y @@ -16,9 +15,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,72 +25,55 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y CONFIG_UID16=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y # CONFIG_AIO is not set CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -102,8 +81,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -119,6 +101,7 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -282,10 +265,7 @@ CONFIG_HZ=250 # CONFIG_SCHED_HRTICK is not set CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y # CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -335,12 +315,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -351,9 +329,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -364,7 +343,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -382,7 +361,7 @@ CONFIG_C_AMBEN_ALL=y # EBIU_AMBCTL Control # CONFIG_BANK_0=0x7BB0 -CONFIG_BANK_1=0x7BB0 +CONFIG_BANK_1=0x5554 CONFIG_BANK_2=0x7BB0 CONFIG_BANK_3=0xFFC0 @@ -407,6 +386,7 @@ CONFIG_BINFMT_ZFLAT=y # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling @@ -420,6 +400,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -443,6 +428,7 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" @@ -466,9 +452,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -479,8 +463,13 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -495,21 +484,22 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # -CONFIG_MTD_CHAR=y +CONFIG_MTD_CHAR=m CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set @@ -522,9 +512,9 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y @@ -536,11 +526,9 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_INTELEXT is not set # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y CONFIG_MTD_ROM=m # CONFIG_MTD_ABSENT is not set @@ -550,7 +538,7 @@ CONFIG_MTD_ROM=m # CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_GPIO_ADDR=y +# CONFIG_MTD_GPIO_ADDR is not set # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -573,11 +561,6 @@ CONFIG_MTD_GPIO_ADDR=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -603,46 +586,12 @@ CONFIG_HAVE_IDE=y # SCSI device support # # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -664,9 +613,6 @@ CONFIG_PHYLIB=y # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y @@ -677,11 +623,9 @@ CONFIG_BFIN_TX_DESC_NUM=10 CONFIG_BFIN_RX_DESC_NUM=20 CONFIG_BFIN_MAC_RMII=y # CONFIG_SMC91X is not set +# CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -689,7 +633,6 @@ CONFIG_BFIN_MAC_RMII=y # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -698,10 +641,7 @@ CONFIG_BFIN_MAC_RMII=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# +# CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters @@ -734,13 +674,17 @@ CONFIG_BFIN_MAC_RMII=y # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set +# CONFIG_BF5xx_EPPI is not set # CONFIG_BFIN_SPORT is not set -# CONFIG_BFIN_TWI_LCD is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_TWI_LCD is not set +CONFIG_BFIN_DMA_INTERFACE=m +CONFIG_SIMPLE_GPIO=m # CONFIG_VT is not set # CONFIG_DEVKMEM is not set # CONFIG_BFIN_JTAG_COMM is not set @@ -754,7 +698,6 @@ CONFIG_BFIN_DMA_INTERFACE=m # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -767,7 +710,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_OTP=y # CONFIG_BFIN_OTP_WRITE_ENABLE is not set @@ -816,9 +758,13 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_AD5252 is not set +# CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set @@ -826,6 +772,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y # @@ -833,17 +780,17 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_BFIN=y # CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_SPI_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y # @@ -856,7 +803,6 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -883,13 +829,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -905,16 +849,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set @@ -946,12 +885,6 @@ CONFIG_BFIN_WDT=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set # # Multifunction device drivers @@ -959,14 +892,10 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set # CONFIG_REGULATOR is not set # @@ -1002,20 +931,20 @@ CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=m +CONFIG_USB=y # CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set CONFIG_USB_OTG_BLACKLIST_HUB=y -CONFIG_USB_MON=m +CONFIG_USB_MON=y # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set @@ -1023,24 +952,24 @@ CONFIG_USB_MON=m # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SOC=y # # Blackfin high speed USB Support # -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_PERIPHERAL=y +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_PERIPHERAL is not set # CONFIG_USB_MUSB_OTG is not set -CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_MUSB_HDRC_HCD=y CONFIG_MUSB_PIO_ONLY=y +CONFIG_MUSB_DMA_POLL=y # CONFIG_USB_MUSB_DEBUG is not set # @@ -1052,31 +981,18 @@ CONFIG_MUSB_PIO_ONLY=y # CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # -# also be needed; see USB_STORAGE Help for more info +# see USB_STORAGE Help for more information # -CONFIG_USB_STORAGE=m -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set # # USB port drivers @@ -1097,6 +1013,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set @@ -1104,50 +1021,9 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2272 is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GADGET is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1214,7 +1090,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_BFIN=y # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -1227,10 +1102,9 @@ CONFIG_RTC_DRV_BFIN=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1239,11 +1113,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -1253,11 +1122,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -1269,7 +1135,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1277,19 +1146,9 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -1298,7 +1157,6 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y @@ -1309,6 +1167,7 @@ CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1323,9 +1182,9 @@ CONFIG_SMB_FS=m # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y +CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set @@ -1349,7 +1208,7 @@ CONFIG_NLS_CODEPAGE_437=y # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set @@ -1376,34 +1235,55 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_FRAME_POINTER is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set # # Tracers # -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set # CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB_TESTCASE is not set CONFIG_DEBUG_VERBOSE=y -# CONFIG_DEBUG_MMRS is not set +CONFIG_DEBUG_MMRS=y +# CONFIG_DEBUG_HWERR is not set # CONFIG_DEBUG_DOUBLEFAULT is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y @@ -1413,10 +1293,9 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_CPLB_INFO is not set CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options @@ -1425,9 +1304,9 @@ CONFIG_ACCESS_CHECK=y CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_ROOTPLUG is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 CONFIG_CRYPTO=y # @@ -1506,7 +1385,6 @@ CONFIG_CRYPTO=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -1514,24 +1392,20 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF533_defconfig b/trunk/arch/blackfin/configs/CM-BF533_defconfig index df56639ab2f2..ae665b93b875 100644 --- a/trunk/arch/blackfin/configs/CM-BF533_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF533_defconfig @@ -1,110 +1,94 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# General setup +# Code maturity level options # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y -CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -# CONFIG_MODULE_UNLOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# CONFIG_BLOCK=y # CONFIG_LBD is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # # IO Schedulers @@ -112,7 +96,7 @@ CONFIG_BLOCK=y CONFIG_IOSCHED_NOOP=y # CONFIG_IOSCHED_AS is not set # CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set @@ -121,7 +105,6 @@ CONFIG_DEFAULT_IOSCHED="noop" CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set # # Blackfin Processor Options @@ -130,10 +113,6 @@ CONFIG_PREEMPT_NONE=y # # Processor and Board Settings # -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set # CONFIG_BF522 is not set # CONFIG_BF523 is not set # CONFIG_BF524 is not set @@ -146,38 +125,28 @@ CONFIG_BF533=y # CONFIG_BF534 is not set # CONFIG_BF536 is not set # CONFIG_BF537 is not set -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set # CONFIG_BF548 is not set -# CONFIG_BF548M is not set # CONFIG_BF549 is not set -# CONFIG_BF549M is not set # CONFIG_BF561 is not set -CONFIG_BF_REV_MIN=3 -CONFIG_BF_REV_MAX=6 # CONFIG_BF_REV_0_0 is not set # CONFIG_BF_REV_0_1 is not set # CONFIG_BF_REV_0_2 is not set CONFIG_BF_REV_0_3=y # CONFIG_BF_REV_0_4 is not set # CONFIG_BF_REV_0_5 is not set -# CONFIG_BF_REV_0_6 is not set # CONFIG_BF_REV_ANY is not set # CONFIG_BF_REV_NONE is not set CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y CONFIG_MEM_MT48LC16M16A2TG_75=y # CONFIG_BFIN533_EZKIT is not set # CONFIG_BFIN533_STAMP is not set -# CONFIG_BLACKSTAMP is not set CONFIG_BFIN533_BLUETECHNIX_CM=y # CONFIG_H8606_HVSISTEMAS is not set -# CONFIG_BFIN532_IP0X is not set +# CONFIG_GENERIC_BF533_BOARD is not set # # BF533/2/1 Specific Configuration @@ -219,7 +188,6 @@ CONFIG_WDTIMER=13 # Board customizations # # CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 # # Clock/PLL Setup @@ -239,20 +207,13 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # -# Misc +# Memory Setup # +CONFIG_MAX_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set @@ -279,12 +240,6 @@ CONFIG_IP_CHECKSUM_L1=y CONFIG_CACHELINE_ALIGNED_L1=y CONFIG_SYSCALL_TAB_L1=y CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y CONFIG_RAMKERNEL=y # CONFIG_ROMKERNEL is not set CONFIG_SELECT_MEMORY_MODEL=y @@ -293,16 +248,12 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_LARGE_ALLOCS=y # CONFIG_BFIN_GPTIMERS is not set -# CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set @@ -311,9 +262,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -324,7 +276,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -349,8 +301,12 @@ CONFIG_BANK_3=0xFFC2 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # +# CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set + +# +# PCCARD (PCMCIA/CardBus) support +# # # Executable file formats @@ -359,19 +315,22 @@ CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_SHARED_FLAT=y -# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set + +# +# Networking +# CONFIG_NET=y # @@ -380,13 +339,45 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set -# CONFIG_INET is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -394,23 +385,31 @@ CONFIG_UNIX=y # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set +# CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set + +# +# QoS and/or fair queueing +# # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set # # Device Drivers @@ -419,22 +418,20 @@ CONFIG_UNIX=y # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set # # User Modules And Translation Layers @@ -447,15 +444,12 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI is not set # CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -466,11 +460,6 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set @@ -479,16 +468,12 @@ CONFIG_MTD_RAM=y # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_UCLINUX is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -504,25 +489,36 @@ CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_ONENAND is not set # -# LPDDR flash memory drivers +# UBI - Unsorted block images # -# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set # -# UBI - Unsorted block images +# Parallel port support # -# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y + +# +# Misc devices +# # CONFIG_IDE is not set # @@ -530,19 +526,34 @@ CONFIG_HAVE_IDE=y # # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# # CONFIG_MD is not set + +# +# Network device support +# CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set -# CONFIG_MACVLAN is not set +# CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_NET_ETHERNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y +# CONFIG_SMSC911X is not set +# CONFIG_DM9000 is not set # CONFIG_NETDEV_1000 is not set +# CONFIG_AX88180 is not set # CONFIG_NETDEV_10000 is not set # @@ -550,17 +561,22 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# # CONFIG_ISDN is not set + +# +# Telephony Support +# # CONFIG_PHONE is not set # @@ -577,15 +593,16 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # Character devices # -# CONFIG_BFIN_DMA_INTERFACE is not set -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set -# CONFIG_BFIN_SPORT is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set -# CONFIG_BFIN_JTAG_COMM is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -596,7 +613,6 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -607,140 +623,175 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # # CAN, the car bus and industrial fieldbus # # CONFIG_CAN4LINUX is not set + +# +# IPMI +# # CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y # -# SPI Master Controller Drivers +# TPM devices # -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y # -# SPI Protocol Masters +# SPI support # -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # -# Sonics Silicon Backplane +# Dallas's 1-wire bus # -# CONFIG_SSB is not set +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# +# CONFIG_DVB_CORE is not set # CONFIG_DAB is not set # # Graphics support # -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# # CONFIG_SOUND is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD/SDIO Card Drivers +# USB support # -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set # -# MMC/SD/SDIO Host Controller Drivers +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set + +# +# LED devices # -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# # CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set # # File systems # -# CONFIG_EXT2_FS is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -750,11 +801,8 @@ CONFIG_FILE_LOCKING=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y # CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -765,8 +813,12 @@ CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -774,106 +826,60 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_DEBUG_VERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_DOUBLEFAULT is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y @@ -882,39 +888,34 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# # CONFIG_CRYPTO is not set -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y +CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF537E_defconfig b/trunk/arch/blackfin/configs/CM-BF537E_defconfig index 22e565c51d66..d74b6f4db35d 100644 --- a/trunk/arch/blackfin/configs/CM-BF537E_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF537E_defconfig @@ -1,13 +1,13 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.28.10 +# Wed Jun 3 06:27:41 2009 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y @@ -16,9 +16,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,40 +26,21 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -71,8 +49,7 @@ CONFIG_EMBEDDED=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set @@ -88,13 +65,12 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -102,8 +78,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -119,6 +98,7 @@ CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_CFQ is not set CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -201,8 +181,7 @@ CONFIG_IRQ_MEM_DMA1=13 CONFIG_IRQ_WATCH=13 CONFIG_IRQ_SPI=10 # CONFIG_BFIN537_STAMP is not set -CONFIG_BFIN537_BLUETECHNIX_CM_E=y -# CONFIG_BFIN537_BLUETECHNIX_CM_U is not set +CONFIG_BFIN537_BLUETECHNIX_CM=y # CONFIG_BFIN537_BLUETECHNIX_TCM is not set # CONFIG_PNAV10 is not set # CONFIG_CAMSIG_MINOTAUR is not set @@ -304,12 +283,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 # CONFIG_BFIN_GPTIMERS is not set # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -320,9 +297,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -333,7 +311,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -359,7 +337,6 @@ CONFIG_BANK_3=0xFFC2 # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set # # Executable file formats @@ -389,6 +366,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -412,6 +394,7 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" @@ -435,9 +418,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -448,8 +429,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set # CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -460,21 +441,16 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set # @@ -510,26 +486,22 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m +# CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_GPIO_ADDR=y -# CONFIG_MTD_UCLINUX is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -544,11 +516,6 @@ CONFIG_MTD_GPIO_ADDR=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -566,14 +533,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -587,7 +549,6 @@ CONFIG_HAVE_IDE=y # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -609,9 +570,6 @@ CONFIG_PHYLIB=y # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y @@ -622,11 +580,8 @@ CONFIG_BFIN_TX_DESC_NUM=10 CONFIG_BFIN_RX_DESC_NUM=20 # CONFIG_BFIN_MAC_RMII is not set # CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set # CONFIG_SMSC911X is not set -# CONFIG_DNET is not set +# CONFIG_DM9000 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -643,10 +598,7 @@ CONFIG_BFIN_RX_DESC_NUM=20 # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -670,12 +622,15 @@ CONFIG_BFIN_RX_DESC_NUM=20 # # Character devices # +# CONFIG_AD9960 is not set CONFIG_BFIN_DMA_INTERFACE=m # CONFIG_BFIN_PPI is not set # CONFIG_BFIN_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set # CONFIG_BFIN_SPI_ADC is not set CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set # CONFIG_BFIN_JTAG_COMM is not set @@ -689,7 +644,6 @@ CONFIG_BFIN_SPORT=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -702,7 +656,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # @@ -715,23 +668,7 @@ CONFIG_UNIX98_PTYS=y # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y @@ -751,21 +688,15 @@ CONFIG_GPIO_SYSFS=y # # SPI GPIO expanders: # -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_VT1211 is not set @@ -827,74 +758,21 @@ CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -CONFIG_USB_GADGET_NET2272=y -CONFIG_USB_NET2272=m -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -911,10 +789,9 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -923,11 +800,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -937,11 +809,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -953,7 +822,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -961,19 +833,9 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_YAFFS_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -982,70 +844,14 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set -CONFIG_LOCKD=m -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=m -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set +# CONFIG_NLS is not set # CONFIG_DLM is not set # @@ -1061,28 +867,14 @@ CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y # # Tracers # -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_DEBUG_VERBOSE=y @@ -1096,10 +888,9 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options @@ -1108,9 +899,8 @@ CONFIG_ACCESS_CHECK=y CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 CONFIG_CRYPTO=y # @@ -1189,7 +979,6 @@ CONFIG_CRYPTO=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -1197,24 +986,19 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF537U_defconfig b/trunk/arch/blackfin/configs/CM-BF537U_defconfig index efcc90d2f345..7fc8dfa1719f 100644 --- a/trunk/arch/blackfin/configs/CM-BF537U_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF537U_defconfig @@ -1,111 +1,94 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# General setup +# Code maturity level options # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y -CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# CONFIG_BLOCK=y # CONFIG_LBD is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # # IO Schedulers @@ -122,7 +105,6 @@ CONFIG_DEFAULT_IOSCHED="noop" CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set # # Blackfin Processor Options @@ -131,10 +113,6 @@ CONFIG_PREEMPT_NONE=y # # Processor and Board Settings # -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set # CONFIG_BF522 is not set # CONFIG_BF523 is not set # CONFIG_BF524 is not set @@ -147,31 +125,22 @@ CONFIG_PREEMPT_NONE=y # CONFIG_BF534 is not set # CONFIG_BF536 is not set CONFIG_BF537=y -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set # CONFIG_BF548 is not set -# CONFIG_BF548M is not set # CONFIG_BF549 is not set -# CONFIG_BF549M is not set # CONFIG_BF561 is not set -CONFIG_BF_REV_MIN=2 -CONFIG_BF_REV_MAX=3 # CONFIG_BF_REV_0_0 is not set # CONFIG_BF_REV_0_1 is not set CONFIG_BF_REV_0_2=y # CONFIG_BF_REV_0_3 is not set # CONFIG_BF_REV_0_4 is not set # CONFIG_BF_REV_0_5 is not set -# CONFIG_BF_REV_0_6 is not set # CONFIG_BF_REV_ANY is not set # CONFIG_BF_REV_NONE is not set CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y CONFIG_MEM_MT48LC16M16A2TG_75=y CONFIG_IRQ_PLL_WAKEUP=7 CONFIG_IRQ_RTC=8 @@ -181,6 +150,7 @@ CONFIG_IRQ_SPORT0_TX=9 CONFIG_IRQ_SPORT1_RX=9 CONFIG_IRQ_SPORT1_TX=9 CONFIG_IRQ_TWI=10 +CONFIG_IRQ_SPI=10 CONFIG_IRQ_UART0_RX=10 CONFIG_IRQ_UART0_TX=10 CONFIG_IRQ_UART1_RX=10 @@ -199,13 +169,11 @@ CONFIG_IRQ_PORTG_INTB=12 CONFIG_IRQ_MEM_DMA0=13 CONFIG_IRQ_MEM_DMA1=13 CONFIG_IRQ_WATCH=13 -CONFIG_IRQ_SPI=10 # CONFIG_BFIN537_STAMP is not set -# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set -CONFIG_BFIN537_BLUETECHNIX_CM_U=y -# CONFIG_BFIN537_BLUETECHNIX_TCM is not set +CONFIG_BFIN537_BLUETECHNIX_CM=y # CONFIG_PNAV10 is not set # CONFIG_CAMSIG_MINOTAUR is not set +# CONFIG_GENERIC_BF537_BOARD is not set # # BF537 Specific Configuration @@ -228,7 +196,6 @@ CONFIG_IRQ_PROG_INTA=12 # Board customizations # # CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 # # Clock/PLL Setup @@ -248,20 +215,13 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # -# Misc +# Memory Setup # +CONFIG_MAX_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set @@ -288,12 +248,6 @@ CONFIG_IP_CHECKSUM_L1=y CONFIG_CACHELINE_ALIGNED_L1=y CONFIG_SYSCALL_TAB_L1=y CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y CONFIG_RAMKERNEL=y # CONFIG_ROMKERNEL is not set CONFIG_SELECT_MEMORY_MODEL=y @@ -302,16 +256,12 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_LARGE_ALLOCS=y # CONFIG_BFIN_GPTIMERS is not set -# CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set @@ -320,9 +270,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -333,7 +284,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -358,8 +309,12 @@ CONFIG_BANK_3=0xFFC2 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # +# CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set + +# +# PCCARD (PCMCIA/CardBus) support +# # # Executable file formats @@ -368,19 +323,22 @@ CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_SHARED_FLAT=y -# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set + +# +# Networking +# CONFIG_NET=y # @@ -389,6 +347,10 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -407,13 +369,15 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_INET_LRO=y # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set @@ -422,7 +386,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -432,23 +395,29 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set + +# +# QoS and/or fair queueing +# # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set # # Device Drivers @@ -457,22 +426,20 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set # # User Modules And Translation Layers @@ -485,15 +452,12 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI is not set # CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -504,29 +468,20 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m +# CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # # Mapping drivers for chip access # -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_GPIO_ADDR=y -# CONFIG_MTD_UCLINUX is not set +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -542,36 +497,36 @@ CONFIG_MTD_GPIO_ADDR=y # CONFIG_MTD_ONENAND is not set # -# LPDDR flash memory drivers +# UBI - Unsorted block images # -# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set # -# UBI - Unsorted block images +# Parallel port support # -# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_MISC_DEVICES=y -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_C2PORT is not set # -# EEPROM support +# Misc devices # -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -579,20 +534,35 @@ CONFIG_HAVE_IDE=y # # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# # CONFIG_MD is not set + +# +# Network device support +# CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_NET_ETHERNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y +# CONFIG_BFIN_MAC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DM9000 is not set # CONFIG_NETDEV_1000 is not set +# CONFIG_AX88180 is not set # CONFIG_NETDEV_10000 is not set # @@ -600,17 +570,22 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# # CONFIG_ISDN is not set + +# +# Telephony Support +# # CONFIG_PHONE is not set # @@ -627,15 +602,16 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set -# CONFIG_BFIN_JTAG_COMM is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -646,7 +622,6 @@ CONFIG_BFIN_SPORT=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -659,201 +634,165 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # # CAN, the car bus and industrial fieldbus # # CONFIG_CAN4LINUX is not set + +# +# IPMI +# # CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y # -# SPI Master Controller Drivers +# TPM devices # -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y # -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: +# SPI support # +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # -# PCI GPIO expanders: +# Dallas's 1-wire bus # - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# # CONFIG_DAB is not set # # Graphics support # -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# # CONFIG_SOUND is not set -CONFIG_USB_SUPPORT=y + +# +# USB support +# CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set # CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_GADGET_MUSB_HDRC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support # CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set CONFIG_USB_GADGET_NET2272=y CONFIG_USB_NET2272=y # CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set # CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH is not set # CONFIG_USB_GADGETFS is not set # CONFIG_USB_FILE_STORAGE is not set # CONFIG_USB_G_SERIAL is not set # CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_MMC is not set # -# OTG and related infrastructure +# LED devices # -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_NEW_LEDS is not set # -# MMC/SD/SDIO Card Drivers +# LED drivers # -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set # -# MMC/SD/SDIO Host Controller Drivers +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock # -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set # # File systems @@ -863,28 +802,24 @@ CONFIG_EXT2_FS_XATTR=y # CONFIG_EXT2_FS_POSIX_ACL is not set # CONFIG_EXT2_FS_SECURITY is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -# CONFIG_DNOTIFY is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -894,11 +829,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -909,8 +841,12 @@ CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -918,29 +854,18 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y + +# +# Network File Systems +# # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set @@ -948,94 +873,41 @@ CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# # CONFIG_DLM is not set +# +# Profiling support +# +# CONFIG_PROFILING is not set + # # Kernel hacking # # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_DEBUG_VERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_DOUBLEFAULT is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y @@ -1044,40 +916,34 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# # CONFIG_CRYPTO is not set -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF548_defconfig b/trunk/arch/blackfin/configs/CM-BF548_defconfig index 7f579cf51127..acca4e51a45a 100644 --- a/trunk/arch/blackfin/configs/CM-BF548_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF548_defconfig @@ -1,14 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.24.4 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y @@ -16,9 +16,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,100 +26,79 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y -# CONFIG_UID16 is not set +CONFIG_UID16=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y -CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set +CONFIG_IOSCHED_AS=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set +CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_DEFAULT_IOSCHED="noop" -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set # # Blackfin Processor Options @@ -131,10 +107,6 @@ CONFIG_PREEMPT_NONE=y # # Processor and Board Settings # -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set # CONFIG_BF522 is not set # CONFIG_BF523 is not set # CONFIG_BF524 is not set @@ -147,29 +119,19 @@ CONFIG_PREEMPT_NONE=y # CONFIG_BF534 is not set # CONFIG_BF536 is not set # CONFIG_BF537 is not set -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set -CONFIG_BF548_std=y -# CONFIG_BF548M is not set +CONFIG_BF548=y # CONFIG_BF549 is not set -# CONFIG_BF549M is not set # CONFIG_BF561 is not set -CONFIG_BF_REV_MIN=0 -CONFIG_BF_REV_MAX=2 # CONFIG_BF_REV_0_0 is not set # CONFIG_BF_REV_0_1 is not set -# CONFIG_BF_REV_0_2 is not set +CONFIG_BF_REV_0_2=y # CONFIG_BF_REV_0_3 is not set # CONFIG_BF_REV_0_4 is not set # CONFIG_BF_REV_0_5 is not set -# CONFIG_BF_REV_0_6 is not set -CONFIG_BF_REV_ANY=y +# CONFIG_BF_REV_ANY is not set # CONFIG_BF_REV_NONE is not set CONFIG_BF54x=y CONFIG_IRQ_PLL_WAKEUP=7 @@ -178,12 +140,15 @@ CONFIG_IRQ_SPORT0_RX=9 CONFIG_IRQ_SPORT0_TX=9 CONFIG_IRQ_SPORT1_RX=9 CONFIG_IRQ_SPORT1_TX=9 -CONFIG_IRQ_SPI0=10 CONFIG_IRQ_UART0_RX=10 CONFIG_IRQ_UART0_TX=10 CONFIG_IRQ_UART1_RX=10 CONFIG_IRQ_UART1_TX=10 CONFIG_IRQ_CNT=8 +CONFIG_IRQ_USB_INT0=11 +CONFIG_IRQ_USB_INT1=11 +CONFIG_IRQ_USB_INT2=11 +CONFIG_IRQ_USB_DMA=11 CONFIG_IRQ_TIMER0=11 CONFIG_IRQ_TIMER1=11 CONFIG_IRQ_TIMER2=11 @@ -192,21 +157,9 @@ CONFIG_IRQ_TIMER4=11 CONFIG_IRQ_TIMER5=11 CONFIG_IRQ_TIMER6=11 CONFIG_IRQ_TIMER7=11 -CONFIG_IRQ_USB_INT0=11 -CONFIG_IRQ_USB_INT1=11 -CONFIG_IRQ_USB_INT2=11 -CONFIG_IRQ_USB_DMA=11 CONFIG_IRQ_TIMER8=11 CONFIG_IRQ_TIMER9=11 CONFIG_IRQ_TIMER10=11 -CONFIG_IRQ_SPORT2_RX=9 -CONFIG_IRQ_SPORT2_TX=9 -CONFIG_IRQ_SPORT3_RX=9 -CONFIG_IRQ_SPORT3_TX=9 -CONFIG_IRQ_SPI1=10 -CONFIG_IRQ_SPI2=10 -CONFIG_IRQ_TWI0=11 -CONFIG_IRQ_TWI1=11 # CONFIG_BFIN548_EZKIT is not set CONFIG_BFIN548_BLUETECHNIX_CM=y @@ -214,7 +167,6 @@ CONFIG_BFIN548_BLUETECHNIX_CM=y # BF548 Specific Configuration # # CONFIG_DEB_DMA_URGENT is not set -# CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set # # Interrupt Priority Assignment @@ -230,6 +182,7 @@ CONFIG_IRQ_SPORT1_ERR=7 CONFIG_IRQ_SPI0_ERR=7 CONFIG_IRQ_UART0_ERR=7 CONFIG_IRQ_EPPI0=8 +CONFIG_IRQ_SPI0=10 CONFIG_IRQ_PINT0=12 CONFIG_IRQ_PINT1=12 CONFIG_IRQ_MDMAS0=13 @@ -244,10 +197,18 @@ CONFIG_IRQ_SPI2_ERR=7 CONFIG_IRQ_UART1_ERR=7 CONFIG_IRQ_UART2_ERR=7 CONFIG_IRQ_CAN0_ERR=7 +CONFIG_IRQ_SPORT2_RX=9 +CONFIG_IRQ_SPORT2_TX=9 +CONFIG_IRQ_SPORT3_RX=9 +CONFIG_IRQ_SPORT3_TX=9 CONFIG_IRQ_EPPI1=9 CONFIG_IRQ_EPPI2=9 +CONFIG_IRQ_SPI1=10 +CONFIG_IRQ_SPI2=10 CONFIG_IRQ_ATAPI_RX=10 CONFIG_IRQ_ATAPI_TX=10 +CONFIG_IRQ_TWI0=11 +CONFIG_IRQ_TWI1=11 CONFIG_IRQ_CAN0_RX=11 CONFIG_IRQ_CAN0_TX=11 CONFIG_IRQ_MDMAS2=13 @@ -294,7 +255,6 @@ CONFIG_PINT3_ASSIGN=0x02020303 # Board customizations # # CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 # # Clock/PLL Setup @@ -314,12 +274,16 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set # CONFIG_GENERIC_TIME is not set +# CONFIG_TICK_ONESHOT is not set # -# Misc +# Memory Setup # +CONFIG_MAX_MEM_SIZE=64 +# CONFIG_MEM_MT46V32M16_6T is not set +CONFIG_MEM_MT46V32M16_5B=y +CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set @@ -346,12 +310,6 @@ CONFIG_ACCESS_OK_L1=y CONFIG_CACHELINE_ALIGNED_L1=y # CONFIG_SYSCALL_TAB_L1 is not set # CONFIG_CPLB_SWITCH_TAB_L1 is not set -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y CONFIG_RAMKERNEL=y # CONFIG_ROMKERNEL is not set CONFIG_SELECT_MEMORY_MODEL=y @@ -360,16 +318,13 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 # CONFIG_BFIN_GPTIMERS is not set -# CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set @@ -378,13 +333,14 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y -# CONFIG_BFIN_EXTMEM_WRITEBACK -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set # CONFIG_BFIN_L2_DCACHEABLE is not set # @@ -393,7 +349,7 @@ CONFIG_BFIN_EXTMEM_WRITETHROUGH=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -413,7 +369,7 @@ CONFIG_C_AMBEN_ALL=y CONFIG_BANK_0=0x7BB0 CONFIG_BANK_1=0x5554 CONFIG_BANK_2=0x7BB0 -CONFIG_BANK_3=0x99B3 +CONFIG_BANK_3=0x99B2 CONFIG_EBIU_MBSCTLVAL=0x0 CONFIG_EBIU_MODEVAL=0x1 CONFIG_EBIU_FCTLVAL=0x6 @@ -421,6 +377,7 @@ CONFIG_EBIU_FCTLVAL=0x6 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # +# CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCCARD is not set @@ -431,19 +388,23 @@ CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y # CONFIG_BINFMT_SHARED_FLAT is not set -# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_SUSPEND_UP_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set + +# +# Networking +# CONFIG_NET=y # @@ -456,7 +417,6 @@ CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -475,16 +435,19 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set @@ -493,7 +456,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -503,21 +465,24 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -536,12 +501,10 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -576,7 +539,6 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y # CONFIG_MTD_ROM is not set @@ -587,8 +549,9 @@ CONFIG_MTD_RAM=y # CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_GPIO_ADDR is not set +CONFIG_MTD_PHYSMAP_START=0x20000000 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -611,11 +574,6 @@ CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -629,31 +587,31 @@ CONFIG_BLK_DEV=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=m +CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y +# CONFIG_SCSI_PROC_FS is not set # # SCSI support type (disk, tape, CD-ROM) # -CONFIG_BLK_DEV_SD=m +CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set @@ -674,54 +632,29 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set +# CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set CONFIG_SMSC911X=y -# CONFIG_DNET is not set +# CONFIG_DM9000 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -732,10 +665,6 @@ CONFIG_SMSC911X=y # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - # # USB Network Adapters # @@ -747,6 +676,7 @@ CONFIG_SMSC911X=y # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -781,7 +711,6 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_GPIO is not set # CONFIG_KEYBOARD_BFIN is not set # CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -797,16 +726,19 @@ CONFIG_INPUT_KEYBOARD=y # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_OTP=y +# CONFIG_BFIN_OTP_WRITE_ENABLE is not set # CONFIG_BFIN_SPORT is not set -# CONFIG_BFIN_TWI_LCD is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_TWI_LCD is not set +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set -CONFIG_DEVKMEM=y -# CONFIG_BFIN_JTAG_COMM is not set +# CONFIG_DEVKMEM is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -817,11 +749,10 @@ CONFIG_DEVKMEM=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_SERIAL_BFIN_DMA is not set -CONFIG_SERIAL_BFIN_PIO=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set # CONFIG_SERIAL_BFIN_UART0 is not set CONFIG_SERIAL_BFIN_UART1=y # CONFIG_BFIN_UART1_CTSRTS is not set @@ -831,10 +762,7 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_OTP=y -# CONFIG_BFIN_OTP_WRITE_ENABLE is not set # # CAN, the car bus and industrial fieldbus @@ -842,53 +770,61 @@ CONFIG_BFIN_OTP=y # CONFIG_CAN4LINUX is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y # -# I2C Hardware Bus support +# I2C Algorithms # +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set # -# I2C system bus drivers (mostly embedded / system-on-chip) +# I2C Hardware Bus support # CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 +CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# # CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set # # Miscellaneous I2C Chip support # +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set # CONFIG_DS1682 is not set +# CONFIG_SENSORS_AD5252 is not set +# CONFIG_EEPROM_LEGACY is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8575 is not set +# CONFIG_SENSORS_PCA9543 is not set # CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set + +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# SPI support +# CONFIG_SPI=y CONFIG_SPI_MASTER=y @@ -896,23 +832,64 @@ CONFIG_SPI_MASTER=y # SPI Master Controller Drivers # CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -926,43 +903,25 @@ CONFIG_BFIN_WDT=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# # CONFIG_DAB is not set +# CONFIG_USB_DABUSB is not set # # Graphics support @@ -976,75 +935,80 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# # CONFIG_SOUND is not set -# CONFIG_HID_SUPPORT is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=m +CONFIG_USB=y # CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=m -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SOC=y # -# Blackfin high speed USB Support +# Blackfin BF54x, BF525 and BF527 high speed USB support # -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_PERIPHERAL=y +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_PERIPHERAL is not set # CONFIG_USB_MUSB_OTG is not set -CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_MUSB_HDRC_HCD=y # CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y +# CONFIG_USB_INVENTRA_DMA is not set # CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set +CONFIG_USB_MUSB_LOGLEVEL=0 # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # -# also be needed; see USB_STORAGE Help for more info +# may also be needed; see USB_STORAGE Help for more information # -CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set @@ -1052,7 +1016,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # @@ -1060,10 +1023,15 @@ CONFIG_USB_STORAGE=m # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y # # USB port drivers # + +# +# USB Serial Converter support +# # CONFIG_USB_SERIAL is not set # @@ -1072,7 +1040,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_AUERSWALD is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1080,6 +1048,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set @@ -1087,75 +1056,38 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2272 is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=m -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -# CONFIG_USB_ETH_RNDIS is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD/SDIO Card Drivers +# MMC/SD Card Drivers # -CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set # -# MMC/SD/SDIO Host Controller Drivers +# MMC/SD Host Controller Drivers # -# CONFIG_MMC_SDHCI is not set -CONFIG_SDH_BFIN=m -# CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set -# CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set +CONFIG_SDH_BFIN=y # CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set +# CONFIG_SPI_MMC is not set # CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # # RTC interfaces @@ -1179,74 +1111,66 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set # # SPI RTC drivers # -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_MAX6902 is not set # # Platform RTC drivers # -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # -CONFIG_RTC_DRV_BFIN=m -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set +CONFIG_RTC_DRV_BFIN=y + +# +# Userspace I/O +# # CONFIG_UIO is not set -# CONFIG_STAGING is not set + +# +# PBX support +# +# CONFIG_PBX is not set # # File systems # -CONFIG_EXT2_FS=m -# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # -# CONFIG_ISO9660_FS is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y # CONFIG_UDF_FS is not set # @@ -1270,7 +1194,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1278,7 +1205,17 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y +CONFIG_YAFFS_FS=m +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +CONFIG_JFFS2_FS=m CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y # CONFIG_JFFS2_FS_WBUF_VERIFY is not set @@ -1290,30 +1227,34 @@ CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_BIND34 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -CONFIG_CIFS=m +CONFIG_SMB_FS=m +CONFIG_SMB_NLS_DEFAULT=y +CONFIG_SMB_NLS_REMOTE="cp437" +CONFIG_CIFS=y # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_XATTR is not set @@ -1326,8 +1267,24 @@ CONFIG_CIFS=m # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m @@ -1369,6 +1326,9 @@ CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m # CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking @@ -1376,39 +1336,14 @@ CONFIG_NLS_UTF8=m # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_DEBUG_VERBOSE=y -# CONFIG_DEBUG_MMRS is not set -# CONFIG_DEBUG_DOUBLEFAULT is not set +CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y @@ -1417,125 +1352,33 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -# CONFIG_BINARY_PRINTF is not set +# CONFIG_SECURITY_CAPABILITIES is not set +# CONFIG_SECURITY_ROOTPLUG is not set +# CONFIG_CRYPTO is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF561_defconfig b/trunk/arch/blackfin/configs/CM-BF561_defconfig index a6df01dac98a..bae4ee6e68bb 100644 --- a/trunk/arch/blackfin/configs/CM-BF561_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF561_defconfig @@ -1,14 +1,15 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.24.4 +# Tue Apr 1 10:50:11 2008 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y @@ -16,9 +17,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,83 +27,62 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -122,7 +99,6 @@ CONFIG_DEFAULT_IOSCHED="noop" CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set # # Blackfin Processor Options @@ -131,10 +107,6 @@ CONFIG_PREEMPT_NONE=y # # Processor and Board Settings # -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set # CONFIG_BF522 is not set # CONFIG_BF523 is not set # CONFIG_BF524 is not set @@ -147,56 +119,44 @@ CONFIG_PREEMPT_NONE=y # CONFIG_BF534 is not set # CONFIG_BF536 is not set # CONFIG_BF537 is not set -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set # CONFIG_BF548 is not set -# CONFIG_BF548M is not set # CONFIG_BF549 is not set -# CONFIG_BF549M is not set CONFIG_BF561=y -# CONFIG_SMP is not set -CONFIG_BF_REV_MIN=3 -CONFIG_BF_REV_MAX=5 # CONFIG_BF_REV_0_0 is not set # CONFIG_BF_REV_0_1 is not set # CONFIG_BF_REV_0_2 is not set CONFIG_BF_REV_0_3=y # CONFIG_BF_REV_0_4 is not set # CONFIG_BF_REV_0_5 is not set -# CONFIG_BF_REV_0_6 is not set # CONFIG_BF_REV_ANY is not set # CONFIG_BF_REV_NONE is not set +CONFIG_BFIN_DUAL_CORE=y CONFIG_MEM_MT48LC8M32B2B5_7=y CONFIG_IRQ_PLL_WAKEUP=7 CONFIG_IRQ_SPORT0_ERROR=7 CONFIG_IRQ_SPORT1_ERROR=7 -CONFIG_IRQ_TIMER0=10 -CONFIG_IRQ_TIMER1=10 -CONFIG_IRQ_TIMER2=10 -CONFIG_IRQ_TIMER3=10 -CONFIG_IRQ_TIMER4=10 -CONFIG_IRQ_TIMER5=10 -CONFIG_IRQ_TIMER6=10 -CONFIG_IRQ_TIMER7=10 CONFIG_IRQ_SPI_ERROR=7 # CONFIG_BFIN561_EZKIT is not set # CONFIG_BFIN561_TEPLA is not set CONFIG_BFIN561_BLUETECHNIX_CM=y +# CONFIG_GENERIC_BF561_BOARD is not set # # BF561 Specific Configuration # +# +# Core B Support +# + # # Core B Support # CONFIG_BF561_COREB=y +# CONFIG_BF561_COREB_RESET is not set # # Interrupt Priority Assignment @@ -236,6 +196,14 @@ CONFIG_IRQ_DMA2_8=9 CONFIG_IRQ_DMA2_9=9 CONFIG_IRQ_DMA2_10=9 CONFIG_IRQ_DMA2_11=9 +CONFIG_IRQ_TIMER0=10 +CONFIG_IRQ_TIMER1=10 +CONFIG_IRQ_TIMER2=10 +CONFIG_IRQ_TIMER3=10 +CONFIG_IRQ_TIMER4=10 +CONFIG_IRQ_TIMER5=10 +CONFIG_IRQ_TIMER6=10 +CONFIG_IRQ_TIMER7=10 CONFIG_IRQ_TIMER8=10 CONFIG_IRQ_TIMER9=10 CONFIG_IRQ_TIMER10=10 @@ -258,7 +226,6 @@ CONFIG_IRQ_WDTIMER=13 # Board customizations # # CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 # # Clock/PLL Setup @@ -278,20 +245,19 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y # CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set +# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # -# Misc +# Memory Setup # +CONFIG_MAX_MEM_SIZE=32 +CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set @@ -318,12 +284,6 @@ CONFIG_IP_CHECKSUM_L1=y CONFIG_CACHELINE_ALIGNED_L1=y CONFIG_SYSCALL_TAB_L1=y CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y CONFIG_RAMKERNEL=y # CONFIG_ROMKERNEL is not set CONFIG_SELECT_MEMORY_MODEL=y @@ -332,16 +292,14 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_LARGE_ALLOCS=y # CONFIG_BFIN_GPTIMERS is not set -# CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set @@ -350,16 +308,15 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y -# CONFIG_BFIN_EXTMEM_WRITEBACK is not set -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set # CONFIG_BFIN_L2_DCACHEABLE is not set -# CONFIG_BFIN_L2_WRITEBACK is not set -# CONFIG_BFIN_L2_WRITETHROUGH is not set # # Memory Protection Unit @@ -367,7 +324,7 @@ CONFIG_BFIN_EXTMEM_WRITETHROUGH=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -396,8 +353,8 @@ CONFIG_BANK_3=0xFFC2 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # +# CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set # # Executable file formats @@ -406,19 +363,18 @@ CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_SHARED_FLAT=y -# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_SUSPEND_UP_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # -# CPU Frequency scaling +# Networking # -# CONFIG_CPU_FREQ is not set CONFIG_NET=y # @@ -427,6 +383,10 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -447,11 +407,14 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set @@ -460,7 +423,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -470,21 +432,24 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -495,22 +460,16 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set # # User Modules And Translation Layers @@ -528,10 +487,8 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI is not set # CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -542,29 +499,20 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m +# CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_UCLINUX is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -579,11 +527,6 @@ CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -596,21 +539,14 @@ CONFIG_BLK_DEV=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y # CONFIG_IDE is not set +# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE0 is not set +# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE1 is not set # # SCSI device support @@ -622,50 +558,26 @@ CONFIG_HAVE_IDE=y # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set +# CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_SMC91X is not set +CONFIG_SMC91X=y +# CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -CONFIG_SMSC911X=m -# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set +# CONFIG_AX88180 is not set # CONFIG_NETDEV_10000 is not set # @@ -673,13 +585,10 @@ CONFIG_SMSC911X=m # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -700,15 +609,16 @@ CONFIG_SMSC911X=m # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set # CONFIG_BFIN_SPORT is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set -# CONFIG_BFIN_JTAG_COMM is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -719,7 +629,6 @@ CONFIG_BFIN_DMA_INTERFACE=m # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -730,7 +639,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # @@ -739,100 +647,54 @@ CONFIG_UNIX98_PTYS=y # CONFIG_CAN4LINUX is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y # -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# - +# SPI support # -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# # CONFIG_DAB is not set # @@ -847,85 +709,42 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set # CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -CONFIG_USB_GADGET_NET2272=y -CONFIG_USB_NET2272=m -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set # CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set + +# +# Userspace I/O +# # CONFIG_UIO is not set -# CONFIG_STAGING is not set + +# +# PBX support +# +# CONFIG_PBX is not set # # File systems @@ -935,28 +754,24 @@ CONFIG_EXT2_FS_XATTR=y # CONFIG_EXT2_FS_POSIX_ACL is not set # CONFIG_EXT2_FS_SECURITY is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -# CONFIG_DNOTIFY is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -966,11 +781,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -982,7 +794,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -990,28 +805,14 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set @@ -1026,47 +827,11 @@ CONFIG_NETWORK_FILESYSTEMS=y # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set +# CONFIG_NLS is not set # CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking @@ -1074,40 +839,14 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_DEBUG_VERBOSE=y CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_DOUBLEFAULT is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y @@ -1116,40 +855,33 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DUAL_CORE_TEST_MODULE is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set +CONFIG_SECURITY_CAPABILITIES=y # CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set # CONFIG_CRYPTO is not set -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/H8606_defconfig b/trunk/arch/blackfin/configs/H8606_defconfig index bc7fae3d8b83..a6a7c8ede705 100644 --- a/trunk/arch/blackfin/configs/H8606_defconfig +++ b/trunk/arch/blackfin/configs/H8606_defconfig @@ -67,7 +67,6 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y CONFIG_RT_MUTEXES=y CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 @@ -250,7 +249,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_LARGE_ALLOCS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y diff --git a/trunk/arch/blackfin/configs/IP0X_defconfig b/trunk/arch/blackfin/configs/IP0X_defconfig index a7e49d631229..1ec9ae2e964b 100644 --- a/trunk/arch/blackfin/configs/IP0X_defconfig +++ b/trunk/arch/blackfin/configs/IP0X_defconfig @@ -68,7 +68,6 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y CONFIG_RT_MUTEXES=y CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 @@ -262,7 +261,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_LARGE_ALLOCS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 # CONFIG_BFIN_GPTIMERS is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y diff --git a/trunk/arch/blackfin/configs/PNAV-10_defconfig b/trunk/arch/blackfin/configs/PNAV-10_defconfig index 67d12768602a..ff377fae061b 100644 --- a/trunk/arch/blackfin/configs/PNAV-10_defconfig +++ b/trunk/arch/blackfin/configs/PNAV-10_defconfig @@ -63,7 +63,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -286,7 +285,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/SRV1_defconfig b/trunk/arch/blackfin/configs/SRV1_defconfig index 52bfa6bf18da..814f9cacf407 100644 --- a/trunk/arch/blackfin/configs/SRV1_defconfig +++ b/trunk/arch/blackfin/configs/SRV1_defconfig @@ -72,7 +72,6 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y CONFIG_RT_MUTEXES=y CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 @@ -272,7 +271,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_LARGE_ALLOCS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_DMA_UNCACHED_2M=y # CONFIG_DMA_UNCACHED_1M is not set # CONFIG_DMA_UNCACHED_NONE is not set @@ -702,7 +700,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set CONFIG_INPUT_UINPUT=y # CONFIG_BF53X_PFBUTTONS is not set -# CONFIG_INPUT_PCF8574 is not set +# CONFIG_TWI_KEYPAD is not set # # Hardware I/O ports diff --git a/trunk/arch/blackfin/configs/TCM-BF537_defconfig b/trunk/arch/blackfin/configs/TCM-BF537_defconfig index 60adfad54db9..375e75a27abc 100644 --- a/trunk/arch/blackfin/configs/TCM-BF537_defconfig +++ b/trunk/arch/blackfin/configs/TCM-BF537_defconfig @@ -1,13 +1,13 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.28-rc2 +# Tue Jan 6 09:22:17 2009 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y @@ -16,9 +16,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,72 +26,49 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y # CONFIG_AIO is not set CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -102,8 +76,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -119,6 +96,7 @@ CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_CFQ is not set CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -150,15 +128,10 @@ CONFIG_BF537=y # CONFIG_BF538 is not set # CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set # CONFIG_BF548 is not set -# CONFIG_BF548M is not set # CONFIG_BF549 is not set -# CONFIG_BF549M is not set # CONFIG_BF561 is not set CONFIG_BF_REV_MIN=2 CONFIG_BF_REV_MAX=3 @@ -200,11 +173,11 @@ CONFIG_IRQ_MEM_DMA1=13 CONFIG_IRQ_WATCH=13 CONFIG_IRQ_SPI=10 # CONFIG_BFIN537_STAMP is not set -# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set -# CONFIG_BFIN537_BLUETECHNIX_CM_U is not set +# CONFIG_BFIN537_BLUETECHNIX_CM is not set CONFIG_BFIN537_BLUETECHNIX_TCM=y # CONFIG_PNAV10 is not set # CONFIG_CAMSIG_MINOTAUR is not set +# CONFIG_GENERIC_BF537_BOARD is not set # # BF537 Specific Configuration @@ -250,10 +223,7 @@ CONFIG_HZ=250 # CONFIG_SCHED_HRTICK is not set CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y # CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -303,12 +273,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 # CONFIG_BFIN_GPTIMERS is not set # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -319,9 +287,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -332,7 +301,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -358,7 +327,6 @@ CONFIG_BANK_3=0xFFC2 # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set # # Executable file formats @@ -375,83 +343,13 @@ CONFIG_BINFMT_SHARED_FLAT=y # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_LRO=y -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set +# CONFIG_NET is not set # # Device Drivers @@ -460,21 +358,15 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set # @@ -510,10 +402,9 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m +# CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # @@ -522,7 +413,7 @@ CONFIG_MTD_ROM=m CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_GPIO_ADDR=y -# CONFIG_MTD_UCLINUX is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # @@ -544,11 +435,6 @@ CONFIG_MTD_GPIO_ADDR=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -557,23 +443,15 @@ CONFIG_MTD_GPIO_ADDR=y CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -586,74 +464,6 @@ CONFIG_HAVE_IDE=y # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set -CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_BFIN_MAC=y -CONFIG_BFIN_MAC_USE_L1=y -CONFIG_BFIN_TX_DESC_NUM=10 -CONFIG_BFIN_RX_DESC_NUM=20 -# CONFIG_BFIN_MAC_RMII is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set # CONFIG_PHONE is not set # @@ -670,12 +480,15 @@ CONFIG_BFIN_RX_DESC_NUM=20 # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set +CONFIG_BFIN_DMA_INTERFACE=m +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set # CONFIG_BFIN_JTAG_COMM is not set @@ -689,7 +502,6 @@ CONFIG_BFIN_SPORT=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -702,7 +514,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # @@ -723,17 +534,39 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_BFIN=y # CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set @@ -747,12 +580,6 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set CONFIG_BFIN_WDT=y -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set # # Multifunction device drivers @@ -761,7 +588,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -771,7 +598,6 @@ CONFIG_SSB_POSSIBLE=y # Multimedia core support # # CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set # CONFIG_VIDEO_MEDIA is not set # @@ -792,81 +618,13 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -CONFIG_USB_GADGET_NET2272=y -CONFIG_USB_NET2272=y -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -883,10 +641,8 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -895,11 +651,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -909,11 +660,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -925,7 +673,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -933,19 +684,9 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -954,62 +695,13 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -# CONFIG_NFS_FS is not set -# CONFIG_NFSD is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set +# CONFIG_NLS is not set # # Kernel hacking @@ -1022,30 +714,12 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_DEBUG_VERBOSE=y @@ -1059,10 +733,9 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options @@ -1071,110 +744,20 @@ CONFIG_ACCESS_CHECK=y # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set +# CONFIG_CRYPTO is not set # # Library routines # -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/include/asm/asm-offsets.h b/trunk/arch/blackfin/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/blackfin/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/blackfin/include/asm/bfin-global.h b/trunk/arch/blackfin/include/asm/bfin-global.h index e6485c305ea6..10064f902d20 100644 --- a/trunk/arch/blackfin/include/asm/bfin-global.h +++ b/trunk/arch/blackfin/include/asm/bfin-global.h @@ -11,6 +11,9 @@ #ifndef __ASSEMBLY__ +#include +#include +#include #include #include @@ -20,12 +23,6 @@ # define DMA_UNCACHED_REGION (2 * 1024 * 1024) #elif defined(CONFIG_DMA_UNCACHED_1M) # define DMA_UNCACHED_REGION (1024 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_512K) -# define DMA_UNCACHED_REGION (512 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_256K) -# define DMA_UNCACHED_REGION (256 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_128K) -# define DMA_UNCACHED_REGION (128 * 1024) #else # define DMA_UNCACHED_REGION (0) #endif @@ -38,7 +35,6 @@ extern unsigned long get_sclk(void); extern unsigned long sclk_to_usecs(unsigned long sclk); extern unsigned long usecs_to_sclk(unsigned long usecs); -struct pt_regs; extern void dump_bfin_process(struct pt_regs *regs); extern void dump_bfin_mem(struct pt_regs *regs); extern void dump_bfin_trace_buffer(void); diff --git a/trunk/arch/blackfin/include/asm/bfin-lq035q1.h b/trunk/arch/blackfin/include/asm/bfin-lq035q1.h deleted file mode 100644 index 57bc21ac2296..000000000000 --- a/trunk/arch/blackfin/include/asm/bfin-lq035q1.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02 - * - * Copyright 2008-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef BFIN_LQ035Q1_H -#define BFIN_LQ035Q1_H - -#define LQ035_RL (0 << 8) /* Right -> Left Scan */ -#define LQ035_LR (1 << 8) /* Left -> Right Scan */ -#define LQ035_TB (1 << 9) /* Top -> Botton Scan */ -#define LQ035_BT (0 << 9) /* Botton -> Top Scan */ -#define LQ035_BGR (1 << 11) /* Use BGR format */ -#define LQ035_RGB (0 << 11) /* Use RGB format */ -#define LQ035_NORM (1 << 13) /* Reversal */ -#define LQ035_REV (0 << 13) /* Reversal */ - -struct bfin_lq035q1fb_disp_info { - - unsigned mode; - /* GPIOs */ - int use_bl; - unsigned gpio_bl; -}; - -#endif /* BFIN_LQ035Q1_H */ diff --git a/trunk/arch/blackfin/include/asm/bug.h b/trunk/arch/blackfin/include/asm/bug.h index 75f6dc336d46..6f4548a13555 100644 --- a/trunk/arch/blackfin/include/asm/bug.h +++ b/trunk/arch/blackfin/include/asm/bug.h @@ -47,7 +47,7 @@ #define BUG() \ do { \ _BUG_OR_WARN(0); \ - unreachable(); \ + for (;;); \ } while (0) #define WARN_ON(condition) \ diff --git a/trunk/arch/blackfin/include/asm/cacheflush.h b/trunk/arch/blackfin/include/asm/cacheflush.h index 2666ff8ea952..417eaac7fe99 100644 --- a/trunk/arch/blackfin/include/asm/cacheflush.h +++ b/trunk/arch/blackfin/include/asm/cacheflush.h @@ -10,7 +10,6 @@ #define _BLACKFIN_CACHEFLUSH_H #include /* for SSYNC() */ -#include /* for _ramend */ extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); diff --git a/trunk/arch/blackfin/include/asm/checksum.h b/trunk/arch/blackfin/include/asm/checksum.h index 623cc7fb00bc..a23415be0de1 100644 --- a/trunk/arch/blackfin/include/asm/checksum.h +++ b/trunk/arch/blackfin/include/asm/checksum.h @@ -8,13 +8,64 @@ #ifndef _BFIN_CHECKSUM_H #define _BFIN_CHECKSUM_H +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +__wsum csum_partial(const void *buff, int len, __wsum sum); + +/* + * the same as csum_partial, but copies from src while it + * checksums + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +__wsum csum_partial_copy(const void *src, void *dst, + int len, __wsum sum); + +/* + * the same as csum_partial_copy, but copies from user space. + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, int *csum_err); + +#define csum_partial_copy_nocheck(src, dst, len, sum) \ + csum_partial_copy((src), (dst), (len), (sum)) + +__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl); + +/* + * Fold a partial checksum + */ + +static inline __sum16 csum_fold(__wsum sum) +{ + while (sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + return ((~(sum << 16)) >> 16); +} + /* * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ static inline __wsum -__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, unsigned short proto, __wsum sum) { unsigned int carry; @@ -37,8 +88,19 @@ __csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, return (sum); } -#define csum_tcpudp_nofold __csum_tcpudp_nofold -#include +static inline __sum16 +csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); +} + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ + +extern __sum16 ip_compute_csum(const void *buff, int len); -#endif +#endif /* _BFIN_CHECKSUM_H */ diff --git a/trunk/arch/blackfin/include/asm/clocks.h b/trunk/arch/blackfin/include/asm/clocks.h index 6f0b61852f58..f80dad5ff257 100644 --- a/trunk/arch/blackfin/include/asm/clocks.h +++ b/trunk/arch/blackfin/include/asm/clocks.h @@ -9,8 +9,6 @@ #ifndef _BFIN_CLOCKS_H #define _BFIN_CLOCKS_H -#include - #ifdef CONFIG_CCLK_DIV_1 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1 # define CONFIG_CCLK_DIV 1 diff --git a/trunk/arch/blackfin/include/asm/dma-mapping.h b/trunk/arch/blackfin/include/asm/dma-mapping.h index f9172ff30e5c..7a23d824ac96 100644 --- a/trunk/arch/blackfin/include/asm/dma-mapping.h +++ b/trunk/arch/blackfin/include/asm/dma-mapping.h @@ -7,9 +7,9 @@ #ifndef _BLACKFIN_DMA_MAPPING_H #define _BLACKFIN_DMA_MAPPING_H -#include -struct scatterlist; +#include +void dma_alloc_init(unsigned long start, unsigned long end); void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp); void dma_free_coherent(struct device *dev, size_t size, void *vaddr, @@ -20,51 +20,13 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, */ #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) -#define dma_supported(d, m) (1) -#define dma_get_cache_alignment() (32) -#define dma_is_consistent(d, h) (1) -static inline int -dma_set_mask(struct device *dev, u64 dma_mask) +static inline +int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { - if (!dev->dma_mask || !dma_supported(dev, dma_mask)) - return -EIO; - - *dev->dma_mask = dma_mask; - return 0; } -static inline int -dma_mapping_error(struct device *dev, dma_addr_t dma_addr) -{ - return 0; -} - -extern void -__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir); -static inline void -_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir) -{ - if (!__builtin_constant_p(dir)) { - __dma_sync(addr, size, dir); - return; - } - - switch (dir) { - case DMA_NONE: - BUG(); - case DMA_TO_DEVICE: /* writeback only */ - flush_dcache_range(addr, addr + size); - break; - case DMA_FROM_DEVICE: /* invalidate only */ - case DMA_BIDIRECTIONAL: /* flush and invalidate */ - /* Blackfin has no dedicated invalidate (it includes a flush) */ - invalidate_dcache_range(addr, addr + size); - break; - } -} - /* * Map a single buffer of the indicated size for DMA in streaming mode. * The 32-bit bus address to use is returned. @@ -72,13 +34,8 @@ _dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir) * Once the device is given the dma address, the device owns this memory * until either pci_unmap_single or pci_dma_sync_single is performed. */ -static inline dma_addr_t -dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction dir) -{ - _dma_sync((dma_addr_t)ptr, size, dir); - return (dma_addr_t) ptr; -} +extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction); static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, @@ -96,12 +53,8 @@ dma_map_page(struct device *dev, struct page *page, * After this call, reads by the cpu to the buffer are guarenteed to see * whatever the device wrote there. */ -static inline void -dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction dir) -{ - BUG_ON(!valid_dma_direction(dir)); -} +extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction); static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, @@ -127,66 +80,38 @@ dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, * the same here. */ extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir); + enum dma_data_direction direction); /* * Unmap a set of streaming mode DMA translations. * Again, cpu read rules concerning calls here are the same as for * pci_unmap_single() above. */ -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, - int nhwentries, enum dma_data_direction dir) -{ - BUG_ON(!valid_dma_direction(dir)); -} +extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, enum dma_data_direction direction); -static inline void -dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle, - unsigned long offset, size_t size, - enum dma_data_direction dir) +static inline void dma_sync_single_for_cpu(struct device *dev, + dma_addr_t handle, size_t size, + enum dma_data_direction dir) { - BUG_ON(!valid_dma_direction(dir)); } -static inline void -dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle, - unsigned long offset, size_t size, - enum dma_data_direction dir) +static inline void dma_sync_single_for_device(struct device *dev, + dma_addr_t handle, size_t size, + enum dma_data_direction dir) { - _dma_sync(handle + offset, size, dir); } -static inline void -dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, - enum dma_data_direction dir) +static inline void dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, + int nents, enum dma_data_direction dir) { - dma_sync_single_range_for_cpu(dev, handle, 0, size, dir); } -static inline void -dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, - enum dma_data_direction dir) -{ - dma_sync_single_range_for_device(dev, handle, 0, size, dir); -} - -static inline void -dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir) -{ - BUG_ON(!valid_dma_direction(dir)); -} - -extern void -dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir); - -static inline void -dma_cache_sync(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction dir) +static inline void dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, + int nents, enum dma_data_direction dir) { - _dma_sync((dma_addr_t)vaddr, size, dir); } #endif /* _BLACKFIN_DMA_MAPPING_H */ diff --git a/trunk/arch/blackfin/include/asm/dma.h b/trunk/arch/blackfin/include/asm/dma.h index bd2e62243abe..c9a59622e23f 100644 --- a/trunk/arch/blackfin/include/asm/dma.h +++ b/trunk/arch/blackfin/include/asm/dma.h @@ -10,70 +10,46 @@ #include #include -#include #include #include -#include - -/* DMA_CONFIG Masks */ -#define DMAEN 0x0001 /* DMA Channel Enable */ -#define WNR 0x0002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ -#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ -#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ -#define RESTART 0x0020 /* DMA Buffer Clear */ -#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ -#define DI_EN 0x0080 /* Data Interrupt Enable */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define NDSIZE 0x0f00 /* Next Descriptor Size */ -#define DMAFLOW 0x7000 /* Flow Control */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ - -/* DMA_IRQ_STATUS Masks */ -#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ -#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + +#define MAX_DMA_ADDRESS PAGE_OFFSET + +/***************************************************************************** +* Generic DMA Declarations +* +****************************************************************************/ +enum dma_chan_status { + DMA_CHANNEL_FREE, + DMA_CHANNEL_REQUESTED, + DMA_CHANNEL_ENABLED, +}; /*------------------------- * config reg bits value *-------------------------*/ -#define DATA_SIZE_8 0 -#define DATA_SIZE_16 1 -#define DATA_SIZE_32 2 +#define DATA_SIZE_8 0 +#define DATA_SIZE_16 1 +#define DATA_SIZE_32 2 -#define DMA_FLOW_STOP 0 -#define DMA_FLOW_AUTO 1 -#define DMA_FLOW_ARRAY 4 -#define DMA_FLOW_SMALL 6 -#define DMA_FLOW_LARGE 7 +#define DMA_FLOW_STOP 0 +#define DMA_FLOW_AUTO 1 +#define DMA_FLOW_ARRAY 4 +#define DMA_FLOW_SMALL 6 +#define DMA_FLOW_LARGE 7 -#define DIMENSION_LINEAR 0 -#define DIMENSION_2D 1 +#define DIMENSION_LINEAR 0 +#define DIMENSION_2D 1 -#define DIR_READ 0 -#define DIR_WRITE 1 +#define DIR_READ 0 +#define DIR_WRITE 1 -#define INTR_DISABLE 0 -#define INTR_ON_BUF 2 -#define INTR_ON_ROW 3 +#define INTR_DISABLE 0 +#define INTR_ON_BUF 2 +#define INTR_ON_ROW 3 #define DMA_NOSYNC_KEEP_DMA_BUF 0 -#define DMA_SYNC_RESTART 1 +#define DMA_SYNC_RESTART 1 struct dmasg { void *next_desc_addr; @@ -128,9 +104,11 @@ struct dma_register { }; +struct mutex; struct dma_channel { + struct mutex dmalock; const char *device_id; - atomic_t chan_status; + enum dma_chan_status chan_status; volatile struct dma_register *regs; struct dmasg *sg; /* large mode descriptor */ unsigned int irq; @@ -242,20 +220,27 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize static inline int dma_channel_active(unsigned int channel) { - return atomic_read(&dma_ch[channel].chan_status); + if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) + return 0; + else + return 1; } static inline void disable_dma(unsigned int channel) { dma_ch[channel].regs->cfg &= ~DMAEN; SSYNC(); + dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED; } static inline void enable_dma(unsigned int channel) { dma_ch[channel].regs->curr_x_count = 0; dma_ch[channel].regs->curr_y_count = 0; dma_ch[channel].regs->cfg |= DMAEN; + dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED; } +void free_dma(unsigned int channel); +int request_dma(unsigned int channel, const char *device_id); int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data); static inline void dma_disable_irq(unsigned int channel) diff --git a/trunk/arch/blackfin/include/asm/dpmc.h b/trunk/arch/blackfin/include/asm/dpmc.h index 1597ae5041ee..925e66cb2d49 100644 --- a/trunk/arch/blackfin/include/asm/dpmc.h +++ b/trunk/arch/blackfin/include/asm/dpmc.h @@ -1,7 +1,7 @@ /* * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver * - * Copyright (C) 2004-2009 Analog Device Inc. + * Copyright (C) 2004-2008 Analog Device Inc. * * Licensed under the GPL-2 */ @@ -9,109 +9,7 @@ #ifndef _BLACKFIN_DPMC_H_ #define _BLACKFIN_DPMC_H_ -/* PLL_CTL Masks */ -#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ -#define PLL_OFF 0x0002 /* PLL Not Powered */ -#define STOPCK 0x0008 /* Core Clock Off */ -#define PDWN 0x0020 /* Enter Deep Sleep Mode */ -#ifdef __ADSPBF539__ -# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */ -# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */ -#else -# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ -# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ -#endif -#define BYPASS 0x0100 /* Bypass the PLL */ -#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ -#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ -#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ - -/* PLL_DIV Masks */ -#define SSEL 0x000F /* System Select */ -#define CSEL 0x0030 /* Core Select */ -#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ -#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ -#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ -#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ - -#define CCLK_DIV1 CSEL_DIV1 -#define CCLK_DIV2 CSEL_DIV2 -#define CCLK_DIV4 CSEL_DIV4 -#define CCLK_DIV8 CSEL_DIV8 - -#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -/* PLL_STAT Masks */ -#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ -#define FULL_ON 0x0002 /* Processor In Full On Mode */ -#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ -#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ - -#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */ -#define CANWS 0x0800 /* CAN Wake-Up Status */ -#define USBWS 0x2000 /* USB Wake-Up Status */ -#define KPADWS 0x4000 /* Keypad Wake-Up Status */ -#define ROTWS 0x8000 /* Rotary Wake-Up Status */ -#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ - -/* VR_CTL Masks */ -#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ -#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */ -#else -#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ -#endif -#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ - -#define GAIN 0x000C /* Voltage Level Gain */ -#define GAIN_5 0x0000 /* GAIN = 5 */ -#define GAIN_10 0x0004 /* GAIN = 1 */ -#define GAIN_20 0x0008 /* GAIN = 2 */ -#define GAIN_50 0x000C /* GAIN = 5 */ - -#define VLEV 0x00F0 /* Internal Voltage Level */ -#ifdef __ADSPBF52x__ -#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#else -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ -#endif - -#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ -#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ -#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ -#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */ -#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ -#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ -#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ -#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ -#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ - -#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ -#else -#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ -#endif - +#ifdef __KERNEL__ #ifndef __ASSEMBLY__ void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); @@ -156,5 +54,6 @@ struct bfin_dpmc_platform_data { w[P0 + (x - PLL_CTL)] = R0;\ #endif +#endif /* __KERNEL__ */ #endif /*_BLACKFIN_DPMC_H_*/ diff --git a/trunk/arch/blackfin/include/asm/elf.h b/trunk/arch/blackfin/include/asm/elf.h index 5b50f0ecacf8..8e0764c81eaf 100644 --- a/trunk/arch/blackfin/include/asm/elf.h +++ b/trunk/arch/blackfin/include/asm/elf.h @@ -55,6 +55,7 @@ do { \ _regs->p2 = _dynamic_addr; \ } while(0) +#define USE_ELF_CORE_DUMP #define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC #define ELF_EXEC_PAGESIZE 4096 diff --git a/trunk/arch/blackfin/include/asm/gpio.h b/trunk/arch/blackfin/include/asm/gpio.h index 539468a05057..5b44d05ca53e 100644 --- a/trunk/arch/blackfin/include/asm/gpio.h +++ b/trunk/arch/blackfin/include/asm/gpio.h @@ -159,11 +159,6 @@ struct gpio_port_t { }; #endif -#ifdef BFIN_SPECIAL_GPIO_BANKS -void bfin_special_gpio_free(unsigned gpio); -int bfin_special_gpio_request(unsigned gpio, const char *label); -#endif - #ifdef CONFIG_PM unsigned int bfin_pm_standby_setup(void); diff --git a/trunk/arch/blackfin/include/asm/gptimers.h b/trunk/arch/blackfin/include/asm/gptimers.h index c722acdda0d3..89f08decb8e0 100644 --- a/trunk/arch/blackfin/include/asm/gptimers.h +++ b/trunk/arch/blackfin/include/asm/gptimers.h @@ -172,25 +172,25 @@ /* The actual gptimer API */ -void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); -uint32_t get_gptimer_pwidth(unsigned int timer_id); -void set_gptimer_period(unsigned int timer_id, uint32_t period); -uint32_t get_gptimer_period(unsigned int timer_id); -uint32_t get_gptimer_count(unsigned int timer_id); -int get_gptimer_intr(unsigned int timer_id); -void clear_gptimer_intr(unsigned int timer_id); -int get_gptimer_over(unsigned int timer_id); -void clear_gptimer_over(unsigned int timer_id); -void set_gptimer_config(unsigned int timer_id, uint16_t config); -uint16_t get_gptimer_config(unsigned int timer_id); -int get_gptimer_run(unsigned int timer_id); -void set_gptimer_pulse_hi(unsigned int timer_id); -void clear_gptimer_pulse_hi(unsigned int timer_id); +void set_gptimer_pwidth(int timer_id, uint32_t width); +uint32_t get_gptimer_pwidth(int timer_id); +void set_gptimer_period(int timer_id, uint32_t period); +uint32_t get_gptimer_period(int timer_id); +uint32_t get_gptimer_count(int timer_id); +int get_gptimer_intr(int timer_id); +void clear_gptimer_intr(int timer_id); +int get_gptimer_over(int timer_id); +void clear_gptimer_over(int timer_id); +void set_gptimer_config(int timer_id, uint16_t config); +uint16_t get_gptimer_config(int timer_id); +int get_gptimer_run(int timer_id); +void set_gptimer_pulse_hi(int timer_id); +void clear_gptimer_pulse_hi(int timer_id); void enable_gptimers(uint16_t mask); void disable_gptimers(uint16_t mask); void disable_gptimers_sync(uint16_t mask); uint16_t get_enabled_gptimers(void); -uint32_t get_gptimer_status(unsigned int group); -void set_gptimer_status(unsigned int group, uint32_t value); +uint32_t get_gptimer_status(int group); +void set_gptimer_status(int group, uint32_t value); #endif diff --git a/trunk/arch/blackfin/include/asm/io.h b/trunk/arch/blackfin/include/asm/io.h index 29e55b9d88bc..d1f5029189a7 100644 --- a/trunk/arch/blackfin/include/asm/io.h +++ b/trunk/arch/blackfin/include/asm/io.h @@ -31,14 +31,12 @@ static inline unsigned char readb(const volatile void __iomem *addr) unsigned int val; int tmp; - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = b [%2] (z);" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); + __asm__ __volatile__ ("cli %1;\n\t" + "NOP; NOP; SSYNC;\n\t" + "%0 = b [%2] (z);\n\t" + "sti %1;\n\t" + : "=d"(val), "=d"(tmp): "a"(addr) + ); return (unsigned char) val; } @@ -48,14 +46,12 @@ static inline unsigned short readw(const volatile void __iomem *addr) unsigned int val; int tmp; - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = w [%2] (z);" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); + __asm__ __volatile__ ("cli %1;\n\t" + "NOP; NOP; SSYNC;\n\t" + "%0 = w [%2] (z);\n\t" + "sti %1;\n\t" + : "=d"(val), "=d"(tmp): "a"(addr) + ); return (unsigned short) val; } @@ -65,23 +61,20 @@ static inline unsigned int readl(const volatile void __iomem *addr) unsigned int val; int tmp; - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = [%2];" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); - + __asm__ __volatile__ ("cli %1;\n\t" + "NOP; NOP; SSYNC;\n\t" + "%0 = [%2];\n\t" + "sti %1;\n\t" + : "=d"(val), "=d"(tmp): "a"(addr) + ); return val; } #endif /* __ASSEMBLY__ */ -#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) +#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) #define __raw_readb readb #define __raw_readw readw @@ -89,9 +82,9 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel -#define memset_io(a, b, c) memset((void *)(a), (b), (c)) -#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) -#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) /* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ #define __io(port) ((void *)(unsigned long)(port)) @@ -99,30 +92,30 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define inb(port) readb(__io(port)) #define inw(port) readw(__io(port)) #define inl(port) readl(__io(port)) -#define outb(x, port) writeb(x, __io(port)) -#define outw(x, port) writew(x, __io(port)) -#define outl(x, port) writel(x, __io(port)) +#define outb(x,port) writeb(x,__io(port)) +#define outw(x,port) writew(x,__io(port)) +#define outl(x,port) writel(x,__io(port)) #define inb_p(port) inb(__io(port)) #define inw_p(port) inw(__io(port)) #define inl_p(port) inl(__io(port)) -#define outb_p(x, port) outb(x, __io(port)) -#define outw_p(x, port) outw(x, __io(port)) -#define outl_p(x, port) outl(x, __io(port)) - -#define ioread8_rep(a, d, c) readsb(a, d, c) -#define ioread16_rep(a, d, c) readsw(a, d, c) -#define ioread32_rep(a, d, c) readsl(a, d, c) -#define iowrite8_rep(a, s, c) writesb(a, s, c) -#define iowrite16_rep(a, s, c) writesw(a, s, c) -#define iowrite32_rep(a, s, c) writesl(a, s, c) - -#define ioread8(x) readb(x) -#define ioread16(x) readw(x) -#define ioread32(x) readl(x) -#define iowrite8(val, x) writeb(val, x) -#define iowrite16(val, x) writew(val, x) -#define iowrite32(val, x) writel(val, x) +#define outb_p(x,port) outb(x,__io(port)) +#define outw_p(x,port) outw(x,__io(port)) +#define outl_p(x,port) outl(x,__io(port)) + +#define ioread8_rep(a,d,c) readsb(a,d,c) +#define ioread16_rep(a,d,c) readsw(a,d,c) +#define ioread32_rep(a,d,c) readsl(a,d,c) +#define iowrite8_rep(a,s,c) writesb(a,s,c) +#define iowrite16_rep(a,s,c) writesw(a,s,c) +#define iowrite32_rep(a,s,c) writesl(a,s,c) + +#define ioread8(X) readb(X) +#define ioread16(X) readw(X) +#define ioread32(X) readl(X) +#define iowrite8(val,X) writeb(val,X) +#define iowrite16(val,X) writew(val,X) +#define iowrite32(val,X) writel(val,X) #define mmiowb() wmb() diff --git a/trunk/arch/blackfin/include/asm/ipipe.h b/trunk/arch/blackfin/include/asm/ipipe.h index d3b40449ca0e..4617ba66278f 100644 --- a/trunk/arch/blackfin/include/asm/ipipe.h +++ b/trunk/arch/blackfin/include/asm/ipipe.h @@ -35,9 +35,9 @@ #include #include -#define IPIPE_ARCH_STRING "1.12-00" +#define IPIPE_ARCH_STRING "1.11-00" #define IPIPE_MAJOR_NUMBER 1 -#define IPIPE_MINOR_NUMBER 12 +#define IPIPE_MINOR_NUMBER 11 #define IPIPE_PATCH_NUMBER 0 #ifdef CONFIG_SMP @@ -124,6 +124,16 @@ static inline int __ipipe_check_tickdev(const char *devname) return 1; } +static inline void __ipipe_lock_root(void) +{ + set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)); +} + +static inline void __ipipe_unlock_root(void) +{ + clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)); +} + void __ipipe_enable_pipeline(void); #define __ipipe_hook_critical_ipi(ipd) do { } while (0) diff --git a/trunk/arch/blackfin/include/asm/ipipe_base.h b/trunk/arch/blackfin/include/asm/ipipe_base.h index 00409201d9ed..490098f532a7 100644 --- a/trunk/arch/blackfin/include/asm/ipipe_base.h +++ b/trunk/arch/blackfin/include/asm/ipipe_base.h @@ -51,15 +51,23 @@ extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ -void __ipipe_stall_root(void); - -unsigned long __ipipe_test_and_stall_root(void); - -unsigned long __ipipe_test_root(void); - -void __ipipe_lock_root(void); - -void __ipipe_unlock_root(void); +#define __ipipe_stall_root() \ + do { \ + volatile unsigned long *p = &__ipipe_root_status; \ + set_bit(0, p); \ + } while (0) + +#define __ipipe_test_and_stall_root() \ + ({ \ + volatile unsigned long *p = &__ipipe_root_status; \ + test_and_set_bit(0, p); \ + }) + +#define __ipipe_test_root() \ + ({ \ + const unsigned long *p = &__ipipe_root_status; \ + test_bit(0, p); \ + }) #endif /* !__ASSEMBLY__ */ diff --git a/trunk/arch/blackfin/include/asm/irqflags.h b/trunk/arch/blackfin/include/asm/irqflags.h index 813a1af3e865..9b19a19d9ae9 100644 --- a/trunk/arch/blackfin/include/asm/irqflags.h +++ b/trunk/arch/blackfin/include/asm/irqflags.h @@ -33,7 +33,6 @@ static inline unsigned long bfin_cli(void) #ifdef CONFIG_IPIPE -#include #include #include @@ -50,12 +49,12 @@ static inline unsigned long bfin_cli(void) barrier(); \ } while (0) -#define raw_local_irq_enable() \ - do { \ - barrier(); \ - ipipe_check_context(ipipe_root_domain); \ - __ipipe_unstall_root(); \ - } while (0) +static inline void raw_local_irq_enable(void) +{ + barrier(); + ipipe_check_context(ipipe_root_domain); + __ipipe_unstall_root(); +} #define raw_local_save_flags_ptr(x) \ do { \ diff --git a/trunk/arch/blackfin/include/asm/kgdb.h b/trunk/arch/blackfin/include/asm/kgdb.h index 8651afe12990..c8b256d2ea30 100644 --- a/trunk/arch/blackfin/include/asm/kgdb.h +++ b/trunk/arch/blackfin/include/asm/kgdb.h @@ -10,6 +10,9 @@ #include +/* gdb locks */ +#define KGDB_MAX_NO_CPUS 8 + /* * BUFMAX defines the maximum number of characters in inbound/outbound buffers. * At least NUMREGBYTES*2 are needed for register packets. diff --git a/trunk/arch/blackfin/include/asm/mem_init.h b/trunk/arch/blackfin/include/asm/mem_init.h index 7c8fe834ff22..4179e329b9c9 100644 --- a/trunk/arch/blackfin/include/asm/mem_init.h +++ b/trunk/arch/blackfin/include/asm/mem_init.h @@ -295,3 +295,156 @@ #else #define PLL_BYPASS 0 #endif + +/***************************************Currently Not Being Used *********************************/ + +#if defined(CONFIG_FLASH_SPEED_BWAT) && \ +defined(CONFIG_FLASH_SPEED_BRAT) && \ +defined(CONFIG_FLASH_SPEED_BHT) && \ +defined(CONFIG_FLASH_SPEED_BST) && \ +defined(CONFIG_FLASH_SPEED_BTT) + +#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) +#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 + +#if (flash_EBIU_AMBCTL_TT > 3) +#define flash_EBIU_AMBCTL0_TT B0TT_4 +#endif +#if (flash_EBIU_AMBCTL_TT == 3) +#define flash_EBIU_AMBCTL0_TT B0TT_3 +#endif +#if (flash_EBIU_AMBCTL_TT == 2) +#define flash_EBIU_AMBCTL0_TT B0TT_2 +#endif +#if (flash_EBIU_AMBCTL_TT < 2) +#define flash_EBIU_AMBCTL0_TT B0TT_1 +#endif + +#if (flash_EBIU_AMBCTL_ST > 3) +#define flash_EBIU_AMBCTL0_ST B0ST_4 +#endif +#if (flash_EBIU_AMBCTL_ST == 3) +#define flash_EBIU_AMBCTL0_ST B0ST_3 +#endif +#if (flash_EBIU_AMBCTL_ST == 2) +#define flash_EBIU_AMBCTL0_ST B0ST_2 +#endif +#if (flash_EBIU_AMBCTL_ST < 2) +#define flash_EBIU_AMBCTL0_ST B0ST_1 +#endif + +#if (flash_EBIU_AMBCTL_HT > 2) +#define flash_EBIU_AMBCTL0_HT B0HT_3 +#endif +#if (flash_EBIU_AMBCTL_HT == 2) +#define flash_EBIU_AMBCTL0_HT B0HT_2 +#endif +#if (flash_EBIU_AMBCTL_HT == 1) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) +#define flash_EBIU_AMBCTL0_HT B0HT_0 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif + +#if (flash_EBIU_AMBCTL_WAT > 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_15 +#endif +#if (flash_EBIU_AMBCTL_WAT == 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_14 +#endif +#if (flash_EBIU_AMBCTL_WAT == 13) +#define flash_EBIU_AMBCTL0_WAT B0WAT_13 +#endif +#if (flash_EBIU_AMBCTL_WAT == 12) +#define flash_EBIU_AMBCTL0_WAT B0WAT_12 +#endif +#if (flash_EBIU_AMBCTL_WAT == 11) +#define flash_EBIU_AMBCTL0_WAT B0WAT_11 +#endif +#if (flash_EBIU_AMBCTL_WAT == 10) +#define flash_EBIU_AMBCTL0_WAT B0WAT_10 +#endif +#if (flash_EBIU_AMBCTL_WAT == 9) +#define flash_EBIU_AMBCTL0_WAT B0WAT_9 +#endif +#if (flash_EBIU_AMBCTL_WAT == 8) +#define flash_EBIU_AMBCTL0_WAT B0WAT_8 +#endif +#if (flash_EBIU_AMBCTL_WAT == 7) +#define flash_EBIU_AMBCTL0_WAT B0WAT_7 +#endif +#if (flash_EBIU_AMBCTL_WAT == 6) +#define flash_EBIU_AMBCTL0_WAT B0WAT_6 +#endif +#if (flash_EBIU_AMBCTL_WAT == 5) +#define flash_EBIU_AMBCTL0_WAT B0WAT_5 +#endif +#if (flash_EBIU_AMBCTL_WAT == 4) +#define flash_EBIU_AMBCTL0_WAT B0WAT_4 +#endif +#if (flash_EBIU_AMBCTL_WAT == 3) +#define flash_EBIU_AMBCTL0_WAT B0WAT_3 +#endif +#if (flash_EBIU_AMBCTL_WAT == 2) +#define flash_EBIU_AMBCTL0_WAT B0WAT_2 +#endif +#if (flash_EBIU_AMBCTL_WAT == 1) +#define flash_EBIU_AMBCTL0_WAT B0WAT_1 +#endif + +#if (flash_EBIU_AMBCTL_RAT > 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_15 +#endif +#if (flash_EBIU_AMBCTL_RAT == 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_14 +#endif +#if (flash_EBIU_AMBCTL_RAT == 13) +#define flash_EBIU_AMBCTL0_RAT B0RAT_13 +#endif +#if (flash_EBIU_AMBCTL_RAT == 12) +#define flash_EBIU_AMBCTL0_RAT B0RAT_12 +#endif +#if (flash_EBIU_AMBCTL_RAT == 11) +#define flash_EBIU_AMBCTL0_RAT B0RAT_11 +#endif +#if (flash_EBIU_AMBCTL_RAT == 10) +#define flash_EBIU_AMBCTL0_RAT B0RAT_10 +#endif +#if (flash_EBIU_AMBCTL_RAT == 9) +#define flash_EBIU_AMBCTL0_RAT B0RAT_9 +#endif +#if (flash_EBIU_AMBCTL_RAT == 8) +#define flash_EBIU_AMBCTL0_RAT B0RAT_8 +#endif +#if (flash_EBIU_AMBCTL_RAT == 7) +#define flash_EBIU_AMBCTL0_RAT B0RAT_7 +#endif +#if (flash_EBIU_AMBCTL_RAT == 6) +#define flash_EBIU_AMBCTL0_RAT B0RAT_6 +#endif +#if (flash_EBIU_AMBCTL_RAT == 5) +#define flash_EBIU_AMBCTL0_RAT B0RAT_5 +#endif +#if (flash_EBIU_AMBCTL_RAT == 4) +#define flash_EBIU_AMBCTL0_RAT B0RAT_4 +#endif +#if (flash_EBIU_AMBCTL_RAT == 3) +#define flash_EBIU_AMBCTL0_RAT B0RAT_3 +#endif +#if (flash_EBIU_AMBCTL_RAT == 2) +#define flash_EBIU_AMBCTL0_RAT B0RAT_2 +#endif +#if (flash_EBIU_AMBCTL_RAT == 1) +#define flash_EBIU_AMBCTL0_RAT B0RAT_1 +#endif + +#define flash_EBIU_AMBCTL0 \ + (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ + flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) +#endif diff --git a/trunk/arch/blackfin/include/asm/mmu_context.h b/trunk/arch/blackfin/include/asm/mmu_context.h index ae8ef4ffd806..4a3be376ad5b 100644 --- a/trunk/arch/blackfin/include/asm/mmu_context.h +++ b/trunk/arch/blackfin/include/asm/mmu_context.h @@ -66,8 +66,8 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base) #define activate_mm(prev, next) switch_mm(prev, next, NULL) -static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, - struct task_struct *tsk) +static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, + struct task_struct *tsk) { #ifdef CONFIG_MPU unsigned int cpu = smp_processor_id(); @@ -95,24 +95,7 @@ static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next #endif } -#ifdef CONFIG_IPIPE -#define lock_mm_switch(flags) local_irq_save_hw_cond(flags) -#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags) -#else -#define lock_mm_switch(flags) do { (void)(flags); } while (0) -#define unlock_mm_switch(flags) do { (void)(flags); } while (0) -#endif /* CONFIG_IPIPE */ - #ifdef CONFIG_MPU -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - unsigned long flags; - lock_mm_switch(flags); - __switch_mm(prev, next, tsk); - unlock_mm_switch(flags); -} - static inline void protect_page(struct mm_struct *mm, unsigned long addr, unsigned long flags) { @@ -145,12 +128,6 @@ static inline void update_protections(struct mm_struct *mm) set_mask_dcplbs(mm->context.page_rwx_mask, cpu); } } -#else /* !CONFIG_MPU */ -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - __switch_mm(prev, next, tsk); -} #endif static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) @@ -196,10 +173,4 @@ static inline void destroy_context(struct mm_struct *mm) #endif } -#define ipipe_mm_switch_protect(flags) \ - local_irq_save_hw_cond(flags) - -#define ipipe_mm_switch_unprotect(flags) \ - local_irq_restore_hw_cond(flags) - #endif diff --git a/trunk/arch/blackfin/include/asm/module.h b/trunk/arch/blackfin/include/asm/module.h index 4282b169ead9..9c1cfffddd9b 100644 --- a/trunk/arch/blackfin/include/asm/module.h +++ b/trunk/arch/blackfin/include/asm/module.h @@ -7,6 +7,8 @@ #ifndef _ASM_BFIN_MODULE_H #define _ASM_BFIN_MODULE_H +#define MODULE_SYMBOL_PREFIX "_" + #define Elf_Shdr Elf32_Shdr #define Elf_Sym Elf32_Sym #define Elf_Ehdr Elf32_Ehdr diff --git a/trunk/arch/blackfin/include/asm/pci.h b/trunk/arch/blackfin/include/asm/pci.h index 99cae2e3bac7..61277358c865 100644 --- a/trunk/arch/blackfin/include/asm/pci.h +++ b/trunk/arch/blackfin/include/asm/pci.h @@ -4,19 +4,145 @@ #define _ASM_BFIN_PCI_H #include -#include -#include +/* + * + * Written by Wout Klaren. + */ + +/* Added by Chang Junxiao */ #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x10000000 +#define PCI_DMA_BUS_IS_PHYS (1) +struct pci_ops; + +/* + * Structure with hardware dependent information and functions of the + * PCI bus. + */ +struct pci_bus_info { + + /* + * Resources of the PCI bus. + */ + struct resource mem_space; + struct resource io_space; + + /* + * System dependent functions. + */ + struct pci_ops *bfin_pci_ops; + void (*fixup) (int pci_modify); + void (*conf_device) (unsigned char bus, unsigned char device_fn); +}; + +#define pcibios_assign_all_busses() 0 static inline void pcibios_set_master(struct pci_dev *dev) { + /* No special bus mastering setup handling */ } static inline void pcibios_penalize_isa_irq(int irq) { + /* We don't do dynamic PCI IRQ allocation */ } +static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, + size_t size, int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* return virt_to_bus(ptr); */ + return (dma_addr_t) ptr; +} + +/* Unmap a single streaming mode DMA translation. The dma_addr and size + * must match what was provided for in a previous pci_map_single call. All + * other usages are undefined. + * + * After this call, reads by the cpu to the buffer are guarenteed to see + * whatever the device wrote there. + */ +static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, + size_t size, int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* Nothing to do */ +} + +/* Map a set of buffers described by scatterlist in streaming + * mode for DMA. This is the scather-gather version of the + * above pci_map_single interface. Here the scatter gather list + * elements are each tagged with the appropriate dma address + * and length. They are obtained via sg_dma_{address,length}(SG). + * + * NOTE: An implementation may be able to use a smaller number of + * DMA address/length pairs than there are SG table elements. + * (for example via virtual mapping capabilities) + * The routine returns the number of addr/length pairs actually + * used, at most nents. + * + * Device ownership issues as mentioned above for pci_map_single are + * the same here. + */ +static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + return nents; +} + +/* Unmap a set of streaming mode DMA translations. + * Again, cpu read rules concerning calls here are the same as for + * pci_unmap_single() above. + */ +static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* Nothing to do */ +} + +/* Make physical memory consistent for a single + * streaming mode DMA translation after a transfer. + * + * If you perform a pci_map_single() but wish to interrogate the + * buffer using the cpu, yet do not wish to teardown the PCI dma + * mapping, you must call this function before doing so. At the + * next point you give the PCI dma address back to the card, the + * device again owns the buffer. + */ +static inline void pci_dma_sync_single(struct pci_dev *hwdev, + dma_addr_t dma_handle, size_t size, + int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* Nothing to do */ +} + +/* Make physical memory consistent for a set of streaming + * mode DMA translations after a transfer. + * + * The same as pci_dma_sync_single but for a scatter-gather list, + * same rules and usage. + */ +static inline void pci_dma_sync_sg(struct pci_dev *hwdev, + struct scatterlist *sg, int nelems, + int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* Nothing to do */ +} #endif /* _ASM_BFIN_PCI_H */ diff --git a/trunk/arch/blackfin/include/asm/ptrace.h b/trunk/arch/blackfin/include/asm/ptrace.h index b33a4488f498..27290c955a7a 100644 --- a/trunk/arch/blackfin/include/asm/ptrace.h +++ b/trunk/arch/blackfin/include/asm/ptrace.h @@ -89,9 +89,9 @@ struct pt_regs { #define PTRACE_GETREGS 12 #define PTRACE_SETREGS 13 /* ptrace signal */ -#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ -#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ -#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ +#define PTRACE_GETFDPIC 31 +#define PTRACE_GETFDPIC_EXEC 0 +#define PTRACE_GETFDPIC_INTERP 1 #define PS_S (0x0002) diff --git a/trunk/arch/blackfin/include/asm/sections.h b/trunk/arch/blackfin/include/asm/sections.h index 42f6c53c59c6..1f5381fbb4a7 100644 --- a/trunk/arch/blackfin/include/asm/sections.h +++ b/trunk/arch/blackfin/include/asm/sections.h @@ -13,18 +13,10 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; extern unsigned long _ramstart, _ramend, _rambase; extern unsigned long memory_start, memory_end, physical_mem_end; -/* - * The weak markings on the lengths might seem weird, but this is required - * in order to make gcc accept the fact that these may actually have a value - * of 0 (since they aren't actually addresses, but sizes of sections). - */ -extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[]; -extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[], - _data_l1_lma[], __weak _data_l1_len[]; -extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], - _data_b_l1_lma[], __weak _data_b_l1_len[]; -extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], - _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[]; +extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], + _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], + _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], + _ebss_l2[], _l2_lma_start[]; #include diff --git a/trunk/arch/blackfin/include/asm/thread_info.h b/trunk/arch/blackfin/include/asm/thread_info.h index a40d9368c38a..afb3a8626380 100644 --- a/trunk/arch/blackfin/include/asm/thread_info.h +++ b/trunk/arch/blackfin/include/asm/thread_info.h @@ -103,13 +103,11 @@ static inline struct thread_info *current_thread_info(void) #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ #define TIF_FREEZE 6 /* is freezing for suspend */ #define TIF_IRQ_SYNC 7 /* sync pipeline stage */ -#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */ /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1< #include -#include +#ifdef CONFIG_ACCESS_CHECK +# include +#endif #define get_ds() (KERNEL_DS) #define get_fs() (current_thread_info()->addr_limit) diff --git a/trunk/arch/blackfin/include/asm/unistd.h b/trunk/arch/blackfin/include/asm/unistd.h index 22886cbdae7a..779be02a910a 100644 --- a/trunk/arch/blackfin/include/asm/unistd.h +++ b/trunk/arch/blackfin/include/asm/unistd.h @@ -388,9 +388,8 @@ #define __NR_pwritev 367 #define __NR_rt_tgsigqueueinfo 368 #define __NR_perf_event_open 369 -#define __NR_recvmmsg 370 -#define __NR_syscall 371 +#define __NR_syscall 370 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ diff --git a/trunk/arch/blackfin/kernel/bfin_dma_5xx.c b/trunk/arch/blackfin/kernel/bfin_dma_5xx.c index 924c00286bab..3946aff4f414 100644 --- a/trunk/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/trunk/arch/blackfin/kernel/bfin_dma_5xx.c @@ -37,8 +37,9 @@ static int __init blackfin_dma_init(void) printk(KERN_INFO "Blackfin DMA Controller\n"); for (i = 0; i < MAX_DMA_CHANNELS; i++) { - atomic_set(&dma_ch[i].chan_status, 0); + dma_ch[i].chan_status = DMA_CHANNEL_FREE; dma_ch[i].regs = dma_io_base_addr[i]; + mutex_init(&(dma_ch[i].dmalock)); } /* Mark MEMDMA Channel 0 as requested since we're using it internally */ request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); @@ -59,7 +60,7 @@ static int proc_dma_show(struct seq_file *m, void *v) int i; for (i = 0; i < MAX_DMA_CHANNELS; ++i) - if (dma_channel_active(i)) + if (dma_ch[i].chan_status != DMA_CHANNEL_FREE) seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id); return 0; @@ -106,11 +107,20 @@ int request_dma(unsigned int channel, const char *device_id) } #endif - if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) { + mutex_lock(&(dma_ch[channel].dmalock)); + + if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED) + || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) { + mutex_unlock(&(dma_ch[channel].dmalock)); pr_debug("DMA CHANNEL IN USE \n"); return -EBUSY; + } else { + dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED; + pr_debug("DMA CHANNEL IS ALLOCATED \n"); } + mutex_unlock(&(dma_ch[channel].dmalock)); + #ifdef CONFIG_BF54x if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) { unsigned int per_map; @@ -138,20 +148,21 @@ EXPORT_SYMBOL(request_dma); int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) { - int ret; - unsigned int irq; - - BUG_ON(channel >= MAX_DMA_CHANNELS || !callback || - !atomic_read(&dma_ch[channel].chan_status)); + BUG_ON(channel >= MAX_DMA_CHANNELS || + dma_ch[channel].chan_status == DMA_CHANNEL_FREE); - irq = channel2irq(channel); - ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data); - if (ret) - return ret; + if (callback != NULL) { + int ret; + unsigned int irq = channel2irq(channel); - dma_ch[channel].irq = irq; - dma_ch[channel].data = data; + ret = request_irq(irq, callback, IRQF_DISABLED, + dma_ch[channel].device_id, data); + if (ret) + return ret; + dma_ch[channel].irq = irq; + dma_ch[channel].data = data; + } return 0; } EXPORT_SYMBOL(set_dma_callback); @@ -173,7 +184,7 @@ void free_dma(unsigned int channel) { pr_debug("freedma() : BEGIN \n"); BUG_ON(channel >= MAX_DMA_CHANNELS || - !atomic_read(&dma_ch[channel].chan_status)); + dma_ch[channel].chan_status == DMA_CHANNEL_FREE); /* Halt the DMA */ disable_dma(channel); @@ -183,7 +194,9 @@ void free_dma(unsigned int channel) free_irq(dma_ch[channel].irq, dma_ch[channel].data); /* Clear the DMA Variable in the Channel */ - atomic_set(&dma_ch[channel].chan_status, 0); + mutex_lock(&(dma_ch[channel].dmalock)); + dma_ch[channel].chan_status = DMA_CHANNEL_FREE; + mutex_unlock(&(dma_ch[channel].dmalock)); pr_debug("freedma() : END \n"); } @@ -197,14 +210,13 @@ int blackfin_dma_suspend(void) { int i; - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - if (dma_ch[i].regs->cfg & DMAEN) { + for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) { + if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) { printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); return -EBUSY; } - if (i < MAX_DMA_SUSPEND_CHANNELS) - dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; + dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; } return 0; diff --git a/trunk/arch/blackfin/kernel/bfin_gpio.c b/trunk/arch/blackfin/kernel/bfin_gpio.c index a174596cc009..22705eeff34f 100644 --- a/trunk/arch/blackfin/kernel/bfin_gpio.c +++ b/trunk/arch/blackfin/kernel/bfin_gpio.c @@ -100,12 +100,6 @@ u8 pmux_offset[][16] = { }; # endif -#elif defined(BF538_FAMILY) -static unsigned short * const port_fer[] = { - (unsigned short *) PORTCIO_FER, - (unsigned short *) PORTDIO_FER, - (unsigned short *) PORTEIO_FER, -}; #endif static unsigned short reserved_gpio_map[GPIO_BANK_NUM]; @@ -169,27 +163,6 @@ static int cmp_label(unsigned short ident, const char *label) static void port_setup(unsigned gpio, unsigned short usage) { -#if defined(BF538_FAMILY) - /* - * BF538/9 Port C,D and E are special. - * Inverted PORT_FER polarity on CDE and no PORF_FER on F - * Regular PORT F GPIOs are handled here, CDE are exclusively - * managed by GPIOLIB - */ - - if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES) - return; - - gpio -= MAX_BLACKFIN_GPIOS; - - if (usage == GPIO_USAGE) - *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); - else - *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); - SSYNC(); - return; -#endif - if (check_gpio(gpio)) return; @@ -789,8 +762,6 @@ int peripheral_request(unsigned short per, const char *label) if (!(per & P_DEFINED)) return -ENODEV; - BUG_ON(ident >= MAX_RESOURCES); - local_irq_save_hw(flags); /* If a pin can be muxed as either GPIO or peripheral, make @@ -1008,76 +979,6 @@ void bfin_gpio_free(unsigned gpio) } EXPORT_SYMBOL(bfin_gpio_free); -#ifdef BFIN_SPECIAL_GPIO_BANKS -static unsigned short reserved_special_gpio_map[gpio_bank(MAX_RESOURCES)]; - -int bfin_special_gpio_request(unsigned gpio, const char *label) -{ - unsigned long flags; - - local_irq_save_hw(flags); - - /* - * Allow that the identical GPIO can - * be requested from the same driver twice - * Do nothing and return - - */ - - if (cmp_label(gpio, label) == 0) { - local_irq_restore_hw(flags); - return 0; - } - - if (unlikely(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { - local_irq_restore_hw(flags); - printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", - gpio, get_label(gpio)); - - return -EBUSY; - } - if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { - local_irq_restore_hw(flags); - printk(KERN_ERR - "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", - gpio, get_label(gpio)); - - return -EBUSY; - } - - reserved_special_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); - reserved_peri_map[gpio_bank(gpio)] |= gpio_bit(gpio); - - set_label(gpio, label); - local_irq_restore_hw(flags); - port_setup(gpio, GPIO_USAGE); - - return 0; -} -EXPORT_SYMBOL(bfin_special_gpio_request); - -void bfin_special_gpio_free(unsigned gpio) -{ - unsigned long flags; - - might_sleep(); - - local_irq_save_hw(flags); - - if (unlikely(!(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { - gpio_error(gpio); - local_irq_restore_hw(flags); - return; - } - - reserved_special_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); - reserved_peri_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); - set_label(gpio, "free"); - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(bfin_special_gpio_free); -#endif - - int bfin_gpio_irq_request(unsigned gpio, const char *label) { unsigned long flags; diff --git a/trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c index 8d42b9e50dfa..b52c1f8c4bc0 100644 --- a/trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c @@ -92,6 +92,6 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) icplb_tbl[cpu][i_i++].data = 0; } -void __init generate_cplb_tables_all(void) +void generate_cplb_tables_all(void) { } diff --git a/trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 930c01c06813..69e0e530d70f 100644 --- a/trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu) addr = L2_START; d_data = L2_DMEMORY; } else if (addr >= physical_mem_end) { - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { - addr &= ~(4 * 1024 * 1024 - 1); + if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE + && (status & FAULT_USERSUPV)) { + addr &= ~0x3fffff; d_data &= ~PAGE_SIZE_4KB; d_data |= PAGE_SIZE_4MB; - d_data |= CPLB_USER_RD | CPLB_USER_WR; } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { addr &= ~(1 * 1024 * 1024 - 1); @@ -203,12 +203,7 @@ static noinline int icplb_miss(unsigned int cpu) addr = L2_START; i_data = L2_IMEMORY; } else if (addr >= physical_mem_end) { - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { - addr &= ~(4 * 1024 * 1024 - 1); - i_data &= ~PAGE_SIZE_4KB; - i_data |= PAGE_SIZE_4MB; - i_data |= CPLB_USER_RD; - } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH + if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & FAULT_USERSUPV)) { addr &= ~(1 * 1024 * 1024 - 1); i_data &= ~PAGE_SIZE_4KB; diff --git a/trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 282a7919821b..fd9a2f31e686 100644 --- a/trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -89,25 +89,15 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) void __init generate_cplb_tables_all(void) { - unsigned long uncached_end; int i_d, i_i; i_d = 0; /* Normal RAM, including MTD FS. */ #ifdef CONFIG_MTD_UCLINUX - uncached_end = memory_mtd_start + mtd_size; + dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size; #else - uncached_end = memory_end; + dcplb_bounds[i_d].eaddr = memory_end; #endif - /* - * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached - * so that we don't have to use 4kB pages and cause CPLB thrashing - */ - if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION || - ((_ramend - uncached_end) >= 1 * 1024 * 1024)) - dcplb_bounds[i_d].eaddr = uncached_end; - else - dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024); dcplb_bounds[i_d++].data = SDRAM_DGENERIC; /* DMA uncached region. */ if (DMA_UNCACHED_REGION) { @@ -145,15 +135,18 @@ void __init generate_cplb_tables_all(void) i_i = 0; /* Normal RAM, including MTD FS. */ - icplb_bounds[i_i].eaddr = uncached_end; +#ifdef CONFIG_MTD_UCLINUX + icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size; +#else + icplb_bounds[i_i].eaddr = memory_end; +#endif icplb_bounds[i_i++].data = SDRAM_IGENERIC; + /* DMA uncached region. */ + if (DMA_UNCACHED_REGION) { + icplb_bounds[i_i].eaddr = _ramend; + icplb_bounds[i_i++].data = 0; + } if (_ramend != physical_mem_end) { - /* DMA uncached region. */ - if (DMA_UNCACHED_REGION) { - /* Normally this hole is caught by the async below. */ - icplb_bounds[i_i].eaddr = _ramend; - icplb_bounds[i_i++].data = 0; - } /* Reserved memory. */ icplb_bounds[i_i].eaddr = physical_mem_end; icplb_bounds[i_i++].data = (reserved_mem_icache_on ? diff --git a/trunk/arch/blackfin/kernel/dma-mapping.c b/trunk/arch/blackfin/kernel/dma-mapping.c index e937f323d82c..e74e74d7733f 100644 --- a/trunk/arch/blackfin/kernel/dma-mapping.c +++ b/trunk/arch/blackfin/kernel/dma-mapping.c @@ -7,25 +7,30 @@ */ #include -#include +#include #include +#include #include +#include #include +#include #include +#include +#include static spinlock_t dma_page_lock; -static unsigned long *dma_page; +static unsigned int *dma_page; static unsigned int dma_pages; static unsigned long dma_base; static unsigned long dma_size; static unsigned int dma_initialized; -static void dma_alloc_init(unsigned long start, unsigned long end) +void dma_alloc_init(unsigned long start, unsigned long end) { spin_lock_init(&dma_page_lock); dma_initialized = 0; - dma_page = (unsigned long *)__get_free_page(GFP_KERNEL); + dma_page = (unsigned int *)__get_free_page(GFP_KERNEL); memset(dma_page, 0, PAGE_SIZE); dma_base = PAGE_ALIGN(start); dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start); @@ -53,11 +58,10 @@ static unsigned long __alloc_dma_pages(unsigned int pages) spin_lock_irqsave(&dma_page_lock, flags); for (i = 0; i < dma_pages;) { - if (test_bit(i++, dma_page) == 0) { + if (dma_page[i++] == 0) { if (++count == pages) { while (count--) - __set_bit(--i, dma_page); - + dma_page[--i] = 1; ret = dma_base + (i << PAGE_SHIFT); break; } @@ -80,14 +84,14 @@ static void __free_dma_pages(unsigned long addr, unsigned int pages) } spin_lock_irqsave(&dma_page_lock, flags); - for (i = page; i < page + pages; i++) - __clear_bit(i, dma_page); - + for (i = page; i < page + pages; i++) { + dma_page[i] = 0; + } spin_unlock_irqrestore(&dma_page_lock, flags); } void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) + dma_addr_t * dma_handle, gfp_t gfp) { void *ret; @@ -111,14 +115,21 @@ dma_free_coherent(struct device *dev, size_t size, void *vaddr, EXPORT_SYMBOL(dma_free_coherent); /* - * Streaming DMA mappings + * Dummy functions defined for some existing drivers */ -void __dma_sync(dma_addr_t addr, size_t size, - enum dma_data_direction dir) + +dma_addr_t +dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction) { - _dma_sync(addr, size, dir); + BUG_ON(direction == DMA_NONE); + + invalidate_dcache_range((unsigned long)ptr, + (unsigned long)ptr + size); + + return (dma_addr_t) ptr; } -EXPORT_SYMBOL(__dma_sync); +EXPORT_SYMBOL(dma_map_single); int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, @@ -126,23 +137,30 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, { int i; + BUG_ON(direction == DMA_NONE); + for (i = 0; i < nents; i++, sg++) { sg->dma_address = (dma_addr_t) sg_virt(sg); - __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); + + invalidate_dcache_range(sg_dma_address(sg), + sg_dma_address(sg) + + sg_dma_len(sg)); } return nents; } EXPORT_SYMBOL(dma_map_sg); -void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, - int nelems, enum dma_data_direction direction) +void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction) { - int i; + BUG_ON(direction == DMA_NONE); +} +EXPORT_SYMBOL(dma_unmap_single); - for (i = 0; i < nelems; i++, sg++) { - sg->dma_address = (dma_addr_t) sg_virt(sg); - __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); - } +void dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); } -EXPORT_SYMBOL(dma_sync_sg_for_device); +EXPORT_SYMBOL(dma_unmap_sg); diff --git a/trunk/arch/blackfin/kernel/gptimers.c b/trunk/arch/blackfin/kernel/gptimers.c index cdbe075de1dc..7281a91d26b5 100644 --- a/trunk/arch/blackfin/kernel/gptimers.c +++ b/trunk/arch/blackfin/kernel/gptimers.c @@ -137,7 +137,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] = #endif }; -void set_gptimer_pwidth(unsigned int timer_id, uint32_t value) +void set_gptimer_pwidth(int timer_id, uint32_t value) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->width = value; @@ -145,14 +145,14 @@ void set_gptimer_pwidth(unsigned int timer_id, uint32_t value) } EXPORT_SYMBOL(set_gptimer_pwidth); -uint32_t get_gptimer_pwidth(unsigned int timer_id) +uint32_t get_gptimer_pwidth(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return timer_regs[timer_id]->width; } EXPORT_SYMBOL(get_gptimer_pwidth); -void set_gptimer_period(unsigned int timer_id, uint32_t period) +void set_gptimer_period(int timer_id, uint32_t period) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->period = period; @@ -160,28 +160,28 @@ void set_gptimer_period(unsigned int timer_id, uint32_t period) } EXPORT_SYMBOL(set_gptimer_period); -uint32_t get_gptimer_period(unsigned int timer_id) +uint32_t get_gptimer_period(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return timer_regs[timer_id]->period; } EXPORT_SYMBOL(get_gptimer_period); -uint32_t get_gptimer_count(unsigned int timer_id) +uint32_t get_gptimer_count(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return timer_regs[timer_id]->counter; } EXPORT_SYMBOL(get_gptimer_count); -uint32_t get_gptimer_status(unsigned int group) +uint32_t get_gptimer_status(int group) { tassert(group < BFIN_TIMER_NUM_GROUP); return group_regs[group]->status; } EXPORT_SYMBOL(get_gptimer_status); -void set_gptimer_status(unsigned int group, uint32_t value) +void set_gptimer_status(int group, uint32_t value) { tassert(group < BFIN_TIMER_NUM_GROUP); group_regs[group]->status = value; @@ -189,42 +189,42 @@ void set_gptimer_status(unsigned int group, uint32_t value) } EXPORT_SYMBOL(set_gptimer_status); -int get_gptimer_intr(unsigned int timer_id) +int get_gptimer_intr(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_intr); -void clear_gptimer_intr(unsigned int timer_id) +void clear_gptimer_intr(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id]; } EXPORT_SYMBOL(clear_gptimer_intr); -int get_gptimer_over(unsigned int timer_id) +int get_gptimer_over(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_over); -void clear_gptimer_over(unsigned int timer_id) +void clear_gptimer_over(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id]; } EXPORT_SYMBOL(clear_gptimer_over); -int get_gptimer_run(unsigned int timer_id) +int get_gptimer_run(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_run); -void set_gptimer_config(unsigned int timer_id, uint16_t config) +void set_gptimer_config(int timer_id, uint16_t config) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->config = config; @@ -232,7 +232,7 @@ void set_gptimer_config(unsigned int timer_id, uint16_t config) } EXPORT_SYMBOL(set_gptimer_config); -uint16_t get_gptimer_config(unsigned int timer_id) +uint16_t get_gptimer_config(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return timer_regs[timer_id]->config; @@ -280,7 +280,7 @@ void disable_gptimers_sync(uint16_t mask) } EXPORT_SYMBOL(disable_gptimers_sync); -void set_gptimer_pulse_hi(unsigned int timer_id) +void set_gptimer_pulse_hi(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->config |= TIMER_PULSE_HI; @@ -288,7 +288,7 @@ void set_gptimer_pulse_hi(unsigned int timer_id) } EXPORT_SYMBOL(set_gptimer_pulse_hi); -void clear_gptimer_pulse_hi(unsigned int timer_id) +void clear_gptimer_pulse_hi(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->config &= ~TIMER_PULSE_HI; diff --git a/trunk/arch/blackfin/kernel/ipipe.c b/trunk/arch/blackfin/kernel/ipipe.c index a77307a4473b..5d7382396dc0 100644 --- a/trunk/arch/blackfin/kernel/ipipe.c +++ b/trunk/arch/blackfin/kernel/ipipe.c @@ -335,70 +335,3 @@ void __ipipe_enable_root_irqs_hw(void) __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); bfin_sti(bfin_irq_flags); } - -/* - * We could use standard atomic bitops in the following root status - * manipulation routines, but let's prepare for SMP support in the - * same move, preventing CPU migration as required. - */ -void __ipipe_stall_root(void) -{ - unsigned long *p, flags; - - local_irq_save_hw(flags); - p = &__ipipe_root_status; - __set_bit(IPIPE_STALL_FLAG, p); - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(__ipipe_stall_root); - -unsigned long __ipipe_test_and_stall_root(void) -{ - unsigned long *p, flags; - int x; - - local_irq_save_hw(flags); - p = &__ipipe_root_status; - x = __test_and_set_bit(IPIPE_STALL_FLAG, p); - local_irq_restore_hw(flags); - - return x; -} -EXPORT_SYMBOL(__ipipe_test_and_stall_root); - -unsigned long __ipipe_test_root(void) -{ - const unsigned long *p; - unsigned long flags; - int x; - - local_irq_save_hw_smp(flags); - p = &__ipipe_root_status; - x = test_bit(IPIPE_STALL_FLAG, p); - local_irq_restore_hw_smp(flags); - - return x; -} -EXPORT_SYMBOL(__ipipe_test_root); - -void __ipipe_lock_root(void) -{ - unsigned long *p, flags; - - local_irq_save_hw(flags); - p = &__ipipe_root_status; - __set_bit(IPIPE_SYNCDEFER_FLAG, p); - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(__ipipe_lock_root); - -void __ipipe_unlock_root(void) -{ - unsigned long *p, flags; - - local_irq_save_hw(flags); - p = &__ipipe_root_status; - __clear_bit(IPIPE_SYNCDEFER_FLAG, p); - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(__ipipe_unlock_root); diff --git a/trunk/arch/blackfin/kernel/kgdb.c b/trunk/arch/blackfin/kernel/kgdb.c index f1036b6b9293..cce79d05b90b 100644 --- a/trunk/arch/blackfin/kernel/kgdb.c +++ b/trunk/arch/blackfin/kernel/kgdb.c @@ -24,6 +24,16 @@ #include #include +/* Put the error code here just in case the user cares. */ +int gdb_bfin_errcode; +/* Likewise, the vector number here (since GDB only gets the signal + number through the usual means, and that's not very specific). */ +int gdb_bfin_vector = -1; + +#if KGDB_MAX_NO_CPUS != 8 +#error change the definition of slavecpulocks +#endif + void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) { gdb_regs[BFIN_R0] = regs->r0; @@ -359,6 +369,13 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags) } #endif +void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code) +{ + /* Master processor is completely in the debugger */ + gdb_bfin_vector = eVector; + gdb_bfin_errcode = err_code; +} + int kgdb_arch_handle_exception(int vector, int signo, int err_code, char *remcom_in_buffer, char *remcom_out_buffer, diff --git a/trunk/arch/blackfin/kernel/kgdb_test.c b/trunk/arch/blackfin/kernel/kgdb_test.c index 9a4b07594389..59fc42dc5d6a 100644 --- a/trunk/arch/blackfin/kernel/kgdb_test.c +++ b/trunk/arch/blackfin/kernel/kgdb_test.c @@ -17,9 +17,8 @@ #include -/* Symbols are here for kgdb test to poke directly */ static char cmdline[256]; -static size_t len; +static unsigned long len; #ifndef CONFIG_SMP static int num1 __attribute__((l1_data)); @@ -28,10 +27,11 @@ void kgdb_l1_test(void) __attribute__((l1_text)); void kgdb_l1_test(void) { - pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); - pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test); - num1 = num1 + 10; - pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); + printk(KERN_ALERT "L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); + printk(KERN_ALERT "L1 : code function addr = 0x%p\n", kgdb_l1_test); + num1 = num1 + 10 ; + printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); + return ; } #endif @@ -42,10 +42,11 @@ void kgdb_l2_test(void) __attribute__((l2)); void kgdb_l2_test(void) { - pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); - pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test); - num2 = num2 + 20; - pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); + printk(KERN_ALERT "L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); + printk(KERN_ALERT "L2 : code function addr = 0x%p\n", kgdb_l2_test); + num2 = num2 + 20 ; + printk(KERN_ALERT "L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); + return ; } #endif @@ -53,14 +54,12 @@ void kgdb_l2_test(void) int kgdb_test(char *name, int len, int count, int z) { - pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z); + printk(KERN_ALERT "kgdb name(%d): %s, %d, %d\n", len, name, count, z); count = z; return count; } -static ssize_t -kgdb_test_proc_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos) +static int test_proc_output(char *buf) { kgdb_test("hello world!", 12, 0x55, 0x10); #ifndef CONFIG_SMP @@ -73,31 +72,49 @@ kgdb_test_proc_read(struct file *file, char __user *buf, return 0; } -static ssize_t -kgdb_test_proc_write(struct file *file, const char __user *buffer, - size_t count, loff_t *pos) +static int test_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) { - len = min_t(size_t, 255, count); + int len; + + len = test_proc_output(page); + if (len <= off+count) + *eof = 1; + *start = page + off; + len -= off; + if (len > count) + len = count; + if (len < 0) + len = 0; + return len; +} + +static int test_write_proc(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + if (count >= 256) + len = 255; + else + len = count; + memcpy(cmdline, buffer, count); cmdline[len] = 0; return len; } -static const struct file_operations kgdb_test_proc_fops = { - .owner = THIS_MODULE, - .read = kgdb_test_proc_read, - .write = kgdb_test_proc_write, -}; - static int __init kgdbtest_init(void) { struct proc_dir_entry *entry; - entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops); + entry = create_proc_entry("kgdbtest", 0, NULL); if (entry == NULL) return -ENOMEM; + entry->read_proc = test_read_proc; + entry->write_proc = test_write_proc; + entry->data = NULL; + return 0; } diff --git a/trunk/arch/blackfin/kernel/process.c b/trunk/arch/blackfin/kernel/process.c index b56b0e485e0b..45876427eb2d 100644 --- a/trunk/arch/blackfin/kernel/process.c +++ b/trunk/arch/blackfin/kernel/process.c @@ -258,12 +258,9 @@ void finish_atomic_sections (struct pt_regs *regs) int __user *up0 = (int __user *)regs->p0; switch (regs->pc) { - default: - /* not in middle of an atomic step, so resume like normal */ - return; - case ATOMIC_XCHG32 + 2: put_user(regs->r1, up0); + regs->pc = ATOMIC_XCHG32 + 4; break; case ATOMIC_CAS32 + 2: @@ -271,6 +268,7 @@ void finish_atomic_sections (struct pt_regs *regs) if (regs->r0 == regs->r1) case ATOMIC_CAS32 + 6: put_user(regs->r2, up0); + regs->pc = ATOMIC_CAS32 + 8; break; case ATOMIC_ADD32 + 2: @@ -278,6 +276,7 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_ADD32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_ADD32 + 6; break; case ATOMIC_SUB32 + 2: @@ -285,6 +284,7 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_SUB32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_SUB32 + 6; break; case ATOMIC_IOR32 + 2: @@ -292,6 +292,7 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_IOR32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_IOR32 + 6; break; case ATOMIC_AND32 + 2: @@ -299,6 +300,7 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_AND32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_AND32 + 6; break; case ATOMIC_XOR32 + 2: @@ -306,15 +308,9 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_XOR32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_XOR32 + 6; break; } - - /* - * We've finished the atomic section, and the only thing left for - * userspace is to do a RTS, so we might as well handle that too - * since we need to update the PC anyways. - */ - regs->pc = regs->rets; } static inline @@ -336,58 +332,12 @@ int in_mem_const(unsigned long addr, unsigned long size, { return in_mem_const_off(addr, size, 0, const_addr, const_size); } -#define ASYNC_ENABLED(bnum, bctlnum) \ +#define IN_ASYNC(bnum, bctlnum) \ ({ \ - (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \ - bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \ - 1; \ + (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \ + bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \ + BFIN_MEM_ACCESS_CORE; \ }) -/* - * We can't read EBIU banks that aren't enabled or we end up hanging - * on the access to the async space. Make sure we validate accesses - * that cross async banks too. - * 0 - found, but unusable - * 1 - found & usable - * 2 - not found - */ -static -int in_async(unsigned long addr, unsigned long size) -{ - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) { - if (!ASYNC_ENABLED(0, 0)) - return 0; - if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) - return 1; - size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr; - addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE; - } - if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) { - if (!ASYNC_ENABLED(1, 0)) - return 0; - if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) - return 1; - size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr; - addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE; - } - if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) { - if (!ASYNC_ENABLED(2, 1)) - return 0; - if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) - return 1; - size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr; - addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE; - } - if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { - if (ASYNC_ENABLED(3, 1)) - return 0; - if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) - return 1; - return 0; - } - - /* not within async bounds */ - return 2; -} int bfin_mem_access_type(unsigned long addr, unsigned long size) { @@ -424,11 +374,17 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size) if (addr >= SYSMMR_BASE) return BFIN_MEM_ACCESS_CORE_ONLY; - switch (in_async(addr, size)) { - case 0: return -EFAULT; - case 1: return BFIN_MEM_ACCESS_CORE; - case 2: /* fall through */; - } + /* We can't read EBIU banks that aren't enabled or we end up hanging + * on the access to the async space. + */ + if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE)) + return IN_ASYNC(0, 0); + if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE)) + return IN_ASYNC(1, 0); + if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE)) + return IN_ASYNC(2, 1); + if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE)) + return IN_ASYNC(3, 1); if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) return BFIN_MEM_ACCESS_CORE; @@ -445,8 +401,6 @@ __attribute__((l1_text)) /* Return 1 if access to memory range is OK, 0 otherwise */ int _access_ok(unsigned long addr, unsigned long size) { - int aret; - if (size == 0) return 1; /* Check that things do not wrap around */ @@ -496,11 +450,6 @@ int _access_ok(unsigned long addr, unsigned long size) if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) return 1; #endif - - aret = in_async(addr, size); - if (aret < 2) - return aret; - if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) return 1; diff --git a/trunk/arch/blackfin/kernel/ptrace.c b/trunk/arch/blackfin/kernel/ptrace.c index 65567dc4b9f5..56b0ba12175f 100644 --- a/trunk/arch/blackfin/kernel/ptrace.c +++ b/trunk/arch/blackfin/kernel/ptrace.c @@ -316,6 +316,19 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) case BFIN_MEM_ACCESS_CORE_ONLY: copied = access_process_vm(child, addr, &data, to_copy, 1); + if (copied) + break; + + /* hrm, why didn't that work ... maybe no mapping */ + if (addr >= FIXED_CODE_START && + addr + to_copy <= FIXED_CODE_END) { + copy_to_user_page(0, 0, 0, paddr, &data, to_copy); + copied = to_copy; + } else if (addr >= BOOT_ROM_START) { + memcpy(paddr, &data, to_copy); + copied = to_copy; + } + break; case BFIN_MEM_ACCESS_DMA: if (safe_dma_memcpy(paddr, &data, to_copy)) diff --git a/trunk/arch/blackfin/kernel/setup.c b/trunk/arch/blackfin/kernel/setup.c index 95448ae9c43a..c202a44d1416 100644 --- a/trunk/arch/blackfin/kernel/setup.c +++ b/trunk/arch/blackfin/kernel/setup.c @@ -178,10 +178,10 @@ void __init bfin_cache_init(void) void __init bfin_relocate_l1_mem(void) { - unsigned long text_l1_len = (unsigned long)_text_l1_len; - unsigned long data_l1_len = (unsigned long)_data_l1_len; - unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len; - unsigned long l2_len = (unsigned long)_l2_len; + unsigned long l1_code_length; + unsigned long l1_data_a_length; + unsigned long l1_data_b_length; + unsigned long l2_length; early_shadow_stamp(); @@ -201,23 +201,30 @@ void __init bfin_relocate_l1_mem(void) blackfin_dma_early_init(); - /* if necessary, copy L1 text to L1 instruction SRAM */ - if (L1_CODE_LENGTH && text_l1_len) - early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len); + /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ + l1_code_length = _etext_l1 - _stext_l1; + if (l1_code_length) + early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); - /* if necessary, copy L1 data to L1 data bank A SRAM */ - if (L1_DATA_A_LENGTH && data_l1_len) - early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len); + /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ + l1_data_a_length = _sbss_l1 - _sdata_l1; + if (l1_data_a_length) + early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); - /* if necessary, copy L1 data B to L1 data bank B SRAM */ - if (L1_DATA_B_LENGTH && data_b_l1_len) - early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len); + /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ + l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; + if (l1_data_b_length) + early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + + l1_data_a_length, l1_data_b_length); early_dma_memcpy_done(); - /* if necessary, copy L2 text/data to L2 SRAM */ - if (L2_LENGTH && l2_len) - memcpy(_stext_l2, _l2_lma, l2_len); + /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */ + if (L2_LENGTH != 0) { + l2_length = _sbss_l2 - _stext_l2; + if (l2_length) + memcpy(_stext_l2, _l2_lma_start, l2_length); + } } /* add_memory_region to memmap */ @@ -601,6 +608,11 @@ static __init void memory_setup(void) page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); #endif +#if !defined(CONFIG_MTD_UCLINUX) + /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/ + memory_end -= SIZE_4K; +#endif + init_mm.start_code = (unsigned long)_stext; init_mm.end_code = (unsigned long)_etext; init_mm.end_data = (unsigned long)_edata; @@ -905,7 +917,7 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n"); if (bfin_compiled_revid() == 0xffff) - printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid()); + printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU); else if (bfin_compiled_revid() == -1) printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); else diff --git a/trunk/arch/blackfin/kernel/signal.c b/trunk/arch/blackfin/kernel/signal.c index e0fd63e9e38a..9d90c18fab23 100644 --- a/trunk/arch/blackfin/kernel/signal.c +++ b/trunk/arch/blackfin/kernel/signal.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include @@ -333,20 +332,3 @@ asmlinkage void do_signal(struct pt_regs *regs) sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); } } - -/* - * notification of userspace execution resumption - */ -asmlinkage void do_notify_resume(struct pt_regs *regs) -{ - if (test_thread_flag(TIF_SIGPENDING) || test_thread_flag(TIF_RESTORE_SIGMASK)) - do_signal(regs); - - if (test_thread_flag(TIF_NOTIFY_RESUME)) { - clear_thread_flag(TIF_NOTIFY_RESUME); - tracehook_notify_resume(regs); - if (current->replacement_session_keyring) - key_replace_session_keyring(); - } -} - diff --git a/trunk/arch/blackfin/kernel/time-ts.c b/trunk/arch/blackfin/kernel/time-ts.c index 17c38c5b5b22..359cfb1815ca 100644 --- a/trunk/arch/blackfin/kernel/time-ts.c +++ b/trunk/arch/blackfin/kernel/time-ts.c @@ -22,6 +22,8 @@ #include #include +#if defined(CONFIG_CYCLES_CLOCKSOURCE) + /* Accelerators for sched_clock() * convert from cycles(64bits) => nanoseconds (64bits) * basic equation: @@ -44,11 +46,20 @@ * -johnstul@us.ibm.com "math is hard, lets go shopping!" */ +static unsigned long cyc2ns_scale; #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ -#if defined(CONFIG_CYCLES_CLOCKSOURCE) +static inline void set_cyc2ns_scale(unsigned long cpu_khz) +{ + cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR) / cpu_khz; +} -static notrace cycle_t bfin_read_cycles(struct clocksource *cs) +static inline unsigned long long cycles_2_ns(cycle_t cyc) +{ + return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; +} + +static cycle_t bfin_read_cycles(struct clocksource *cs) { return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); } @@ -58,18 +69,19 @@ static struct clocksource bfin_cs_cycles = { .rating = 400, .read = bfin_read_cycles, .mask = CLOCKSOURCE_MASK(64), - .shift = CYC2NS_SCALE_FACTOR, + .shift = 22, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static inline unsigned long long bfin_cs_cycles_sched_clock(void) +unsigned long long sched_clock(void) { - return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles), - bfin_cs_cycles.mult, bfin_cs_cycles.shift); + return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles)); } static int __init bfin_cs_cycles_init(void) { + set_cyc2ns_scale(get_cclk() / 1000); + bfin_cs_cycles.mult = \ clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift); @@ -96,7 +108,7 @@ void __init setup_gptimer0(void) enable_gptimers(TIMER0bit); } -static cycle_t bfin_read_gptimer0(struct clocksource *cs) +static cycle_t bfin_read_gptimer0(void) { return bfin_read_TIMER0_COUNTER(); } @@ -106,16 +118,10 @@ static struct clocksource bfin_cs_gptimer0 = { .rating = 350, .read = bfin_read_gptimer0, .mask = CLOCKSOURCE_MASK(32), - .shift = CYC2NS_SCALE_FACTOR, + .shift = 22, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static inline unsigned long long bfin_cs_gptimer0_sched_clock(void) -{ - return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(), - bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift); -} - static int __init bfin_cs_gptimer0_init(void) { setup_gptimer0(); @@ -132,19 +138,6 @@ static int __init bfin_cs_gptimer0_init(void) # define bfin_cs_gptimer0_init() #endif - -#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE) -/* prefer to use cycles since it has higher rating */ -notrace unsigned long long sched_clock(void) -{ -#if defined(CONFIG_CYCLES_CLOCKSOURCE) - return bfin_cs_cycles_sched_clock(); -#else - return bfin_cs_gptimer0_sched_clock(); -#endif -} -#endif - #ifdef CONFIG_CORE_TIMER_IRQ_L1 __attribute__((l1_text)) #endif diff --git a/trunk/arch/blackfin/kernel/time.c b/trunk/arch/blackfin/kernel/time.c index 13c1ee3e6408..bd3b53da295e 100644 --- a/trunk/arch/blackfin/kernel/time.c +++ b/trunk/arch/blackfin/kernel/time.c @@ -184,3 +184,11 @@ void __init time_init(void) time_sched_init(timer_interrupt); } + +/* + * Scheduler clock - returns current time in nanosec units. + */ +unsigned long long sched_clock(void) +{ + return (unsigned long long)jiffies *(NSEC_PER_SEC / HZ); +} diff --git a/trunk/arch/blackfin/kernel/traps.c b/trunk/arch/blackfin/kernel/traps.c index d3cbcd6bd985..9636bace00e8 100644 --- a/trunk/arch/blackfin/kernel/traps.c +++ b/trunk/arch/blackfin/kernel/traps.c @@ -119,15 +119,6 @@ static void decode_address(char *buf, unsigned long address) return; } - /* - * Don't walk any of the vmas if we are oopsing, it has been known - * to cause problems - corrupt vmas (kernel crashes) cause double faults - */ - if (oops_in_progress) { - strcat(buf, "/* kernel dynamic memory (maybe user-space) */"); - return; - } - /* looks like we're off in user-land, so let's walk all the * mappings of all our processes and see if we can't be a whee * bit more specific @@ -524,36 +515,6 @@ asmlinkage notrace void trap_c(struct pt_regs *fp) break; /* External Memory Addressing Error */ case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): - if (ANOMALY_05000310) { - static unsigned long anomaly_rets; - - if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) && - (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) { - /* - * A false hardware error will happen while fetching at - * the L1 instruction SRAM boundary. Ignore it. - */ - anomaly_rets = fp->rets; - goto traps_done; - } else if (fp->rets == anomaly_rets) { - /* - * While boundary code returns to a function, at the ret - * point, a new false hardware error might occur too based - * on tests. Ignore it too. - */ - goto traps_done; - } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) && - (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) { - /* - * If boundary code calls a function, at the entry point, - * a new false hardware error maybe happen based on tests. - * Ignore it too. - */ - goto traps_done; - } else - anomaly_rets = 0; - } - info.si_code = BUS_ADRERR; sig = SIGBUS; strerror = KERN_NOTICE HWC_x3(KERN_NOTICE); @@ -1015,12 +976,12 @@ void dump_bfin_process(struct pt_regs *fp) !((unsigned long)current & 0x3) && current->pid) { verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n"); if (current->comm >= (char *)FIXED_CODE_START) - verbose_printk(KERN_NOTICE "COMM=%s PID=%d", + verbose_printk(KERN_NOTICE "COMM=%s PID=%d\n", current->comm, current->pid); else - verbose_printk(KERN_NOTICE "COMM= invalid"); + verbose_printk(KERN_NOTICE "COMM= invalid\n"); - printk(KERN_CONT " CPU=%d\n", current_thread_info()->cpu); + printk(KERN_NOTICE "CPU = %d\n", current_thread_info()->cpu); if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) verbose_printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" diff --git a/trunk/arch/blackfin/kernel/vmlinux.lds.S b/trunk/arch/blackfin/kernel/vmlinux.lds.S index 66799e763dc9..10e12539000e 100644 --- a/trunk/arch/blackfin/kernel/vmlinux.lds.S +++ b/trunk/arch/blackfin/kernel/vmlinux.lds.S @@ -4,6 +4,8 @@ * Licensed under the GPL-2 or later */ +#define VMLINUX_SYMBOL(_sym_) _##_sym_ + #include #include #include @@ -121,6 +123,8 @@ SECTIONS EXIT_DATA } + __l1_lma_start = .; + .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data)) { . = ALIGN(4); @@ -132,11 +136,9 @@ SECTIONS . = ALIGN(4); __etext_l1 = .; } - __text_l1_lma = LOADADDR(.text_l1); - __text_l1_len = SIZEOF(.text_l1); - ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!") + ASSERT (SIZEOF(.text_l1) <= L1_CODE_LENGTH, "L1 text overflow!") - .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len) + .data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1)) { . = ALIGN(4); __sdata_l1 = .; @@ -152,11 +154,9 @@ SECTIONS . = ALIGN(4); __ebss_l1 = .; } - __data_l1_lma = LOADADDR(.data_l1); - __data_l1_len = SIZEOF(.data_l1); - ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!") + ASSERT (SIZEOF(.data_l1) <= L1_DATA_A_LENGTH, "L1 data A overflow!") - .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len) + .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1)) { . = ALIGN(4); __sdata_b_l1 = .; @@ -169,11 +169,11 @@ SECTIONS . = ALIGN(4); __ebss_b_l1 = .; } - __data_b_l1_lma = LOADADDR(.data_b_l1); - __data_b_l1_len = SIZEOF(.data_b_l1); - ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!") + ASSERT (SIZEOF(.data_b_l1) <= L1_DATA_B_LENGTH, "L1 data B overflow!") + + __l2_lma_start = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); - .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len) + .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1)) { . = ALIGN(4); __stext_l2 = .; @@ -195,14 +195,12 @@ SECTIONS . = ALIGN(4); __ebss_l2 = .; } - __l2_lma = LOADADDR(.text_data_l2); - __l2_len = SIZEOF(.text_data_l2); - ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!") + ASSERT (SIZEOF(.text_data_l2) <= L2_LENGTH, "L2 overflow!") /* Force trailing alignment of our init section so that when we * free our init memory, we don't leave behind a partial page. */ - . = __l2_lma + __l2_len; + . = LOADADDR(.text_data_l2) + SIZEOF(.text_data_l2); . = ALIGN(PAGE_SIZE); ___init_end = .; diff --git a/trunk/arch/blackfin/lib/Makefile b/trunk/arch/blackfin/lib/Makefile index 42c47dc9e12f..635288fc5f54 100644 --- a/trunk/arch/blackfin/lib/Makefile +++ b/trunk/arch/blackfin/lib/Makefile @@ -5,7 +5,7 @@ lib-y := \ ashldi3.o ashrdi3.o lshrdi3.o \ muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \ - memcpy.o memset.o memcmp.o memchr.o memmove.o \ + checksum.o memcpy.o memset.o memcmp.o memchr.o memmove.o \ strcmp.o strcpy.o strncmp.o strncpy.o \ umulsi3_highpart.o smulsi3_highpart.o \ ins.o outs.o diff --git a/trunk/arch/blackfin/lib/checksum.c b/trunk/arch/blackfin/lib/checksum.c new file mode 100644 index 000000000000..c62969dc1bbb --- /dev/null +++ b/trunk/arch/blackfin/lib/checksum.c @@ -0,0 +1,125 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + * + * An implementation of the TCP/IP protocol suite for the LINUX operating + * system. INET is implemented using the BSD Socket interface as the + * means of communication with the user level. + * + */ + +#include +#include +#include + +#ifdef CONFIG_IP_CHECKSUM_L1 +static unsigned short do_csum(const unsigned char *buff, int len)__attribute__((l1_text)); +#endif + +static unsigned short do_csum(const unsigned char *buff, int len) +{ + register unsigned long sum = 0; + int swappem = 0; + + if (1 & (unsigned long)buff) { + sum = *buff << 8; + buff++; + len--; + ++swappem; + } + + while (len > 1) { + sum += *(unsigned short *)buff; + buff += 2; + len -= 2; + } + + if (len > 0) + sum += *buff; + + /* Fold 32-bit sum to 16 bits */ + while (sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + + if (swappem) + sum = ((sum & 0xff00) >> 8) + ((sum & 0x00ff) << 8); + + return sum; + +} + +/* + * This is a version of ip_compute_csum() optimized for IP headers, + * which always checksum on 4 octet boundaries. + */ +__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl) +{ + return (__force __sum16)~do_csum(iph, ihl * 4); +} +EXPORT_SYMBOL(ip_fast_csum); + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +__wsum csum_partial(const void *buff, int len, __wsum sum) +{ + /* + * Just in case we get nasty checksum data... + * Like 0xffff6ec3 in the case of our IPv6 multicast header. + * We fold to begin with, as well as at the end. + */ + sum = (sum & 0xffff) + (sum >> 16); + + sum += do_csum(buff, len); + + sum = (sum & 0xffff) + (sum >> 16); + + return sum; +} +EXPORT_SYMBOL(csum_partial); + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ +__sum16 ip_compute_csum(const void *buff, int len) +{ + return (__force __sum16)~do_csum(buff, len); +} +EXPORT_SYMBOL(ip_compute_csum); + +/* + * copy from fs while checksumming, otherwise like csum_partial + */ + +__wsum +csum_partial_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, int *csum_err) +{ + if (csum_err) + *csum_err = 0; + memcpy(dst, (__force void *)src, len); + return csum_partial(dst, len, sum); +} +EXPORT_SYMBOL(csum_partial_copy_from_user); + +/* + * copy from ds while checksumming, otherwise like csum_partial + */ + +__wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum) +{ + memcpy(dst, src, len); + return csum_partial(dst, len, sum); +} +EXPORT_SYMBOL(csum_partial_copy); diff --git a/trunk/arch/blackfin/mach-bf518/Kconfig b/trunk/arch/blackfin/mach-bf518/Kconfig index 4ab2d166c832..4c76fefb7a3b 100644 --- a/trunk/arch/blackfin/mach-bf518/Kconfig +++ b/trunk/arch/blackfin/mach-bf518/Kconfig @@ -1,7 +1,3 @@ -config BF51x - def_bool y - depends on (BF512 || BF514 || BF516 || BF518) - if (BF51x) source "arch/blackfin/mach-bf518/boards/Kconfig" diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf518/include/mach/blackfin.h index 9053462be4b1..6cfb246aebec 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/blackfin.h @@ -58,4 +58,10 @@ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_GCTL 0x24 /* Global Control Register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF514.h index 108fa4bde277..e1d99911025d 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF514.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF514.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF514_H @@ -10,8 +10,15 @@ /* include all Core registers and bit definitions */ #include "defBF514.h" -/* BF514 is BF512 + RSI */ -#include "cdefBF512.h" +/* include core specific register pointer definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ + +/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "cdefBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF514 that are not in the common header */ /* Removable Storage Interface Registers */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF516.h index 2751592ef1c1..6b364eda4947 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF516.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF516.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF516_H @@ -10,8 +10,15 @@ /* include all Core registers and bit definitions */ #include "defBF516.h" -/* BF516 is BF514 + EMAC */ -#include "cdefBF514.h" +/* include core specific register pointer definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ + +/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "cdefBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF516 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ @@ -178,4 +185,71 @@ #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) +/* Removable Storage Interface Registers */ + +#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL) +#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) +#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) +#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) +#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) +#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) +#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) +#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) +#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) +#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) +#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) +#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) +#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) +#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) +#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) +#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) +#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) +#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) +#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) +#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) +#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) +#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) +#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) +#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) +#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) +#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) +#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) +#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) +#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) +#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) +#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) +#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) +#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) +#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) +#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) +#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) +#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL) +#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val) +#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) +#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) +#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT) +#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val) +#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK) +#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val) +#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) +#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) +#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) +#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) +#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) +#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) +#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) +#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) +#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) +#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) +#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) +#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) +#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4) +#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val) +#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5) +#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val) +#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6) +#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val) +#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7) +#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val) + #endif /* _CDEF_BF516_H */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF518.h index 7fb7f0eab990..929b90650bd4 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF518.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF518.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF518_H @@ -10,10 +10,181 @@ /* include all Core registers and bit definitions */ #include "defBF518.h" -/* BF518 is BF516 + IEEE-1588 */ -#include "cdefBF516.h" +/* include core specific register pointer definitions */ +#include -/* PTP TSYNC Registers */ +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ + +/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "cdefBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF518 that are not in the common header */ + + +/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ + +#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) +#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) +#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) +#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) +#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) +#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) +#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) +#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) +#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) +#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) +#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) +#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) +#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) +#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) +#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) +#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) +#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) +#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) +#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) +#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) +#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) +#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) +#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) +#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) +#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) +#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) +#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) +#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) +#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) +#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) +#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) +#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) +#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) +#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) +#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) +#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) +#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) +#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) + +#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) +#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) +#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) +#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) +#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) +#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) +#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) +#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) +#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) +#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) +#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) +#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) +#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) +#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) +#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) +#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) + +#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) +#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) +#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) +#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) +#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) +#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) +#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) +#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) +#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) +#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) + +#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) +#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) +#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) +#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) +#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) +#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) +#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) +#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) +#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) +#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) +#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) +#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) +#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) +#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) +#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) +#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) +#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) +#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) +#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) +#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) +#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) +#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) +#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) +#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) +#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) +#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) +#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) +#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) +#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) +#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) +#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) +#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) +#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) +#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) +#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) +#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) +#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) +#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) +#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) +#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) +#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) +#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) +#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) +#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) +#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) +#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) +#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) +#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) + +#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) +#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) +#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) +#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) +#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) +#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) +#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) +#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) +#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) +#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) +#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) +#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) +#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) +#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) +#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) +#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) +#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) +#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) +#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) +#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) +#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) +#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) +#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) +#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) +#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) +#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) +#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) +#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) +#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) +#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) +#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) +#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) +#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) +#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) +#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) +#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) +#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) +#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) +#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) +#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) +#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) +#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) +#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) +#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) +#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) +#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) #define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL) #define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) @@ -56,4 +227,72 @@ #define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD) #define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val) +/* Removable Storage Interface Registers */ + +#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL) +#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) +#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) +#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) +#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) +#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) +#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) +#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) +#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) +#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) +#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) +#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) +#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) +#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) +#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) +#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) +#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) +#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) +#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) +#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) +#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) +#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) +#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) +#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) +#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) +#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) +#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) +#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) +#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) +#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) +#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) +#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) +#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) +#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) +#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) +#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) +#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL) +#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val) +#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) +#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) +#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT) +#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val) +#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK) +#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val) +#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) +#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) +#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) +#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) +#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) +#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) +#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) +#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) +#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) +#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) +#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) +#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) +#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4) +#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val) +#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5) +#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val) +#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6) +#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val) +#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7) +#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val) + + #endif /* _CDEF_BF518_H */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h index e548e9d1d6fa..1d970df7aee9 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h @@ -131,6 +131,23 @@ #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) +#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) +#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) +#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) +#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) +#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) +#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) +#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) +#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) +#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) +#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) +#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) +#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) +#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) + + /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) @@ -827,7 +844,6 @@ #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) @@ -1046,6 +1062,17 @@ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) +/* OTP/FUSE Registers */ + +#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) +#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) +#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) +#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) +#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) +#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) +#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) +#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) + /* Security Registers */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) @@ -1055,6 +1082,52 @@ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) +/* OTP Read/Write Data Buffer Registers */ + +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) + +/* NFC Registers */ + +#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) +#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) +#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) +#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) +#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) +#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) +#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) +#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) +#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) +#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) +#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) +#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) +#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) +#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) +#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) +#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) +#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) +#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) +#define bfin_read_NFC_RST() bfin_read16(NFC_RST) +#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) +#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) +#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) +#define bfin_read_NFC_READ() bfin_read16(NFC_READ) +#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) +#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) +#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) +#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) +#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) +#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) +#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) +#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) +#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) + /* These need to be last due to the cdef/linux inter-dependencies */ #include diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h index 92e950d6e996..b5adca23a788 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h @@ -7,8 +7,49 @@ #ifndef _DEF_BF514_H #define _DEF_BF514_H -/* BF514 is BF512 + RSI */ -#include "defBF512.h" +/* Include all Core registers and bit definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ + +/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "defBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF514 that are not in the common header */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ +#define SDH_COMMAND 0xFFC0390C /* SDH Command */ +#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ +#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ +#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ +#define SDH_STATUS 0xFFC03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ +#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ +#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ +#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ +#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ /* Removable Storage Interface Registers */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF516.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF516.h index 22a3aa0d2629..7eb18774d727 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF516.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF516.h @@ -7,8 +7,13 @@ #ifndef _DEF_BF516_H #define _DEF_BF516_H -/* BF516 is BF514 + EMAC */ -#include "defBF514.h" +/* Include all Core registers and bit definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ + +/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "defBF51x_base.h" /* The following are the #defines needed by ADSP-BF516 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ @@ -389,4 +394,208 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ +/* SDH Registers */ + +#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ +#define SDH_COMMAND 0xFFC0390C /* SDH Command */ +#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ +#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ +#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ +#define SDH_STATUS 0xFFC03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ +#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ +#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ +#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ +#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ + +/* Removable Storage Interface Registers */ + +#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ +#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ +#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ +#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ +#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ +#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ +#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ +#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ +#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ +#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ +#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ +#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ +#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ +#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ +#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ +#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ +#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ +#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ +#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ +#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ +#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ +#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ +#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ +#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ +#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ +#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ +#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ +#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ +#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ +#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ +#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ +#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + #endif /* _DEF_BF516_H */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF518.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF518.h index cb18270e55c2..794cf06eb5ba 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF518.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF518.h @@ -7,8 +7,461 @@ #ifndef _DEF_BF518_H #define _DEF_BF518_H -/* BF518 is BF516 + IEEE-1588 */ -#include "defBF516.h" +/* Include all Core registers and bit definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ + +/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "defBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF518 that are not in the common header */ +/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ + +#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ +#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ +#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ +#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ +#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ +#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ +#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ +#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ +#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ +#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ +#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ +#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ +#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ +#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ +#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ +#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ +#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ +#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ +#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ + +#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ +#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ +#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ +#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ +#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ +#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ +#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ +#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ + +#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ +#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ +#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ +#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ +#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ + +#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ +#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ +#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ +#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ +#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ +#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ +#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ +#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ +#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ +#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ +#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ +#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ +#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ +#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ +#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ +#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ +#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ +#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ +#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ +#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ +#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ +#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ +#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ +#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ + +#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ +#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ +#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ +#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ +#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ +#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ +#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ +#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ +#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ +#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ +#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ +#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ +#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ +#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ +#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ +#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ +#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ +#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ +#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ +#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ +#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ +#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ +#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ + +/* Listing for IEEE-Supported Count Registers */ + +#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ +#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ +#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ +#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ +#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ +#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ +#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ +#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ +#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ +#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ +#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ +#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ +#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ +#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ +#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ +#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ +#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ +#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ +#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ +#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ +#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ +#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ +#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ +#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ + +#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ +#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ +#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ +#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ +#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ +#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ +#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ +#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ +#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ +#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ +#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ +#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ +#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ +#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ +#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ +#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ +#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ +#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ +#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ +#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ +#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ +#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ +#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ + +/*********************************************************************************** +** System MMR Register Bits And Macros +** +** Disclaimer: All macros are intended to make C and Assembly code more readable. +** Use these macros carefully, as any that do left shifts for field +** depositing will result in the lower order bits being destroyed. Any +** macro that shifts left to properly position the bit-field should be +** used as part of an OR to initialize a register and NOT as a dynamic +** modifier UNLESS the lower order bits are saved and ORed back in when +** the macro is used. +*************************************************************************************/ + +/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ + +/* EMAC_OPMODE Masks */ + +#define RE 0x00000001 /* Receiver Enable */ +#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ +#define HU 0x00000010 /* Hash Filter Unicast Address */ +#define HM 0x00000020 /* Hash Filter Multicast Address */ +#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ +#define PR 0x00000080 /* Promiscuous Mode Enable */ +#define IFE 0x00000100 /* Inverse Filtering Enable */ +#define DBF 0x00000200 /* Disable Broadcast Frame Reception */ +#define PBF 0x00000400 /* Pass Bad Frames Enable */ +#define PSF 0x00000800 /* Pass Short Frames Enable */ +#define RAF 0x00001000 /* Receive-All Mode */ +#define TE 0x00010000 /* Transmitter Enable */ +#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ +#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ +#define DC 0x00080000 /* Deferral Check */ +#define BOLMT 0x00300000 /* Back-Off Limit */ +#define BOLMT_10 0x00000000 /* 10-bit range */ +#define BOLMT_8 0x00100000 /* 8-bit range */ +#define BOLMT_4 0x00200000 /* 4-bit range */ +#define BOLMT_1 0x00300000 /* 1-bit range */ +#define DRTY 0x00400000 /* Disable TX Retry On Collision */ +#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ +#define RMII 0x01000000 /* RMII/MII* Mode */ +#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ +#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ +#define LB 0x08000000 /* Internal Loopback Enable */ +#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ + +/* EMAC_STAADD Masks */ + +#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ +#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ +#define STADISPRE 0x00000004 /* Disable Preamble Generation */ +#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ +#define REGAD 0x000007C0 /* STA Register Address */ +#define PHYAD 0x0000F800 /* PHY Device Address */ + +#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ +#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ + +/* EMAC_STADAT Mask */ + +#define STADATA 0x0000FFFF /* Station Management Data */ + +/* EMAC_FLC Masks */ + +#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ +#define FLCE 0x00000002 /* Flow Control Enable */ +#define PCF 0x00000004 /* Pass Control Frames */ +#define BKPRSEN 0x00000008 /* Enable Backpressure */ +#define FLCPAUSE 0xFFFF0000 /* Pause Time */ + +#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ + +/* EMAC_WKUP_CTL Masks */ + +#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ +#define MPKE 0x00000002 /* Magic Packet Enable */ +#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ +#define GUWKE 0x00000008 /* Global Unicast Wake Enable */ +#define MPKS 0x00000020 /* Magic Packet Received Status */ +#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ + +/* EMAC_WKUP_FFCMD Masks */ + +#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ +#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ +#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ +#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ +#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ +#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ +#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ +#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ + +/* EMAC_WKUP_FFOFF Masks */ + +#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ +#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ +#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ +#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ + +#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ +#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ +#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ +#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ +/* Set ALL Offsets */ +#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) + +/* EMAC_WKUP_FFCRC0 Masks */ + +#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ +#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ + +#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ +#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ + +/* EMAC_WKUP_FFCRC1 Masks */ + +#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ +#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ + +#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ +#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ + +/* EMAC_SYSCTL Masks */ + +#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ +#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ +#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ +#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ +#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ + +#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ + +/* EMAC_SYSTAT Masks */ + +#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ +#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ +#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ +#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ +#define WAKEDET 0x00000010 /* Wake-Up Detected Status */ +#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ +#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ +#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ + +/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ + +#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ +#define RX_COMP 0x00001000 /* RX Frame Complete */ +#define RX_OK 0x00002000 /* RX Frame Received With No Errors */ +#define RX_LONG 0x00004000 /* RX Frame Too Long Error */ +#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ +#define RX_CRC 0x00010000 /* RX Frame CRC Error */ +#define RX_LEN 0x00020000 /* RX Frame Length Error */ +#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ +#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ +#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ +#define RX_PHY 0x00200000 /* RX Frame PHY Error */ +#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ +#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ +#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ +#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ +#define RX_CTL 0x04000000 /* RX Control Frame Indicator */ +#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ +#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ +#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ +#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ +#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ + +/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ + +#define TX_COMP 0x00000001 /* TX Frame Complete */ +#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ +#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ +#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ +#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ +#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ +#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ +#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ +#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ +#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ +#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ +#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ +#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ +#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ +#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ + +/* EMAC_MMC_CTL Masks */ +#define RSTC 0x00000001 /* Reset All Counters */ +#define CROLL 0x00000002 /* Counter Roll-Over Enable */ +#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ +#define MMCE 0x00000008 /* Enable MMC Counter Operation */ + +/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ +#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ +#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ +#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ +#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ +#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ +#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ +#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ +#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ +#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ +#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ +#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ +#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ +#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ +#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ +#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ +#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ +#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ +#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ +#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ +#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ +#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ +#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ +#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ +#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ + +/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ + +#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ +#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ +#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ +#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ +#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ +#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ +#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ +#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ +#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ +#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ +#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ +#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ +#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ +#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ +#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ +#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ +#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ +#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ +#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ +#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ +#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ +#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ +#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ +#define SDH_COMMAND 0xFFC0390C /* SDH Command */ +#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ +#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ +#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ +#define SDH_STATUS 0xFFC03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ +#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ +#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ +#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ +#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ + +/* Removable Storage Interface Registers */ + +#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ +#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ +#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ +#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ +#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ +#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ +#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ +#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ +#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ +#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ +#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ +#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ +#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ +#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ +#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ +#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ +#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ +#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ +#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ +#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ +#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ +#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ +#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ +#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ +#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ +#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ +#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ +#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ +#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ +#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ +#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ +#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ /* PTP TSYNC Registers */ @@ -36,6 +489,141 @@ #define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ #define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + /* Bit masks for EMAC_PTP_CTL */ #define PTP_EN 0x1 /* Enable the PTP_TSYNC module */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h index 9241205fb992..f9fd2b2a2956 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h @@ -585,6 +585,58 @@ ** modifier UNLESS the lower order bits are saved and ORed back in when ** the macro is used. *************************************************************************************/ +/* +** ********************* PLL AND RESET MASKS ****************************************/ +/* PLL_CTL Masks */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* PLL Not Powered */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Enter Deep Sleep Mode */ +#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* VR_CTL Masks */ +#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ +#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ +#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ +#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ +#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 @@ -704,6 +756,66 @@ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ +/* ********* WATCHDOG TIMER MASKS ******************** */ + +/* Watchdog Timer WDOG_CTL Register Masks */ + +#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ +#define WDEV_RESET 0x0000 /* generate reset event on roll over */ +#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ +#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ +#define WDEV_NONE 0x0006 /* no event on roll over */ +#define WDEN 0x0FF0 /* enable watchdog */ +#define WDDIS 0x0AD0 /* disable watchdog */ +#define WDRO 0x8000 /* watchdog rolled over latch */ + +/* depreciated WDOG_CTL Register Masks for legacy code */ + + +#define ICTL WDEV +#define ENABLE_RESET WDEV_RESET +#define WDOG_RESET WDEV_RESET +#define ENABLE_NMI WDEV_NMI +#define WDOG_NMI WDEV_NMI +#define ENABLE_GPI WDEV_GPI +#define WDOG_GPI WDEV_GPI +#define DISABLE_EVT WDEV_NONE +#define WDOG_NONE WDEV_NONE + +#define TMR_EN WDEN +#define TMR_DIS WDDIS +#define TRO WDRO +#define ICTL_P0 0x01 + #define ICTL_P1 0x02 +#define TRO_P 0x0F + + + +/* *************** REAL TIME CLOCK MASKS **************************/ +/* RTC_STAT and RTC_ALARM Masks */ +#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ +#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ALARM Macro z=day y=hr x=min w=sec */ +#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F)) + +/* RTC_ICTL and RTC_ISTAT Masks */ +#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ +#define ALARM 0x0002 /* Alarm Interrupt Enable */ +#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MINUTE 0x0008 /* Minutes Interrupt Enable */ +#define HOUR 0x0010 /* Hours Interrupt Enable */ +#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WRITE_PENDING 0x4000 /* Write Pending Status */ +#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_FAST / RTC_PREN Mask */ +#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ + + /* ************** UART CONTROLLER MASKS *************************/ /* UARTx_LCR Masks */ #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ @@ -1260,6 +1372,33 @@ /* ************************** DMA CONTROLLER MASKS ********************************/ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0900 /* Next Descriptor Size */ +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ @@ -1277,6 +1416,13 @@ #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + + /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ /* PPI_CONTROL Masks */ #define PORT_EN 0x0001 /* PPI Port Enable */ @@ -1684,6 +1830,46 @@ #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ #define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ +/* Bit masks for OTP_CONTROL */ + +#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ +#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ +#define nFIEN 0x0 +#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ +#define nFTESTDEC 0x0 +#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ +#define nFWRTEST 0x0 +#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ +#define nFRDEN 0x0 +#define FWREN 0x8000 /* OTP/Fuse Write Enable */ +#define nFWREN 0x0 + +/* Bit masks for OTP_BEN */ + +#define FBEN 0xffff /* OTP/Fuse Byte Enable */ + +/* Bit masks for OTP_STATUS */ + +#define FCOMP 0x1 /* OTP/Fuse Access Complete */ +#define nFCOMP 0x0 +#define FERROR 0x2 /* OTP/Fuse Access Error */ +#define nFERROR 0x0 +#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ +#define nMMRGLOAD 0x0 +#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ +#define nMMRGLOCK 0x0 +#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ +#define nFPGMEN 0x0 + +/* Bit masks for OTP_TIMING */ + +#define USECDIV 0xff /* Micro Second Divider */ +#define READACC 0x7f00 /* Read Access Time */ +#define CPUMPRL 0x38000 /* Charge Pump Release Time */ +#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ +#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ +#define PGMTIME 0xff000000 /* Program Time */ + /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ diff --git a/trunk/arch/blackfin/mach-bf527/Kconfig b/trunk/arch/blackfin/mach-bf527/Kconfig index 1f8cbe9d6b9a..848ac6f86823 100644 --- a/trunk/arch/blackfin/mach-bf527/Kconfig +++ b/trunk/arch/blackfin/mach-bf527/Kconfig @@ -1,7 +1,3 @@ -config BF52x - def_bool y - depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) - if (BF52x) source "arch/blackfin/mach-bf527/boards/Kconfig" diff --git a/trunk/arch/blackfin/mach-bf527/boards/cm_bf527.c b/trunk/arch/blackfin/mach-bf527/boards/cm_bf527.c index 7ab0800e2914..f1996b13a3da 100644 --- a/trunk/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/trunk/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -15,6 +15,9 @@ #include #include #include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif #include #include #include @@ -62,7 +65,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -314,6 +317,45 @@ static struct platform_device sl811_hcd_device = { }; #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +static struct resource isp1362_hcd_resources[] = { + { + .start = 0x20360000, + .end = 0x20360000, + .flags = IORESOURCE_MEM, + }, { + .start = 0x20360004, + .end = 0x20360004, + .flags = IORESOURCE_MEM, + }, { + .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", @@ -799,6 +841,10 @@ static struct platform_device *cmbf527_devices[] __initdata = { &sl811_hcd_device, #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) + &isp1362_hcd_device, +#endif + #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) &bfin_isp1760_device, #endif diff --git a/trunk/arch/blackfin/mach-bf527/boards/ezkit.c b/trunk/arch/blackfin/mach-bf527/boards/ezkit.c index 5294fdd20732..f09665f74ba0 100644 --- a/trunk/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/trunk/arch/blackfin/mach-bf527/boards/ezkit.c @@ -13,6 +13,9 @@ #include #include #include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif #include #include #include @@ -60,7 +63,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -370,6 +373,45 @@ static struct platform_device sl811_hcd_device = { }; #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +static struct resource isp1362_hcd_resources[] = { + { + .start = 0x20360000, + .end = 0x20360000, + .flags = IORESOURCE_MEM, + }, { + .start = 0x20360004, + .end = 0x20360004, + .flags = IORESOURCE_MEM, + }, { + .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", @@ -646,6 +688,12 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ +#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +static struct platform_device bfin_fb_device = { + .name = "bf537-lq035", +}; +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { #ifdef CONFIG_SERIAL_BFIN_UART0 @@ -802,7 +850,7 @@ static struct platform_device bfin_device_gpiokeys = { }; #endif -#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) #include #include @@ -876,6 +924,10 @@ static struct platform_device *stamp_devices[] __initdata = { &sl811_hcd_device, #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) + &isp1362_hcd_device, +#endif + #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) &bfin_isp1760_device, #endif @@ -905,6 +957,10 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_spi0_device, #endif +#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) + &bfin_fb_device, +#endif + #if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE) &bf52x_t350mcqb_device, #endif @@ -935,7 +991,7 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_device_gpiokeys, #endif -#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) &bfin_rotary_device, #endif diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf527/include/mach/blackfin.h index f714c5de3073..e7d6034f268f 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/blackfin.h @@ -46,4 +46,10 @@ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_GCTL 0x24 /* Global Control Register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF525.h index d7e2751c6bcc..dc3119e9f663 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF525.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF525.h @@ -10,8 +10,15 @@ /* include all Core registers and bit definitions */ #include "defBF525.h" -/* BF525 is BF522 + USB */ -#include "cdefBF522.h" +/* include core specific register pointer definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ + +/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ +#include "cdefBF52x_base.h" + +/* The following are the #defines needed by ADSP-BF525 that are not in the common header */ /* USB Control Registers */ diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF527.h index c7ba544d50b6..d6579449ee46 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF527.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF527.h @@ -10,8 +10,15 @@ /* include all Core registers and bit definitions */ #include "defBF527.h" -/* BF527 is BF525 + EMAC */ -#include "cdefBF525.h" +/* include core specific register pointer definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ + +/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ +#include "cdefBF52x_base.h" + +/* The following are the #defines needed by ADSP-BF527 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ @@ -178,4 +185,417 @@ #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endpoint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) + +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) + +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endpoint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) + +/* USB Endpoint 1 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) + +/* USB Endpoint 2 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) + +/* USB Endpoint 3 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) + +/* USB Endpoint 4 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) + +/* USB Endpoint 5 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) + +/* USB Endpoint 6 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) + +/* USB Endpoint 7 Control Registers */ + +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) + +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + #endif /* _CDEF_BF527_H */ diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h index 12f2ad45314e..7014dde10dd6 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h @@ -844,7 +844,6 @@ #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) @@ -1063,6 +1062,17 @@ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) +/* OTP/FUSE Registers */ + +#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) +#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) +#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) +#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) +#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) +#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) +#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) +#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) + /* Security Registers */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) @@ -1072,6 +1082,17 @@ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) +/* OTP Read/Write Data Buffer Registers */ + +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) + /* NFC Registers */ #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/defBF525.h b/trunk/arch/blackfin/mach-bf527/include/mach/defBF525.h index c136f7032962..82abefc1ef6c 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/defBF525.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/defBF525.h @@ -7,8 +7,15 @@ #ifndef _DEF_BF525_H #define _DEF_BF525_H -/* BF525 is BF522 + USB */ -#include "defBF522.h" +/* Include all Core registers and bit definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ + +/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ +#include "defBF52x_base.h" + +/* The following are the #defines needed by ADSP-BF525 that are not in the common header */ /* USB Control Registers */ diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/defBF527.h b/trunk/arch/blackfin/mach-bf527/include/mach/defBF527.h index 4dd58fb33156..570a125df025 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/defBF527.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/defBF527.h @@ -7,9 +7,15 @@ #ifndef _DEF_BF527_H #define _DEF_BF527_H -/* BF527 is BF525 + EMAC */ -#include "defBF525.h" +/* Include all Core registers and bit definitions */ +#include +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ + +/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ +#include "defBF52x_base.h" + +/* The following are the #defines needed by ADSP-BF527 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ @@ -388,4 +394,673 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ +/* USB Control Registers */ + +#define USB_FADDR 0xffc03800 /* Function address register */ +#define USB_POWER 0xffc03804 /* Power management register */ +#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03820 /* USB frame number */ +#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ + +#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ + +#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ +#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ +#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ +#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ +#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ +#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ +#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ +#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ + +#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define nENABLE_SUSPENDM 0x0 +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define nSUSPEND_MODE 0x0 +#define RESUME_MODE 0x4 /* DMA Mode */ +#define nRESUME_MODE 0x0 +#define RESET 0x8 /* Reset indicator */ +#define nRESET 0x0 +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define nHS_MODE 0x0 +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define nHS_ENABLE 0x0 +#define SOFT_CONN 0x40 /* Soft connect */ +#define nSOFT_CONN 0x0 +#define ISO_UPDATE 0x80 /* Isochronous update */ +#define nISO_UPDATE 0x0 + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define nEP0_TX 0x0 +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define nEP1_TX 0x0 +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define nEP2_TX 0x0 +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define nEP3_TX 0x0 +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define nEP4_TX 0x0 +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define nEP5_TX 0x0 +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define nEP6_TX 0x0 +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ +#define nEP7_TX 0x0 + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define nEP1_RX 0x0 +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define nEP2_RX 0x0 +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define nEP3_RX 0x0 +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define nEP4_RX 0x0 +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define nEP5_RX 0x0 +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define nEP6_RX 0x0 +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ +#define nEP7_RX 0x0 + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define nEP0_TX_E 0x0 +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define nEP1_TX_E 0x0 +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define nEP2_TX_E 0x0 +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define nEP3_TX_E 0x0 +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define nEP4_TX_E 0x0 +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define nEP5_TX_E 0x0 +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define nEP6_TX_E 0x0 +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ +#define nEP7_TX_E 0x0 + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define nEP1_RX_E 0x0 +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define nEP2_RX_E 0x0 +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define nEP3_RX_E 0x0 +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define nEP4_RX_E 0x0 +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define nEP5_RX_E 0x0 +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define nEP6_RX_E 0x0 +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ +#define nEP7_RX_E 0x0 + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define nSUSPEND_B 0x0 +#define RESUME_B 0x2 /* Resume indicator */ +#define nRESUME_B 0x0 +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define nRESET_OR_BABLE_B 0x0 +#define SOF_B 0x8 /* Start of frame */ +#define nSOF_B 0x0 +#define CONN_B 0x10 /* Connection indicator */ +#define nCONN_B 0x0 +#define DISCON_B 0x20 /* Disconnect indicator */ +#define nDISCON_B 0x0 +#define SESSION_REQ_B 0x40 /* Session Request */ +#define nSESSION_REQ_B 0x0 +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ +#define nVBUS_ERROR_B 0x0 + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define nSUSPEND_BE 0x0 +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define nRESUME_BE 0x0 +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define nRESET_OR_BABLE_BE 0x0 +#define SOF_BE 0x8 /* Start of frame int enable */ +#define nSOF_BE 0x0 +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define nCONN_BE 0x0 +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define nDISCON_BE 0x0 +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define nSESSION_REQ_BE 0x0 +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ +#define nVBUS_ERROR_BE 0x0 + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define nGLOBAL_ENA 0x0 +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define nEP1_TX_ENA 0x0 +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define nEP2_TX_ENA 0x0 +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define nEP3_TX_ENA 0x0 +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define nEP4_TX_ENA 0x0 +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define nEP5_TX_ENA 0x0 +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define nEP6_TX_ENA 0x0 +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define nEP7_TX_ENA 0x0 +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define nEP1_RX_ENA 0x0 +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define nEP2_RX_ENA 0x0 +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define nEP3_RX_ENA 0x0 +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define nEP4_RX_ENA 0x0 +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define nEP5_RX_ENA 0x0 +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define nEP6_RX_ENA 0x0 +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ +#define nEP7_RX_ENA 0x0 + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define nSESSION 0x0 +#define HOST_REQ 0x2 /* Host negotiation request */ +#define nHOST_REQ 0x0 +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define nHOST_MODE 0x0 +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define nVBUS0 0x0 +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define nVBUS1 0x0 +#define LSDEV 0x20 /* Low-speed indicator */ +#define nLSDEV 0x0 +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define nFSDEV 0x0 +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ +#define nB_DEVICE 0x0 + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define nDRIVE_VBUS_ON 0x0 +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define nDRIVE_VBUS_OFF 0x0 +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define nCHRG_VBUS_START 0x0 +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define nCHRG_VBUS_END 0x0 +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define nDISCHRG_VBUS_START 0x0 +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ +#define nDISCHRG_VBUS_END 0x0 + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define nDRIVE_VBUS_ON_ENA 0x0 +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define nDRIVE_VBUS_OFF_ENA 0x0 +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define nCHRG_VBUS_START_ENA 0x0 +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define nCHRG_VBUS_END_ENA 0x0 +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define nDISCHRG_VBUS_START_ENA 0x0 +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ +#define nDISCHRG_VBUS_END_ENA 0x0 + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define nRXPKTRDY 0x0 +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define nTXPKTRDY 0x0 +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define nSTALL_SENT 0x0 +#define DATAEND 0x8 /* Data end indicator */ +#define nDATAEND 0x0 +#define SETUPEND 0x10 /* Setup end */ +#define nSETUPEND 0x0 +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define nSENDSTALL 0x0 +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define nSERVICED_RXPKTRDY 0x0 +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define nSERVICED_SETUPEND 0x0 +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define nFLUSHFIFO 0x0 +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define nSTALL_RECEIVED_H 0x0 +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define nSETUPPKT_H 0x0 +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define nERROR_H 0x0 +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define nREQPKT_H 0x0 +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define nSTATUSPKT_H 0x0 +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ +#define nNAK_TIMEOUT_H 0x0 + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define nTXPKTRDY_T 0x0 +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define nFIFO_NOT_EMPTY_T 0x0 +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define nUNDERRUN_T 0x0 +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define nFLUSHFIFO_T 0x0 +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define nSTALL_SEND_T 0x0 +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define nSTALL_SENT_T 0x0 +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define nCLEAR_DATATOGGLE_T 0x0 +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define nINCOMPTX_T 0x0 +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define nDMAREQMODE_T 0x0 +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define nFORCE_DATATOGGLE_T 0x0 +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define nDMAREQ_ENA_T 0x0 +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define nISO_T 0x0 +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define nAUTOSET_T 0x0 +#define ERROR_TH 0x4 /* error condition host mode */ +#define nERROR_TH 0x0 +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define nSTALL_RECEIVED_TH 0x0 +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ +#define nNAK_TIMEOUT_TH 0x0 + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define nRXPKTRDY_R 0x0 +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define nFIFO_FULL_R 0x0 +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define nOVERRUN_R 0x0 +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define nDATAERROR_R 0x0 +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define nFLUSHFIFO_R 0x0 +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define nSTALL_SEND_R 0x0 +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define nSTALL_SENT_R 0x0 +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define nCLEAR_DATATOGGLE_R 0x0 +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define nINCOMPRX_R 0x0 +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define nDMAREQMODE_R 0x0 +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define nDISNYET_R 0x0 +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define nDMAREQ_ENA_R 0x0 +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define nISO_R 0x0 +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define nAUTOCLEAR_R 0x0 +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define nERROR_RH 0x0 +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define nREQPKT_RH 0x0 +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define nSTALL_RECEIVED_RH 0x0 +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define nINCOMPRX_RH 0x0 +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define nDMAREQMODE_RH 0x0 +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ +#define nAUTOREQ_RH 0x0 + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define nDMA0_INT 0x0 +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define nDMA1_INT 0x0 +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define nDMA2_INT 0x0 +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define nDMA3_INT 0x0 +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define nDMA4_INT 0x0 +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define nDMA5_INT 0x0 +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define nDMA6_INT 0x0 +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ +#define nDMA7_INT 0x0 + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define nDMA_ENA 0x0 +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define nDIRECTION 0x0 +#define MODE 0x4 /* DMA Bus error */ +#define nMODE 0x0 +#define INT_ENA 0x8 /* Interrupt enable */ +#define nINT_ENA 0x0 +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ +#define nBUSERROR 0x0 + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + #endif /* _DEF_BF527_H */ diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h index 8b18b5359210..b9dbb73d7ef0 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h @@ -586,6 +586,58 @@ ** modifier UNLESS the lower order bits are saved and ORed back in when ** the macro is used. *************************************************************************************/ +/* +** ********************* PLL AND RESET MASKS ****************************************/ +/* PLL_CTL Masks */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* PLL Not Powered */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Enter Deep Sleep Mode */ +#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* VR_CTL Masks */ +#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ +#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ +#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ +#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ +#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 @@ -705,6 +757,66 @@ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ +/* ********* WATCHDOG TIMER MASKS ******************** */ + +/* Watchdog Timer WDOG_CTL Register Masks */ + +#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ +#define WDEV_RESET 0x0000 /* generate reset event on roll over */ +#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ +#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ +#define WDEV_NONE 0x0006 /* no event on roll over */ +#define WDEN 0x0FF0 /* enable watchdog */ +#define WDDIS 0x0AD0 /* disable watchdog */ +#define WDRO 0x8000 /* watchdog rolled over latch */ + +/* depreciated WDOG_CTL Register Masks for legacy code */ + + +#define ICTL WDEV +#define ENABLE_RESET WDEV_RESET +#define WDOG_RESET WDEV_RESET +#define ENABLE_NMI WDEV_NMI +#define WDOG_NMI WDEV_NMI +#define ENABLE_GPI WDEV_GPI +#define WDOG_GPI WDEV_GPI +#define DISABLE_EVT WDEV_NONE +#define WDOG_NONE WDEV_NONE + +#define TMR_EN WDEN +#define TMR_DIS WDDIS +#define TRO WDRO +#define ICTL_P0 0x01 + #define ICTL_P1 0x02 +#define TRO_P 0x0F + + + +/* *************** REAL TIME CLOCK MASKS **************************/ +/* RTC_STAT and RTC_ALARM Masks */ +#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ +#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ALARM Macro z=day y=hr x=min w=sec */ +#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F)) + +/* RTC_ICTL and RTC_ISTAT Masks */ +#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ +#define ALARM 0x0002 /* Alarm Interrupt Enable */ +#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MINUTE 0x0008 /* Minutes Interrupt Enable */ +#define HOUR 0x0010 /* Hours Interrupt Enable */ +#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WRITE_PENDING 0x4000 /* Write Pending Status */ +#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_FAST / RTC_PREN Mask */ +#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ + + /* ************** UART CONTROLLER MASKS *************************/ /* UARTx_LCR Masks */ #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ @@ -1269,6 +1381,33 @@ /* ************************** DMA CONTROLLER MASKS ********************************/ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0900 /* Next Descriptor Size */ +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ @@ -1286,6 +1425,13 @@ #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + + /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ /* PPI_CONTROL Masks */ #define PORT_EN 0x0001 /* PPI Port Enable */ @@ -1697,6 +1843,46 @@ #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ #define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ +/* Bit masks for OTP_CONTROL */ + +#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ +#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ +#define nFIEN 0x0 +#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ +#define nFTESTDEC 0x0 +#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ +#define nFWRTEST 0x0 +#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ +#define nFRDEN 0x0 +#define FWREN 0x8000 /* OTP/Fuse Write Enable */ +#define nFWREN 0x0 + +/* Bit masks for OTP_BEN */ + +#define FBEN 0xffff /* OTP/Fuse Byte Enable */ + +/* Bit masks for OTP_STATUS */ + +#define FCOMP 0x1 /* OTP/Fuse Access Complete */ +#define nFCOMP 0x0 +#define FERROR 0x2 /* OTP/Fuse Access Error */ +#define nFERROR 0x0 +#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ +#define nMMRGLOAD 0x0 +#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ +#define nMMRGLOCK 0x0 +#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ +#define nFPGMEN 0x0 + +/* Bit masks for OTP_TIMING */ + +#define USECDIV 0xff /* Micro Second Divider */ +#define READACC 0x7f00 /* Read Access Time */ +#define CPUMPRL 0x38000 /* Charge Pump Release Time */ +#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ +#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ +#define PGMTIME 0xff000000 /* Program Time */ + /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ diff --git a/trunk/arch/blackfin/mach-bf533/boards/H8606.c b/trunk/arch/blackfin/mach-bf533/boards/H8606.c index 4adceb0bdb6d..43f43a095a99 100644 --- a/trunk/arch/blackfin/mach-bf533/boards/H8606.c +++ b/trunk/arch/blackfin/mach-bf533/boards/H8606.c @@ -166,6 +166,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) /* SPI ADC chip */ static struct bfin5xx_spi_chip spi_adc_chip_info = { + .ctl_reg = 0x1000, .enable_dma = 1, /* use dma transfer with this chip*/ .bits_per_word = 16, }; @@ -173,6 +174,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { + .ctl_reg = 0x1000, .enable_dma = 0, .bits_per_word = 16, }; @@ -256,6 +258,12 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ +#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +static struct platform_device bfin_fb_device = { + .name = "bf537-fb", +}; +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { { diff --git a/trunk/arch/blackfin/mach-bf533/boards/ip0x.c b/trunk/arch/blackfin/mach-bf533/boards/ip0x.c index 8ec42ba35b9e..644be5e5ab6f 100644 --- a/trunk/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/trunk/arch/blackfin/mach-bf533/boards/ip0x.c @@ -20,7 +20,6 @@ #endif #include #include -#include /* * Name the Board for the /proc/cpuinfo @@ -108,6 +107,20 @@ static struct platform_device dm9000_device2 = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { +/* + * CPOL (Clock Polarity) + * 0 - Active high SCK + * 1 - Active low SCK + * CPHA (Clock Phase) Selects transfer format and operation mode + * 0 - SCLK toggles from middle of the first data bit, slave select + * pins controlled by hardware. + * 1 - SCLK toggles from beginning of first data bit, slave select + * pins controller by user software. + * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work + * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0 + * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1 + */ + .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */ .enable_dma = 0, /* if 1 - block!!! */ .bits_per_word = 8, }; diff --git a/trunk/arch/blackfin/mach-bf533/boards/stamp.c b/trunk/arch/blackfin/mach-bf533/boards/stamp.c index 6d68dcfa2da2..82f70efd66e7 100644 --- a/trunk/arch/blackfin/mach-bf533/boards/stamp.c +++ b/trunk/arch/blackfin/mach-bf533/boards/stamp.c @@ -321,6 +321,12 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ +#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +static struct platform_device bfin_fb_device = { + .name = "bf537-fb", +}; +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { { diff --git a/trunk/arch/blackfin/mach-bf533/include/mach/defBF532.h b/trunk/arch/blackfin/mach-bf533/include/mach/defBF532.h index e9ff491c0953..02b328eb0e07 100644 --- a/trunk/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/trunk/arch/blackfin/mach-bf533/include/mach/defBF532.h @@ -370,6 +370,72 @@ /* System MMR Register Bits */ /******************************************************************************* */ +/* ********************* PLL AND RESET MASKS ************************ */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x0008 /* Core clock off */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */ +#if !defined(__ADSPBF538__) +/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */ +# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#endif +#define BYPASS 0x0100 /* Bypass the PLL */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ + +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ + +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5 */ +#define GAIN_10 0x0004 /* GAIN = 10 */ +#define GAIN_20 0x0008 /* GAIN = 20 */ +#define GAIN_50 0x000C /* GAIN = 50 */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 @@ -637,7 +703,54 @@ /* ********** DMA CONTROLLER MASKS *********************8 */ -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define DMAFLOW 0x00007000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ + +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + +/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ diff --git a/trunk/arch/blackfin/mach-bf537/boards/pnav10.c b/trunk/arch/blackfin/mach-bf537/boards/pnav10.c index 4e0afda472ab..9ba290466b56 100644 --- a/trunk/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/trunk/arch/blackfin/mach-bf537/boards/pnav10.c @@ -13,6 +13,9 @@ #include #include #include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif #include #include #include @@ -144,6 +147,45 @@ static struct platform_device sl811_hcd_device = { }; #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +static struct resource isp1362_hcd_resources[] = { + { + .start = 0x20360000, + .end = 0x20360000, + .flags = IORESOURCE_MEM, + }, { + .start = 0x20360004, + .end = 0x20360004, + .flags = IORESOURCE_MEM, + }, { + .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", @@ -450,6 +492,10 @@ static struct platform_device *stamp_devices[] __initdata = { &sl811_hcd_device, #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) + &isp1362_hcd_device, +#endif + #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, #endif diff --git a/trunk/arch/blackfin/mach-bf537/boards/stamp.c b/trunk/arch/blackfin/mach-bf537/boards/stamp.c index ac9b52e0087c..c46baa5e6d9b 100644 --- a/trunk/arch/blackfin/mach-bf537/boards/stamp.c +++ b/trunk/arch/blackfin/mach-bf537/boards/stamp.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include #include -#include -#include #include #include #include @@ -68,7 +65,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -79,6 +76,7 @@ static struct platform_device bfin_isp1760_device = { #endif #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include #include static struct gpio_keys_button bfin_gpio_keys_table[] = { @@ -197,6 +195,28 @@ static struct platform_device dm9000_device = { }; #endif +#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) +static struct resource ax88180_resources[] = { + [0] = { + .start = 0x20300000, + .end = 0x20300000 + 0x8000, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PF7, + .end = IRQ_PF7, + .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL), + }, +}; + +static struct platform_device ax88180_device = { + .name = "ax88180", + .id = -1, + .num_resources = ARRAY_SIZE(ax88180_resources), + .resource = ax88180_resources, +}; +#endif + #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) static struct resource sl811_hcd_resources[] = { { @@ -252,8 +272,8 @@ static struct resource isp1362_hcd_resources[] = { .end = 0x20360004, .flags = IORESOURCE_MEM, }, { - .start = IRQ_PF3, - .end = IRQ_PF3, + .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, }, }; @@ -280,44 +300,6 @@ static struct platform_device isp1362_hcd_device = { }; #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN_RX, - .end = IRQ_CAN_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_TX, - .end = IRQ_CAN_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_ERROR, - .end = IRQ_CAN_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif - #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", @@ -532,14 +514,15 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = { }; #endif -#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) +#if defined(CONFIG_INPUT_EVAL_AD7147EBZ) +#include #include static struct bfin5xx_spi_chip ad7147_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, }; -static struct ad714x_slider_plat ad7147_spi_slider_plat[] = { +static struct ad714x_slider_plat slider_plat[] = { { .start_stage = 0, .end_stage = 7, @@ -547,7 +530,7 @@ static struct ad714x_slider_plat ad7147_spi_slider_plat[] = { }, }; -static struct ad714x_button_plat ad7147_spi_button_plat[] = { +static struct ad714x_button_plat button_plat[] = { { .keycode = BTN_FORWARD, .l_mask = 0, @@ -574,11 +557,11 @@ static struct ad714x_button_plat ad7147_spi_button_plat[] = { .h_mask = 0x400, }, }; -static struct ad714x_platform_data ad7147_spi_platform_data = { +static struct ad714x_platform_data ad7147_platfrom_data = { .slider_num = 1, .button_num = 5, - .slider = ad7147_spi_slider_plat, - .button = ad7147_spi_button_plat, + .slider = slider_plat, + .button = button_plat, .stage_cfg_reg = { {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600}, {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650}, @@ -597,9 +580,10 @@ static struct ad714x_platform_data ad7147_spi_platform_data = { }; #endif -#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE) +#if defined(CONFIG_INPUT_EVAL_AD7142EB) +#include #include -static struct ad714x_button_plat ad7142_i2c_button_plat[] = { +static struct ad714x_button_plat button_plat[] = { { .keycode = BTN_1, .l_mask = 0, @@ -621,9 +605,9 @@ static struct ad714x_button_plat ad7142_i2c_button_plat[] = { .h_mask = 0x8, }, }; -static struct ad714x_platform_data ad7142_i2c_platform_data = { +static struct ad714x_platform_data ad7142_platfrom_data = { .button_num = 4, - .button = ad7142_i2c_button_plat, + .button = button_plat, .stage_cfg_reg = { /* fixme: figure out right setting for all comoponent according * to hardware feature of EVAL-AD7142EB board */ @@ -712,7 +696,8 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { #endif #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) -#include +#include +#include static const struct adxl34x_platform_data adxl34x_info = { .x_axis_offset = 0, .y_axis_offset = 0, @@ -736,7 +721,9 @@ static const struct adxl34x_platform_data adxl34x_info = { .ev_code_y = ABS_Y, /* EV_REL */ .ev_code_z = ABS_Z, /* EV_REL */ - .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ + .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ + .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */ + .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */ /* .ev_code_ff = KEY_F,*/ /* EV_KEY */ /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ @@ -774,47 +761,6 @@ static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { }; #endif -#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) -static struct bfin5xx_spi_chip adf7021_spi_chip_info = { - .bits_per_word = 16, - .cs_gpio = GPIO_PF10, -}; - -#include -#define TXREG 0x0160A470 -static const u32 adf7021_regs[] = { - 0x09608FA0, - 0x00575011, - 0x00A7F092, - 0x2B141563, - 0x81F29E94, - 0x00003155, - 0x050A4F66, - 0x00000007, - 0x00000008, - 0x000231E9, - 0x3296354A, - 0x891A2B3B, - 0x00000D9C, - 0x0000000D, - 0x0000000E, - 0x0000000F, -}; - -static struct adf702x_platform_data adf7021_platform_data = { - .regs_base = (void *)SPORT1_TCR1, - .dma_ch_rx = CH_SPORT1_RX, - .dma_ch_tx = CH_SPORT1_TX, - .irq_sport_err = IRQ_SPORT1_ERROR, - .gpio_int_rfs = GPIO_PF8, - .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI, - P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0}, - .adf702x_model = MODEL_ADF7021, - .adf702x_regs = adf7021_regs, - .tx_reg = TXREG, -}; -#endif - #if defined(CONFIG_MTD_DATAFLASH) \ || defined(CONFIG_MTD_DATAFLASH_MODULE) @@ -848,13 +794,6 @@ static struct bfin5xx_spi_chip data_flash_chip_info = { }; #endif -#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) -static struct bfin5xx_spi_chip spi_adxl34x_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -916,7 +855,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) +#if defined(CONFIG_INPUT_EVAL_AD7147EBZ) { .modalias = "ad714x_captouch", .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ @@ -924,7 +863,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .bus_num = 0, .chip_select = 5, .mode = SPI_MODE_3, - .platform_data = &ad7147_spi_platform_data, + .platform_data = &ad7147_platfrom_data, .controller_data = &ad7147_spi_chip_info, }, #endif @@ -993,30 +932,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_0, }, #endif -#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) - { - .modalias = "adxl34x", - .platform_data = &adxl34x_info, - .irq = IRQ_PF6, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - .controller_data = &spi_adxl34x_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) - { - .modalias = "adf702x", - .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 0, /* GPIO controlled SSEL */ - .controller_data = &adf7021_spi_chip_info, - .platform_data = &adf7021_platform_data, - .mode = SPI_MODE_0, - }, -#endif - }; #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) @@ -1260,6 +1175,7 @@ static struct platform_device i2c_bfin_twi_device = { #endif #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) +#include #include static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { [0] = KEY_GRAVE, @@ -1352,33 +1268,35 @@ static struct adp5588_kpad_platform_data adp5588_kpad_data = { * ADP5520/5501 Backlight Data */ -static struct adp5520_backlight_platform_data adp5520_backlight_data = { - .fade_in = ADP5520_FADE_T_1200ms, - .fade_out = ADP5520_FADE_T_1200ms, - .fade_led_law = ADP5520_BL_LAW_LINEAR, - .en_ambl_sens = 1, - .abml_filt = ADP5520_BL_AMBL_FILT_640ms, - .l1_daylight_max = ADP5520_BL_CUR_mA(15), - .l1_daylight_dim = ADP5520_BL_CUR_mA(0), - .l2_office_max = ADP5520_BL_CUR_mA(7), - .l2_office_dim = ADP5520_BL_CUR_mA(0), - .l3_dark_max = ADP5520_BL_CUR_mA(3), - .l3_dark_dim = ADP5520_BL_CUR_mA(0), - .l2_trip = ADP5520_L2_COMP_CURR_uA(700), - .l2_hyst = ADP5520_L2_COMP_CURR_uA(50), - .l3_trip = ADP5520_L3_COMP_CURR_uA(80), - .l3_hyst = ADP5520_L3_COMP_CURR_uA(20), +static struct adp5520_backlight_platfrom_data adp5520_backlight_data = { + .fade_in = FADE_T_1200ms, + .fade_out = FADE_T_1200ms, + .fade_led_law = BL_LAW_LINEAR, + .en_ambl_sens = 1, + .abml_filt = BL_AMBL_FILT_640ms, + .l1_daylight_max = BL_CUR_mA(15), + .l1_daylight_dim = BL_CUR_mA(0), + .l2_office_max = BL_CUR_mA(7), + .l2_office_dim = BL_CUR_mA(0), + .l3_dark_max = BL_CUR_mA(3), + .l3_dark_dim = BL_CUR_mA(0), + .l2_trip = L2_COMP_CURR_uA(700), + .l2_hyst = L2_COMP_CURR_uA(50), + .l3_trip = L3_COMP_CURR_uA(80), + .l3_hyst = L3_COMP_CURR_uA(20), }; /* * ADP5520/5501 LEDs Data */ +#include + static struct led_info adp5520_leds[] = { { .name = "adp5520-led1", .default_trigger = "none", - .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms, + .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | LED_OFFT_600ms, }, #ifdef ADP5520_EN_ALL_LEDS { @@ -1394,50 +1312,51 @@ static struct led_info adp5520_leds[] = { #endif }; -static struct adp5520_leds_platform_data adp5520_leds_data = { +static struct adp5520_leds_platfrom_data adp5520_leds_data = { .num_leds = ARRAY_SIZE(adp5520_leds), .leds = adp5520_leds, - .fade_in = ADP5520_FADE_T_600ms, - .fade_out = ADP5520_FADE_T_600ms, - .led_on_time = ADP5520_LED_ONT_600ms, + .fade_in = FADE_T_600ms, + .fade_out = FADE_T_600ms, + .led_on_time = LED_ONT_600ms, }; /* * ADP5520 GPIO Data */ -static struct adp5520_gpio_platform_data adp5520_gpio_data = { +static struct adp5520_gpio_platfrom_data adp5520_gpio_data = { .gpio_start = 50, - .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2, - .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2, + .gpio_en_mask = GPIO_C1 | GPIO_C2 | GPIO_R2, + .gpio_pullup_mask = GPIO_C1 | GPIO_C2 | GPIO_R2, }; /* * ADP5520 Keypad Data */ +#include static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = { - [ADP5520_KEY(0, 0)] = KEY_GRAVE, - [ADP5520_KEY(0, 1)] = KEY_1, - [ADP5520_KEY(0, 2)] = KEY_2, - [ADP5520_KEY(0, 3)] = KEY_3, - [ADP5520_KEY(1, 0)] = KEY_4, - [ADP5520_KEY(1, 1)] = KEY_5, - [ADP5520_KEY(1, 2)] = KEY_6, - [ADP5520_KEY(1, 3)] = KEY_7, - [ADP5520_KEY(2, 0)] = KEY_8, - [ADP5520_KEY(2, 1)] = KEY_9, - [ADP5520_KEY(2, 2)] = KEY_0, - [ADP5520_KEY(2, 3)] = KEY_MINUS, - [ADP5520_KEY(3, 0)] = KEY_EQUAL, - [ADP5520_KEY(3, 1)] = KEY_BACKSLASH, - [ADP5520_KEY(3, 2)] = KEY_BACKSPACE, - [ADP5520_KEY(3, 3)] = KEY_ENTER, -}; - -static struct adp5520_keys_platform_data adp5520_keys_data = { - .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0, - .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0, + [KEY(0, 0)] = KEY_GRAVE, + [KEY(0, 1)] = KEY_1, + [KEY(0, 2)] = KEY_2, + [KEY(0, 3)] = KEY_3, + [KEY(1, 0)] = KEY_4, + [KEY(1, 1)] = KEY_5, + [KEY(1, 2)] = KEY_6, + [KEY(1, 3)] = KEY_7, + [KEY(2, 0)] = KEY_8, + [KEY(2, 1)] = KEY_9, + [KEY(2, 2)] = KEY_0, + [KEY(2, 3)] = KEY_MINUS, + [KEY(3, 0)] = KEY_EQUAL, + [KEY(3, 1)] = KEY_BACKSLASH, + [KEY(3, 2)] = KEY_BACKSPACE, + [KEY(3, 3)] = KEY_ENTER, +}; + +static struct adp5520_keys_platfrom_data adp5520_keys_data = { + .rows_en_mask = ROW_R3 | ROW_R2 | ROW_R1 | ROW_R0, + .cols_en_mask = COL_C3 | COL_C2 | COL_C1 | COL_C0, .keymap = adp5520_keymap, .keymapsize = ARRAY_SIZE(adp5520_keymap), .repeat = 0, @@ -1447,81 +1366,50 @@ static struct adp5520_keys_platform_data adp5520_keys_data = { * ADP5520/5501 Multifuction Device Init Data */ +static struct adp5520_subdev_info adp5520_subdevs[] = { + { + .name = "adp5520-backlight", + .id = ID_ADP5520, + .platform_data = &adp5520_backlight_data, + }, + { + .name = "adp5520-led", + .id = ID_ADP5520, + .platform_data = &adp5520_leds_data, + }, + { + .name = "adp5520-gpio", + .id = ID_ADP5520, + .platform_data = &adp5520_gpio_data, + }, + { + .name = "adp5520-keys", + .id = ID_ADP5520, + .platform_data = &adp5520_keys_data, + }, +}; + static struct adp5520_platform_data adp5520_pdev_data = { - .backlight = &adp5520_backlight_data, - .leds = &adp5520_leds_data, - .gpio = &adp5520_gpio_data, - .keys = &adp5520_keys_data, + .num_subdevs = ARRAY_SIZE(adp5520_subdevs), + .subdevs = adp5520_subdevs, }; #endif #if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE) #include -static struct adp5588_gpio_platform_data adp5588_gpio_data = { +static struct adp5588_gpio_platfrom_data adp5588_gpio_data = { .gpio_start = 50, .pullup_dis_mask = 0, }; #endif -#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE) -#include -static struct led_info adp8870_leds[] = { - { - .name = "adp8870-led7", - .default_trigger = "none", - .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms, - }, -}; - - -static struct adp8870_backlight_platform_data adp8870_pdata = { - .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 | - ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */ - .pwm_assign = 0, /* 1 = Enables PWM mode */ - - .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */ - .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */ - .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */ - - .en_ambl_sens = 1, /* 1 = enable ambient light sensor */ - .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */ - - .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - - .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ - .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ - .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */ - .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */ - .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */ - .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */ - .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */ - .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */ - - .leds = adp8870_leds, - .num_leds = ARRAY_SIZE(adp8870_leds), - .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */ - .led_fade_in = ADP8870_FADE_T_600ms, - .led_fade_out = ADP8870_FADE_T_600ms, - .led_on_time = ADP8870_LED_ONT_200ms, -}; -#endif - static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE) +#if defined(CONFIG_INPUT_EVAL_AD7142EB) { I2C_BOARD_INFO("ad7142_captouch", 0x2C), .irq = IRQ_PG5, - .platform_data = (void *)&ad7142_i2c_platform_data, + .platform_data = (void *)&ad7142_platfrom_data, }, #endif #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) @@ -1574,32 +1462,6 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { I2C_BOARD_INFO("bfin-adv7393", 0x2B), }, #endif -#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) - { - I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C), - }, -#endif -#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE) - { - I2C_BOARD_INFO("adp8870", 0x2B), - .platform_data = (void *)&adp8870_pdata, - }, -#endif -#if defined(CONFIG_SND_SOC_ADAU1371) || defined(CONFIG_SND_SOC_ADAU1371_MODULE) - { - I2C_BOARD_INFO("adau1371", 0x1A), - }, -#endif -#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE) - { - I2C_BOARD_INFO("adau1761", 0x38), - }, -#endif -#if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE) - { - I2C_BOARD_INFO("ad5258", 0x18), - }, -#endif }; #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) @@ -1740,8 +1602,8 @@ static struct platform_device *stamp_devices[] __initdata = { &dm9000_device, #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) - &bfin_can_device, +#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) + &ax88180_device, #endif #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) diff --git a/trunk/arch/blackfin/mach-bf537/include/mach/bf537.h b/trunk/arch/blackfin/mach-bf537/include/mach/bf537.h index 8b291418ca32..17fab4474669 100644 --- a/trunk/arch/blackfin/mach-bf537/include/mach/bf537.h +++ b/trunk/arch/blackfin/mach-bf537/include/mach/bf537.h @@ -9,6 +9,16 @@ #ifndef __MACH_BF537_H__ #define __MACH_BF537_H__ +/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ + +#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ +#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */ +#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ +#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ +#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */ +#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */ +#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ + #define OFFSET_(x) ((x) & 0x0000FFFF) /*some misc defines*/ diff --git a/trunk/arch/blackfin/mach-bf537/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf537/include/mach/blackfin.h index a12d4b6a221d..eab006d260c5 100644 --- a/trunk/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf537/include/mach/blackfin.h @@ -40,4 +40,10 @@ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_GCTL 0x24 /* Global Control Register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h b/trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h index 066d5c261f47..a6d20ca57683 100644 --- a/trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -958,6 +958,67 @@ ** modifier UNLESS the lower order bits are saved and ORed back in when ** the macro is used. *************************************************************************************/ +/* +** ********************* PLL AND RESET MASKS ****************************************/ +/* PLL_CTL Masks */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* PLL Not Powered */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Enter Deep Sleep Mode */ +#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5 */ +#define GAIN_10 0x0004 /* GAIN = 10 */ +#define GAIN_20 0x0008 /* GAIN = 20 */ +#define GAIN_50 0x000C /* GAIN = 50 */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ +#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ +#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ +#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ +#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 @@ -1584,6 +1645,34 @@ #define BGSTAT 0x0020 /* Bus Grant Status */ /* ************************** DMA CONTROLLER MASKS ********************************/ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0900 /* Next Descriptor Size */ + +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ @@ -1601,6 +1690,12 @@ #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ /* PPI_CONTROL Masks */ #define PORT_EN 0x0001 /* PPI Port Enable */ diff --git a/trunk/arch/blackfin/mach-bf538/Makefile b/trunk/arch/blackfin/mach-bf538/Makefile index c0be54f2cd2b..8cd2719684db 100644 --- a/trunk/arch/blackfin/mach-bf538/Makefile +++ b/trunk/arch/blackfin/mach-bf538/Makefile @@ -3,4 +3,3 @@ # obj-y := ints-priority.o dma.o -obj-$(CONFIG_GPIOLIB) += ext-gpio.o diff --git a/trunk/arch/blackfin/mach-bf538/boards/ezkit.c b/trunk/arch/blackfin/mach-bf538/boards/ezkit.c index c296bb1ed503..14af5c2088d4 100644 --- a/trunk/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/trunk/arch/blackfin/mach-bf538/boards/ezkit.c @@ -151,44 +151,6 @@ static struct platform_device bfin_sir2_device = { #endif #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN_RX, - .end = IRQ_CAN_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_TX, - .end = IRQ_CAN_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_ERROR, - .end = IRQ_CAN_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif - /* * USB-LAN EzExtender board * Driver needs to know address, irq and flag pin. @@ -648,10 +610,6 @@ static struct platform_device *cm_bf538_devices[] __initdata = { #endif #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) - &bfin_can_device, -#endif - #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, #endif diff --git a/trunk/arch/blackfin/mach-bf538/ext-gpio.c b/trunk/arch/blackfin/mach-bf538/ext-gpio.c deleted file mode 100644 index 180b1252679f..000000000000 --- a/trunk/arch/blackfin/mach-bf538/ext-gpio.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs - * - * Copyright 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include - -#define DEFINE_REG(reg, off) \ -static inline u16 read_##reg(void __iomem *port) \ - { return bfin_read16(port + off); } \ -static inline void write_##reg(void __iomem *port, u16 v) \ - { bfin_write16(port + off, v); } - -DEFINE_REG(PORTIO, 0x00) -DEFINE_REG(PORTIO_CLEAR, 0x10) -DEFINE_REG(PORTIO_SET, 0x20) -DEFINE_REG(PORTIO_DIR, 0x40) -DEFINE_REG(PORTIO_INEN, 0x50) - -static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip) -{ - switch (chip->base) { - default: /* not really needed, but keeps gcc happy */ - case GPIO_PC0: return (void __iomem *)PORTCIO; - case GPIO_PD0: return (void __iomem *)PORTDIO; - case GPIO_PE0: return (void __iomem *)PORTEIO; - } -} - -static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - return !!(read_PORTIO(port) & (1u << gpio)); -} - -static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - if (value) - write_PORTIO_SET(port, (1u << gpio)); - else - write_PORTIO_CLEAR(port, (1u << gpio)); -} - -static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio)); - write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio)); - return 0; -} - -static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio)); - bf538_gpio_set_value(port, gpio, value); - write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio)); - return 0; -} - -static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_special_gpio_request(chip->base + gpio, chip->label); -} - -static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_special_gpio_free(chip->base + gpio); -} - -/* We don't set the irq fields as these banks cannot generate interrupts */ - -static struct gpio_chip bf538_portc_chip = { - .label = "GPIO-PC", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PC0, - .ngpio = GPIO_PC9 - GPIO_PC0 + 1, -}; - -static struct gpio_chip bf538_portd_chip = { - .label = "GPIO-PD", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PD0, - .ngpio = GPIO_PD13 - GPIO_PD0 + 1, -}; - -static struct gpio_chip bf538_porte_chip = { - .label = "GPIO-PE", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PE0, - .ngpio = GPIO_PE15 - GPIO_PE0 + 1, -}; - -static int __init bf538_extgpio_setup(void) -{ - return gpiochip_add(&bf538_portc_chip) | - gpiochip_add(&bf538_portd_chip) | - gpiochip_add(&bf538_porte_chip); -} -arch_initcall(bf538_extgpio_setup); diff --git a/trunk/arch/blackfin/mach-bf538/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf538/include/mach/blackfin.h index 08b5eabb1ed5..278e8942eef2 100644 --- a/trunk/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf538/include/mach/blackfin.h @@ -37,4 +37,10 @@ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_GCTL 0x24 /* Global Control Register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h b/trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h index fac563e6f62f..5f6c34dfd08e 100644 --- a/trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h @@ -468,31 +468,31 @@ /* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ /* GPIO Port C Register Names */ -#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ -#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ -#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ -#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ -#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ -#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ -#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ +#define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */ +#define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */ +#define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */ +#define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */ +#define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */ +#define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ +#define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ /* GPIO Port D Register Names */ -#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ -#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ -#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ -#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ -#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ -#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ -#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ +#define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */ +#define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */ +#define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */ +#define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */ +#define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */ +#define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ +#define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ /* GPIO Port E Register Names */ -#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ -#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ -#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ -#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ -#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ -#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ -#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ +#define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */ +#define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */ +#define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */ +#define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */ +#define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */ +#define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ +#define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ @@ -1422,6 +1422,81 @@ /* System MMR Register Bits and Macros */ /******************************************************************************* */ +/* ********************* PLL AND RESET MASKS ************************ */ +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* Shut off PLL clocks */ + +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */ +#define IN_DELAY 0x0014 /* EBIU Input Delay Select */ +#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ + +/* PLL_CTL Macros */ +#ifdef _MISRA_RULES +#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ +#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6) +#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2)) +#else +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ +#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6) +#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2)) +#endif /* _MISRA_RULES */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ + +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +/* PLL_DIV Macros */ +#ifdef _MISRA_RULES +#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ +#else +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ +#endif /* _MISRA_RULES */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ + +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5 */ +#define GAIN_10 0x0004 /* GAIN = 10 */ +#define GAIN_20 0x0008 /* GAIN = 20 */ +#define GAIN_50 0x000C /* GAIN = 50 */ + +#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ +#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + /* SWRST Mask */ #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ @@ -1534,6 +1609,91 @@ #endif /* _MISRA_RULES */ +/* ********* WATCHDOG TIMER MASKS ******************** */ +/* Watchdog Timer WDOG_CTL Register Masks */ +#ifdef _MISRA_RULES +#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */ +#else +#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ +#endif /* _MISRA_RULES */ +#define WDEV_RESET 0x0000 /* generate reset event on roll over */ +#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ +#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ +#define WDEV_NONE 0x0006 /* no event on roll over */ +#define WDEN 0x0FF0 /* enable watchdog */ +#define WDDIS 0x0AD0 /* disable watchdog */ +#define WDRO 0x8000 /* watchdog rolled over latch */ + +/* deprecated WDOG_CTL Register Masks for legacy code */ +#define ICTL WDEV +#define ENABLE_RESET WDEV_RESET +#define WDOG_RESET WDEV_RESET +#define ENABLE_NMI WDEV_NMI +#define WDOG_NMI WDEV_NMI +#define ENABLE_GPI WDEV_GPI +#define WDOG_GPI WDEV_GPI +#define DISABLE_EVT WDEV_NONE +#define WDOG_NONE WDEV_NONE + +#define TMR_EN WDEN +#define WDOG_DISABLE WDDIS +#define TRO WDRO + +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + + +/* *************** REAL TIME CLOCK MASKS **************************/ +/* RTC_STAT and RTC_ALARM register */ +#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTHR 0x0001F000 /* Real-Time Clock Hours */ +#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ICTL register */ +#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ +#define AIE 0x0002 /* Alarm Interrupt Enable */ +#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MIE 0x0008 /* Minutes Interrupt Enable */ +#define HIE 0x0010 /* Hours Interrupt Enable */ +#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WCIE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_ISTAT register */ +#define SWEF 0x0001 /* Stopwatch Event Flag */ +#define AEF 0x0002 /* Alarm Event Flag */ +#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ +#define MEF 0x0008 /* Minutes Event Flag */ +#define HEF 0x0010 /* Hours Event Flag */ +#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ +#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ +#define WPS 0x4000 /* Write Pending Status (RO) */ +#define WCOM 0x8000 /* Write Complete */ + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ +#define PREN 0x00000001 + /* ** Must be set after power-up for proper operation of RTC */ + +/* Deprecated RTC_STAT and RTC_ALARM Masks */ +#define RTC_SEC RTSEC /* Real-Time Clock Seconds */ +#define RTC_MIN RTMIN /* Real-Time Clock Minutes */ +#define RTC_HR RTHR /* Real-Time Clock Hours */ +#define RTC_DAY RTDAY /* Real-Time Clock Days */ + +/* Deprecated RTC_ICTL/RTC_ISTAT Masks */ +#define STOPWATCH SWIE /* Stopwatch Interrupt Enable */ +#define ALARM AIE /* Alarm Interrupt Enable */ +#define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */ +#define MINUTE MIE /* Minutes Interrupt Enable */ +#define HOUR HIE /* Hours Interrupt Enable */ +#define DAY DIE /* 24 Hours (Days) Interrupt Enable */ +#define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */ + + /* ***************************** UART CONTROLLER MASKS ********************** */ /* UARTx_LCR Register */ #ifdef _MISRA_RULES @@ -1757,6 +1917,52 @@ /* ********** DMA CONTROLLER MASKS ***********************/ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Word Size 8 bits */ +#define WDSIZE_16 0x0004 /* Word Size 16 bits */ +#define WDSIZE_32 0x0008 /* Word Size 32 bits */ +#define DMA2D 0x0010 /* 2D/1D* Mode */ +#define RESTART 0x0020 /* Restart */ +#define DI_SEL 0x0040 /* Data Interrupt Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE 0x0900 /* Next Descriptor Size */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ + +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +#define DMAEN_P 0x0 /* Channel Enable */ +#define WNR_P 0x1 /* Channel Direction (W/R*) */ +#define DMA2D_P 0x4 /* 2D/1D* Mode */ +#define RESTART_P 0x5 /* Restart */ +#define DI_SEL_P 0x6 /* Data Interrupt Select */ +#define DI_EN_P 0x7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Done Indicator */ +#define DMA_ERR 0x0002 /* DMA Error Indicator */ +#define DFETCH 0x0004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0x0 /* DMA Done Indicator */ +#define DMA_ERR_P 0x1 /* DMA Error Indicator */ +#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 0x3 /* DMA Running Indicator */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ @@ -2419,6 +2625,1019 @@ #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ +/********************************* MXVR MASKS ****************************************/ + +/* MXVR_CONFIG Masks */ + +#define MXVREN 0x00000001lu +#define MMSM 0x00000002lu +#define ACTIVE 0x00000004lu +#define SDELAY 0x00000008lu +#define NCMRXEN 0x00000010lu +#define RWRRXEN 0x00000020lu +#define MTXEN 0x00000040lu +#define MTXON 0x00000080lu /*legacy*/ +#define MTXONB 0x00000080lu +#define EPARITY 0x00000100lu +#define MSB 0x00001E00lu +#define APRXEN 0x00002000lu +#define WAKEUP 0x00004000lu +#define LMECH 0x00008000lu + +#ifdef _MISRA_RULES +#define SET_MSB(x) (((x)&0xFu) << 0x9) +#else +#define SET_MSB(x) (((x)&0xF) << 0x9) +#endif /* _MISRA_RULES */ + + +/* MXVR_PLL_CTL_0 Masks */ + +#define MXTALCEN 0x00000001lu +#define MXTALFEN 0x00000002lu +#define MPLLMS 0x00000008lu +#define MXTALMUL 0x00000030lu +#define MPLLEN 0x00000040lu +#define MPLLEN0 0x00000040lu /* legacy */ +#define MPLLEN1 0x00000080lu /* legacy */ +#define MMCLKEN 0x00000100lu +#define MMCLKMUL 0x00001E00lu +#define MPLLRSTB 0x00002000lu +#define MPLLRSTB0 0x00002000lu /* legacy */ +#define MPLLRSTB1 0x00004000lu /* legacy */ +#define MBCLKEN 0x00010000lu +#define MBCLKDIV 0x001E0000lu +#define MPLLCDR 0x00200000lu +#define MPLLCDR0 0x00200000lu /* legacy */ +#define MPLLCDR1 0x00400000lu /* legacy */ +#define INVRX 0x00800000lu +#define MFSEN 0x01000000lu +#define MFSDIV 0x1E000000lu +#define MFSSEL 0x60000000lu +#define MFSSYNC 0x80000000lu + +#define MXTALMUL_256FS 0x00000000lu /* legacy */ +#define MXTALMUL_384FS 0x00000010lu /* legacy */ +#define MXTALMUL_512FS 0x00000020lu /* legacy */ +#define MXTALMUL_1024FS 0x00000030lu + +#define MMCLKMUL_1024FS 0x00000000lu +#define MMCLKMUL_512FS 0x00000200lu +#define MMCLKMUL_256FS 0x00000400lu +#define MMCLKMUL_128FS 0x00000600lu +#define MMCLKMUL_64FS 0x00000800lu +#define MMCLKMUL_32FS 0x00000A00lu +#define MMCLKMUL_16FS 0x00000C00lu +#define MMCLKMUL_8FS 0x00000E00lu +#define MMCLKMUL_4FS 0x00001000lu +#define MMCLKMUL_2FS 0x00001200lu +#define MMCLKMUL_1FS 0x00001400lu +#define MMCLKMUL_1536FS 0x00001A00lu +#define MMCLKMUL_768FS 0x00001C00lu +#define MMCLKMUL_384FS 0x00001E00lu + +#define MBCLKDIV_DIV2 0x00020000lu +#define MBCLKDIV_DIV4 0x00040000lu +#define MBCLKDIV_DIV8 0x00060000lu +#define MBCLKDIV_DIV16 0x00080000lu +#define MBCLKDIV_DIV32 0x000A0000lu +#define MBCLKDIV_DIV64 0x000C0000lu +#define MBCLKDIV_DIV128 0x000E0000lu +#define MBCLKDIV_DIV256 0x00100000lu +#define MBCLKDIV_DIV512 0x00120000lu +#define MBCLKDIV_DIV1024 0x00140000lu + +#define MFSDIV_DIV2 0x02000000lu +#define MFSDIV_DIV4 0x04000000lu +#define MFSDIV_DIV8 0x06000000lu +#define MFSDIV_DIV16 0x08000000lu +#define MFSDIV_DIV32 0x0A000000lu +#define MFSDIV_DIV64 0x0C000000lu +#define MFSDIV_DIV128 0x0E000000lu +#define MFSDIV_DIV256 0x10000000lu +#define MFSDIV_DIV512 0x12000000lu +#define MFSDIV_DIV1024 0x14000000lu + +#define MFSSEL_CLOCK 0x00000000lu +#define MFSSEL_PULSE_HI 0x20000000lu +#define MFSSEL_PULSE_LO 0x40000000lu + + +/* MXVR_PLL_CTL_1 Masks */ + +#define MSTO 0x00000001lu +#define MSTO0 0x00000001lu /* legacy */ +#define MHOGGD 0x00000004lu +#define MHOGGD0 0x00000004lu /* legacy */ +#define MHOGGD1 0x00000008lu /* legacy */ +#define MSHAPEREN 0x00000010lu +#define MSHAPEREN0 0x00000010lu /* legacy */ +#define MSHAPEREN1 0x00000020lu /* legacy */ +#define MPLLCNTEN 0x00008000lu +#define MPLLCNT 0xFFFF0000lu + +#ifdef _MISRA_RULES +#define SET_MPLLCNT(x) (((x)&0xFFFFu) << 0x10) +#else +#define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10) +#endif /* _MISRA_RULES */ + + +/* MXVR_PLL_CTL_2 Masks */ + +#define MSHAPERSEL 0x00000007lu +#define MCPSEL 0x000000E0lu + +/* MXVR_INT_STAT_0 Masks */ + +#define NI2A 0x00000001lu +#define NA2I 0x00000002lu +#define SBU2L 0x00000004lu +#define SBL2U 0x00000008lu +#define PRU 0x00000010lu +#define MPRU 0x00000020lu +#define DRU 0x00000040lu +#define MDRU 0x00000080lu +#define SBU 0x00000100lu +#define ATU 0x00000200lu +#define FCZ0 0x00000400lu +#define FCZ1 0x00000800lu +#define PERR 0x00001000lu +#define MH2L 0x00002000lu +#define ML2H 0x00004000lu +#define WUP 0x00008000lu +#define FU2L 0x00010000lu +#define FL2U 0x00020000lu +#define BU2L 0x00040000lu +#define BL2U 0x00080000lu +#define PCZ 0x00400000lu +#define FERR 0x00800000lu +#define CMR 0x01000000lu +#define CMROF 0x02000000lu +#define CMTS 0x04000000lu +#define CMTC 0x08000000lu +#define RWRC 0x10000000lu +#define BCZ 0x20000000lu +#define BMERR 0x40000000lu +#define DERR 0x80000000lu + + +/* MXVR_INT_EN_0 Masks */ + +#define NI2AEN NI2A +#define NA2IEN NA2I +#define SBU2LEN SBU2L +#define SBL2UEN SBL2U +#define PRUEN PRU +#define MPRUEN MPRU +#define DRUEN DRU +#define MDRUEN MDRU +#define SBUEN SBU +#define ATUEN ATU +#define FCZ0EN FCZ0 +#define FCZ1EN FCZ1 +#define PERREN PERR +#define MH2LEN MH2L +#define ML2HEN ML2H +#define WUPEN WUP +#define FU2LEN FU2L +#define FL2UEN FL2U +#define BU2LEN BU2L +#define BL2UEN BL2U +#define PCZEN PCZ +#define FERREN FERR +#define CMREN CMR +#define CMROFEN CMROF +#define CMTSEN CMTS +#define CMTCEN CMTC +#define RWRCEN RWRC +#define BCZEN BCZ +#define BMERREN BMERR +#define DERREN DERR + + +/* MXVR_INT_STAT_1 Masks */ + +#define APR 0x00000004lu +#define APROF 0x00000008lu +#define APTS 0x00000040lu +#define APTC 0x00000080lu +#define APRCE 0x00000400lu +#define APRPE 0x00000800lu + +#define HDONE0 0x00000001lu +#define DONE0 0x00000002lu +#define HDONE1 0x00000010lu +#define DONE1 0x00000020lu +#define HDONE2 0x00000100lu +#define DONE2 0x00000200lu +#define HDONE3 0x00001000lu +#define DONE3 0x00002000lu +#define HDONE4 0x00010000lu +#define DONE4 0x00020000lu +#define HDONE5 0x00100000lu +#define DONE5 0x00200000lu +#define HDONE6 0x01000000lu +#define DONE6 0x02000000lu +#define HDONE7 0x10000000lu +#define DONE7 0x20000000lu + +#define DONEX(x) (0x00000002 << (4 * (x))) +#define HDONEX(x) (0x00000001 << (4 * (x))) + + +/* MXVR_INT_EN_1 Masks */ + +#define APREN APR +#define APROFEN APROF +#define APTSEN APTS +#define APTCEN APTC +#define APRCEEN APRCE +#define APRPEEN APRPE + +#define HDONEEN0 HDONE0 +#define DONEEN0 DONE0 +#define HDONEEN1 HDONE1 +#define DONEEN1 DONE1 +#define HDONEEN2 HDONE2 +#define DONEEN2 DONE2 +#define HDONEEN3 HDONE3 +#define DONEEN3 DONE3 +#define HDONEEN4 HDONE4 +#define DONEEN4 DONE4 +#define HDONEEN5 HDONE5 +#define DONEEN5 DONE5 +#define HDONEEN6 HDONE6 +#define DONEEN6 DONE6 +#define HDONEEN7 HDONE7 +#define DONEEN7 DONE7 + +#define DONEENX(x) (0x00000002 << (4 * (x))) +#define HDONEENX(x) (0x00000001 << (4 * (x))) + + +/* MXVR_STATE_0 Masks */ + +#define NACT 0x00000001lu +#define SBLOCK 0x00000002lu +#define PFDLOCK 0x00000004lu +#define PFDLOCK0 0x00000004lu /* legacy */ +#define PDD 0x00000008lu +#define PDD0 0x00000008lu /* legacy */ +#define PVCO 0x00000010lu +#define PVCO0 0x00000010lu /* legacy */ +#define PFDLOCK1 0x00000020lu /* legacy */ +#define PDD1 0x00000040lu /* legacy */ +#define PVCO1 0x00000080lu /* legacy */ +#define APBSY 0x00000100lu +#define APARB 0x00000200lu +#define APTX 0x00000400lu +#define APRX 0x00000800lu +#define CMBSY 0x00001000lu +#define CMARB 0x00002000lu +#define CMTX 0x00004000lu +#define CMRX 0x00008000lu +#define MRXONB 0x00010000lu +#define RGSIP 0x00020000lu +#define DALIP 0x00040000lu +#define ALIP 0x00080000lu +#define RRDIP 0x00100000lu +#define RWRIP 0x00200000lu +#define FLOCK 0x00400000lu +#define BLOCK 0x00800000lu +#define RSB 0x0F000000lu +#define DERRNUM 0xF0000000lu + + +/* MXVR_STATE_1 Masks */ + +#define STXNUMB 0x0000000Flu +#define SRXNUMB 0x000000F0lu +#define APCONT 0x00000100lu +#define DMAACTIVEX 0x00FF0000lu +#define DMAACTIVE0 0x00010000lu +#define DMAACTIVE1 0x00020000lu +#define DMAACTIVE2 0x00040000lu +#define DMAACTIVE3 0x00080000lu +#define DMAACTIVE4 0x00100000lu +#define DMAACTIVE5 0x00200000lu +#define DMAACTIVE6 0x00400000lu +#define DMAACTIVE7 0x00800000lu +#define DMAPMENX 0xFF000000lu +#define DMAPMEN0 0x01000000lu +#define DMAPMEN1 0x02000000lu +#define DMAPMEN2 0x04000000lu +#define DMAPMEN3 0x08000000lu +#define DMAPMEN4 0x10000000lu +#define DMAPMEN5 0x20000000lu +#define DMAPMEN6 0x40000000lu +#define DMAPMEN7 0x80000000lu + + +/* MXVR_POSITION Masks */ + +#define PVALID 0x8000 +#define POSITION 0x003F + + +/* MXVR_MAX_POSITION Masks */ + +#define MPVALID 0x8000 +#define MPOSITION 0x003F + + +/* MXVR_DELAY Masks */ + +#define DVALID 0x8000 +#define DELAY 0x003F + + +/* MXVR_MAX_DELAY Masks */ + +#define MDVALID 0x8000 +#define MDELAY 0x003F + + +/* MXVR_LADDR Masks */ + +#define LVALID 0x80000000lu +#define LADDR 0x0000FFFFlu + + +/* MXVR_GADDR Masks */ + +#define GVALID 0x8000 +#define GADDRL 0x00FF + + +/* MXVR_AADDR Masks */ + +#define AVALID 0x80000000lu +#define AADDR 0x0000FFFFlu + + +/* MXVR_ALLOC_0 Masks */ + +#define CIU0 0x00000080lu +#define CIU1 0x00008000lu +#define CIU2 0x00800000lu +#define CIU3 0x80000000lu + +#define CL0 0x0000007Flu +#define CL1 0x00007F00lu +#define CL2 0x007F0000lu +#define CL3 0x7F000000lu + + +/* MXVR_ALLOC_1 Masks */ + +#define CIU4 0x00000080lu +#define CIU5 0x00008000lu +#define CIU6 0x00800000lu +#define CIU7 0x80000000lu + +#define CL4 0x0000007Flu +#define CL5 0x00007F00lu +#define CL6 0x007F0000lu +#define CL7 0x7F000000lu + + +/* MXVR_ALLOC_2 Masks */ + +#define CIU8 0x00000080lu +#define CIU9 0x00008000lu +#define CIU10 0x00800000lu +#define CIU11 0x80000000lu + +#define CL8 0x0000007Flu +#define CL9 0x00007F00lu +#define CL10 0x007F0000lu +#define CL11 0x7F000000lu + + +/* MXVR_ALLOC_3 Masks */ + +#define CIU12 0x00000080lu +#define CIU13 0x00008000lu +#define CIU14 0x00800000lu +#define CIU15 0x80000000lu + +#define CL12 0x0000007Flu +#define CL13 0x00007F00lu +#define CL14 0x007F0000lu +#define CL15 0x7F000000lu + + +/* MXVR_ALLOC_4 Masks */ + +#define CIU16 0x00000080lu +#define CIU17 0x00008000lu +#define CIU18 0x00800000lu +#define CIU19 0x80000000lu + +#define CL16 0x0000007Flu +#define CL17 0x00007F00lu +#define CL18 0x007F0000lu +#define CL19 0x7F000000lu + + +/* MXVR_ALLOC_5 Masks */ + +#define CIU20 0x00000080lu +#define CIU21 0x00008000lu +#define CIU22 0x00800000lu +#define CIU23 0x80000000lu + +#define CL20 0x0000007Flu +#define CL21 0x00007F00lu +#define CL22 0x007F0000lu +#define CL23 0x7F000000lu + + +/* MXVR_ALLOC_6 Masks */ + +#define CIU24 0x00000080lu +#define CIU25 0x00008000lu +#define CIU26 0x00800000lu +#define CIU27 0x80000000lu + +#define CL24 0x0000007Flu +#define CL25 0x00007F00lu +#define CL26 0x007F0000lu +#define CL27 0x7F000000lu + + +/* MXVR_ALLOC_7 Masks */ + +#define CIU28 0x00000080lu +#define CIU29 0x00008000lu +#define CIU30 0x00800000lu +#define CIU31 0x80000000lu + +#define CL28 0x0000007Flu +#define CL29 0x00007F00lu +#define CL30 0x007F0000lu +#define CL31 0x7F000000lu + + +/* MXVR_ALLOC_8 Masks */ + +#define CIU32 0x00000080lu +#define CIU33 0x00008000lu +#define CIU34 0x00800000lu +#define CIU35 0x80000000lu + +#define CL32 0x0000007Flu +#define CL33 0x00007F00lu +#define CL34 0x007F0000lu +#define CL35 0x7F000000lu + + +/* MXVR_ALLOC_9 Masks */ + +#define CIU36 0x00000080lu +#define CIU37 0x00008000lu +#define CIU38 0x00800000lu +#define CIU39 0x80000000lu + +#define CL36 0x0000007Flu +#define CL37 0x00007F00lu +#define CL38 0x007F0000lu +#define CL39 0x7F000000lu + + +/* MXVR_ALLOC_10 Masks */ + +#define CIU40 0x00000080lu +#define CIU41 0x00008000lu +#define CIU42 0x00800000lu +#define CIU43 0x80000000lu + +#define CL40 0x0000007Flu +#define CL41 0x00007F00lu +#define CL42 0x007F0000lu +#define CL43 0x7F000000lu + + +/* MXVR_ALLOC_11 Masks */ + +#define CIU44 0x00000080lu +#define CIU45 0x00008000lu +#define CIU46 0x00800000lu +#define CIU47 0x80000000lu + +#define CL44 0x0000007Flu +#define CL45 0x00007F00lu +#define CL46 0x007F0000lu +#define CL47 0x7F000000lu + + +/* MXVR_ALLOC_12 Masks */ + +#define CIU48 0x00000080lu +#define CIU49 0x00008000lu +#define CIU50 0x00800000lu +#define CIU51 0x80000000lu + +#define CL48 0x0000007Flu +#define CL49 0x00007F00lu +#define CL50 0x007F0000lu +#define CL51 0x7F000000lu + + +/* MXVR_ALLOC_13 Masks */ + +#define CIU52 0x00000080lu +#define CIU53 0x00008000lu +#define CIU54 0x00800000lu +#define CIU55 0x80000000lu + +#define CL52 0x0000007Flu +#define CL53 0x00007F00lu +#define CL54 0x007F0000lu +#define CL55 0x7F000000lu + + +/* MXVR_ALLOC_14 Masks */ + +#define CIU56 0x00000080lu +#define CIU57 0x00008000lu +#define CIU58 0x00800000lu +#define CIU59 0x80000000lu + +#define CL56 0x0000007Flu +#define CL57 0x00007F00lu +#define CL58 0x007F0000lu +#define CL59 0x7F000000lu + + +/* MXVR_SYNC_LCHAN_0 Masks */ + +#define LCHANPC0 0x0000000Flu +#define LCHANPC1 0x000000F0lu +#define LCHANPC2 0x00000F00lu +#define LCHANPC3 0x0000F000lu +#define LCHANPC4 0x000F0000lu +#define LCHANPC5 0x00F00000lu +#define LCHANPC6 0x0F000000lu +#define LCHANPC7 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_1 Masks */ + +#define LCHANPC8 0x0000000Flu +#define LCHANPC9 0x000000F0lu +#define LCHANPC10 0x00000F00lu +#define LCHANPC11 0x0000F000lu +#define LCHANPC12 0x000F0000lu +#define LCHANPC13 0x00F00000lu +#define LCHANPC14 0x0F000000lu +#define LCHANPC15 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_2 Masks */ + +#define LCHANPC16 0x0000000Flu +#define LCHANPC17 0x000000F0lu +#define LCHANPC18 0x00000F00lu +#define LCHANPC19 0x0000F000lu +#define LCHANPC20 0x000F0000lu +#define LCHANPC21 0x00F00000lu +#define LCHANPC22 0x0F000000lu +#define LCHANPC23 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_3 Masks */ + +#define LCHANPC24 0x0000000Flu +#define LCHANPC25 0x000000F0lu +#define LCHANPC26 0x00000F00lu +#define LCHANPC27 0x0000F000lu +#define LCHANPC28 0x000F0000lu +#define LCHANPC29 0x00F00000lu +#define LCHANPC30 0x0F000000lu +#define LCHANPC31 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_4 Masks */ + +#define LCHANPC32 0x0000000Flu +#define LCHANPC33 0x000000F0lu +#define LCHANPC34 0x00000F00lu +#define LCHANPC35 0x0000F000lu +#define LCHANPC36 0x000F0000lu +#define LCHANPC37 0x00F00000lu +#define LCHANPC38 0x0F000000lu +#define LCHANPC39 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_5 Masks */ + +#define LCHANPC40 0x0000000Flu +#define LCHANPC41 0x000000F0lu +#define LCHANPC42 0x00000F00lu +#define LCHANPC43 0x0000F000lu +#define LCHANPC44 0x000F0000lu +#define LCHANPC45 0x00F00000lu +#define LCHANPC46 0x0F000000lu +#define LCHANPC47 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_6 Masks */ + +#define LCHANPC48 0x0000000Flu +#define LCHANPC49 0x000000F0lu +#define LCHANPC50 0x00000F00lu +#define LCHANPC51 0x0000F000lu +#define LCHANPC52 0x000F0000lu +#define LCHANPC53 0x00F00000lu +#define LCHANPC54 0x0F000000lu +#define LCHANPC55 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_7 Masks */ + +#define LCHANPC56 0x0000000Flu +#define LCHANPC57 0x000000F0lu +#define LCHANPC58 0x00000F00lu +#define LCHANPC59 0x0000F000lu + + +/* MXVR_DMAx_CONFIG Masks */ + +#define MDMAEN 0x00000001lu +#define DD 0x00000002lu +#define LCHAN 0x000003C0lu +#define BITSWAPEN 0x00000400lu +#define BYSWAPEN 0x00000800lu +#define MFLOW 0x00007000lu +#define FIXEDPM 0x00080000lu +#define STARTPAT 0x00300000lu +#define STOPPAT 0x00C00000lu +#define COUNTPOS 0x1C000000lu + +#define DD_TX 0x00000000lu +#define DD_RX 0x00000002lu + +#define LCHAN_0 0x00000000lu +#define LCHAN_1 0x00000040lu +#define LCHAN_2 0x00000080lu +#define LCHAN_3 0x000000C0lu +#define LCHAN_4 0x00000100lu +#define LCHAN_5 0x00000140lu +#define LCHAN_6 0x00000180lu +#define LCHAN_7 0x000001C0lu + +#define MFLOW_STOP 0x00000000lu +#define MFLOW_AUTO 0x00001000lu +#define MFLOW_PVC 0x00002000lu +#define MFLOW_PSS 0x00003000lu +#define MFLOW_PFC 0x00004000lu + +#define STARTPAT_0 0x00000000lu +#define STARTPAT_1 0x00100000lu + +#define STOPPAT_0 0x00000000lu +#define STOPPAT_1 0x00400000lu + +#define COUNTPOS_0 0x00000000lu +#define COUNTPOS_1 0x04000000lu +#define COUNTPOS_2 0x08000000lu +#define COUNTPOS_3 0x0C000000lu +#define COUNTPOS_4 0x10000000lu +#define COUNTPOS_5 0x14000000lu +#define COUNTPOS_6 0x18000000lu +#define COUNTPOS_7 0x1C000000lu + + +/* MXVR_AP_CTL Masks */ + +#define STARTAP 0x00000001lu +#define CANCELAP 0x00000002lu +#define RESETAP 0x00000004lu +#define APRBE0 0x00004000lu +#define APRBE1 0x00008000lu +#define APRBEX 0x0000C000lu + + +/* MXVR_CM_CTL Masks */ + +#define STARTCM 0x00000001lu +#define CANCELCM 0x00000002lu +#define CMRBEX 0xFFFF0000lu +#define CMRBE0 0x00010000lu +#define CMRBE1 0x00020000lu +#define CMRBE2 0x00040000lu +#define CMRBE3 0x00080000lu +#define CMRBE4 0x00100000lu +#define CMRBE5 0x00200000lu +#define CMRBE6 0x00400000lu +#define CMRBE7 0x00800000lu +#define CMRBE8 0x01000000lu +#define CMRBE9 0x02000000lu +#define CMRBE10 0x04000000lu +#define CMRBE11 0x08000000lu +#define CMRBE12 0x10000000lu +#define CMRBE13 0x20000000lu +#define CMRBE14 0x40000000lu +#define CMRBE15 0x80000000lu + + +/* MXVR_PAT_DATA_x Masks */ + +#define MATCH_DATA_0 0x000000FFlu +#define MATCH_DATA_1 0x0000FF00lu +#define MATCH_DATA_2 0x00FF0000lu +#define MATCH_DATA_3 0xFF000000lu + + + +/* MXVR_PAT_EN_x Masks */ + +#define MATCH_EN_0_0 0x00000001lu +#define MATCH_EN_0_1 0x00000002lu +#define MATCH_EN_0_2 0x00000004lu +#define MATCH_EN_0_3 0x00000008lu +#define MATCH_EN_0_4 0x00000010lu +#define MATCH_EN_0_5 0x00000020lu +#define MATCH_EN_0_6 0x00000040lu +#define MATCH_EN_0_7 0x00000080lu + +#define MATCH_EN_1_0 0x00000100lu +#define MATCH_EN_1_1 0x00000200lu +#define MATCH_EN_1_2 0x00000400lu +#define MATCH_EN_1_3 0x00000800lu +#define MATCH_EN_1_4 0x00001000lu +#define MATCH_EN_1_5 0x00002000lu +#define MATCH_EN_1_6 0x00004000lu +#define MATCH_EN_1_7 0x00008000lu + +#define MATCH_EN_2_0 0x00010000lu +#define MATCH_EN_2_1 0x00020000lu +#define MATCH_EN_2_2 0x00040000lu +#define MATCH_EN_2_3 0x00080000lu +#define MATCH_EN_2_4 0x00100000lu +#define MATCH_EN_2_5 0x00200000lu +#define MATCH_EN_2_6 0x00400000lu +#define MATCH_EN_2_7 0x00800000lu + +#define MATCH_EN_3_0 0x01000000lu +#define MATCH_EN_3_1 0x02000000lu +#define MATCH_EN_3_2 0x04000000lu +#define MATCH_EN_3_3 0x08000000lu +#define MATCH_EN_3_4 0x10000000lu +#define MATCH_EN_3_5 0x20000000lu +#define MATCH_EN_3_6 0x40000000lu +#define MATCH_EN_3_7 0x80000000lu + + +/* MXVR_ROUTING_0 Masks */ + +#define MUTE_CH0 0x00000080lu +#define MUTE_CH1 0x00008000lu +#define MUTE_CH2 0x00800000lu +#define MUTE_CH3 0x80000000lu + +#define TX_CH0 0x0000007Flu +#define TX_CH1 0x00007F00lu +#define TX_CH2 0x007F0000lu +#define TX_CH3 0x7F000000lu + + +/* MXVR_ROUTING_1 Masks */ + +#define MUTE_CH4 0x00000080lu +#define MUTE_CH5 0x00008000lu +#define MUTE_CH6 0x00800000lu +#define MUTE_CH7 0x80000000lu + +#define TX_CH4 0x0000007Flu +#define TX_CH5 0x00007F00lu +#define TX_CH6 0x007F0000lu +#define TX_CH7 0x7F000000lu + + +/* MXVR_ROUTING_2 Masks */ + +#define MUTE_CH8 0x00000080lu +#define MUTE_CH9 0x00008000lu +#define MUTE_CH10 0x00800000lu +#define MUTE_CH11 0x80000000lu + +#define TX_CH8 0x0000007Flu +#define TX_CH9 0x00007F00lu +#define TX_CH10 0x007F0000lu +#define TX_CH11 0x7F000000lu + +/* MXVR_ROUTING_3 Masks */ + +#define MUTE_CH12 0x00000080lu +#define MUTE_CH13 0x00008000lu +#define MUTE_CH14 0x00800000lu +#define MUTE_CH15 0x80000000lu + +#define TX_CH12 0x0000007Flu +#define TX_CH13 0x00007F00lu +#define TX_CH14 0x007F0000lu +#define TX_CH15 0x7F000000lu + + +/* MXVR_ROUTING_4 Masks */ + +#define MUTE_CH16 0x00000080lu +#define MUTE_CH17 0x00008000lu +#define MUTE_CH18 0x00800000lu +#define MUTE_CH19 0x80000000lu + +#define TX_CH16 0x0000007Flu +#define TX_CH17 0x00007F00lu +#define TX_CH18 0x007F0000lu +#define TX_CH19 0x7F000000lu + + +/* MXVR_ROUTING_5 Masks */ + +#define MUTE_CH20 0x00000080lu +#define MUTE_CH21 0x00008000lu +#define MUTE_CH22 0x00800000lu +#define MUTE_CH23 0x80000000lu + +#define TX_CH20 0x0000007Flu +#define TX_CH21 0x00007F00lu +#define TX_CH22 0x007F0000lu +#define TX_CH23 0x7F000000lu + + +/* MXVR_ROUTING_6 Masks */ + +#define MUTE_CH24 0x00000080lu +#define MUTE_CH25 0x00008000lu +#define MUTE_CH26 0x00800000lu +#define MUTE_CH27 0x80000000lu + +#define TX_CH24 0x0000007Flu +#define TX_CH25 0x00007F00lu +#define TX_CH26 0x007F0000lu +#define TX_CH27 0x7F000000lu + + +/* MXVR_ROUTING_7 Masks */ + +#define MUTE_CH28 0x00000080lu +#define MUTE_CH29 0x00008000lu +#define MUTE_CH30 0x00800000lu +#define MUTE_CH31 0x80000000lu + +#define TX_CH28 0x0000007Flu +#define TX_CH29 0x00007F00lu +#define TX_CH30 0x007F0000lu +#define TX_CH31 0x7F000000lu + + +/* MXVR_ROUTING_8 Masks */ + +#define MUTE_CH32 0x00000080lu +#define MUTE_CH33 0x00008000lu +#define MUTE_CH34 0x00800000lu +#define MUTE_CH35 0x80000000lu + +#define TX_CH32 0x0000007Flu +#define TX_CH33 0x00007F00lu +#define TX_CH34 0x007F0000lu +#define TX_CH35 0x7F000000lu + + +/* MXVR_ROUTING_9 Masks */ + +#define MUTE_CH36 0x00000080lu +#define MUTE_CH37 0x00008000lu +#define MUTE_CH38 0x00800000lu +#define MUTE_CH39 0x80000000lu + +#define TX_CH36 0x0000007Flu +#define TX_CH37 0x00007F00lu +#define TX_CH38 0x007F0000lu +#define TX_CH39 0x7F000000lu + + +/* MXVR_ROUTING_10 Masks */ + +#define MUTE_CH40 0x00000080lu +#define MUTE_CH41 0x00008000lu +#define MUTE_CH42 0x00800000lu +#define MUTE_CH43 0x80000000lu + +#define TX_CH40 0x0000007Flu +#define TX_CH41 0x00007F00lu +#define TX_CH42 0x007F0000lu +#define TX_CH43 0x7F000000lu + + +/* MXVR_ROUTING_11 Masks */ + +#define MUTE_CH44 0x00000080lu +#define MUTE_CH45 0x00008000lu +#define MUTE_CH46 0x00800000lu +#define MUTE_CH47 0x80000000lu + +#define TX_CH44 0x0000007Flu +#define TX_CH45 0x00007F00lu +#define TX_CH46 0x007F0000lu +#define TX_CH47 0x7F000000lu + + +/* MXVR_ROUTING_12 Masks */ + +#define MUTE_CH48 0x00000080lu +#define MUTE_CH49 0x00008000lu +#define MUTE_CH50 0x00800000lu +#define MUTE_CH51 0x80000000lu + +#define TX_CH48 0x0000007Flu +#define TX_CH49 0x00007F00lu +#define TX_CH50 0x007F0000lu +#define TX_CH51 0x7F000000lu + + +/* MXVR_ROUTING_13 Masks */ + +#define MUTE_CH52 0x00000080lu +#define MUTE_CH53 0x00008000lu +#define MUTE_CH54 0x00800000lu +#define MUTE_CH55 0x80000000lu + +#define TX_CH52 0x0000007Flu +#define TX_CH53 0x00007F00lu +#define TX_CH54 0x007F0000lu +#define TX_CH55 0x7F000000lu + + +/* MXVR_ROUTING_14 Masks */ + +#define MUTE_CH56 0x00000080lu +#define MUTE_CH57 0x00008000lu +#define MUTE_CH58 0x00800000lu +#define MUTE_CH59 0x80000000lu + +#define TX_CH56 0x0000007Flu +#define TX_CH57 0x00007F00lu +#define TX_CH58 0x007F0000lu +#define TX_CH59 0x7F000000lu + + +/* Control Message Receive Buffer (CMRB) Address Offsets */ + +#define CMRB_STRIDE 0x00000016lu + +#define CMRB_DST_OFFSET 0x00000000lu +#define CMRB_SRC_OFFSET 0x00000002lu +#define CMRB_DATA_OFFSET 0x00000005lu + + +/* Control Message Transmit Buffer (CMTB) Address Offsets */ + +#define CMTB_PRIO_OFFSET 0x00000000lu +#define CMTB_DST_OFFSET 0x00000002lu +#define CMTB_SRC_OFFSET 0x00000004lu +#define CMTB_TYPE_OFFSET 0x00000006lu +#define CMTB_DATA_OFFSET 0x00000007lu + +#define CMTB_ANSWER_OFFSET 0x0000000Alu + +#define CMTB_STAT_N_OFFSET 0x00000018lu +#define CMTB_STAT_A_OFFSET 0x00000016lu +#define CMTB_STAT_D_OFFSET 0x0000000Elu +#define CMTB_STAT_R_OFFSET 0x00000014lu +#define CMTB_STAT_W_OFFSET 0x00000014lu +#define CMTB_STAT_G_OFFSET 0x00000014lu + + +/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */ + +#define APRB_STRIDE 0x00000400lu + +#define APRB_DST_OFFSET 0x00000000lu +#define APRB_LEN_OFFSET 0x00000002lu +#define APRB_SRC_OFFSET 0x00000004lu +#define APRB_DATA_OFFSET 0x00000006lu + + +/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */ + +#define APTB_PRIO_OFFSET 0x00000000lu +#define APTB_DST_OFFSET 0x00000002lu +#define APTB_LEN_OFFSET 0x00000004lu +#define APTB_SRC_OFFSET 0x00000006lu +#define APTB_DATA_OFFSET 0x00000008lu + + +/* Remote Read Buffer (RRDB) Address Offsets */ + +#define RRDB_WADDR_OFFSET 0x00000100lu +#define RRDB_WLEN_OFFSET 0x00000101lu + + + /* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ /* CAN_CONTROL Masks */ #define SRS 0x0001 /* Software Reset */ diff --git a/trunk/arch/blackfin/mach-bf538/include/mach/gpio.h b/trunk/arch/blackfin/mach-bf538/include/mach/gpio.h index 0c346fba9619..295c78a465c2 100644 --- a/trunk/arch/blackfin/mach-bf538/include/mach/gpio.h +++ b/trunk/arch/blackfin/mach-bf538/include/mach/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2009 Analog Devices Inc. + * Copyright (C) 2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -7,8 +7,11 @@ #ifndef _MACH_GPIO_H_ #define _MACH_GPIO_H_ + /* FIXME: + * For now only support PORTF GPIOs. + * PORT C,D and E are for peripheral usage only + */ #define MAX_BLACKFIN_GPIOS 16 -#define BFIN_SPECIAL_GPIO_BANKS 3 #define GPIO_PF0 0 /* PF */ #define GPIO_PF1 1 diff --git a/trunk/arch/blackfin/mach-bf538/include/mach/portmux.h b/trunk/arch/blackfin/mach-bf538/include/mach/portmux.h index 0083ba13ee9e..6121cf8b5872 100644 --- a/trunk/arch/blackfin/mach-bf538/include/mach/portmux.h +++ b/trunk/arch/blackfin/mach-bf538/include/mach/portmux.h @@ -7,7 +7,7 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ -#define MAX_RESOURCES 64 +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS #define P_TMR2 (P_DONTCARE) #define P_TMR1 (P_DONTCARE) diff --git a/trunk/arch/blackfin/mach-bf548/Kconfig b/trunk/arch/blackfin/mach-bf548/Kconfig index 70189a0d1a19..a09623dfd550 100644 --- a/trunk/arch/blackfin/mach-bf548/Kconfig +++ b/trunk/arch/blackfin/mach-bf548/Kconfig @@ -1,27 +1,3 @@ -config BF542 - def_bool y - depends on BF542_std || BF542M -config BF544 - def_bool y - depends on BF544_std || BF544M -config BF547 - def_bool y - depends on BF547_std || BF547M -config BF548 - def_bool y - depends on BF548_std || BF548M -config BF549 - def_bool y - depends on BF549_std || BF549M - -config BF54xM - def_bool y - depends on (BF542M || BF544M || BF547M || BF548M || BF549M) - -config BF54x - def_bool y - depends on (BF542 || BF544 || BF547 || BF548 || BF549) - if (BF54x) source "arch/blackfin/mach-bf548/boards/Kconfig" diff --git a/trunk/arch/blackfin/mach-bf548/boards/ezkit.c b/trunk/arch/blackfin/mach-bf548/boards/ezkit.c index 60193f72777c..1a5286bbb3fa 100644 --- a/trunk/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/trunk/arch/blackfin/mach-bf548/boards/ezkit.c @@ -62,7 +62,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -154,7 +154,7 @@ static struct platform_device bf54x_kpad_device = { }; #endif -#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) #include static struct bfin_rotary_platform_data bfin_rotary_data = { @@ -186,7 +186,7 @@ static struct platform_device bfin_rotary_device = { #endif #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) -#include +#include static const struct adxl34x_platform_data adxl34x_info = { .x_axis_offset = 0, .y_axis_offset = 0, @@ -210,17 +210,14 @@ static const struct adxl34x_platform_data adxl34x_info = { .ev_code_y = ABS_Y, /* EV_REL */ .ev_code_z = ABS_Z, /* EV_REL */ - .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ + .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ + .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */ + .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */ /* .ev_code_ff = KEY_F,*/ /* EV_KEY */ /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, .fifo_mode = ADXL_FIFO_STREAM, - .orientation_enable = ADXL_EN_ORIENTATION_3D, - .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, - .divisor_length = ADXL_LP_FILTER_DIVISOR_16, - /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ - .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, }; #endif @@ -464,44 +461,6 @@ static struct platform_device musb_device = { }; #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN0_RX, - .end = IRQ_CAN0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_TX, - .end = IRQ_CAN0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_ERROR, - .end = IRQ_CAN0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif - #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) static struct resource bfin_atapi_resources[] = { { @@ -994,10 +953,6 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_isp1760_device, #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) - &bfin_can_device, -#endif - #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) &bfin_atapi_device, #endif @@ -1019,7 +974,7 @@ static struct platform_device *ezkit_devices[] __initdata = { &bf54x_kpad_device, #endif -#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) &bfin_rotary_device, #endif diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/bf548.h b/trunk/arch/blackfin/mach-bf548/include/mach/bf548.h index 751e5e11ecf8..7bead5ce0f3b 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/bf548.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/bf548.h @@ -81,6 +81,18 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN) +#if defined(CONFIG_BF542M) +# define CONFIG_BF542 +#elif defined(CONFIG_BF544M) +# define CONFIG_BF544 +#elif defined(CONFIG_BF547M) +# define CONFIG_BF547 +#elif defined(CONFIG_BF548M) +# define CONFIG_BF548 +#elif defined(CONFIG_BF549M) +# define CONFIG_BF549 +#endif + #if defined(CONFIG_BF542) # define CPU "BF542" # define CPUID 0x27de diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf548/include/mach/blackfin.h index 5684030ccc21..13302b67857a 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/blackfin.h @@ -64,4 +64,10 @@ #define OFFSET_THR 0x28 /* Transmit Holding register */ #define OFFSET_RBR 0x2C /* Receive Buffer register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF547.h index bc650e6ea482..423421515134 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF547.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF547.h @@ -4,21 +4,21 @@ * Licensed under the GPL-2 or later. */ -#ifndef _CDEF_BF547_H -#define _CDEF_BF547_H +#ifndef _CDEF_BF548_H +#define _CDEF_BF548_H /* include all Core registers and bit definitions */ -#include "defBF547.h" +#include "defBF548.h" /* include core sbfin_read_()ecific register pointer definitions */ #include -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */ +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" -/* The following are the #defines needed by ADSP-BF547 that are not in the common header */ +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ /* Timer Registers */ @@ -805,4 +805,4 @@ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#endif /* _CDEF_BF547_H */ +#endif /* _CDEF_BF548_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF548.h index 3523e08f7968..df84180410c4 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF548.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF548.h @@ -18,8 +18,165 @@ /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" -/* The BF548 is like the BF547, but has additional CANs */ -#include "cdefBF547.h" +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* SPORT0 Registers */ + +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* UART2 Registers */ + +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) +#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) +#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) +#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) +#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) + +/* Two Wire Interface Registers (TWI1) */ + +/* SPI2 Registers */ + +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) /* CAN Controller 1 Config 1 Registers */ @@ -766,4 +923,631 @@ #define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) #define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + #endif /* _CDEF_BF548_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF549.h index 80201ed41f80..34c84c7fb256 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF549.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF549.h @@ -18,8 +18,165 @@ /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" -/* The BF549 is like the BF544, but has MXVR */ -#include "cdefBF547.h" +/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* SPORT0 Registers */ + +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* UART2 Registers */ + +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) +#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) +#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) +#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) +#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) + +/* Two Wire Interface Registers (TWI1) */ + +/* SPI2 Registers */ + +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) /* MXVR Registers */ @@ -307,4 +464,1376 @@ #define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT) #define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val) +/* CAN Controller 1 Config 1 Registers */ + +#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) +#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) +#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) +#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) +#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) +#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) +#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) +#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) +#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) +#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) +#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) +#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) +#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) +#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) +#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) +#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) +#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) +#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) +#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) +#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) +#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) +#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) +#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) +#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) +#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) +#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) + +/* CAN Controller 1 Config 2 Registers */ + +#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) +#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) +#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) +#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) +#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) +#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) +#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) +#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) +#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) +#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) +#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) +#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) +#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) +#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) +#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) +#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) +#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) +#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) +#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) +#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) +#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) +#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) +#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) +#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) +#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) +#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) + +/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */ + +#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) +#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) +#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) +#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) +#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) +#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) +#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) +#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) +#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) +#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) +#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) +#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) +#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) +#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) +#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) +#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) +#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) +#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) +#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) +#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) +#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) +#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) +#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) +#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) +#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) +#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) +#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) +#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) +#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) +#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) +#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) +#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) +#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) +#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) +#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) +#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) +#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) +#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) +#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) +#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) +#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) +#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) +#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) +#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) +#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) +#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) +#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) +#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) +#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) +#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) +#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) +#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) +#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) +#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) +#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) +#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) +#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) +#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) +#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) +#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) +#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) +#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) +#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) +#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) +#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) +#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) +#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) +#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) +#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) +#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) +#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) +#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) +#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) +#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) +#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) +#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) +#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) +#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) +#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) +#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) +#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) +#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) +#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) +#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) +#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) +#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) +#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) +#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) +#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) +#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) +#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) +#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) +#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) +#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) +#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) +#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) +#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) +#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) +#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) +#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) +#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) +#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) +#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) +#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) +#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) +#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) +#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) +#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) +#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) +#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) +#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) +#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) +#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) +#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) +#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) +#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) +#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) +#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) +#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) +#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) +#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) +#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) +#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) +#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) +#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) +#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) +#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) +#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) +#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) +#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) +#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) +#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) +#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) +#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) +#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) +#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) +#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) +#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) +#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) +#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) +#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) +#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) +#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) +#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) +#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) +#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) +#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) +#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) +#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) +#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) +#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) +#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) +#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) +#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) +#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) +#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) +#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) +#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) +#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) +#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) +#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) +#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) +#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) +#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) +#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) +#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) +#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) +#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) +#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) +#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) +#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) +#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) +#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) +#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) +#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) +#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) +#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) +#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) +#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) +#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) +#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) +#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) +#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) +#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) +#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) +#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) +#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) +#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) +#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) +#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) +#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) +#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) +#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) +#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) +#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) +#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) +#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) +#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) +#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) +#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) +#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) +#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) +#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) +#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) +#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) +#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) +#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) +#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) +#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) +#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) +#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) +#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) +#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) +#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) +#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) +#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) +#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) +#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) +#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) +#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) +#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) +#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) +#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) +#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) +#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) +#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) +#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) +#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) +#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) +#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) +#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) +#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) +#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) +#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) +#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) +#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) +#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) +#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) +#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) +#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) +#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) +#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) +#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) +#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) +#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) +#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) +#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) +#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) +#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) +#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) +#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) +#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) +#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) +#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) +#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) +#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) +#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) +#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) +#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) +#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) +#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) +#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) +#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) +#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) +#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) +#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) +#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) +#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) +#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) +#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) +#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) +#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) +#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) +#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) +#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) +#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) +#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) +#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) +#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) +#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) +#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) +#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) +#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) +#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) +#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) +#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) +#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) +#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) +#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) +#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) +#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) +#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) +#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) +#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) +#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) +#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) +#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) +#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) +#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) +#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) +#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) +#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) +#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) +#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) +#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) +#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) +#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) +#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) +#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) +#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) +#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) +#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) +#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) +#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) +#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) +#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) +#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) +#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) +#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) +#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) +#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) +#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) +#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) +#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) +#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) +#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) +#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) +#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) +#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) +#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) +#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) +#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) +#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) +#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) +#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) +#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) +#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) +#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) +#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) +#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) +#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) +#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) +#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) +#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) +#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) +#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) +#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) +#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) +#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) +#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) +#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) +#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) +#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) +#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) +#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) +#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) +#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) +#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) +#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) +#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) +#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) +#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) +#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) +#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) +#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) +#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) +#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) +#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) +#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) +#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) +#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) +#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) +#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) +#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) +#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) +#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) +#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) +#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) +#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) +#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) +#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) +#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) +#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) +#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) +#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) +#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) +#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) +#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) +#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) +#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) +#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) +#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) +#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) +#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) +#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) +#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) +#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) +#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) +#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) +#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) +#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) +#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) +#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) +#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) +#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) +#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) +#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) +#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) +#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) +#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) +#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) +#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) +#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) +#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) +#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) +#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) +#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) +#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) +#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) +#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) +#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) +#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) +#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) +#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) +#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) +#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) +#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) +#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) +#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) +#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) +#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) +#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) +#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) +#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) +#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) +#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) +#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) +#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) +#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) +#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) +#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) +#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) +#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) +#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) +#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) +#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) +#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) +#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) +#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) +#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) +#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) +#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) +#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) +#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) +#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) +#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) +#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) +#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) +#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) +#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) +#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) +#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) +#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) +#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) +#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) +#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) +#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) +#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) +#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) +#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) +#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) +#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) +#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) +#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) +#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) +#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) +#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) +#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) +#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) +#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) +#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) +#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) +#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) +#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) +#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) +#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) +#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) +#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) +#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) +#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) +#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) +#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) +#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) +#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) +#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) +#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) +#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) +#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) +#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) +#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) +#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) +#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) +#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) +#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) +#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) +#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) +#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) +#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) +#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) +#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) +#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) +#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) +#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) +#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) +#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) +#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) +#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) +#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) +#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) +#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) +#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) +#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) +#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) +#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) +#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) +#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) +#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) +#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) +#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) +#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) +#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) +#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) +#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) +#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) +#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) +#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) +#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) +#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) +#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) +#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) +#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) +#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) +#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) +#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) +#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) +#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) +#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) +#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) +#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) +#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) +#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) +#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) +#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) +#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) +#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) +#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) +#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) +#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) +#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) +#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) +#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) +#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) +#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) +#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) +#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) +#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) +#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) +#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) +#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) +#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) +#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) +#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) +#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) +#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) +#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) +#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) +#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) +#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) +#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) +#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) +#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) +#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) +#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) +#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) +#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) +#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) +#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) +#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) +#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) +#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) +#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) +#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) +#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) +#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) +#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) +#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) +#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) +#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) +#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) +#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) +#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) +#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) +#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) +#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) +#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) +#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) +#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) +#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) +#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) +#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) +#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) +#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) +#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) +#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) +#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) +#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) +#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) +#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) +#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) +#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) +#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) +#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) +#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) +#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) +#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) +#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) +#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) +#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) +#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) +#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) +#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) +#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) +#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) +#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) +#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) +#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) +#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) +#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) +#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) +#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) +#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) +#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) +#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) +#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) +#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) +#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) +#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) +#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) +#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) +#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) +#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) +#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) +#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) +#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) +#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) +#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) +#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) +#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) +#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) +#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) +#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) +#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) +#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) +#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) +#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) +#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) +#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) +#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) + +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + #endif /* _CDEF_BF549_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index 32f71e6a7c15..a2e9d9849eba 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h @@ -2615,6 +2615,17 @@ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) +/* OTP/FUSE Registers */ + +#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) +#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) +#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) +#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) +#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) +#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) +#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) +#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) + /* Security Registers */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) @@ -2629,6 +2640,17 @@ #define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) +/* OTP Read/Write Data Buffer Registers */ + +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) + /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ /* legacy definitions */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h index f916c52a148a..39f588dcd382 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h @@ -624,9 +624,9 @@ #define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define COMPLETE 0x8 /* DMA Complete */ #define HSHK 0x10 /* Host Handshake */ -#define HSTIMEOUT 0x20 /* Host Timeout */ +#define TIMEOUT 0x20 /* Host Timeout */ #define HIRQ 0x40 /* Host Interrupt Request */ #define ALLOW_CNFG 0x80 /* Allow New Configuration */ #define DMA_DIR 0x100 /* DMA Direction */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h index 72c343646b2a..c4dcf302d9f5 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h @@ -4,18 +4,18 @@ * Licensed under the ADI BSD license or the GPL-2 (or later) */ -#ifndef _DEF_BF547_H -#define _DEF_BF547_H +#ifndef _DEF_BF548_H +#define _DEF_BF548_H /* Include all Core registers and bit definitions */ #include -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */ +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" -/* The following are the #defines needed by ADSP-BF547 that are not in the common header */ +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ /* Timer Registers */ @@ -1217,4 +1217,4 @@ /* ******************************************* */ -#endif /* _DEF_BF547_H */ +#endif /* _DEF_BF548_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF548.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF548.h index 3fb33b040ab7..a5079980968c 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF548.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF548.h @@ -15,8 +15,115 @@ /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" -/* The BF548 is like the BF547, but has additional CANs */ -#include "defBF547.h" +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* SPORT0 Registers */ + +#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ +#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ +#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ +#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ +#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ +#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ +#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ +#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* UART2 Registers */ + +#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ +#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ +#define UART2_GCTL 0xffc02108 /* Global Control Register */ +#define UART2_LCR 0xffc0210c /* Line Control Register */ +#define UART2_MCR 0xffc02110 /* Modem Control Register */ +#define UART2_LSR 0xffc02114 /* Line Status Register */ +#define UART2_MSR 0xffc02118 /* Modem Status Register */ +#define UART2_SCR 0xffc0211c /* Scratch Register */ +#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ +#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ +#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPI2 Registers */ + +#define SPI2_REGBASE 0xffc02400 +#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ +#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ +#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ +#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ /* CAN Controller 1 Config 1 Registers */ @@ -401,4 +508,1096 @@ #define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ #define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define HSTIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + + #endif /* _DEF_BF548_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF549.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF549.h index 5a04e6d4017e..f7f043560c6f 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF549.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF549.h @@ -10,13 +10,121 @@ /* Include all Core registers and bit definitions */ #include + /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" -/* The BF549 is like the BF544, but has MXVR */ -#include "defBF547.h" +/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* SPORT0 Registers */ + +#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ +#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ +#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ +#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ +#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ +#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ +#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ +#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* UART2 Registers */ + +#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ +#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ +#define UART2_GCTL 0xffc02108 /* Global Control Register */ +#define UART2_LCR 0xffc0210c /* Line Control Register */ +#define UART2_MCR 0xffc02110 /* Modem Control Register */ +#define UART2_LSR 0xffc02114 /* Line Status Register */ +#define UART2_MSR 0xffc02118 /* Modem Status Register */ +#define UART2_SCR 0xffc0211c /* Scratch Register */ +#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ +#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ +#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPI2 Registers */ + +#define SPI2_REGBASE 0xffc02400 +#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ +#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ +#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ +#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ /* MXVR Registers */ @@ -188,4 +296,2418 @@ #define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ #define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ +/* CAN Controller 1 Config 1 Registers */ + +#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ +#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */ +#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */ +#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */ +#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ +#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ +#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */ +#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */ +#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ +#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ +#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ +#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ +#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ + +/* CAN Controller 1 Config 2 Registers */ + +#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ +#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */ +#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */ +#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */ +#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ +#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ +#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */ +#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */ +#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ +#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ +#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ +#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ +#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ + +/* CAN Controller 1 Clock/Interrupt/Counter Registers */ + +#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */ +#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */ +#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */ +#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */ +#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */ +#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */ +#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */ +#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */ +#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */ +#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */ +#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */ +#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */ +#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */ +#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */ +#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */ +#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ +#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ +#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ +#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ +#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ +#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ +#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ +#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ +#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ +#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ +#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ +#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ +#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ +#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ +#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ +#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ +#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ +#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ +#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ +#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ +#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ +#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ +#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ +#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ +#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ +#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ +#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ +#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ +#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ +#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ +#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ +#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ +#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ +#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ +#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ +#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ +#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ +#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ +#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ +#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ +#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ +#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ +#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ +#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ +#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ +#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ +#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ +#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ +#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ +#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ +#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ +#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ +#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ +#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ +#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ +#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ +#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ +#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ +#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ +#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ +#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ +#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ +#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ +#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ +#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ +#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */ +#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */ +#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ +#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ +#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */ +#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ +#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ +#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ +#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */ +#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */ +#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ +#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ +#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */ +#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ +#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ +#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ +#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */ +#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */ +#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ +#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ +#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */ +#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ +#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ +#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ +#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */ +#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */ +#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ +#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ +#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */ +#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ +#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ +#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ +#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */ +#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */ +#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ +#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ +#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */ +#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ +#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ +#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ +#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */ +#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */ +#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ +#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */ +#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */ +#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ +#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ +#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ +#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */ +#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */ +#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ +#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */ +#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */ +#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ +#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ +#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ +#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */ +#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */ +#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ +#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */ +#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */ +#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ +#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ +#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ +#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */ +#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */ +#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ +#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ +#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */ +#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ +#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ +#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ +#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */ +#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */ +#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ +#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ +#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */ +#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ +#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ +#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ +#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */ +#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */ +#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ +#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ +#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */ +#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ +#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ +#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ +#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */ +#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */ +#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ +#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ +#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */ +#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ +#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ +#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ +#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */ +#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */ +#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ +#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ +#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */ +#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ +#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ +#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ +#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */ +#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */ +#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ +#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */ +#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */ +#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ +#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ +#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ +#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */ +#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */ +#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ +#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */ +#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */ +#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ +#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ +#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ +#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */ +#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */ +#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ +#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */ +#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ +#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ +#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ +#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */ +#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */ +#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ +#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ +#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */ +#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ +#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ +#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ +#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */ +#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */ +#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ +#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ +#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */ +#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ +#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ +#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ +#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */ +#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */ +#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ +#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ +#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */ +#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ +#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ +#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ +#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */ +#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */ +#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ +#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ +#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */ +#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ +#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ +#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ +#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */ +#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */ +#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ +#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ +#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */ +#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ +#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ +#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ +#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */ +#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */ +#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ +#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */ +#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */ +#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ +#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ +#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ +#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */ +#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */ +#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ +#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */ +#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */ +#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ +#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ +#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ +#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */ +#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */ +#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ +#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */ +#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */ +#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ +#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ +#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ +#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */ +#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */ +#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ +#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ +#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */ +#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ +#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ +#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ +#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */ +#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */ +#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ +#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ +#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */ +#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ +#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ +#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ +#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */ +#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */ +#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ +#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ +#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */ +#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ +#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ +#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ +#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */ +#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */ +#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ +#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ +#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */ +#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ +#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ +#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ +#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */ +#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */ +#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ +#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ +#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */ +#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ +#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ +#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ +#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */ +#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */ +#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ +#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */ +#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */ +#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ +#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ +#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ +#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */ +#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */ +#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ +#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */ +#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */ +#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ +#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ +#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ +#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */ +#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */ +#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ +#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ +#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ + +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define TIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for MXVR_CONFIG */ + +#define MXVREN 0x1 /* MXVR Enable */ +#define MMSM 0x2 /* MXVR Master/Slave Mode Select */ +#define ACTIVE 0x4 /* Active Mode */ +#define SDELAY 0x8 /* Synchronous Data Delay */ +#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ +#define RWRRXEN 0x20 /* Remote Write Receive Enable */ +#define MTXEN 0x40 /* MXVR Transmit Data Enable */ +#define MTXONB 0x80 /* MXVR Phy Transmitter On */ +#define EPARITY 0x100 /* Even Parity Select */ +#define MSB 0x1e00 /* Master Synchronous Boundary */ +#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ +#define WAKEUP 0x4000 /* Wake-Up */ +#define LMECH 0x8000 /* Lock Mechanism Select */ + +/* Bit masks for MXVR_STATE_0 */ + +#define NACT 0x1 /* Network Activity */ +#define SBLOCK 0x2 /* Super Block Lock */ +#define FMPLLST 0xc /* Frequency Multiply PLL SM State */ +#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ +#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ +#define APARB 0x200 /* Asynchronous Packet Arbitrating */ +#define APTX 0x400 /* Asynchronous Packet Transmitting */ +#define APRX 0x800 /* Receiving Asynchronous Packet */ +#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ +#define CMARB 0x2000 /* Control Message Arbitrating */ +#define CMTX 0x4000 /* Control Message Transmitting */ +#define CMRX 0x8000 /* Receiving Control Message */ +#define MRXONB 0x10000 /* MRXONB Pin State */ +#define RGSIP 0x20000 /* Remote Get Source In Progress */ +#define DALIP 0x40000 /* Resource Deallocate In Progress */ +#define ALIP 0x80000 /* Resource Allocate In Progress */ +#define RRDIP 0x100000 /* Remote Read In Progress */ +#define RWRIP 0x200000 /* Remote Write In Progress */ +#define FLOCK 0x400000 /* Frame Lock */ +#define BLOCK 0x800000 /* Block Lock */ +#define RSB 0xf000000 /* Received Synchronous Boundary */ +#define DERRNUM 0xf0000000 /* DMA Error Channel Number */ + +/* Bit masks for MXVR_STATE_1 */ + +#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ +#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ +#define APCONT 0x100 /* Asynchronous Packet Continuation */ +#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ +#define DMAACTIVE0 0x10000 /* DMA0 Active */ +#define DMAACTIVE1 0x20000 /* DMA1 Active */ +#define DMAACTIVE2 0x40000 /* DMA2 Active */ +#define DMAACTIVE3 0x80000 /* DMA3 Active */ +#define DMAACTIVE4 0x100000 /* DMA4 Active */ +#define DMAACTIVE5 0x200000 /* DMA5 Active */ +#define DMAACTIVE6 0x400000 /* DMA6 Active */ +#define DMAACTIVE7 0x800000 /* DMA7 Active */ +#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ +#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ +#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ +#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ +#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ +#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ +#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ +#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ + +/* Bit masks for MXVR_INT_STAT_0 */ + +#define NI2A 0x1 /* Network Inactive to Active */ +#define NA2I 0x2 /* Network Active to Inactive */ +#define SBU2L 0x4 /* Super Block Unlock to Lock */ +#define SBL2U 0x8 /* Super Block Lock to Unlock */ +#define PRU 0x10 /* Position Register Updated */ +#define MPRU 0x20 /* Maximum Position Register Updated */ +#define DRU 0x40 /* Delay Register Updated */ +#define MDRU 0x80 /* Maximum Delay Register Updated */ +#define SBU 0x100 /* Synchronous Boundary Updated */ +#define ATU 0x200 /* Allocation Table Updated */ +#define FCZ0 0x400 /* Frame Counter 0 Zero */ +#define FCZ1 0x800 /* Frame Counter 1 Zero */ +#define PERR 0x1000 /* Parity Error */ +#define MH2L 0x2000 /* MRXONB High to Low */ +#define ML2H 0x4000 /* MRXONB Low to High */ +#define WUP 0x8000 /* Wake-Up Preamble Received */ +#define FU2L 0x10000 /* Frame Unlock to Lock */ +#define FL2U 0x20000 /* Frame Lock to Unlock */ +#define BU2L 0x40000 /* Block Unlock to Lock */ +#define BL2U 0x80000 /* Block Lock to Unlock */ +#define OBERR 0x100000 /* DMA Out of Bounds Error */ +#define PFL 0x200000 /* PLL Frequency Locked */ +#define SCZ 0x400000 /* System Clock Counter Zero */ +#define FERR 0x800000 /* FIFO Error */ +#define CMR 0x1000000 /* Control Message Received */ +#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ +#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ +#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ +#define RWRC 0x10000000 /* Remote Write Control Message Completed */ +#define BCZ 0x20000000 /* Block Counter Zero */ +#define BMERR 0x40000000 /* Biphase Mark Coding Error */ +#define DERR 0x80000000 /* DMA Error */ + +/* Bit masks for MXVR_INT_STAT_1 */ + +#define HDONE0 0x1 /* DMA0 Half Done */ +#define DONE0 0x2 /* DMA0 Done */ +#define APR 0x4 /* Asynchronous Packet Received */ +#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ +#define HDONE1 0x10 /* DMA1 Half Done */ +#define DONE1 0x20 /* DMA1 Done */ +#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ +#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ +#define HDONE2 0x100 /* DMA2 Half Done */ +#define DONE2 0x200 /* DMA2 Done */ +#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ +#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ +#define HDONE3 0x1000 /* DMA3 Half Done */ +#define DONE3 0x2000 /* DMA3 Done */ +#define HDONE4 0x10000 /* DMA4 Half Done */ +#define DONE4 0x20000 /* DMA4 Done */ +#define HDONE5 0x100000 /* DMA5 Half Done */ +#define DONE5 0x200000 /* DMA5 Done */ +#define HDONE6 0x1000000 /* DMA6 Half Done */ +#define DONE6 0x2000000 /* DMA6 Done */ +#define HDONE7 0x10000000 /* DMA7 Half Done */ +#define DONE7 0x20000000 /* DMA7 Done */ + +/* Bit masks for MXVR_INT_EN_0 */ + +#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ +#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ +#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ +#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ +#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ +#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ +#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ +#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ +#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ +#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ +#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ +#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ +#define PERREN 0x1000 /* Parity Error Interrupt Enable */ +#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ +#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ +#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ +#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ +#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ +#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ +#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ +#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ +#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ +#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ +#define FERREN 0x800000 /* FIFO Error Interrupt Enable */ +#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ +#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ +#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ +#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ +#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ +#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ +#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ +#define DERREN 0x80000000 /* DMA Error Interrupt Enable */ + +/* Bit masks for MXVR_INT_EN_1 */ + +#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ +#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ +#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ +#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ +#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ +#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ +#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ +#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ +#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ +#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ +#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ +#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ +#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ +#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ +#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ +#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ +#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ +#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ +#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ +#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ +#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ +#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ + +/* Bit masks for MXVR_POSITION */ + +#define POSITION 0x3f /* Node Position */ +#define PVALID 0x8000 /* Node Position Valid */ + +/* Bit masks for MXVR_MAX_POSITION */ + +#define MPOSITION 0x3f /* Maximum Node Position */ +#define MPVALID 0x8000 /* Maximum Node Position Valid */ + +/* Bit masks for MXVR_DELAY */ + +#define DELAY 0x3f /* Node Frame Delay */ +#define DVALID 0x8000 /* Node Frame Delay Valid */ + +/* Bit masks for MXVR_MAX_DELAY */ + +#define MDELAY 0x3f /* Maximum Node Frame Delay */ +#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ + +/* Bit masks for MXVR_LADDR */ + +#define LADDR 0xffff /* Logical Address */ +#define LVALID 0x80000000 /* Logical Address Valid */ + +/* Bit masks for MXVR_GADDR */ + +#define GADDRL 0xff /* Group Address Lower Byte */ +#define GVALID 0x8000 /* Group Address Valid */ + +/* Bit masks for MXVR_AADDR */ + +#define AADDR 0xffff /* Alternate Address */ +#define AVALID 0x80000000 /* Alternate Address Valid */ + +/* Bit masks for MXVR_ALLOC_0 */ + +#define CL0 0x7f /* Channel 0 Connection Label */ +#define CIU0 0x80 /* Channel 0 In Use */ +#define CL1 0x7f00 /* Channel 0 Connection Label */ +#define CIU1 0x8000 /* Channel 0 In Use */ +#define CL2 0x7f0000 /* Channel 0 Connection Label */ +#define CIU2 0x800000 /* Channel 0 In Use */ +#define CL3 0x7f000000 /* Channel 0 Connection Label */ +#define CIU3 0x80000000 /* Channel 0 In Use */ + +/* Bit masks for MXVR_ALLOC_1 */ + +#define CL4 0x7f /* Channel 4 Connection Label */ +#define CIU4 0x80 /* Channel 4 In Use */ +#define CL5 0x7f00 /* Channel 5 Connection Label */ +#define CIU5 0x8000 /* Channel 5 In Use */ +#define CL6 0x7f0000 /* Channel 6 Connection Label */ +#define CIU6 0x800000 /* Channel 6 In Use */ +#define CL7 0x7f000000 /* Channel 7 Connection Label */ +#define CIU7 0x80000000 /* Channel 7 In Use */ + +/* Bit masks for MXVR_ALLOC_2 */ + +#define CL8 0x7f /* Channel 8 Connection Label */ +#define CIU8 0x80 /* Channel 8 In Use */ +#define CL9 0x7f00 /* Channel 9 Connection Label */ +#define CIU9 0x8000 /* Channel 9 In Use */ +#define CL10 0x7f0000 /* Channel 10 Connection Label */ +#define CIU10 0x800000 /* Channel 10 In Use */ +#define CL11 0x7f000000 /* Channel 11 Connection Label */ +#define CIU11 0x80000000 /* Channel 11 In Use */ + +/* Bit masks for MXVR_ALLOC_3 */ + +#define CL12 0x7f /* Channel 12 Connection Label */ +#define CIU12 0x80 /* Channel 12 In Use */ +#define CL13 0x7f00 /* Channel 13 Connection Label */ +#define CIU13 0x8000 /* Channel 13 In Use */ +#define CL14 0x7f0000 /* Channel 14 Connection Label */ +#define CIU14 0x800000 /* Channel 14 In Use */ +#define CL15 0x7f000000 /* Channel 15 Connection Label */ +#define CIU15 0x80000000 /* Channel 15 In Use */ + +/* Bit masks for MXVR_ALLOC_4 */ + +#define CL16 0x7f /* Channel 16 Connection Label */ +#define CIU16 0x80 /* Channel 16 In Use */ +#define CL17 0x7f00 /* Channel 17 Connection Label */ +#define CIU17 0x8000 /* Channel 17 In Use */ +#define CL18 0x7f0000 /* Channel 18 Connection Label */ +#define CIU18 0x800000 /* Channel 18 In Use */ +#define CL19 0x7f000000 /* Channel 19 Connection Label */ +#define CIU19 0x80000000 /* Channel 19 In Use */ + +/* Bit masks for MXVR_ALLOC_5 */ + +#define CL20 0x7f /* Channel 20 Connection Label */ +#define CIU20 0x80 /* Channel 20 In Use */ +#define CL21 0x7f00 /* Channel 21 Connection Label */ +#define CIU21 0x8000 /* Channel 21 In Use */ +#define CL22 0x7f0000 /* Channel 22 Connection Label */ +#define CIU22 0x800000 /* Channel 22 In Use */ +#define CL23 0x7f000000 /* Channel 23 Connection Label */ +#define CIU23 0x80000000 /* Channel 23 In Use */ + +/* Bit masks for MXVR_ALLOC_6 */ + +#define CL24 0x7f /* Channel 24 Connection Label */ +#define CIU24 0x80 /* Channel 24 In Use */ +#define CL25 0x7f00 /* Channel 25 Connection Label */ +#define CIU25 0x8000 /* Channel 25 In Use */ +#define CL26 0x7f0000 /* Channel 26 Connection Label */ +#define CIU26 0x800000 /* Channel 26 In Use */ +#define CL27 0x7f000000 /* Channel 27 Connection Label */ +#define CIU27 0x80000000 /* Channel 27 In Use */ + +/* Bit masks for MXVR_ALLOC_7 */ + +#define CL28 0x7f /* Channel 28 Connection Label */ +#define CIU28 0x80 /* Channel 28 In Use */ +#define CL29 0x7f00 /* Channel 29 Connection Label */ +#define CIU29 0x8000 /* Channel 29 In Use */ +#define CL30 0x7f0000 /* Channel 30 Connection Label */ +#define CIU30 0x800000 /* Channel 30 In Use */ +#define CL31 0x7f000000 /* Channel 31 Connection Label */ +#define CIU31 0x80000000 /* Channel 31 In Use */ + +/* Bit masks for MXVR_ALLOC_8 */ + +#define CL32 0x7f /* Channel 32 Connection Label */ +#define CIU32 0x80 /* Channel 32 In Use */ +#define CL33 0x7f00 /* Channel 33 Connection Label */ +#define CIU33 0x8000 /* Channel 33 In Use */ +#define CL34 0x7f0000 /* Channel 34 Connection Label */ +#define CIU34 0x800000 /* Channel 34 In Use */ +#define CL35 0x7f000000 /* Channel 35 Connection Label */ +#define CIU35 0x80000000 /* Channel 35 In Use */ + +/* Bit masks for MXVR_ALLOC_9 */ + +#define CL36 0x7f /* Channel 36 Connection Label */ +#define CIU36 0x80 /* Channel 36 In Use */ +#define CL37 0x7f00 /* Channel 37 Connection Label */ +#define CIU37 0x8000 /* Channel 37 In Use */ +#define CL38 0x7f0000 /* Channel 38 Connection Label */ +#define CIU38 0x800000 /* Channel 38 In Use */ +#define CL39 0x7f000000 /* Channel 39 Connection Label */ +#define CIU39 0x80000000 /* Channel 39 In Use */ + +/* Bit masks for MXVR_ALLOC_10 */ + +#define CL40 0x7f /* Channel 40 Connection Label */ +#define CIU40 0x80 /* Channel 40 In Use */ +#define CL41 0x7f00 /* Channel 41 Connection Label */ +#define CIU41 0x8000 /* Channel 41 In Use */ +#define CL42 0x7f0000 /* Channel 42 Connection Label */ +#define CIU42 0x800000 /* Channel 42 In Use */ +#define CL43 0x7f000000 /* Channel 43 Connection Label */ +#define CIU43 0x80000000 /* Channel 43 In Use */ + +/* Bit masks for MXVR_ALLOC_11 */ + +#define CL44 0x7f /* Channel 44 Connection Label */ +#define CIU44 0x80 /* Channel 44 In Use */ +#define CL45 0x7f00 /* Channel 45 Connection Label */ +#define CIU45 0x8000 /* Channel 45 In Use */ +#define CL46 0x7f0000 /* Channel 46 Connection Label */ +#define CIU46 0x800000 /* Channel 46 In Use */ +#define CL47 0x7f000000 /* Channel 47 Connection Label */ +#define CIU47 0x80000000 /* Channel 47 In Use */ + +/* Bit masks for MXVR_ALLOC_12 */ + +#define CL48 0x7f /* Channel 48 Connection Label */ +#define CIU48 0x80 /* Channel 48 In Use */ +#define CL49 0x7f00 /* Channel 49 Connection Label */ +#define CIU49 0x8000 /* Channel 49 In Use */ +#define CL50 0x7f0000 /* Channel 50 Connection Label */ +#define CIU50 0x800000 /* Channel 50 In Use */ +#define CL51 0x7f000000 /* Channel 51 Connection Label */ +#define CIU51 0x80000000 /* Channel 51 In Use */ + +/* Bit masks for MXVR_ALLOC_13 */ + +#define CL52 0x7f /* Channel 52 Connection Label */ +#define CIU52 0x80 /* Channel 52 In Use */ +#define CL53 0x7f00 /* Channel 53 Connection Label */ +#define CIU53 0x8000 /* Channel 53 In Use */ +#define CL54 0x7f0000 /* Channel 54 Connection Label */ +#define CIU54 0x800000 /* Channel 54 In Use */ +#define CL55 0x7f000000 /* Channel 55 Connection Label */ +#define CIU55 0x80000000 /* Channel 55 In Use */ + +/* Bit masks for MXVR_ALLOC_14 */ + +#define CL56 0x7f /* Channel 56 Connection Label */ +#define CIU56 0x80 /* Channel 56 In Use */ +#define CL57 0x7f00 /* Channel 57 Connection Label */ +#define CIU57 0x8000 /* Channel 57 In Use */ +#define CL58 0x7f0000 /* Channel 58 Connection Label */ +#define CIU58 0x800000 /* Channel 58 In Use */ +#define CL59 0x7f000000 /* Channel 59 Connection Label */ +#define CIU59 0x80000000 /* Channel 59 In Use */ + +/* MXVR_SYNC_LCHAN_0 Masks */ + +#define LCHANPC0 0x0000000Flu +#define LCHANPC1 0x000000F0lu +#define LCHANPC2 0x00000F00lu +#define LCHANPC3 0x0000F000lu +#define LCHANPC4 0x000F0000lu +#define LCHANPC5 0x00F00000lu +#define LCHANPC6 0x0F000000lu +#define LCHANPC7 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_1 Masks */ + +#define LCHANPC8 0x0000000Flu +#define LCHANPC9 0x000000F0lu +#define LCHANPC10 0x00000F00lu +#define LCHANPC11 0x0000F000lu +#define LCHANPC12 0x000F0000lu +#define LCHANPC13 0x00F00000lu +#define LCHANPC14 0x0F000000lu +#define LCHANPC15 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_2 Masks */ + +#define LCHANPC16 0x0000000Flu +#define LCHANPC17 0x000000F0lu +#define LCHANPC18 0x00000F00lu +#define LCHANPC19 0x0000F000lu +#define LCHANPC20 0x000F0000lu +#define LCHANPC21 0x00F00000lu +#define LCHANPC22 0x0F000000lu +#define LCHANPC23 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_3 Masks */ + +#define LCHANPC24 0x0000000Flu +#define LCHANPC25 0x000000F0lu +#define LCHANPC26 0x00000F00lu +#define LCHANPC27 0x0000F000lu +#define LCHANPC28 0x000F0000lu +#define LCHANPC29 0x00F00000lu +#define LCHANPC30 0x0F000000lu +#define LCHANPC31 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_4 Masks */ + +#define LCHANPC32 0x0000000Flu +#define LCHANPC33 0x000000F0lu +#define LCHANPC34 0x00000F00lu +#define LCHANPC35 0x0000F000lu +#define LCHANPC36 0x000F0000lu +#define LCHANPC37 0x00F00000lu +#define LCHANPC38 0x0F000000lu +#define LCHANPC39 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_5 Masks */ + +#define LCHANPC40 0x0000000Flu +#define LCHANPC41 0x000000F0lu +#define LCHANPC42 0x00000F00lu +#define LCHANPC43 0x0000F000lu +#define LCHANPC44 0x000F0000lu +#define LCHANPC45 0x00F00000lu +#define LCHANPC46 0x0F000000lu +#define LCHANPC47 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_6 Masks */ + +#define LCHANPC48 0x0000000Flu +#define LCHANPC49 0x000000F0lu +#define LCHANPC50 0x00000F00lu +#define LCHANPC51 0x0000F000lu +#define LCHANPC52 0x000F0000lu +#define LCHANPC53 0x00F00000lu +#define LCHANPC54 0x0F000000lu +#define LCHANPC55 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_7 Masks */ + +#define LCHANPC56 0x0000000Flu +#define LCHANPC57 0x000000F0lu +#define LCHANPC58 0x00000F00lu +#define LCHANPC59 0x0000F000lu + +/* Bit masks for MXVR_DMAx_CONFIG */ + +#define MDMAEN 0x1 /* DMA Channel Enable */ +#define DMADD 0x2 /* DMA Channel Direction */ +#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ +#define LCHAN 0x3c0 /* DMA Channel Logical Channel */ +#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ +#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ +#define MFLOW 0x7000 /* DMA Channel Operation Flow */ +#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ +#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ +#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ +#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ + +/* Bit masks for MXVR_AP_CTL */ + +#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ +#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ +#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ +#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ +#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ + +/* Bit masks for MXVR_APRB_START_ADDR */ + +#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ + +/* Bit masks for MXVR_APRB_CURR_ADDR */ + +#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ + +/* Bit masks for MXVR_APTB_START_ADDR */ + +#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ + +/* Bit masks for MXVR_APTB_CURR_ADDR */ + +#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ + +/* Bit masks for MXVR_CM_CTL */ + +#define STARTCM 0x1 /* Start Control Message Transmission */ +#define CANCELCM 0x2 /* Cancel Control Message Transmission */ +#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ +#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ +#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ +#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ +#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ +#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ +#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ +#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ +#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ +#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ +#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ +#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ +#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ +#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ +#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ +#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ + +/* Bit masks for MXVR_CMRB_START_ADDR */ + +#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ + +/* Bit masks for MXVR_CMRB_CURR_ADDR */ + +#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ + +/* Bit masks for MXVR_CMTB_START_ADDR */ + +#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ + +/* Bit masks for MXVR_CMTB_CURR_ADDR */ + +#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ + +/* Bit masks for MXVR_RRDB_START_ADDR */ + +#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ + +/* Bit masks for MXVR_RRDB_CURR_ADDR */ + +#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ + +/* Bit masks for MXVR_PAT_DATAx */ + +#define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */ +#define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */ +#define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */ +#define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */ + +/* Bit masks for MXVR_PAT_EN_0 */ + +#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ +#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ +#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ +#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ +#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ +#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ +#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ +#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ +#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ +#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ +#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ +#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ +#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ +#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ +#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ +#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ +#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ +#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ +#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ +#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ +#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ +#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ +#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ +#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ +#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ +#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ +#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ +#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ +#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ +#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ +#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ +#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ + +/* Bit masks for MXVR_PAT_EN_1 */ + +#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ +#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ +#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ +#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ +#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ +#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ +#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ +#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ +#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ +#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ +#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ +#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ +#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ +#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ +#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ +#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ +#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ +#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ +#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ +#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ +#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ +#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ +#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ +#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ +#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ +#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ +#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ +#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ +#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ +#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ +#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ +#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ + +/* Bit masks for MXVR_FRAME_CNT_0 */ + +#define FCNT 0xffff /* Frame Count */ + +/* Bit masks for MXVR_FRAME_CNT_1 */ + +#define FCNT 0xffff /* Frame Count */ + +/* Bit masks for MXVR_ROUTING_0 */ + +#define TX_CH0 0x3f /* Transmit Channel 0 */ +#define MUTE_CH0 0x80 /* Mute Channel 0 */ +#define TX_CH1 0x3f00 /* Transmit Channel 0 */ +#define MUTE_CH1 0x8000 /* Mute Channel 0 */ +#define TX_CH2 0x3f0000 /* Transmit Channel 0 */ +#define MUTE_CH2 0x800000 /* Mute Channel 0 */ +#define TX_CH3 0x3f000000 /* Transmit Channel 0 */ +#define MUTE_CH3 0x80000000 /* Mute Channel 0 */ + +/* Bit masks for MXVR_ROUTING_1 */ + +#define TX_CH4 0x3f /* Transmit Channel 4 */ +#define MUTE_CH4 0x80 /* Mute Channel 4 */ +#define TX_CH5 0x3f00 /* Transmit Channel 5 */ +#define MUTE_CH5 0x8000 /* Mute Channel 5 */ +#define TX_CH6 0x3f0000 /* Transmit Channel 6 */ +#define MUTE_CH6 0x800000 /* Mute Channel 6 */ +#define TX_CH7 0x3f000000 /* Transmit Channel 7 */ +#define MUTE_CH7 0x80000000 /* Mute Channel 7 */ + +/* Bit masks for MXVR_ROUTING_2 */ + +#define TX_CH8 0x3f /* Transmit Channel 8 */ +#define MUTE_CH8 0x80 /* Mute Channel 8 */ +#define TX_CH9 0x3f00 /* Transmit Channel 9 */ +#define MUTE_CH9 0x8000 /* Mute Channel 9 */ +#define TX_CH10 0x3f0000 /* Transmit Channel 10 */ +#define MUTE_CH10 0x800000 /* Mute Channel 10 */ +#define TX_CH11 0x3f000000 /* Transmit Channel 11 */ +#define MUTE_CH11 0x80000000 /* Mute Channel 11 */ + +/* Bit masks for MXVR_ROUTING_3 */ + +#define TX_CH12 0x3f /* Transmit Channel 12 */ +#define MUTE_CH12 0x80 /* Mute Channel 12 */ +#define TX_CH13 0x3f00 /* Transmit Channel 13 */ +#define MUTE_CH13 0x8000 /* Mute Channel 13 */ +#define TX_CH14 0x3f0000 /* Transmit Channel 14 */ +#define MUTE_CH14 0x800000 /* Mute Channel 14 */ +#define TX_CH15 0x3f000000 /* Transmit Channel 15 */ +#define MUTE_CH15 0x80000000 /* Mute Channel 15 */ + +/* Bit masks for MXVR_ROUTING_4 */ + +#define TX_CH16 0x3f /* Transmit Channel 16 */ +#define MUTE_CH16 0x80 /* Mute Channel 16 */ +#define TX_CH17 0x3f00 /* Transmit Channel 17 */ +#define MUTE_CH17 0x8000 /* Mute Channel 17 */ +#define TX_CH18 0x3f0000 /* Transmit Channel 18 */ +#define MUTE_CH18 0x800000 /* Mute Channel 18 */ +#define TX_CH19 0x3f000000 /* Transmit Channel 19 */ +#define MUTE_CH19 0x80000000 /* Mute Channel 19 */ + +/* Bit masks for MXVR_ROUTING_5 */ + +#define TX_CH20 0x3f /* Transmit Channel 20 */ +#define MUTE_CH20 0x80 /* Mute Channel 20 */ +#define TX_CH21 0x3f00 /* Transmit Channel 21 */ +#define MUTE_CH21 0x8000 /* Mute Channel 21 */ +#define TX_CH22 0x3f0000 /* Transmit Channel 22 */ +#define MUTE_CH22 0x800000 /* Mute Channel 22 */ +#define TX_CH23 0x3f000000 /* Transmit Channel 23 */ +#define MUTE_CH23 0x80000000 /* Mute Channel 23 */ + +/* Bit masks for MXVR_ROUTING_6 */ + +#define TX_CH24 0x3f /* Transmit Channel 24 */ +#define MUTE_CH24 0x80 /* Mute Channel 24 */ +#define TX_CH25 0x3f00 /* Transmit Channel 25 */ +#define MUTE_CH25 0x8000 /* Mute Channel 25 */ +#define TX_CH26 0x3f0000 /* Transmit Channel 26 */ +#define MUTE_CH26 0x800000 /* Mute Channel 26 */ +#define TX_CH27 0x3f000000 /* Transmit Channel 27 */ +#define MUTE_CH27 0x80000000 /* Mute Channel 27 */ + +/* Bit masks for MXVR_ROUTING_7 */ + +#define TX_CH28 0x3f /* Transmit Channel 28 */ +#define MUTE_CH28 0x80 /* Mute Channel 28 */ +#define TX_CH29 0x3f00 /* Transmit Channel 29 */ +#define MUTE_CH29 0x8000 /* Mute Channel 29 */ +#define TX_CH30 0x3f0000 /* Transmit Channel 30 */ +#define MUTE_CH30 0x800000 /* Mute Channel 30 */ +#define TX_CH31 0x3f000000 /* Transmit Channel 31 */ +#define MUTE_CH31 0x80000000 /* Mute Channel 31 */ + +/* Bit masks for MXVR_ROUTING_8 */ + +#define TX_CH32 0x3f /* Transmit Channel 32 */ +#define MUTE_CH32 0x80 /* Mute Channel 32 */ +#define TX_CH33 0x3f00 /* Transmit Channel 33 */ +#define MUTE_CH33 0x8000 /* Mute Channel 33 */ +#define TX_CH34 0x3f0000 /* Transmit Channel 34 */ +#define MUTE_CH34 0x800000 /* Mute Channel 34 */ +#define TX_CH35 0x3f000000 /* Transmit Channel 35 */ +#define MUTE_CH35 0x80000000 /* Mute Channel 35 */ + +/* Bit masks for MXVR_ROUTING_9 */ + +#define TX_CH36 0x3f /* Transmit Channel 36 */ +#define MUTE_CH36 0x80 /* Mute Channel 36 */ +#define TX_CH37 0x3f00 /* Transmit Channel 37 */ +#define MUTE_CH37 0x8000 /* Mute Channel 37 */ +#define TX_CH38 0x3f0000 /* Transmit Channel 38 */ +#define MUTE_CH38 0x800000 /* Mute Channel 38 */ +#define TX_CH39 0x3f000000 /* Transmit Channel 39 */ +#define MUTE_CH39 0x80000000 /* Mute Channel 39 */ + +/* Bit masks for MXVR_ROUTING_10 */ + +#define TX_CH40 0x3f /* Transmit Channel 40 */ +#define MUTE_CH40 0x80 /* Mute Channel 40 */ +#define TX_CH41 0x3f00 /* Transmit Channel 41 */ +#define MUTE_CH41 0x8000 /* Mute Channel 41 */ +#define TX_CH42 0x3f0000 /* Transmit Channel 42 */ +#define MUTE_CH42 0x800000 /* Mute Channel 42 */ +#define TX_CH43 0x3f000000 /* Transmit Channel 43 */ +#define MUTE_CH43 0x80000000 /* Mute Channel 43 */ + +/* Bit masks for MXVR_ROUTING_11 */ + +#define TX_CH44 0x3f /* Transmit Channel 44 */ +#define MUTE_CH44 0x80 /* Mute Channel 44 */ +#define TX_CH45 0x3f00 /* Transmit Channel 45 */ +#define MUTE_CH45 0x8000 /* Mute Channel 45 */ +#define TX_CH46 0x3f0000 /* Transmit Channel 46 */ +#define MUTE_CH46 0x800000 /* Mute Channel 46 */ +#define TX_CH47 0x3f000000 /* Transmit Channel 47 */ +#define MUTE_CH47 0x80000000 /* Mute Channel 47 */ + +/* Bit masks for MXVR_ROUTING_12 */ + +#define TX_CH48 0x3f /* Transmit Channel 48 */ +#define MUTE_CH48 0x80 /* Mute Channel 48 */ +#define TX_CH49 0x3f00 /* Transmit Channel 49 */ +#define MUTE_CH49 0x8000 /* Mute Channel 49 */ +#define TX_CH50 0x3f0000 /* Transmit Channel 50 */ +#define MUTE_CH50 0x800000 /* Mute Channel 50 */ +#define TX_CH51 0x3f000000 /* Transmit Channel 51 */ +#define MUTE_CH51 0x80000000 /* Mute Channel 51 */ + +/* Bit masks for MXVR_ROUTING_13 */ + +#define TX_CH52 0x3f /* Transmit Channel 52 */ +#define MUTE_CH52 0x80 /* Mute Channel 52 */ +#define TX_CH53 0x3f00 /* Transmit Channel 53 */ +#define MUTE_CH53 0x8000 /* Mute Channel 53 */ +#define TX_CH54 0x3f0000 /* Transmit Channel 54 */ +#define MUTE_CH54 0x800000 /* Mute Channel 54 */ +#define TX_CH55 0x3f000000 /* Transmit Channel 55 */ +#define MUTE_CH55 0x80000000 /* Mute Channel 55 */ + +/* Bit masks for MXVR_ROUTING_14 */ + +#define TX_CH56 0x3f /* Transmit Channel 56 */ +#define MUTE_CH56 0x80 /* Mute Channel 56 */ +#define TX_CH57 0x3f00 /* Transmit Channel 57 */ +#define MUTE_CH57 0x8000 /* Mute Channel 57 */ +#define TX_CH58 0x3f0000 /* Transmit Channel 58 */ +#define MUTE_CH58 0x800000 /* Mute Channel 58 */ +#define TX_CH59 0x3f000000 /* Transmit Channel 59 */ +#define MUTE_CH59 0x80000000 /* Mute Channel 59 */ + +/* Bit masks for MXVR_BLOCK_CNT */ + +#define BCNT 0xffff /* Block Count */ + +/* Bit masks for MXVR_CLK_CTL */ + +#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ +#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ +#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ +#define CLKX3SEL 0x80 /* Clock Generation Source Select */ +#define MMCLKEN 0x100 /* Master Clock Enable */ +#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ +#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ +#define MBCLKEN 0x10000 /* Bit Clock Enable */ +#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ +#define INVRX 0x800000 /* Invert Receive Data */ +#define MFSEN 0x1000000 /* Frame Sync Enable */ +#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ +#define MFSSEL 0x60000000 /* Frame Sync Select */ +#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ + +/* Bit masks for MXVR_CDRPLL_CTL */ + +#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ +#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ +#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ +#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ +#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ +#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ +#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ +#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ +#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ + +/* Bit masks for MXVR_FMPLL_CTL */ + +#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ +#define FMRSTB 0x2 /* MXVR FMPLL Reset */ +#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ +#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ +#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ +#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ + +/* Bit masks for MXVR_PIN_CTL */ + +#define MTXONBOD 0x1 /* MTXONB Open Drain Select */ +#define MTXONBG 0x2 /* MTXONB Gates MTX Select */ +#define MFSOE 0x10 /* MFS Output Enable */ +#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ +#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ + +/* Bit masks for MXVR_SCLK_CNT */ + +#define SCNT 0xffff /* System Clock Count */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + +/* ************************ */ +/* MXVR Address Offsets */ +/* ************************ */ + +/* Control Message Receive Buffer (CMRB) Address Offsets */ + +#define CMRB_STRIDE 0x00000016lu + +#define CMRB_DST_OFFSET 0x00000000lu +#define CMRB_SRC_OFFSET 0x00000002lu +#define CMRB_DATA_OFFSET 0x00000005lu + +/* Control Message Transmit Buffer (CMTB) Address Offsets */ + +#define CMTB_PRIO_OFFSET 0x00000000lu +#define CMTB_DST_OFFSET 0x00000002lu +#define CMTB_SRC_OFFSET 0x00000004lu +#define CMTB_TYPE_OFFSET 0x00000006lu +#define CMTB_DATA_OFFSET 0x00000007lu + +#define CMTB_ANSWER_OFFSET 0x0000000Alu + +#define CMTB_STAT_N_OFFSET 0x00000018lu +#define CMTB_STAT_A_OFFSET 0x00000016lu +#define CMTB_STAT_D_OFFSET 0x0000000Elu +#define CMTB_STAT_R_OFFSET 0x00000014lu +#define CMTB_STAT_W_OFFSET 0x00000014lu +#define CMTB_STAT_G_OFFSET 0x00000014lu + +/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */ + +#define APRB_STRIDE 0x00000400lu + +#define APRB_DST_OFFSET 0x00000000lu +#define APRB_LEN_OFFSET 0x00000002lu +#define APRB_SRC_OFFSET 0x00000004lu +#define APRB_DATA_OFFSET 0x00000006lu + +/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */ + +#define APTB_PRIO_OFFSET 0x00000000lu +#define APTB_DST_OFFSET 0x00000002lu +#define APTB_LEN_OFFSET 0x00000004lu +#define APTB_SRC_OFFSET 0x00000006lu +#define APTB_DATA_OFFSET 0x00000008lu + +/* Remote Read Buffer (RRDB) Address Offsets */ + +#define RRDB_WADDR_OFFSET 0x00000100lu +#define RRDB_WLEN_OFFSET 0x00000101lu + +/* **************** */ +/* MXVR Macros */ +/* **************** */ + +/* MXVR_CONFIG Macros */ + +#define SET_MSB(x) ( ( (x) & 0xF ) << 9) + +/* MXVR_INT_STAT_1 Macros */ + +#define DONEX(x) (0x00000002 << (4 * (x))) +#define HDONEX(x) (0x00000001 << (4 * (x))) + +/* MXVR_INT_EN_1 Macros */ + +#define DONEENX(x) (0x00000002 << (4 * (x))) +#define HDONEENX(x) (0x00000001 << (4 * (x))) + +/* MXVR_CDRPLL_CTL Macros */ + +#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16) + +/* MXVR_FMPLL_CTL Macros */ + +#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24) +#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24) + #endif /* _DEF_BF549_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index ab04d137fd8b..8590c8c78336 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -1609,6 +1609,44 @@ #define PINT2 0x40000000 /* Pin Interrupt 2 */ #define PINT3 0x80000000 /* Pin Interrupt 3 */ +/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ + +#define DMAEN 0x1 /* DMA Channel Enable */ +#define WNR 0x2 /* DMA Direction */ +#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ +#define DMA2D 0x10 /* DMA Mode */ +#define RESTART 0x20 /* Work Unit Transitions */ +#define DI_SEL 0x40 /* Data Interrupt Timing Select */ +#define DI_EN 0x80 /* Data Interrupt Enable */ + +#define NDSIZE 0xf00 /* Flex Descriptor Size */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ + +#define DMAFLOW 0xf000 /* Next Operation */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ + +#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x2 /* DMA Error Interrupt Status */ +#define DFETCH 0x4 /* DMA Descriptor Fetch */ +#define DMA_RUN 0x8 /* DMA Channel Running */ + /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define CTYPE 0x40 /* DMA Channel Type */ @@ -1777,6 +1815,10 @@ #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ #define CORE_MERROR 0x80 /* Core Error (2nd) */ +/* Bit masks for EBIU_ERRADD */ + +#define ERROR_ADDRESS 0xffffffff /* Error Address */ + /* Bit masks for EBIU_RSTCTL */ #define DDRSRESET 0x1 /* DDR soft reset */ @@ -1785,6 +1827,98 @@ #define SRACK 0x10 /* Self-refresh acknowledge */ #define MDDRENABLE 0x20 /* Mobile DDR enable */ +/* Bit masks for EBIU_DDRBRC0 */ + +#define BRC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC1 */ + +#define BRC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC2 */ + +#define BRC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC3 */ + +#define BRC3 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC4 */ + +#define BRC4 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC5 */ + +#define BRC5 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC6 */ + +#define BRC6 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC7 */ + +#define BRC7 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC0 */ + +#define BWC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC1 */ + +#define BWC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC2 */ + +#define BWC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC3 */ + +#define BWC3 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC4 */ + +#define BWC4 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC5 */ + +#define BWC5 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC6 */ + +#define BWC6 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC7 */ + +#define BWC7 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRACCT */ + +#define ACCT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRTACT */ + +#define TECT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRARCT */ + +#define ARCT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC0 */ + +#define GC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC1 */ + +#define GC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC2 */ + +#define GC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC3 */ + +#define GC3 0xffffffff /* Count */ + /* Bit masks for EBIU_DDRMCEN */ #define B0WCENABLE 0x1 /* Bank 0 write count enable */ @@ -1958,6 +2092,12 @@ #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ +/* Bit masks for WDOG_CTL */ + +#define WDEV 0x6 /* Watchdog Event */ +#define WDEN 0xff0 /* Watchdog Enable */ +#define WDRO 0x8000 /* Watchdog Rolled Over */ + /* Bit masks for CNT_CONFIG */ #define CNTE 0x1 /* Counter Enable */ @@ -2009,6 +2149,81 @@ #define DPRESCALE 0xf /* Load Counter Register */ +/* Bit masks for RTC_STAT */ + +#define SECONDS 0x3f /* Seconds */ +#define MINUTES 0xfc0 /* Minutes */ +#define HOURS 0x1f000 /* Hours */ +#define DAY_COUNTER 0xfffe0000 /* Day Counter */ + +/* Bit masks for RTC_ICTL */ + +#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ +#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ +#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ +#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ +#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ +#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ +#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ +#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ + +/* Bit masks for RTC_ISTAT */ + +#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ +#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ +#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ +#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ +#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ +#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ +#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ +#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ +#define WRITE_COMPLETE 0x8000 /* Write Complete */ + +/* Bit masks for RTC_SWCNT */ + +#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */ + +/* Bit masks for RTC_ALARM */ + +#define SECONDS 0x3f /* Seconds */ +#define MINUTES 0xfc0 /* Minutes */ +#define HOURS 0x1f000 /* Hours */ +#define DAY 0xfffe0000 /* Day */ + +/* Bit masks for RTC_PREN */ + +#define PREN 0x1 /* Prescaler Enable */ + +/* Bit masks for OTP_CONTROL */ + +#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ +#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ +#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ +#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ +#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ +#define FWREN 0x8000 /* OTP/Fuse Write Enable */ + +/* Bit masks for OTP_BEN */ + +#define FBEN 0xffff /* OTP/Fuse Byte Enable */ + +/* Bit masks for OTP_STATUS */ + +#define FCOMP 0x1 /* OTP/Fuse Access Complete */ +#define FERROR 0x2 /* OTP/Fuse Access Error */ +#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ +#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ +#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ + +/* Bit masks for OTP_TIMING */ + +#define USECDIV 0xff /* Micro Second Divider */ +#define READACC 0x7f00 /* Read Access Time */ +#define CPUMPRL 0x38000 /* Charge Pump Release Time */ +#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ +#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ +#define PGMTIME 0xff000000 /* Program Time */ + /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ @@ -2037,6 +2252,26 @@ #define AFEXIT 0x10 /* Authentication Firmware Exit */ #define SECSTAT 0xe0 /* Secure Status */ +/* Bit masks for PLL_DIV */ + +#define CSEL 0x30 /* Core Select */ +#define SSEL 0xf /* System Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ + +/* Bit masks for PLL_CTL */ + +#define MSEL 0x7e00 /* Multiplier Select */ +#define BYPASS 0x100 /* PLL Bypass Enable */ +#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ +#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ +#define PDWN 0x20 /* Power Down */ +#define STOPCK 0x8 /* Stop Clock */ +#define PLL_OFF 0x2 /* Disable PLL */ +#define DF 0x1 /* Divide Frequency */ + /* SWRST Masks */ #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ @@ -2044,6 +2279,52 @@ #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ +/* Bit masks for PLL_STAT */ + +#define PLL_LOCKED 0x20 /* PLL Locked Status */ +#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ +#define FULL_ON 0x2 /* Full-On Mode */ +#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ +#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ +#define CANWS 0x800 /* CAN Wake-Up Status */ +#define USBWS 0x2000 /* USB Wake-Up Status */ +#define KPADWS 0x4000 /* Keypad Wake-Up Status */ +#define ROTWS 0x8000 /* Rotary Wake-Up Status */ +#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ + +/* Bit masks for VR_CTL */ + +#define FREQ 0x3 /* Regulator Switching Frequency */ +#define GAIN 0xc /* Voltage Output Level Gain */ +#define VLEV 0xf0 /* Internal Voltage Level */ +#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ +#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ +#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ +#define GPWE 0x400 /* General-Purpose Wake-Up Enable */ +#define USBWE 0x800 /* USB Wake-Up Enable */ +#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ +#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ + +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + /* Bit masks for NFC_CTL */ #define WR_DLY 0xf /* Write Strobe Delay */ @@ -2208,6 +2489,14 @@ #define UCCT 0x40 /* Universal Counter CAN Trigger */ #define UCE 0x80 /* Universal Counter Enable */ +/* Bit masks for CAN0_UCCNT */ + +#define UCCNT 0xffff /* Universal Counter Count Value */ + +/* Bit masks for CAN0_UCRC */ + +#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */ + /* Bit masks for CAN0_CEC */ #define RXECNT 0xff /* Receive Error Counter */ diff --git a/trunk/arch/blackfin/mach-bf561/boards/Kconfig b/trunk/arch/blackfin/mach-bf561/boards/Kconfig index 1aa529b9f8bb..e4bc6d7c5a6a 100644 --- a/trunk/arch/blackfin/mach-bf561/boards/Kconfig +++ b/trunk/arch/blackfin/mach-bf561/boards/Kconfig @@ -19,11 +19,4 @@ config BFIN561_BLUETECHNIX_CM help CM-BF561 support for EVAL- and DEV-Board. -config BFIN561_ACVILON - bool "BF561-ACVILON" - help - BF561-ACVILON System On Module support (SO-DIMM 144). - For more information about Acvilon BF561 SoM - please go to http://www.niistt.ru/ - endchoice diff --git a/trunk/arch/blackfin/mach-bf561/boards/Makefile b/trunk/arch/blackfin/mach-bf561/boards/Makefile index a5879f7857ad..3a152559e957 100644 --- a/trunk/arch/blackfin/mach-bf561/boards/Makefile +++ b/trunk/arch/blackfin/mach-bf561/boards/Makefile @@ -2,7 +2,6 @@ # arch/blackfin/mach-bf561/boards/Makefile # -obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o obj-$(CONFIG_BFIN561_TEPLA) += tepla.o diff --git a/trunk/arch/blackfin/mach-bf561/boards/acvilon.c b/trunk/arch/blackfin/mach-bf561/boards/acvilon.c deleted file mode 100644 index 07e8dc8770da..000000000000 --- a/trunk/arch/blackfin/mach-bf561/boards/acvilon.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * File: arch/blackfin/mach-bf561/acvilon.c - * Based on: arch/blackfin/mach-bf561/ezkit.c - * Author: - * - * Created: - * Description: - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * Copyright 2009 CJSC "NII STT" - * - * Bugs: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * - * For more information about Acvilon BF561 SoM please - * go to http://www.niistt.ru/ - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Acvilon board"; - -#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x20000000, - .end = 0x20000000 + 0x000fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF15, - .end = IRQ_PF15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .port1_disable = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760-hcd", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -static struct resource bfin_i2c_pca_resources[] = { - { - .name = "pca9564-regs", - .start = 0x2C000000, - .end = 0x2C000000 + 16, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, - }, { - - .start = IRQ_PF8, - .end = IRQ_PF8, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -struct i2c_pca9564_pf_platform_data pca9564_platform_data = { - .gpio = -1, - .i2c_clock_speed = 330000, - .timeout = 10000 -}; - -/* PCA9564 I2C Bus driver */ -static struct platform_device bfin_i2c_pca_device = { - .name = "i2c-pca-platform", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources), - .resource = bfin_i2c_pca_resources, - .dev = { - .platform_data = &pca9564_platform_data, - } -}; - -/* I2C devices fitted. */ -static struct i2c_board_info acvilon_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("ds1339", 0x68), - }, - { - I2C_BOARD_INFO("tcn75", 0x49), - }, -}; - -#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) -static struct platdata_mtd_ram mtd_ram_data = { - .mapname = "rootfs(RAM)", - .bankwidth = 4, -}; - -static struct resource mtd_ram_resource = { - .start = 0x4000000, - .end = 0x5ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mtd_ram_device = { - .name = "mtd-ram", - .id = 0, - .dev = { - .platform_data = &mtd_ram_data, - }, - .num_resources = 1, - .resource = &mtd_ram_resource, -}; -#endif - -#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -#include -static struct resource smsc911x_resources[] = { - { - .name = "smsc911x-memory", - .start = 0x28000000, - .end = 0x28000000 + 0xFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .flags = SMSC911X_USE_32BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; -#endif - -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL + 2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART_RX, - .end = IRQ_UART_RX + 1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_ERROR, - .end = IRQ_UART_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART_TX, - .end = CH_UART_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART_RX, - .end = CH_UART_RX, - .flags = IORESOURCE_DMA, - }, -}; - -unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - /* Passed to driver */ - .platform_data = &bfin_uart0_peripherals, - }, -}; -#endif -#endif - -#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) - -#ifdef CONFIG_MTD_PARTITIONS -const char *part_probes[] = { "cmdlinepart", NULL }; - -static struct mtd_partition bfin_plat_nand_partitions[] = { - { - .name = "params(nand)", - .size = 32 * 1024 * 1024, - .offset = 0, - }, { - .name = "userfs(nand)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; -#endif - -#define BFIN_NAND_PLAT_CLE 2 -#define BFIN_NAND_PLAT_ALE 3 - -static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE)); - else - writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE)); -} - -#define BFIN_NAND_PLAT_READY GPIO_PF10 -static int bfin_plat_nand_dev_ready(struct mtd_info *mtd) -{ - return gpio_get_value(BFIN_NAND_PLAT_READY); -} - -static struct platform_nand_data bfin_plat_nand_data = { - .chip = { - .chip_delay = 30, -#ifdef CONFIG_MTD_PARTITIONS - .part_probe_types = part_probes, - .partitions = bfin_plat_nand_partitions, - .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), -#endif - }, - .ctrl = { - .cmd_ctrl = bfin_plat_nand_cmd_ctrl, - .dev_ready = bfin_plat_nand_dev_ready, - }, -}; - -#define MAX(x, y) (x > y ? x : y) -static struct resource bfin_plat_nand_resources = { - .start = 0x24000000, - .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_IO, -}; - -static struct platform_device bfin_async_nand_device = { - .name = "gen_nand", - .id = -1, - .num_resources = 1, - .resource = &bfin_plat_nand_resources, - .dev = { - .platform_data = &bfin_plat_nand_data, - }, -}; - -static void bfin_plat_nand_init(void) -{ - gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); -} -#else -static void bfin_plat_nand_init(void) -{ -} -#endif - -#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) -static struct mtd_partition bfin_spi_dataflash_partitions[] = { - { - .name = "bootloader", - .size = 0x4200, - .offset = 0, - .mask_flags = MTD_CAP_ROM}, - { - .name = "u-boot", - .size = 0x42000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "u-boot(params)", - .size = 0x4200, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "kernel", - .size = 0x294000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "params", - .size = 0x42000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "rootfs", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_dataflash_data = { - .name = "SPI Dataflash", - .parts = bfin_spi_dataflash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), -}; - -/* DataFlash chip */ -static struct bfin5xx_spi_chip data_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip */ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 3, - .controller_data = &spidev_chip_info, - }, -#endif -#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select */ - .platform_data = &bfin_spi_dataflash_data, - .controller_data = &data_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -static struct resource bfin_gpios_resources = { - .start = 31, -/* .end = MAX_BLACKFIN_GPIOS - 1, */ - .end = 32, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device bfin_gpios_device = { - .name = "simple-gpio", - .id = -1, - .num_resources = 1, - .resource = &bfin_gpios_resources, -}; - -static const unsigned int cclk_vlev_datasheet[] = { - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 300000000), - VRPAIR(VLEV_095, 313000000), - VRPAIR(VLEV_100, 350000000), - VRPAIR(VLEV_105, 400000000), - VRPAIR(VLEV_110, 444000000), - VRPAIR(VLEV_115, 450000000), - VRPAIR(VLEV_120, 475000000), - VRPAIR(VLEV_125, 500000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */ , -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *acvilon_devices[] __initdata = { - &bfin_dpmc, - -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) - &bfin_spi0_device, -#endif - -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - - &bfin_gpios_device, - -#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) - &smsc911x_device, -#endif - - &bfin_i2c_pca_device, - -#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) - &bfin_async_nand_device, -#endif - -#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) - &mtd_ram_device, -#endif - -}; - -static int __init acvilon_init(void) -{ - int ret; - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - - bfin_plat_nand_init(); - ret = - platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices)); - if (ret < 0) - return ret; - - i2c_register_board_info(0, acvilon_i2c_devs, - ARRAY_SIZE(acvilon_i2c_devs)); - - bfin_write_FIO0_FLAG_C(1 << 14); - msleep(5); - bfin_write_FIO0_FLAG_S(1 << 14); - - spi_register_board_info(bfin_spi_board_info, - ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(acvilon_init); - -static struct platform_device *acvilon_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(acvilon_early_devices, - ARRAY_SIZE(acvilon_early_devices)); -} diff --git a/trunk/arch/blackfin/mach-bf561/boards/ezkit.c b/trunk/arch/blackfin/mach-bf561/boards/ezkit.c index ffd3e6a80d1a..9e2d8cfba546 100644 --- a/trunk/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/trunk/arch/blackfin/mach-bf561/boards/ezkit.c @@ -49,7 +49,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -159,6 +159,28 @@ static struct platform_device smc91x_device = { }; #endif +#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) +static struct resource ax88180_resources[] = { + [0] = { + .start = 0x2c000000, + .end = 0x2c000000 + 0x8000, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PF10, + .end = IRQ_PF10, + .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL), + }, +}; + +static struct platform_device ax88180_device = { + .name = "ax88180", + .id = -1, + .num_resources = ARRAY_SIZE(ax88180_resources), + .resource = ax88180_resources, +}; +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { { @@ -399,6 +421,10 @@ static struct platform_device *ezkit_devices[] __initdata = { &smc91x_device, #endif +#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) + &ax88180_device, +#endif + #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) &net2272_bfin_device, #endif diff --git a/trunk/arch/blackfin/mach-bf561/coreb.c b/trunk/arch/blackfin/mach-bf561/coreb.c index deb2271d09a3..1e60a92dd602 100644 --- a/trunk/arch/blackfin/mach-bf561/coreb.c +++ b/trunk/arch/blackfin/mach-bf561/coreb.c @@ -22,8 +22,8 @@ #define CMD_COREB_STOP 3 #define CMD_COREB_RESET 4 -static long -coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +static int +coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { int ret = 0; @@ -49,8 +49,8 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } static const struct file_operations coreb_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = coreb_ioctl, + .owner = THIS_MODULE, + .ioctl = coreb_ioctl, }; static struct miscdevice coreb_dev = { diff --git a/trunk/arch/blackfin/mach-bf561/include/mach/defBF561.h b/trunk/arch/blackfin/mach-bf561/include/mach/defBF561.h index 4c8e36b7fb33..a31e509553fb 100644 --- a/trunk/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/trunk/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -884,11 +884,65 @@ /* System MMR Register Bits */ /******************************************************************************* */ +/* ********************* PLL AND RESET MASKS ************************ */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ +#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x00000008 /* Core clock off */ +#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ +#define BYPASS 0x00000100 /* Bypass the PLL */ + /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 #define CHIPID_MANUFACTURE 0x00000FFE +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + +/* PLL_DIV Masks */ +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CSEL 0x30 /* Core Select */ +#define SSEL 0xf /* System Select */ +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ + /* SICA_SYSCR Masks */ #define COREB_SRAM_INIT 0x0020 @@ -1096,6 +1150,53 @@ /* ********** DMA CONTROLLER MASKS *********************8 */ +/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define DMAFLOW 0x00007000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ + +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ diff --git a/trunk/arch/blackfin/mach-bf561/smp.c b/trunk/arch/blackfin/mach-bf561/smp.c index 0192532e96a2..510f57641495 100644 --- a/trunk/arch/blackfin/mach-bf561/smp.c +++ b/trunk/arch/blackfin/mach-bf561/smp.c @@ -52,6 +52,8 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ void __cpuinit platform_secondary_init(unsigned int cpu) { + local_irq_disable(); + /* Clone setup for peripheral interrupt sources from CoreA. */ bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); @@ -68,6 +70,11 @@ void __cpuinit platform_secondary_init(unsigned int cpu) bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); SSYNC(); + local_irq_enable(); + + /* Calibrate loops per jiffy value. */ + calibrate_delay(); + /* Store CPU-private information to the cpu_data array. */ bfin_setup_cpudata(cpu); @@ -101,13 +108,9 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle barrier(); } - if (cpu_isset(cpu, cpu_callin_map)) { - cpu_set(cpu, cpu_online_map); - /* release the lock and let coreb run */ - spin_unlock(&boot_lock); - return 0; - } else - panic("CPU%u: processor failed to boot\n", cpu); + spin_unlock(&boot_lock); + + return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS; } void __init platform_request_ipi(irq_handler_t handler) diff --git a/trunk/arch/blackfin/mach-common/clocks-init.c b/trunk/arch/blackfin/mach-common/clocks-init.c index d5cfe611b778..ef6870e9eea6 100644 --- a/trunk/arch/blackfin/mach-common/clocks-init.c +++ b/trunk/arch/blackfin/mach-common/clocks-init.c @@ -13,7 +13,6 @@ #include #include #include -#include #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ #define PLL_CTL_VAL \ diff --git a/trunk/arch/blackfin/mach-common/cpufreq.c b/trunk/arch/blackfin/mach-common/cpufreq.c index 777582897253..01506504e6d0 100644 --- a/trunk/arch/blackfin/mach-common/cpufreq.c +++ b/trunk/arch/blackfin/mach-common/cpufreq.c @@ -13,7 +13,7 @@ #include #include #include -#include + /* this is the table of CCLK frequencies, in Hz */ /* .index is the entry in the auxillary dpm_state_table[] */ @@ -138,8 +138,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) dpm_state_table[index].tscale); } - policy->cpuinfo.transition_latency = 50000; /* 50us assumed */ - + policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000; /*Now ,only support one cpu */ policy->cur = cclk; cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); diff --git a/trunk/arch/blackfin/mach-common/dpmc_modes.S b/trunk/arch/blackfin/mach-common/dpmc_modes.S index b03716896051..8009a512fb11 100644 --- a/trunk/arch/blackfin/mach-common/dpmc_modes.S +++ b/trunk/arch/blackfin/mach-common/dpmc_modes.S @@ -404,21 +404,6 @@ ENTRY(_do_hibernate) PM_SYS_PUSH(EBIU_FCTL) #endif -#ifdef PORTCIO_FER - PM_SYS_PUSH16(PORTCIO_DIR) - PM_SYS_PUSH16(PORTCIO_INEN) - PM_SYS_PUSH16(PORTCIO) - PM_SYS_PUSH16(PORTCIO_FER) - PM_SYS_PUSH16(PORTDIO_DIR) - PM_SYS_PUSH16(PORTDIO_INEN) - PM_SYS_PUSH16(PORTDIO) - PM_SYS_PUSH16(PORTDIO_FER) - PM_SYS_PUSH16(PORTEIO_DIR) - PM_SYS_PUSH16(PORTEIO_INEN) - PM_SYS_PUSH16(PORTEIO) - PM_SYS_PUSH16(PORTEIO_FER) -#endif - PM_SYS_PUSH16(SYSCR) /* Save Core MMRs */ @@ -731,21 +716,6 @@ ENTRY(_do_hibernate) P0.L = lo(PLL_CTL); PM_SYS_POP16(SYSCR) -#ifdef PORTCIO_FER - PM_SYS_POP16(PORTEIO_FER) - PM_SYS_POP16(PORTEIO) - PM_SYS_POP16(PORTEIO_INEN) - PM_SYS_POP16(PORTEIO_DIR) - PM_SYS_POP16(PORTDIO_FER) - PM_SYS_POP16(PORTDIO) - PM_SYS_POP16(PORTDIO_INEN) - PM_SYS_POP16(PORTDIO_DIR) - PM_SYS_POP16(PORTCIO_FER) - PM_SYS_POP16(PORTCIO) - PM_SYS_POP16(PORTCIO_INEN) - PM_SYS_POP16(PORTCIO_DIR) -#endif - #ifdef EBIU_FCTL PM_SYS_POP(EBIU_FCTL) PM_SYS_POP(EBIU_MODE) diff --git a/trunk/arch/blackfin/mach-common/entry.S b/trunk/arch/blackfin/mach-common/entry.S index b0ed0b487ff2..f3f8bb46b517 100644 --- a/trunk/arch/blackfin/mach-common/entry.S +++ b/trunk/arch/blackfin/mach-common/entry.S @@ -713,8 +713,6 @@ ENTRY(_system_call) cc = BITTST(r7, TIF_RESTORE_SIGMASK); if cc jump .Lsyscall_do_signals; cc = BITTST(r7, TIF_SIGPENDING); - if cc jump .Lsyscall_do_signals; - cc = BITTST(r7, TIF_NOTIFY_RESUME); if !cc jump .Lsyscall_really_exit; .Lsyscall_do_signals: /* Reenable interrupts. */ @@ -723,7 +721,7 @@ ENTRY(_system_call) r0 = sp; SP += -12; - call _do_notify_resume; + call _do_signal; SP += 12; .Lsyscall_really_exit: diff --git a/trunk/arch/blackfin/mach-common/ints-priority.c b/trunk/arch/blackfin/mach-common/ints-priority.c index 1873b2c1fede..660ea1bec54c 100644 --- a/trunk/arch/blackfin/mach-common/ints-priority.c +++ b/trunk/arch/blackfin/mach-common/ints-priority.c @@ -25,20 +25,11 @@ #include #include #include -#include -#include -#include #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) #ifdef BF537_FAMILY # define BF537_GENERIC_ERROR_INT_DEMUX -# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */ -# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */ -# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ -# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ -# define UART_ERR_MASK (0x6) /* UART_IIR */ -# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ #else # undef BF537_GENERIC_ERROR_INT_DEMUX #endif @@ -333,9 +324,11 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, irq = IRQ_CAN_ERROR; else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) irq = IRQ_SPI_ERROR; - else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK) + else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) && + (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0)) irq = IRQ_UART0_ERROR; - else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK) + else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) && + (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0)) irq = IRQ_UART1_ERROR; if (irq) { diff --git a/trunk/arch/blackfin/mach-common/smp.c b/trunk/arch/blackfin/mach-common/smp.c index 369e687582b7..d92b168c8328 100644 --- a/trunk/arch/blackfin/mach-common/smp.c +++ b/trunk/arch/blackfin/mach-common/smp.c @@ -336,6 +336,13 @@ int __cpuinit __cpu_up(unsigned int cpu) ret = platform_boot_secondary(cpu, idle); + if (ret) { + cpu_clear(cpu, cpu_present_map); + printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret); + free_task(idle); + } else + cpu_set(cpu, cpu_online_map); + secondary_stack = NULL; return ret; @@ -411,16 +418,9 @@ void __cpuinit secondary_start_kernel(void) setup_secondary(cpu); - platform_secondary_init(cpu); - local_irq_enable(); - /* - * Calibrate loops per jiffy value. - * IRQs need to be enabled here - D-cache can be invalidated - * in timer irq handler, so core B can read correct jiffies. - */ - calibrate_delay(); + platform_secondary_init(cpu); cpu_idle(); } diff --git a/trunk/arch/cris/arch-v32/kernel/head.S b/trunk/arch/cris/arch-v32/kernel/head.S index 76266f80a5f1..3db478eb5155 100644 --- a/trunk/arch/cris/arch-v32/kernel/head.S +++ b/trunk/arch/cris/arch-v32/kernel/head.S @@ -10,6 +10,7 @@ * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so * -traditional must not be used when assembling this file. */ +#include #include #include #include diff --git a/trunk/arch/cris/include/asm/asm-offsets.h b/trunk/arch/cris/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/cris/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/cris/include/asm/elf.h b/trunk/arch/cris/include/asm/elf.h index 8a3d8e2b33c1..0f51b10b9f4f 100644 --- a/trunk/arch/cris/include/asm/elf.h +++ b/trunk/arch/cris/include/asm/elf.h @@ -64,6 +64,8 @@ typedef unsigned long elf_fpregset_t; #define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 /* End of excerpt from {binutils}/include/elf/cris.h. */ +#define USE_ELF_CORE_DUMP + #define ELF_EXEC_PAGESIZE 8192 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/cris/kernel/asm-offsets.c b/trunk/arch/cris/kernel/asm-offsets.c index dd7b8e983221..ddd6fbbe75de 100644 --- a/trunk/arch/cris/kernel/asm-offsets.c +++ b/trunk/arch/cris/kernel/asm-offsets.c @@ -1,5 +1,6 @@ #include #include +#include /* * Generate definitions needed by assembly language modules. diff --git a/trunk/arch/cris/kernel/vmlinux.lds.S b/trunk/arch/cris/kernel/vmlinux.lds.S index d49d17d2a14f..bbfda67d2907 100644 --- a/trunk/arch/cris/kernel/vmlinux.lds.S +++ b/trunk/arch/cris/kernel/vmlinux.lds.S @@ -8,6 +8,7 @@ * the kernel has booted. */ +#include #include #include diff --git a/trunk/arch/frv/include/asm/asm-offsets.h b/trunk/arch/frv/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/frv/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/frv/include/asm/elf.h b/trunk/arch/frv/include/asm/elf.h index c3819804a74b..7bbf6e47f8c8 100644 --- a/trunk/arch/frv/include/asm/elf.h +++ b/trunk/arch/frv/include/asm/elf.h @@ -115,6 +115,7 @@ do { \ __kernel_frame0_ptr->gr29 = 0; \ } while(0) +#define USE_ELF_CORE_DUMP #define CORE_DUMP_USE_REGSET #define ELF_FDPIC_CORE_EFLAGS EF_FRV_FDPIC #define ELF_EXEC_PAGESIZE 16384 diff --git a/trunk/arch/frv/kernel/setup.c b/trunk/arch/frv/kernel/setup.c index 75cf7f4b2fa8..55e4fab7c0bc 100644 --- a/trunk/arch/frv/kernel/setup.c +++ b/trunk/arch/frv/kernel/setup.c @@ -10,7 +10,7 @@ * 2 of the License, or (at your option) any later version. */ -#include +#include #include #include #include diff --git a/trunk/arch/h8300/Kconfig b/trunk/arch/h8300/Kconfig index 53cc669e6d59..9420648352b8 100644 --- a/trunk/arch/h8300/Kconfig +++ b/trunk/arch/h8300/Kconfig @@ -10,10 +10,6 @@ config H8300 default y select HAVE_IDE -config SYMBOL_PREFIX - string - default "_" - config MMU bool default n diff --git a/trunk/arch/h8300/include/asm/asm-offsets.h b/trunk/arch/h8300/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/h8300/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/h8300/include/asm/elf.h b/trunk/arch/h8300/include/asm/elf.h index c24fa250d653..94e2284c8816 100644 --- a/trunk/arch/h8300/include/asm/elf.h +++ b/trunk/arch/h8300/include/asm/elf.h @@ -34,6 +34,7 @@ typedef unsigned long elf_fpregset_t; #define ELF_PLAT_INIT(_r) _r->er1 = 0 +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/h8300/include/asm/module.h b/trunk/arch/h8300/include/asm/module.h index 8e46724b7c09..de23231f3196 100644 --- a/trunk/arch/h8300/include/asm/module.h +++ b/trunk/arch/h8300/include/asm/module.h @@ -8,4 +8,6 @@ struct mod_arch_specific { }; #define Elf_Sym Elf32_Sym #define Elf_Ehdr Elf32_Ehdr +#define MODULE_SYMBOL_PREFIX "_" + #endif /* _ASM_H8/300_MODULE_H */ diff --git a/trunk/arch/h8300/kernel/vmlinux.lds.S b/trunk/arch/h8300/kernel/vmlinux.lds.S index 03d356d96e5d..b9e24907e6ea 100644 --- a/trunk/arch/h8300/kernel/vmlinux.lds.S +++ b/trunk/arch/h8300/kernel/vmlinux.lds.S @@ -1,3 +1,4 @@ +#define VMLINUX_SYMBOL(_sym_) _##_sym_ #include #include diff --git a/trunk/arch/ia64/Makefile b/trunk/arch/ia64/Makefile index 475e2725fbde..e7cbaa02cd0b 100644 --- a/trunk/arch/ia64/Makefile +++ b/trunk/arch/ia64/Makefile @@ -103,4 +103,4 @@ archprepare: make_nr_irqs_h FORCE PHONY += make_nr_irqs_h FORCE make_nr_irqs_h: FORCE - $(Q)$(MAKE) $(build)=arch/ia64/kernel include/generated/nr-irqs.h + $(Q)$(MAKE) $(build)=arch/ia64/kernel include/asm-ia64/nr-irqs.h diff --git a/trunk/arch/ia64/hp/common/sba_iommu.c b/trunk/arch/ia64/hp/common/sba_iommu.c index e14c492a8a93..f332e3fe4237 100644 --- a/trunk/arch/ia64/hp/common/sba_iommu.c +++ b/trunk/arch/ia64/hp/common/sba_iommu.c @@ -677,19 +677,12 @@ sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) spin_unlock_irqrestore(&ioc->saved_lock, flags); pide = sba_search_bitmap(ioc, dev, pages_needed, 0); - if (unlikely(pide >= (ioc->res_size << 3))) { - printk(KERN_WARNING "%s: I/O MMU @ %p is" - "out of mapping resources, %u %u %lx\n", - __func__, ioc->ioc_hpa, ioc->res_size, - pages_needed, dma_get_seg_boundary(dev)); - return -1; - } + if (unlikely(pide >= (ioc->res_size << 3))) + panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n", + ioc->ioc_hpa); #else - printk(KERN_WARNING "%s: I/O MMU @ %p is" - "out of mapping resources, %u %u %lx\n", - __func__, ioc->ioc_hpa, ioc->res_size, - pages_needed, dma_get_seg_boundary(dev)); - return -1; + panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n", + ioc->ioc_hpa); #endif } } @@ -972,8 +965,6 @@ static dma_addr_t sba_map_page(struct device *dev, struct page *page, #endif pide = sba_alloc_range(ioc, dev, size); - if (pide < 0) - return 0; iovp = (dma_addr_t) pide << iovp_shift; @@ -1329,7 +1320,6 @@ sba_coalesce_chunks(struct ioc *ioc, struct device *dev, unsigned long dma_offset, dma_len; /* start/len of DMA stream */ int n_mappings = 0; unsigned int max_seg_size = dma_get_max_seg_size(dev); - int idx; while (nents > 0) { unsigned long vaddr = (unsigned long) sba_sg_address(startsg); @@ -1428,22 +1418,16 @@ sba_coalesce_chunks(struct ioc *ioc, struct device *dev, vcontig_sg->dma_length = vcontig_len; dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask; ASSERT(dma_len <= DMA_CHUNK_SIZE); - idx = sba_alloc_range(ioc, dev, dma_len); - if (idx < 0) { - dma_sg->dma_length = 0; - return -1; - } - dma_sg->dma_address = (dma_addr_t)(PIDE_FLAG | (idx << iovp_shift) - | dma_offset); + dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG + | (sba_alloc_range(ioc, dev, dma_len) << iovp_shift) + | dma_offset); n_mappings++; } return n_mappings; } -static void sba_unmap_sg_attrs(struct device *dev, struct scatterlist *sglist, - int nents, enum dma_data_direction dir, - struct dma_attrs *attrs); + /** * sba_map_sg - map Scatter/Gather list * @dev: instance of PCI owned by the driver that's asking. @@ -1509,10 +1493,6 @@ static int sba_map_sg_attrs(struct device *dev, struct scatterlist *sglist, ** Access to the virtual address is what forces a two pass algorithm. */ coalesced = sba_coalesce_chunks(ioc, dev, sglist, nents); - if (coalesced < 0) { - sba_unmap_sg_attrs(dev, sglist, nents, dir, attrs); - return 0; - } /* ** Program the I/O Pdir diff --git a/trunk/arch/ia64/ia32/elfcore32.h b/trunk/arch/ia64/ia32/elfcore32.h index 657725742617..9a3abf58cea3 100644 --- a/trunk/arch/ia64/ia32/elfcore32.h +++ b/trunk/arch/ia64/ia32/elfcore32.h @@ -11,6 +11,8 @@ #include #include +#define USE_ELF_CORE_DUMP 1 + /* Override elfcore.h */ #define _LINUX_ELFCORE_H 1 typedef unsigned int elf_greg_t; diff --git a/trunk/arch/ia64/include/asm/asm-offsets.h b/trunk/arch/ia64/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/ia64/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/ia64/include/asm/dma-mapping.h b/trunk/arch/ia64/include/asm/dma-mapping.h index 7d09a09cdaad..8d3c79cd81e7 100644 --- a/trunk/arch/ia64/include/asm/dma-mapping.h +++ b/trunk/arch/ia64/include/asm/dma-mapping.h @@ -73,7 +73,7 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) if (!dev->dma_mask) return 0; - return addr + size - 1 <= *dev->dma_mask; + return addr + size <= *dev->dma_mask; } static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) diff --git a/trunk/arch/ia64/include/asm/elf.h b/trunk/arch/ia64/include/asm/elf.h index e14108b19c09..86eddee029cb 100644 --- a/trunk/arch/ia64/include/asm/elf.h +++ b/trunk/arch/ia64/include/asm/elf.h @@ -25,6 +25,7 @@ #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_IA_64 +#define USE_ELF_CORE_DUMP #define CORE_DUMP_USE_REGSET /* Least-significant four bits of ELF header's e_flags are OS-specific. The bits are diff --git a/trunk/arch/ia64/include/asm/hw_irq.h b/trunk/arch/ia64/include/asm/hw_irq.h index bf2e37493e04..91619b31dbf5 100644 --- a/trunk/arch/ia64/include/asm/hw_irq.h +++ b/trunk/arch/ia64/include/asm/hw_irq.h @@ -59,13 +59,7 @@ typedef u16 ia64_vector; extern int ia64_first_device_vector; extern int ia64_last_device_vector; -#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_DIG)) -/* Reserve the lower priority vector than device vectors for "move IRQ" IPI */ -#define IA64_IRQ_MOVE_VECTOR 0x30 /* "move IRQ" IPI */ -#define IA64_DEF_FIRST_DEVICE_VECTOR 0x31 -#else #define IA64_DEF_FIRST_DEVICE_VECTOR 0x30 -#endif #define IA64_DEF_LAST_DEVICE_VECTOR 0xe7 #define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector #define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector diff --git a/trunk/arch/ia64/include/asm/io.h b/trunk/arch/ia64/include/asm/io.h index cc8335eb3110..0d9d16e2d949 100644 --- a/trunk/arch/ia64/include/asm/io.h +++ b/trunk/arch/ia64/include/asm/io.h @@ -424,8 +424,6 @@ __writeq (unsigned long val, volatile void __iomem *addr) extern void __iomem * ioremap(unsigned long offset, unsigned long size); extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size); extern void iounmap (volatile void __iomem *addr); -extern void __iomem * early_ioremap (unsigned long phys_addr, unsigned long size); -extern void early_iounmap (volatile void __iomem *addr, unsigned long size); /* * String version of IO memory access ops: diff --git a/trunk/arch/ia64/include/asm/irq.h b/trunk/arch/ia64/include/asm/irq.h index 91b920fd7d53..5282546cdf82 100644 --- a/trunk/arch/ia64/include/asm/irq.h +++ b/trunk/arch/ia64/include/asm/irq.h @@ -13,7 +13,7 @@ #include #include -#include +#include static __inline__ int irq_canonicalize (int irq) diff --git a/trunk/arch/ia64/include/asm/mca.h b/trunk/arch/ia64/include/asm/mca.h index 43f96ab18fa0..c171cdf0a789 100644 --- a/trunk/arch/ia64/include/asm/mca.h +++ b/trunk/arch/ia64/include/asm/mca.h @@ -106,11 +106,6 @@ struct ia64_sal_os_state { unsigned long os_status; /* OS status to SAL, enum below */ unsigned long context; /* 0 if return to same context 1 if return to new context */ - - /* I-resources */ - unsigned long iip; - unsigned long ipsr; - unsigned long ifs; }; enum { diff --git a/trunk/arch/ia64/include/asm/rwsem.h b/trunk/arch/ia64/include/asm/rwsem.h index e8762688e8e3..fbee74b15782 100644 --- a/trunk/arch/ia64/include/asm/rwsem.h +++ b/trunk/arch/ia64/include/asm/rwsem.h @@ -47,7 +47,7 @@ struct rw_semaphore { #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) #define __RWSEM_INITIALIZER(name) \ - { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \ + { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ LIST_HEAD_INIT((name).wait_list) } #define DECLARE_RWSEM(name) \ diff --git a/trunk/arch/ia64/kernel/Makefile b/trunk/arch/ia64/kernel/Makefile index 2a75e937ae8d..6b7edcab0cb5 100644 --- a/trunk/arch/ia64/kernel/Makefile +++ b/trunk/arch/ia64/kernel/Makefile @@ -81,14 +81,17 @@ define cmd_nr_irqs endef # We use internal kbuild rules to avoid the "is up to date" message from make -arch/$(SRCARCH)/kernel/nr-irqs.s: arch/$(SRCARCH)/kernel/nr-irqs.c +arch/$(SRCARCH)/kernel/nr-irqs.s: $(srctree)/arch/$(SRCARCH)/kernel/nr-irqs.c \ + $(wildcard $(srctree)/include/asm-ia64/*/irq.h) $(Q)mkdir -p $(dir $@) $(call if_changed_dep,cc_s_c) -include/generated/nr-irqs.h: arch/$(SRCARCH)/kernel/nr-irqs.s +include/asm-ia64/nr-irqs.h: arch/$(SRCARCH)/kernel/nr-irqs.s $(Q)mkdir -p $(dir $@) $(call cmd,nr_irqs) +clean-files += $(objtree)/include/asm-ia64/nr-irqs.h + # # native ivt.S, entry.S and fsys.S # diff --git a/trunk/arch/ia64/kernel/irq_ia64.c b/trunk/arch/ia64/kernel/irq_ia64.c index d4093a173a3e..70e4bad23432 100644 --- a/trunk/arch/ia64/kernel/irq_ia64.c +++ b/trunk/arch/ia64/kernel/irq_ia64.c @@ -260,6 +260,7 @@ void __setup_vector_irq(int cpu) } #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)) +#define IA64_IRQ_MOVE_VECTOR IA64_DEF_FIRST_DEVICE_VECTOR static enum vector_domain_type { VECTOR_DOMAIN_NONE, @@ -658,8 +659,11 @@ init_IRQ (void) register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL); #ifdef CONFIG_SMP #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG) - if (vector_domain_type != VECTOR_DOMAIN_NONE) + if (vector_domain_type != VECTOR_DOMAIN_NONE) { + BUG_ON(IA64_FIRST_DEVICE_VECTOR != IA64_IRQ_MOVE_VECTOR); + IA64_FIRST_DEVICE_VECTOR++; register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction); + } #endif #endif #ifdef CONFIG_PERFMON diff --git a/trunk/arch/ia64/kernel/mca.c b/trunk/arch/ia64/kernel/mca.c index 32f2639e9b0a..496ac7a99488 100644 --- a/trunk/arch/ia64/kernel/mca.c +++ b/trunk/arch/ia64/kernel/mca.c @@ -888,10 +888,9 @@ ia64_mca_modify_comm(const struct task_struct *previous_current) } static void -finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos, +finish_pt_regs(struct pt_regs *regs, const pal_min_state_area_t *ms, unsigned long *nat) { - const pal_min_state_area_t *ms = sos->pal_min_state; const u64 *bank; /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use @@ -905,10 +904,6 @@ finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos, regs->cr_iip = ms->pmsa_xip; regs->cr_ipsr = ms->pmsa_xpsr; regs->cr_ifs = ms->pmsa_xfs; - - sos->iip = ms->pmsa_iip; - sos->ipsr = ms->pmsa_ipsr; - sos->ifs = ms->pmsa_ifs; } regs->pr = ms->pmsa_pr; regs->b0 = ms->pmsa_br0; @@ -1084,7 +1079,7 @@ ia64_mca_modify_original_stack(struct pt_regs *regs, memcpy(old_regs, regs, sizeof(*regs)); old_regs->loadrs = loadrs; old_unat = old_regs->ar_unat; - finish_pt_regs(old_regs, sos, &old_unat); + finish_pt_regs(old_regs, ms, &old_unat); /* Next stack a struct switch_stack. mca_asm.S built a partial * switch_stack, copy it and fill in the blanks using pt_regs and @@ -1155,7 +1150,7 @@ ia64_mca_modify_original_stack(struct pt_regs *regs, mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n", smp_processor_id(), type, msg); old_unat = regs->ar_unat; - finish_pt_regs(regs, sos, &old_unat); + finish_pt_regs(regs, ms, &old_unat); return previous_current; } diff --git a/trunk/arch/ia64/kernel/perfmon.c b/trunk/arch/ia64/kernel/perfmon.c index 5246285a95fb..599b233bef75 100644 --- a/trunk/arch/ia64/kernel/perfmon.c +++ b/trunk/arch/ia64/kernel/perfmon.c @@ -2200,7 +2200,7 @@ pfm_alloc_file(pfm_context_t *ctx) { struct file *file; struct inode *inode; - struct path path; + struct dentry *dentry; char name[32]; struct qstr this; @@ -2225,19 +2225,18 @@ pfm_alloc_file(pfm_context_t *ctx) /* * allocate a new dcache entry */ - path.dentry = d_alloc(pfmfs_mnt->mnt_sb->s_root, &this); - if (!path.dentry) { + dentry = d_alloc(pfmfs_mnt->mnt_sb->s_root, &this); + if (!dentry) { iput(inode); return ERR_PTR(-ENOMEM); } - path.mnt = mntget(pfmfs_mnt); - path.dentry->d_op = &pfmfs_dentry_operations; - d_add(path.dentry, inode); + dentry->d_op = &pfmfs_dentry_operations; + d_add(dentry, inode); - file = alloc_file(&path, FMODE_READ, &pfm_file_ops); + file = alloc_file(pfmfs_mnt, dentry, FMODE_READ, &pfm_file_ops); if (!file) { - path_put(&path); + dput(dentry); return ERR_PTR(-ENFILE); } diff --git a/trunk/arch/ia64/kvm/asm-offsets.c b/trunk/arch/ia64/kvm/asm-offsets.c index 9324c875caf5..0c3564a7a033 100644 --- a/trunk/arch/ia64/kvm/asm-offsets.c +++ b/trunk/arch/ia64/kvm/asm-offsets.c @@ -22,6 +22,7 @@ * */ +#include #include #include diff --git a/trunk/arch/ia64/mm/ioremap.c b/trunk/arch/ia64/mm/ioremap.c index 3dccdd8eb275..2a140627dfd6 100644 --- a/trunk/arch/ia64/mm/ioremap.c +++ b/trunk/arch/ia64/mm/ioremap.c @@ -21,12 +21,6 @@ __ioremap (unsigned long phys_addr) return (void __iomem *) (__IA64_UNCACHED_OFFSET | phys_addr); } -void __iomem * -early_ioremap (unsigned long phys_addr, unsigned long size) -{ - return __ioremap(phys_addr); -} - void __iomem * ioremap (unsigned long phys_addr, unsigned long size) { @@ -107,11 +101,6 @@ ioremap_nocache (unsigned long phys_addr, unsigned long size) } EXPORT_SYMBOL(ioremap_nocache); -void -early_iounmap (volatile void __iomem *addr, unsigned long size) -{ -} - void iounmap (volatile void __iomem *addr) { diff --git a/trunk/arch/ia64/sn/pci/tioca_provider.c b/trunk/arch/ia64/sn/pci/tioca_provider.c index efb454534e52..35b2a27d2e77 100644 --- a/trunk/arch/ia64/sn/pci/tioca_provider.c +++ b/trunk/arch/ia64/sn/pci/tioca_provider.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -370,7 +369,7 @@ tioca_dma_d48(struct pci_dev *pdev, u64 paddr) static dma_addr_t tioca_dma_mapped(struct pci_dev *pdev, unsigned long paddr, size_t req_size) { - int ps, ps_shift, entry, entries, mapsize; + int i, ps, ps_shift, entry, entries, mapsize, last_entry; u64 xio_addr, end_xio_addr; struct tioca_common *tioca_common; struct tioca_kernel *tioca_kern; @@ -411,13 +410,23 @@ tioca_dma_mapped(struct pci_dev *pdev, unsigned long paddr, size_t req_size) map = tioca_kern->ca_pcigart_pagemap; mapsize = tioca_kern->ca_pcigart_entries; - entry = bitmap_find_next_zero_area(map, mapsize, 0, entries, 0); - if (entry >= mapsize) { + entry = find_first_zero_bit(map, mapsize); + while (entry < mapsize) { + last_entry = find_next_bit(map, mapsize, entry); + + if (last_entry - entry >= entries) + break; + + entry = find_next_zero_bit(map, mapsize, last_entry); + } + + if (entry > mapsize) { kfree(ca_dmamap); goto map_return; } - bitmap_set(map, entry, entries); + for (i = 0; i < entries; i++) + set_bit(entry + i, map); bus_addr = tioca_kern->ca_pciap_base + (entry * ps); diff --git a/trunk/arch/m32r/include/asm/elf.h b/trunk/arch/m32r/include/asm/elf.h index 2f85412ef730..0cc34c94bf2b 100644 --- a/trunk/arch/m32r/include/asm/elf.h +++ b/trunk/arch/m32r/include/asm/elf.h @@ -102,6 +102,7 @@ typedef elf_fpreg_t elf_fpregset_t; */ #define ELF_PLAT_INIT(_r, load_addr) (_r)->r0 = 0 +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE /* diff --git a/trunk/arch/m68k/include/asm/asm-offsets.h b/trunk/arch/m68k/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/m68k/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/m68k/include/asm/elf.h b/trunk/arch/m68k/include/asm/elf.h index 01c193d91412..0b0f49eb876b 100644 --- a/trunk/arch/m68k/include/asm/elf.h +++ b/trunk/arch/m68k/include/asm/elf.h @@ -59,6 +59,7 @@ typedef struct user_m68kfp_struct elf_fpregset_t; is actually used on ASV. */ #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 +#define USE_ELF_CORE_DUMP #ifndef CONFIG_SUN3 #define ELF_EXEC_PAGESIZE 4096 #else diff --git a/trunk/arch/m68k/kernel/head.S b/trunk/arch/m68k/kernel/head.S index ef54128baa0b..86edb5fbcfc3 100644 --- a/trunk/arch/m68k/kernel/head.S +++ b/trunk/arch/m68k/kernel/head.S @@ -196,7 +196,7 @@ * for them and trying to understand what they mean. * * CONFIG_xxx: These are the obvious machine configuration defines created - * during configuration. These are defined in autoconf.h. + * during configuration. These are defined in include/linux/autoconf.h. * * CONSOLE: There is support for head.S console in this file. This * console can talk to a Mac frame buffer, but could easily be extrapolated diff --git a/trunk/arch/microblaze/include/asm/asm-offsets.h b/trunk/arch/microblaze/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/microblaze/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/microblaze/include/asm/elf.h b/trunk/arch/microblaze/include/asm/elf.h index 7d4acf2b278e..f92fc0dda006 100644 --- a/trunk/arch/microblaze/include/asm/elf.h +++ b/trunk/arch/microblaze/include/asm/elf.h @@ -77,6 +77,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #define ELF_DATA ELFDATA2MSB #endif +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index 9541171f1220..fd7620f025fa 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -5,12 +5,9 @@ config MIPS select HAVE_IDE select HAVE_OPROFILE select HAVE_ARCH_KGDB - select HAVE_FUNCTION_TRACER - select HAVE_FUNCTION_TRACE_MCOUNT_TEST - select HAVE_DYNAMIC_FTRACE - select HAVE_FTRACE_MCOUNT_RECORD - select HAVE_FUNCTION_GRAPH_TRACER - select RTC_LIB if !MACH_LOONGSON + # Horrible source of confusion. Die, die, die ... + select EMBEDDED + select RTC_LIB if !LEMOTE_FULOONG2E mainmenu "Linux/MIPS Kernel Configuration" @@ -25,7 +22,6 @@ choice config MACH_ALCHEMY bool "Alchemy processor based machines" - select SYS_SUPPORTS_ZBOOT config AR7 bool "Texas Instruments AR7" @@ -40,7 +36,6 @@ config AR7 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_ZBOOT_UART16550 select GENERIC_GPIO select GCD select VLYNQ @@ -48,6 +43,23 @@ config AR7 Support for the Texas Instruments AR7 System-on-a-Chip family: TNETD7100, 7200 and 7300. +config BASLER_EXCITE + bool "Basler eXcite smart camera" + select CEVT_R4K + select CSRC_R4K + select DMA_COHERENT + select HW_HAS_PCI + select IRQ_CPU + select IRQ_CPU_RM7K + select IRQ_CPU_RM9K + select MIPS_RM9122 + select SYS_HAS_CPU_RM9000 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + help + The eXcite is a smart camera platform manufactured by + Basler Vision Technologies AG. + config BCM47XX bool "BCM47XX based boards" select CEVT_R4K @@ -180,7 +192,6 @@ config LASAT config MACH_LOONGSON bool "Loongson family of machines" - select SYS_SUPPORTS_ZBOOT_UART16550 help This enables the support of Loongson family of machines. @@ -222,7 +233,6 @@ config MIPS_MALTA select SYS_SUPPORTS_MIPS_CMP select SYS_SUPPORTS_MULTITHREADING select SYS_SUPPORTS_SMARTMIPS - select SYS_SUPPORTS_ZBOOT help This enables support for the MIPS Technologies Malta evaluation board. @@ -324,24 +334,6 @@ config PMC_YOSEMITE Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra. -config POWERTV - bool "Cisco PowerTV" - select BOOT_ELF32 - select CEVT_R4K - select CPU_MIPSR2_IRQ_VI - select CPU_MIPSR2_IRQ_EI - select CSRC_POWERTV - select DMA_NONCOHERENT - select HW_HAS_PCI - select SYS_HAS_EARLY_PRINTK - select SYS_HAS_CPU_MIPS32_R2 - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select USB_OHCI_LITTLE_ENDIAN - help - This enables support for the Cisco PowerTV Platform. - config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select ARC @@ -682,11 +674,11 @@ config CAVIUM_OCTEON_REFERENCE_BOARD endchoice source "arch/mips/alchemy/Kconfig" +source "arch/mips/basler/excite/Kconfig" source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" -source "arch/mips/powertv/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" @@ -786,9 +778,6 @@ config CSRC_BCM1480 config CSRC_IOASIC bool -config CSRC_POWERTV - bool - config CSRC_R4K_LIB bool @@ -817,6 +806,20 @@ config DMA_NONCOHERENT config DMA_NEED_PCI_MAP_STATE bool +config EARLY_PRINTK + bool "Early printk" if EMBEDDED && DEBUG_KERNEL + depends on SYS_HAS_EARLY_PRINTK + default y + help + This option enables special console drivers which allow the kernel + to print messages very early in the bootup process. + + This is useful for kernel debugging when your machine crashes very + early before the console code is initialized. For normal operation, + it is not recommended because it looks ugly on some machines and + doesn't cooperate with an X server. You should normally say N here, + unless you want to debug such a crash. + config SYS_HAS_EARLY_PRINTK bool @@ -1066,21 +1069,6 @@ config CPU_LOONGSON2E The Loongson 2E processor implements the MIPS III instruction set with many extensions. - It has an internal FPGA northbridge, which is compatiable to - bonito64. - -config CPU_LOONGSON2F - bool "Loongson 2F" - depends on SYS_HAS_CPU_LOONGSON2F - select CPU_LOONGSON2 - help - The Loongson 2F processor implements the MIPS III instruction set - with many extensions. - - Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller - have a similar programming interface with FPGA northbridge used in - Loongson2E. - config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1306,16 +1294,6 @@ config CPU_CAVIUM_OCTEON endchoice -config SYS_SUPPORTS_ZBOOT - bool - select HAVE_KERNEL_GZIP - select HAVE_KERNEL_BZIP2 - select HAVE_KERNEL_LZMA - -config SYS_SUPPORTS_ZBOOT_UART16550 - bool - select SYS_SUPPORTS_ZBOOT - config CPU_LOONGSON2 bool select CPU_SUPPORTS_32BIT_KERNEL @@ -1325,12 +1303,6 @@ config CPU_LOONGSON2 config SYS_HAS_CPU_LOONGSON2E bool -config SYS_HAS_CPU_LOONGSON2F - bool - select CPU_SUPPORTS_CPUFREQ - select CPU_SUPPORTS_ADDRWINCFG if 64BIT - select CPU_SUPPORTS_UNCACHED_ACCELERATED - config SYS_HAS_CPU_MIPS32_R1 bool @@ -1439,17 +1411,8 @@ config CPU_SUPPORTS_32BIT_KERNEL bool config CPU_SUPPORTS_64BIT_KERNEL bool -config CPU_SUPPORTS_CPUFREQ - bool -config CPU_SUPPORTS_ADDRWINCFG - bool config CPU_SUPPORTS_HUGEPAGES bool -config CPU_SUPPORTS_UNCACHED_ACCELERATED - bool -config MIPS_PGD_C0_CONTEXT - bool - default y if 64BIT && CPU_MIPSR2 # # Set to y for ptrace access to watch registers. @@ -2061,6 +2024,15 @@ config STACKTRACE_SUPPORT source "init/Kconfig" +config PROBE_INITRD_HEADER + bool "Probe initrd header created by addinitrd" + depends on BLK_DEV_INITRD + help + Probe initrd header at the last page of kernel image. + Say Y here if you are using arch/mips/boot/addinitrd.c to + add initrd or initramfs image to the kernel image. + Otherwise, say N. + source "kernel/Kconfig.freezer" menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)" @@ -2132,7 +2104,6 @@ config MMU config I8253 bool - select MIPS_EXTERNAL_TIMER config ZONE_DMA32 bool @@ -2209,8 +2180,6 @@ source "kernel/power/Kconfig" endmenu -source "arch/mips/kernel/cpufreq/Kconfig" - source "net/Kconfig" source "drivers/Kconfig" diff --git a/trunk/arch/mips/Kconfig.debug b/trunk/arch/mips/Kconfig.debug index d2b88a0be519..364ca8938807 100644 --- a/trunk/arch/mips/Kconfig.debug +++ b/trunk/arch/mips/Kconfig.debug @@ -6,66 +6,15 @@ config TRACE_IRQFLAGS_SUPPORT source "lib/Kconfig.debug" -config EARLY_PRINTK - bool "Early printk" if EMBEDDED - depends on SYS_HAS_EARLY_PRINTK - default y - help - This option enables special console drivers which allow the kernel - to print messages very early in the bootup process. - - This is useful for kernel debugging when your machine crashes very - early before the console code is initialized. For normal operation, - it is not recommended because it looks ugly on some machines and - doesn't cooperate with an X server. You should normally say N here, - unless you want to debug such a crash. - -config CMDLINE_BOOL - bool "Built-in kernel command line" - default n - help - For most systems, it is firmware or second stage bootloader that - by default specifies the kernel command line options. However, - it might be necessary or advantageous to either override the - default kernel command line or add a few extra options to it. - For such cases, this option allows you to hardcode your own - command line options directly into the kernel. For that, you - should choose 'Y' here, and fill in the extra boot arguments - in CONFIG_CMDLINE. - - The built-in options will be concatenated to the default command - line if CMDLINE_OVERRIDE is set to 'N'. Otherwise, the default - command line will be ignored and replaced by the built-in string. - - Most MIPS systems will normally expect 'N' here and rely upon - the command line from the firmware or the second-stage bootloader. - config CMDLINE string "Default kernel command string" - depends on CMDLINE_BOOL default "" help On some platforms, there is currently no way for the boot loader to - pass arguments to the kernel. For these platforms, and for the cases - when you want to add some extra options to the command line or ignore - the default command line, you can supply some command-line options at - build time by entering them here. In other cases you can specify - kernel args so that you don't have to set them up in board prom - initialization routines. - - For more information, see the CMDLINE_BOOL and CMDLINE_OVERRIDE - options. - -config CMDLINE_OVERRIDE - bool "Built-in command line overrides firware arguments" - default n - depends on CMDLINE_BOOL - help - By setting this option to 'Y' you will have your kernel ignore - command line arguments from firmware or second stage bootloader. - Instead, the built-in command line will be used exclusively. - - Normally, you will choose 'N' here. + pass arguments to the kernel. For these platforms, you can supply + some command-line options at build time by entering them here. In + other cases you can specify kernel args so that you don't have + to set them up in board prom initialization routines. config DEBUG_STACK_USAGE bool "Enable stack utilization instrumentation" diff --git a/trunk/arch/mips/Makefile b/trunk/arch/mips/Makefile index 1893efd43fca..77f5021218d3 100644 --- a/trunk/arch/mips/Makefile +++ b/trunk/arch/mips/Makefile @@ -48,16 +48,7 @@ ifneq ($(SUBARCH),$(ARCH)) endif endif -ifndef CONFIG_FUNCTION_TRACER cflags-y := -ffunction-sections -endif -ifdef CONFIG_FUNCTION_GRAPH_TRACER - ifndef KBUILD_MCOUNT_RA_ADDRESS - ifeq ($(call cc-option-yn,-mmcount-ra-address), y) - cflags-y += -mmcount-ra-address -DKBUILD_MCOUNT_RA_ADDRESS - endif - endif -endif cflags-y += $(call cc-option, -mno-check-zero-division) ifdef CONFIG_32BIT @@ -78,7 +69,6 @@ endif all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64) -all-$(CONFIG_SYS_SUPPORTS_ZBOOT)+= vmlinuz # # GCC uses -G 0 -mabicalls -fpic as default. We don't want PIC in the kernel @@ -134,8 +124,6 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=r4600) -cflags-$(CONFIG_CPU_LOONGSON2F) += \ - $(call cc-option,-march=loongson2f,-march=r4600) cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap @@ -336,7 +324,6 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/ cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ -mno-branch-likely load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 -load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000 # # MIPS Malta board @@ -344,7 +331,7 @@ load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000 core-$(CONFIG_MIPS_MALTA) += arch/mips/mti-malta/ cflags-$(CONFIG_MIPS_MALTA) += -I$(srctree)/arch/mips/include/asm/mach-malta load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 -all-$(CONFIG_MIPS_MALTA) := vmlinuz.bin +all-$(CONFIG_MIPS_MALTA) := vmlinux.bin # # MIPS SIM @@ -368,6 +355,13 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ cflags-$(CONFIG_PMC_YOSEMITE) += -I$(srctree)/arch/mips/include/asm/mach-yosemite load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 +# +# Basler eXcite +# +core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/ +cflags-$(CONFIG_BASLER_EXCITE) += -I$(srctree)/arch/mips/include/asm/mach-excite +load-$(CONFIG_BASLER_EXCITE) += 0x80100000 + # # LASAT platforms # @@ -446,13 +440,6 @@ cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/ load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000 -# -# Cisco PowerTV Platform -# -core-$(CONFIG_POWERTV) += arch/mips/powertv/ -cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv -load-$(CONFIG_POWERTV) += 0xffffffff90800000 - # # SGI IP22 (Indy/Indigo2) # @@ -594,7 +581,7 @@ load-$(CONFIG_SNI_RM) += 0xffffffff80600000 else load-$(CONFIG_SNI_RM) += 0xffffffff80030000 endif -all-$(CONFIG_SNI_RM) := vmlinuz.ecoff +all-$(CONFIG_SNI_RM) := vmlinux.ecoff # # Common TXx9 @@ -712,23 +699,9 @@ vmlinux.64: vmlinux $(OBJCOPY) -O $(64bit-bfd) $(OBJCOPYFLAGS) $< $@ makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1) -makezboot =$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \ - VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $(1) all: $(all-y) -vmlinuz: vmlinux FORCE - +@$(call makezboot,$@) - -vmlinuz.bin: vmlinux - +@$(call makezboot,$@) - -vmlinuz.ecoff: vmlinux - +@$(call makezboot,$@) - -vmlinuz.srec: vmlinux - +@$(call makezboot,$@) - vmlinux.bin: $(vmlinux-32) +@$(call makeboot,$@) @@ -753,13 +726,11 @@ endif install: $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE) - $(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE) $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE) $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE) archclean: @$(MAKE) $(clean)=arch/mips/boot - @$(MAKE) $(clean)=arch/mips/boot/compressed @$(MAKE) $(clean)=arch/mips/lasat define archhelp @@ -767,18 +738,10 @@ define archhelp echo ' vmlinux.ecoff - ECOFF boot image' echo ' vmlinux.bin - Raw binary boot image' echo ' vmlinux.srec - SREC boot image' - echo ' vmlinuz - Compressed boot(zboot) image' - echo ' vmlinuz.ecoff - ECOFF zboot image' - echo ' vmlinuz.bin - Raw binary zboot image' - echo ' vmlinuz.srec - SREC zboot image' echo echo ' These will be default as apropriate for a configured platform.' endef CLEAN_FILES += vmlinux.32 \ vmlinux.64 \ - vmlinux.ecoff \ - vmlinuz \ - vmlinuz.ecoff \ - vmlinuz.bin \ - vmlinuz.srec + vmlinux.ecoff diff --git a/trunk/arch/mips/ar7/platform.c b/trunk/arch/mips/ar7/platform.c index 85169c08d8dc..835f3f0319ca 100644 --- a/trunk/arch/mips/ar7/platform.c +++ b/trunk/arch/mips/ar7/platform.c @@ -505,7 +505,7 @@ static int __init ar7_register_devices(void) int res; u32 *bootcr, val; #ifdef CONFIG_SERIAL_8250 - static struct uart_port uart_port[2] __initdata; + static struct uart_port uart_port[2]; memset(uart_port, 0, sizeof(struct uart_port) * 2); diff --git a/trunk/arch/mips/basler/excite/Kconfig b/trunk/arch/mips/basler/excite/Kconfig new file mode 100644 index 000000000000..ba506075608b --- /dev/null +++ b/trunk/arch/mips/basler/excite/Kconfig @@ -0,0 +1,9 @@ +config BASLER_EXCITE_PROTOTYPE + bool "Support for pre-release units" + depends on BASLER_EXCITE + default n + help + Pre-series (prototype) units are different from later ones in + some ways. Select this option if you have one of these. Please + note that a kernel built with this option selected will not be + able to run on normal units. diff --git a/trunk/arch/mips/basler/excite/Makefile b/trunk/arch/mips/basler/excite/Makefile new file mode 100644 index 000000000000..cff29cf46d03 --- /dev/null +++ b/trunk/arch/mips/basler/excite/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for Basler eXcite +# + +obj-$(CONFIG_BASLER_EXCITE) += excite_irq.o excite_prom.o excite_setup.o \ + excite_device.o excite_procfs.o + +obj-m += excite_iodev.o diff --git a/trunk/arch/mips/basler/excite/excite_device.c b/trunk/arch/mips/basler/excite/excite_device.c new file mode 100644 index 000000000000..e00bc2d7f301 --- /dev/null +++ b/trunk/arch/mips/basler/excite/excite_device.c @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "excite_iodev.h" + +#define RM9K_GE_UNIT 0 +#define XICAP_UNIT 0 +#define NAND_UNIT 0 + +#define DLL_TIMEOUT 3 /* seconds */ + + +#define RINIT(__start__, __end__, __name__, __parent__) { \ + .name = __name__ "_0", \ + .start = (__start__), \ + .end = (__end__), \ + .flags = 0, \ + .parent = (__parent__) \ +} + +#define RINIT_IRQ(__irq__, __name__) { \ + .name = __name__ "_0", \ + .start = (__irq__), \ + .end = (__irq__), \ + .flags = IORESOURCE_IRQ, \ + .parent = NULL \ +} + + + +enum { + slice_xicap, + slice_eth +}; + + + +static struct resource + excite_ctr_resource __maybe_unused = { + .name = "GPI counters", + .start = 0, + .end = 5, + .flags = 0, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_gpislice_resource __maybe_unused = { + .name = "GPI slices", + .start = 0, + .end = 1, + .flags = 0, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_mdio_channel_resource __maybe_unused = { + .name = "MDIO channels", + .start = 0, + .end = 1, + .flags = 0, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_fifomem_resource __maybe_unused = { + .name = "FIFO memory", + .start = 0, + .end = 767, + .flags = 0, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_scram_resource __maybe_unused = { + .name = "Scratch RAM", + .start = EXCITE_PHYS_SCRAM, + .end = EXCITE_PHYS_SCRAM + EXCITE_SIZE_SCRAM - 1, + .flags = IORESOURCE_MEM, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_fpga_resource __maybe_unused = { + .name = "System FPGA", + .start = EXCITE_PHYS_FPGA, + .end = EXCITE_PHYS_FPGA + EXCITE_SIZE_FPGA - 1, + .flags = IORESOURCE_MEM, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_nand_resource __maybe_unused = { + .name = "NAND flash control", + .start = EXCITE_PHYS_NAND, + .end = EXCITE_PHYS_NAND + EXCITE_SIZE_NAND - 1, + .flags = IORESOURCE_MEM, + .parent = NULL, + .sibling = NULL, + .child = NULL + }, + excite_titan_resource __maybe_unused = { + .name = "TITAN registers", + .start = EXCITE_PHYS_TITAN, + .end = EXCITE_PHYS_TITAN + EXCITE_SIZE_TITAN - 1, + .flags = IORESOURCE_MEM, + .parent = NULL, + .sibling = NULL, + .child = NULL + }; + + + +static void adjust_resources(struct resource *res, unsigned int n) +{ + struct resource *p; + const unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM + | IORESOURCE_IRQ | IORESOURCE_DMA; + + for (p = res; p < res + n; p++) { + const struct resource * const parent = p->parent; + if (parent) { + p->start += parent->start; + p->end += parent->start; + p->flags = parent->flags & mask; + } + } +} + + + +#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) +static struct resource xicap_rsrc[] = { + RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource), + RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource), + RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource), + RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource), + RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource), + RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource), + RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource), + RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource), + RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ) +}; + +static struct platform_device xicap_pdev = { + .name = XICAP_NAME, + .id = XICAP_UNIT, + .num_resources = ARRAY_SIZE(xicap_rsrc), + .resource = xicap_rsrc +}; + +/* + * Create a platform device for the GPI port that receives the + * image data from the embedded camera. + */ +static int __init xicap_devinit(void) +{ + unsigned long tend; + u32 reg; + int retval; + + adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc)); + + /* Power up the slice and configure it. */ + reg = titan_readl(CPTC1R); + reg &= ~(0x11100 << slice_xicap); + titan_writel(reg, CPTC1R); + + /* Enable slice & DLL. */ + reg= titan_readl(CPRR); + reg &= ~(0x00030003 << (slice_xicap * 2)); + titan_writel(reg, CPRR); + + /* Wait for DLLs to lock */ + tend = jiffies + DLL_TIMEOUT * HZ; + while (time_before(jiffies, tend)) { + if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4)))) + break; + yield(); + } + + if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) { + printk(KERN_ERR "%s: DLL not locked after %u seconds\n", + xicap_pdev.name, DLL_TIMEOUT); + retval = -ETIME; + } else { + /* Register platform device */ + retval = platform_device_register(&xicap_pdev); + } + + return retval; +} + +device_initcall(xicap_devinit); +#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */ + + + +#if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) +static struct resource wdt_rsrc[] = { + RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource), + RINIT(0x0084, 0x008f, WDT_RESOURCE_REGS, &excite_titan_resource), + RINIT_IRQ(TITAN_IRQ, WDT_RESOURCE_IRQ) +}; + +static struct platform_device wdt_pdev = { + .name = WDT_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(wdt_rsrc), + .resource = wdt_rsrc +}; + +/* + * Create a platform device for the GPI port that receives the + * image data from the embedded camera. + */ +static int __init wdt_devinit(void) +{ + adjust_resources(wdt_rsrc, ARRAY_SIZE(wdt_rsrc)); + return platform_device_register(&wdt_pdev); +} + +device_initcall(wdt_devinit); +#endif /* defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) */ + + + +static struct resource excite_nandflash_rsrc[] = { + RINIT(0x2000, 0x201f, EXCITE_NANDFLASH_RESOURCE_REGS, &excite_nand_resource) +}; + +static struct platform_device excite_nandflash_pdev = { + .name = "excite_nand", + .id = NAND_UNIT, + .num_resources = ARRAY_SIZE(excite_nandflash_rsrc), + .resource = excite_nandflash_rsrc +}; + +/* + * Create a platform device for the access to the nand-flash + * port + */ +static int __init excite_nandflash_devinit(void) +{ + adjust_resources(excite_nandflash_rsrc, ARRAY_SIZE(excite_nandflash_rsrc)); + + /* nothing to be done here */ + + /* Register platform device */ + return platform_device_register(&excite_nandflash_pdev); +} + +device_initcall(excite_nandflash_devinit); + + + +static struct resource iodev_rsrc[] = { + RINIT_IRQ(FPGA1_IRQ, IODEV_RESOURCE_IRQ) +}; + +static struct platform_device io_pdev = { + .name = IODEV_NAME, + .id = -1, + .num_resources = ARRAY_SIZE(iodev_rsrc), + .resource = iodev_rsrc +}; + +/* + * Create a platform device for the external I/O ports. + */ +static int __init io_devinit(void) +{ + adjust_resources(iodev_rsrc, ARRAY_SIZE(iodev_rsrc)); + return platform_device_register(&io_pdev); +} + +device_initcall(io_devinit); + + + + +#if defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) +static struct resource rm9k_ge_rsrc[] = { + RINIT(0x2200, 0x27ff, RM9K_GE_RESOURCE_MAC, &excite_titan_resource), + RINIT(0x1800, 0x1fff, RM9K_GE_RESOURCE_MSTAT, &excite_titan_resource), + RINIT(0x2000, 0x212f, RM9K_GE_RESOURCE_PKTPROC, &excite_titan_resource), + RINIT(0x5140, 0x5227, RM9K_GE_RESOURCE_XDMA, &excite_titan_resource), + RINIT(0x4870, 0x489f, RM9K_GE_RESOURCE_FIFO_RX, &excite_titan_resource), + RINIT(0x494c, 0x4957, RM9K_GE_RESOURCE_FIFO_TX, &excite_titan_resource), + RINIT(0x0000, 0x007f, RM9K_GE_RESOURCE_FIFOMEM_RX, &excite_fifomem_resource), + RINIT(0x0080, 0x00ff, RM9K_GE_RESOURCE_FIFOMEM_TX, &excite_fifomem_resource), + RINIT(0x0180, 0x019f, RM9K_GE_RESOURCE_PHY, &excite_titan_resource), + RINIT(0x0000, 0x03ff, RM9K_GE_RESOURCE_DMADESC_RX, &excite_scram_resource), + RINIT(0x0400, 0x07ff, RM9K_GE_RESOURCE_DMADESC_TX, &excite_scram_resource), + RINIT(slice_eth, slice_eth, RM9K_GE_RESOURCE_GPI_SLICE, &excite_gpislice_resource), + RINIT(0, 0, RM9K_GE_RESOURCE_MDIO_CHANNEL, &excite_mdio_channel_resource), + RINIT_IRQ(TITAN_IRQ, RM9K_GE_RESOURCE_IRQ_MAIN), + RINIT_IRQ(PHY_IRQ, RM9K_GE_RESOURCE_IRQ_PHY) +}; + +static struct platform_device rm9k_ge_pdev = { + .name = RM9K_GE_NAME, + .id = RM9K_GE_UNIT, + .num_resources = ARRAY_SIZE(rm9k_ge_rsrc), + .resource = rm9k_ge_rsrc +}; + + + +/* + * Create a platform device for the Ethernet port. + */ +static int __init rm9k_ge_devinit(void) +{ + u32 reg; + + adjust_resources(rm9k_ge_rsrc, ARRAY_SIZE(rm9k_ge_rsrc)); + + /* Power up the slice and configure it. */ + reg = titan_readl(CPTC1R); + reg &= ~(0x11000 << slice_eth); + reg |= 0x100 << slice_eth; + titan_writel(reg, CPTC1R); + + /* Take the MAC out of reset, reset the DLLs. */ + reg = titan_readl(CPRR); + reg &= ~(0x00030000 << (slice_eth * 2)); + reg |= 0x3 << (slice_eth * 2); + titan_writel(reg, CPRR); + + return platform_device_register(&rm9k_ge_pdev); +} + +device_initcall(rm9k_ge_devinit); +#endif /* defined(CONFIG_RM9K_GE) || defined(CONFIG_RM9K_GE_MODULE) */ + + + +static int __init excite_setup_devs(void) +{ + int res; + u32 reg; + + /* Enable xdma and fifo interrupts */ + reg = titan_readl(0x0050); + titan_writel(reg | 0x18000000, 0x0050); + + res = request_resource(&iomem_resource, &excite_titan_resource); + if (res) + return res; + res = request_resource(&iomem_resource, &excite_scram_resource); + if (res) + return res; + res = request_resource(&iomem_resource, &excite_fpga_resource); + if (res) + return res; + res = request_resource(&iomem_resource, &excite_nand_resource); + if (res) + return res; + excite_fpga_resource.flags = excite_fpga_resource.parent->flags & + ( IORESOURCE_IO | IORESOURCE_MEM + | IORESOURCE_IRQ | IORESOURCE_DMA); + excite_nand_resource.flags = excite_nand_resource.parent->flags & + ( IORESOURCE_IO | IORESOURCE_MEM + | IORESOURCE_IRQ | IORESOURCE_DMA); + + return 0; +} + +arch_initcall(excite_setup_devs); + diff --git a/trunk/arch/mips/basler/excite/excite_iodev.c b/trunk/arch/mips/basler/excite/excite_iodev.c new file mode 100644 index 000000000000..938b1d0b7652 --- /dev/null +++ b/trunk/arch/mips/basler/excite/excite_iodev.c @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2005 by Basler Vision Technologies AG + * Author: Thomas Koeller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "excite_iodev.h" + + + +static const struct resource *iodev_get_resource(struct platform_device *, const char *, unsigned int); +static int __init iodev_probe(struct platform_device *); +static int __exit iodev_remove(struct platform_device *); +static int iodev_open(struct inode *, struct file *); +static int iodev_release(struct inode *, struct file *); +static ssize_t iodev_read(struct file *, char __user *, size_t s, loff_t *); +static unsigned int iodev_poll(struct file *, struct poll_table_struct *); +static irqreturn_t iodev_irqhdl(int, void *); + + + +static const char iodev_name[] = "iodev"; +static unsigned int iodev_irq; +static DECLARE_WAIT_QUEUE_HEAD(wq); + + + +static const struct file_operations fops = +{ + .owner = THIS_MODULE, + .open = iodev_open, + .release = iodev_release, + .read = iodev_read, + .poll = iodev_poll +}; + +static struct miscdevice miscdev = +{ + .minor = MISC_DYNAMIC_MINOR, + .name = iodev_name, + .fops = &fops +}; + +static struct platform_driver iodev_driver = { + .driver = { + .name = iodev_name, + .owner = THIS_MODULE, + }, + .probe = iodev_probe, + .remove = __devexit_p(iodev_remove), +}; + + + +static const struct resource * +iodev_get_resource(struct platform_device *pdv, const char *name, + unsigned int type) +{ + char buf[80]; + if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf) + return NULL; + return platform_get_resource_byname(pdv, type, buf); +} + + + +/* No hotplugging on the platform bus - use __init */ +static int __init iodev_probe(struct platform_device *dev) +{ + const struct resource * const ri = + iodev_get_resource(dev, IODEV_RESOURCE_IRQ, IORESOURCE_IRQ); + + if (unlikely(!ri)) + return -ENXIO; + + iodev_irq = ri->start; + return misc_register(&miscdev); +} + + + +static int __exit iodev_remove(struct platform_device *dev) +{ + return misc_deregister(&miscdev); +} + +static int iodev_open(struct inode *i, struct file *f) +{ + int ret; + + ret = request_irq(iodev_irq, iodev_irqhdl, IRQF_DISABLED, + iodev_name, &miscdev); + + return ret; +} + +static int iodev_release(struct inode *i, struct file *f) +{ + free_irq(iodev_irq, &miscdev); + return 0; +} + + + + +static ssize_t +iodev_read(struct file *f, char __user *d, size_t s, loff_t *o) +{ + ssize_t ret; + DEFINE_WAIT(w); + + prepare_to_wait(&wq, &w, TASK_INTERRUPTIBLE); + if (!signal_pending(current)) + schedule(); + ret = signal_pending(current) ? -ERESTARTSYS : 0; + finish_wait(&wq, &w); + return ret; +} + + +static unsigned int iodev_poll(struct file *f, struct poll_table_struct *p) +{ + poll_wait(f, &wq, p); + return POLLOUT | POLLWRNORM; +} + +static irqreturn_t iodev_irqhdl(int irq, void *ctxt) +{ + wake_up(&wq); + + return IRQ_HANDLED; +} + +static int __init iodev_init_module(void) +{ + return platform_driver_register(&iodev_driver); +} + + + +static void __exit iodev_cleanup_module(void) +{ + platform_driver_unregister(&iodev_driver); +} + +module_init(iodev_init_module); +module_exit(iodev_cleanup_module); + + + +MODULE_AUTHOR("Thomas Koeller "); +MODULE_DESCRIPTION("Basler eXcite i/o interrupt handler"); +MODULE_VERSION("0.0"); +MODULE_LICENSE("GPL"); diff --git a/trunk/arch/mips/basler/excite/excite_iodev.h b/trunk/arch/mips/basler/excite/excite_iodev.h new file mode 100644 index 000000000000..cbfbb5d2ee62 --- /dev/null +++ b/trunk/arch/mips/basler/excite/excite_iodev.h @@ -0,0 +1,10 @@ +#ifndef __EXCITE_IODEV_H__ +#define __EXCITE_IODEV_H__ + +/* Device name */ +#define IODEV_NAME "iodev" + +/* Resource names */ +#define IODEV_RESOURCE_IRQ "excite_iodev_irq" + +#endif /* __EXCITE_IODEV_H__ */ diff --git a/trunk/arch/mips/basler/excite/excite_irq.c b/trunk/arch/mips/basler/excite/excite_irq.c new file mode 100644 index 000000000000..934e0a6b1011 --- /dev/null +++ b/trunk/arch/mips/basler/excite/excite_irq.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) by Basler Vision Technologies AG + * Author: Thomas Koeller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern asmlinkage void excite_handle_int(void); + +/* + * Initialize the interrupt handler + */ +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + rm7k_cpu_irq_init(); + rm9k_cpu_irq_init(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + const u32 + interrupts = read_c0_cause() >> 8, + mask = ((read_c0_status() >> 8) & 0x000000ff) | + (read_c0_intcontrol() & 0x0000ff00), + pending = interrupts & mask; + u32 msgintflags, msgintmask, msgint; + + /* process timer interrupt */ + if (pending & (1 << TIMER_IRQ)) { + do_IRQ(TIMER_IRQ); + return; + } + + /* Process PCI interrupts */ +#if USB_IRQ < 10 + msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20)); + if ((pending & (1 << USB_IRQ)) && msgint) { +#else + if (pending & (1 << USB_IRQ)) { +#endif + do_IRQ(USB_IRQ); + return; + } + + /* Process TITAN interrupts */ + msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20)); + if ((pending & (1 << TITAN_IRQ)) && msgint) { + ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10)); + do_IRQ(TITAN_IRQ); + return; + } + + /* Process FPGA line #0 interrupts */ + msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20)); + if ((pending & (1 << FPGA0_IRQ)) && msgint) { + do_IRQ(FPGA0_IRQ); + return; + } + + /* Process FPGA line #1 interrupts */ + msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20)); + if ((pending & (1 << FPGA1_IRQ)) && msgint) { + do_IRQ(FPGA1_IRQ); + return; + } + + /* Process PHY interrupts */ + msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10)); + msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10)); + msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20)); + if ((pending & (1 << PHY_IRQ)) && msgint) { + do_IRQ(PHY_IRQ); + return; + } + + /* Process spurious interrupts */ + spurious_interrupt(); +} diff --git a/trunk/arch/mips/basler/excite/excite_procfs.c b/trunk/arch/mips/basler/excite/excite_procfs.c new file mode 100644 index 000000000000..08923e6825b5 --- /dev/null +++ b/trunk/arch/mips/basler/excite/excite_procfs.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2004, 2005 by Basler Vision Technologies AG + * Author: Thomas Koeller + * + * Procfs support for Basler eXcite + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static int excite_unit_id_proc_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%06x", unit_id); + return 0; +} + +static int excite_unit_id_proc_open(struct inode *inode, struct file *file) +{ + return single_open(file, excite_unit_id_proc_show, NULL); +} + +static const struct file_operations excite_unit_id_proc_fops = { + .owner = THIS_MODULE, + .open = excite_unit_id_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int +excite_bootrom_read(char *page, char **start, off_t off, int count, + int *eof, void *data) +{ + void __iomem * src; + + if (off >= EXCITE_SIZE_BOOTROM) { + *eof = 1; + return 0; + } + + if ((off + count) > EXCITE_SIZE_BOOTROM) + count = EXCITE_SIZE_BOOTROM - off; + + src = ioremap(EXCITE_PHYS_BOOTROM + off, count); + if (src) { + memcpy_fromio(page, src, count); + iounmap(src); + *start = page; + } else { + count = -ENOMEM; + } + + return count; +} + +void excite_procfs_init(void) +{ + /* Create & populate /proc/excite */ + struct proc_dir_entry * const pdir = proc_mkdir("excite", NULL); + if (pdir) { + struct proc_dir_entry * e; + + e = proc_create("unit_id", S_IRUGO, pdir, + &excite_unit_id_proc_fops); + if (e) e->size = 6; + + e = create_proc_read_entry("bootrom", S_IRUGO, pdir, + excite_bootrom_read, NULL); + if (e) e->size = EXCITE_SIZE_BOOTROM; + } +} diff --git a/trunk/arch/mips/basler/excite/excite_prom.c b/trunk/arch/mips/basler/excite/excite_prom.c new file mode 100644 index 000000000000..68d8bc597e34 --- /dev/null +++ b/trunk/arch/mips/basler/excite/excite_prom.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2004, 2005 by Thomas Koeller (thomas.koeller@baslerweb.com) + * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and + * Manish Lachwani. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* This struct is used by Redboot to pass arguments to the kernel */ +typedef struct +{ + char *name; + char *val; +} t_env_var; + +struct parmblock { + t_env_var memsize; + t_env_var modetty0; + t_env_var ethaddr; + t_env_var env_end; + char *argv[2]; + char text[0]; +}; + +static unsigned int prom_argc; +static const char ** prom_argv; +static const t_env_var * prom_env; + +static void prom_halt(void) __attribute__((noreturn)); +static void prom_exit(void) __attribute__((noreturn)); + + + +const char *get_system_type(void) +{ + return "Basler eXcite"; +} + +/* + * Halt the system + */ +static void prom_halt(void) +{ + printk(KERN_NOTICE "\n** System halted.\n"); + while (1) + asm volatile ( + "\t.set\tmips3\n" + "\twait\n" + "\t.set\tmips0\n" + ); +} + +/* + * Reset the CPU and re-enter Redboot + */ +static void prom_exit(void) +{ + unsigned int i; + volatile unsigned char * const flg = + (volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_DPR); + + /* Clear the watchdog reset flag, set the reboot flag */ + *flg &= ~0x01; + *flg |= 0x80; + + for (i = 0; i < 10; i++) { + *(volatile unsigned char *) (EXCITE_ADDR_FPGA + EXCITE_FPGA_SYSCTL) = 0x02; + iob(); + mdelay(1000); + } + + printk(KERN_NOTICE "Reset failed\n"); + prom_halt(); +} + +static const char __init *prom_getenv(char *name) +{ + const t_env_var * p; + for (p = prom_env; p->name != NULL; p++) + if(strcmp(name, p->name) == 0) + break; + return p->val; +} + +/* + * Init routine which accepts the variables from Redboot + */ +void __init prom_init(void) +{ + const struct parmblock * const pb = (struct parmblock *) fw_arg2; + + prom_argc = fw_arg0; + prom_argv = (const char **) fw_arg1; + prom_env = &pb->memsize; + + /* Callbacks for halt, restart */ + _machine_restart = (void (*)(char *)) prom_exit; + _machine_halt = prom_halt; + +#ifdef CONFIG_32BIT + /* copy command line */ + strcpy(arcs_cmdline, prom_argv[1]); + memsize = simple_strtol(prom_getenv("memsize"), NULL, 16); + strcpy(modetty, prom_getenv("modetty0")); +#endif /* CONFIG_32BIT */ + +#ifdef CONFIG_64BIT +# error 64 bit support not implemented +#endif /* CONFIG_64BIT */ +} + +/* This is called from free_initmem(), so we need to provide it */ +void __init prom_free_prom_memory(void) +{ + /* Nothing to do */ +} diff --git a/trunk/arch/mips/basler/excite/excite_setup.c b/trunk/arch/mips/basler/excite/excite_setup.c new file mode 100644 index 000000000000..d66b3b8edf2a --- /dev/null +++ b/trunk/arch/mips/basler/excite/excite_setup.c @@ -0,0 +1,302 @@ +/* + * Copyright (C) 2004, 2005 by Basler Vision Technologies AG + * Author: Thomas Koeller + * Based on the PMC-Sierra Yosemite board support by Ralf Baechle and + * Manish Lachwani. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TITAN_UART_CLK 25000000 + +#if 1 +/* normal serial port assignment */ +#define REGBASE_SER0 0x0208 +#define REGBASE_SER1 0x0238 +#define MASK_SER0 0x1 +#define MASK_SER1 0x2 +#else +/* serial ports swapped */ +#define REGBASE_SER0 0x0238 +#define REGBASE_SER1 0x0208 +#define MASK_SER0 0x2 +#define MASK_SER1 0x1 +#endif + +unsigned long memsize; +char modetty[30]; +unsigned int titan_irq = TITAN_IRQ; +static void __iomem * ctl_regs; +u32 unit_id; + +volatile void __iomem * const ocd_base = (void *) (EXCITE_ADDR_OCD); +volatile void __iomem * const titan_base = (void *) (EXCITE_ADDR_TITAN); + +/* Protect access to shared GPI registers */ +DEFINE_SPINLOCK(titan_lock); +int titan_irqflags; + + +/* + * The eXcite platform uses the alternate timer interrupt + * + * Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how + * to handle the alternate timer interrupt of the RM9000. + */ +void __init plat_time_init(void) +{ + const u32 modebit5 = ocd_readl(0x00e4); + unsigned int mult = ((modebit5 >> 11) & 0x1f) + 2; + unsigned int div = ((modebit5 >> 16) & 0x1f) + 2; + + if (div == 33) + div = 1; + mips_hpt_frequency = EXCITE_CPU_EXT_CLOCK * mult / div / 2; +} + +static int __init excite_init_console(void) +{ +#if defined(CONFIG_SERIAL_8250) + static __initdata char serr[] = + KERN_ERR "Serial port #%u setup failed\n"; + struct uart_port up; + + /* Take the DUART out of reset */ + titan_writel(0x00ff1cff, CPRR); + +#if (CONFIG_SERIAL_8250_NR_UARTS > 1) + /* Enable both ports */ + titan_writel(MASK_SER0 | MASK_SER1, UACFG); +#else + /* Enable port #0 only */ + titan_writel(MASK_SER0, UACFG); +#endif + + /* + * Set up serial port #0. Do not use autodetection; the result is + * not what we want. + */ + memset(&up, 0, sizeof(up)); + up.membase = (char *) titan_addr(REGBASE_SER0); + up.irq = TITAN_IRQ; + up.uartclk = TITAN_UART_CLK; + up.regshift = 0; + up.iotype = UPIO_RM9000; + up.type = PORT_RM9000; + up.flags = UPF_SHARE_IRQ; + up.line = 0; + if (early_serial_setup(&up)) + printk(serr, up.line); + +#if CONFIG_SERIAL_8250_NR_UARTS > 1 + /* And now for port #1. */ + up.membase = (char *) titan_addr(REGBASE_SER1); + up.line = 1; + if (early_serial_setup(&up)) + printk(serr, up.line); +#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */ +#else + /* Leave the DUART in reset */ + titan_writel(0x00ff3cff, CPRR); +#endif /* defined(CONFIG_SERIAL_8250) */ + + return 0; +} + +static int __init excite_platform_init(void) +{ + unsigned int i; + unsigned char buf[3]; + u8 reg; + void __iomem * dpr; + + /* BIU buffer allocations */ + ocd_writel(8, CPURSLMT); /* CPU */ + titan_writel(4, CPGRWL); /* GPI / Ethernet */ + + /* Map control registers located in FPGA */ + ctl_regs = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_SYSCTL, 16); + if (!ctl_regs) + panic("eXcite: failed to map platform control registers\n"); + memcpy_fromio(buf, ctl_regs + 2, ARRAY_SIZE(buf)); + unit_id = buf[0] | (buf[1] << 8) | (buf[2] << 16); + + /* Clear the reboot flag */ + dpr = ioremap_nocache(EXCITE_PHYS_FPGA + EXCITE_FPGA_DPR, 1); + reg = __raw_readb(dpr); + __raw_writeb(reg & 0x7f, dpr); + iounmap(dpr); + + /* Interrupt controller setup */ + for (i = INTP0Status0; i < INTP0Status0 + 0x80; i += 0x10) { + ocd_writel(0x00000000, i + 0x04); + ocd_writel(0xffffffff, i + 0x0c); + } + ocd_writel(0x2, NMICONFIG); + + ocd_writel(0x1 << (TITAN_MSGINT % 0x20), + INTP0Mask0 + (0x10 * (TITAN_MSGINT / 0x20))); + ocd_writel((0x1 << (FPGA0_MSGINT % 0x20)) + | ocd_readl(INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))), + INTP0Mask0 + (0x10 * (FPGA0_MSGINT / 0x20))); + ocd_writel((0x1 << (FPGA1_MSGINT % 0x20)) + | ocd_readl(INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))), + INTP0Mask0 + (0x10 * (FPGA1_MSGINT / 0x20))); + ocd_writel((0x1 << (PHY_MSGINT % 0x20)) + | ocd_readl(INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))), + INTP0Mask0 + (0x10 * (PHY_MSGINT / 0x20))); +#if USB_IRQ < 10 + ocd_writel((0x1 << (USB_MSGINT % 0x20)) + | ocd_readl(INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))), + INTP0Mask0 + (0x10 * (USB_MSGINT / 0x20))); +#endif + /* Enable the packet FIFO, XDMA and XDMA arbiter */ + titan_writel(0x00ff18ff, CPRR); + + /* + * Set up the PADMUX. Power down all ethernet slices, + * they will be powered up and configured at device startup. + */ + titan_writel(0x00878206, CPTC1R); + titan_writel(0x00001100, CPTC0R); /* latch PADMUX, enable WCIMODE */ + + /* Reset and enable the FIFO block */ + titan_writel(0x00000001, SDRXFCIE); + titan_writel(0x00000001, SDTXFCIE); + titan_writel(0x00000100, SDRXFCIE); + titan_writel(0x00000000, SDTXFCIE); + + /* + * Initialize the common interrupt shared by all components of + * the GPI/Ethernet subsystem. + */ + titan_writel((EXCITE_PHYS_OCD >> 12), CPCFG0); + titan_writel(TITAN_MSGINT, CPCFG1); + + /* + * XDMA configuration. + * In order for the XDMA to be sharable among multiple drivers, + * the setup must be done here in the platform. The reason is that + * this setup can only be done while the XDMA is in reset. If this + * were done in a driver, it would interrupt all other drivers + * using the XDMA. + */ + titan_writel(0x80021dff, GXCFG); /* XDMA reset */ + titan_writel(0x00000000, CPXCISRA); + titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */ +#if defined(CONFIG_HIGHMEM) +# error change for HIGHMEM support! +#else + titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */ +#endif + titan_writel(0, GXDMA_DESCADR); + + for (i = 0x5040; i <= 0x5300; i += 0x0040) + titan_writel(0x80080000, i); /* reset channel */ + + titan_writel((0x1 << 29) /* no sparse tx descr. */ + | (0x1 << 28) /* no sparse rx descr. */ + | (0x1 << 23) | (0x1 << 24) /* descriptor coherency */ + | (0x1 << 21) | (0x1 << 22) /* data coherency */ + | (0x1 << 17) + | 0x1dff, + GXCFG); + +#if defined(CONFIG_SMP) +# error No SMP support +#else + /* All interrupts go to core #0 only. */ + titan_writel(0x1f007fff, CPDST0A); + titan_writel(0x00000000, CPDST0B); + titan_writel(0x0000ff3f, CPDST1A); + titan_writel(0x00000000, CPDST1B); + titan_writel(0x00ffffff, CPXDSTA); + titan_writel(0x00000000, CPXDSTB); +#endif + + /* Enable DUART interrupts, disable everything else. */ + titan_writel(0x04000000, CPGIG0ER); + titan_writel(0x000000c0, CPGIG1ER); + + excite_procfs_init(); + return 0; +} + +void __init plat_mem_setup(void) +{ + volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000; + + /* Announce RAM to system */ + add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); + + /* Set up the peripheral address map */ + *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0; + *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0; + *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0; + *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0; + wmb(); + *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4; + wmb(); + + ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5); + ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5); + ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13); + ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13); + + /* Local bus slot #0 */ + ocd_writel(0x00040510, LDP0); + ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9); + ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9); + + /* Local bus slot #2 */ + ocd_writel(0x00000330, LDP2); + ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11); + ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11); + + /* Local bus slot #3 */ + ocd_writel(0x00123413, LDP3); + ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12); + ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12); +} + + + +console_initcall(excite_init_console); +arch_initcall(excite_platform_init); + +EXPORT_SYMBOL(titan_lock); +EXPORT_SYMBOL(titan_irqflags); +EXPORT_SYMBOL(titan_irq); +EXPORT_SYMBOL(ocd_base); +EXPORT_SYMBOL(titan_base); diff --git a/trunk/arch/mips/bcm47xx/prom.c b/trunk/arch/mips/bcm47xx/prom.c index c51405e57921..fb284c3b2cff 100644 --- a/trunk/arch/mips/bcm47xx/prom.c +++ b/trunk/arch/mips/bcm47xx/prom.c @@ -100,11 +100,11 @@ static __init void prom_init_console(void) static __init void prom_init_cmdline(void) { - static char buf[COMMAND_LINE_SIZE] __initdata; + static char buf[CL_SIZE] __initdata; /* Get the kernel command line from CFE */ - if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) { - buf[COMMAND_LINE_SIZE - 1] = 0; + if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) { + buf[CL_SIZE-1] = 0; strcpy(arcs_cmdline, buf); } @@ -112,13 +112,13 @@ static __init void prom_init_cmdline(void) * as CFE is not available anymore later in the boot process. */ if ((strstr(arcs_cmdline, "console=")) == NULL) { /* Try to read the default serial port used by CFE */ - if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0) + if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0) || (strncmp("uart", buf, 4))) /* Default to uart0 */ strcpy(buf, "uart0"); /* Compute the new command line */ - snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200", + snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200", arcs_cmdline, buf[4]); } } diff --git a/trunk/arch/mips/boot/Makefile b/trunk/arch/mips/boot/Makefile index 094bc84765a3..2a209d74f0b4 100644 --- a/trunk/arch/mips/boot/Makefile +++ b/trunk/arch/mips/boot/Makefile @@ -25,7 +25,7 @@ strip-flags = $(addprefix --remove-section=,$(drop-sections)) VMLINUX = vmlinux -all: vmlinux.ecoff vmlinux.srec +all: vmlinux.ecoff vmlinux.srec addinitrd vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS) @@ -39,7 +39,11 @@ vmlinux.bin: $(VMLINUX) vmlinux.srec: $(VMLINUX) $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $(obj)/vmlinux.srec -clean-files += elf2ecoff \ +$(obj)/addinitrd: $(obj)/addinitrd.c + $(HOSTCC) -o $@ $^ + +clean-files += addinitrd \ + elf2ecoff \ vmlinux.bin \ vmlinux.ecoff \ vmlinux.srec diff --git a/trunk/arch/mips/boot/addinitrd.c b/trunk/arch/mips/boot/addinitrd.c new file mode 100644 index 000000000000..b5b3febc10cc --- /dev/null +++ b/trunk/arch/mips/boot/addinitrd.c @@ -0,0 +1,131 @@ +/* + * addinitrd - program to add a initrd image to an ecoff kernel + * + * (C) 1999 Thomas Bogendoerfer + * minor modifications, cleanup: Guido Guenther + * further cleanup: Maciej W. Rozycki + */ + +#include +#include +#include +#include +#include +#include + +#include "ecoff.h" + +#define MIPS_PAGE_SIZE 4096 +#define MIPS_PAGE_MASK (MIPS_PAGE_SIZE-1) + +#define swab16(x) \ + ((unsigned short)( \ + (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ + (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) )) + +#define swab32(x) \ + ((unsigned int)( \ + (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \ + (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \ + (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ + (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) )) + +#define SWAB(a) (swab ? swab32(a) : (a)) + +void die(char *s) +{ + perror(s); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int fd_vmlinux, fd_initrd, fd_outfile; + FILHDR efile; + AOUTHDR eaout; + SCNHDR esecs[3]; + struct stat st; + char buf[1024]; + unsigned long loadaddr; + unsigned long initrd_header[2]; + int i, cnt; + int swab = 0; + + if (argc != 4) { + printf("Usage: %s \n", argv[0]); + exit(1); + } + + if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0) + die("open vmlinux"); + if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile) + die("read file header"); + if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout) + die("read aout header"); + if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs) + die("read section headers"); + /* + * check whether the file is good for us + */ + /* TBD */ + + /* + * check, if we have to swab words + */ + if (ntohs(0xaa55) == 0xaa55) { + if (efile.f_magic == swab16(MIPSELMAGIC)) + swab = 1; + } else { + if (efile.f_magic == swab16(MIPSEBMAGIC)) + swab = 1; + } + + /* make sure we have an empty data segment for the initrd */ + if (eaout.dsize || esecs[1].s_size) { + fprintf(stderr, "Data segment not empty. Giving up!\n"); + exit(1); + } + if ((fd_initrd = open (argv[2], O_RDONLY)) < 0) + die("open initrd"); + if (fstat (fd_initrd, &st) < 0) + die("fstat initrd"); + loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size) + + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8; + if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size))) + loadaddr += MIPS_PAGE_SIZE; + initrd_header[0] = SWAB(0x494E5244); + initrd_header[1] = SWAB(st.st_size); + eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8); + eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr); + + if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0) + die("open outfile"); + if (write (fd_outfile, &efile, sizeof efile) != sizeof efile) + die("write file header"); + if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout) + die("write aout header"); + if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs) + die("write section headers"); + /* skip padding */ + if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) + die("lseek vmlinux"); + if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) + die("lseek outfile"); + /* copy text segment */ + cnt = SWAB(eaout.tsize); + while (cnt) { + if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0) + die("read vmlinux"); + if (write (fd_outfile, buf, i) != i) + die("write vmlinux"); + cnt -= i; + } + if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header) + die("write initrd header"); + while ((i = read (fd_initrd, buf, sizeof buf)) > 0) + if (write (fd_outfile, buf, i) != i) + die("write initrd"); + close(fd_vmlinux); + close(fd_initrd); + return 0; +} diff --git a/trunk/arch/mips/boot/compressed/Makefile b/trunk/arch/mips/boot/compressed/Makefile deleted file mode 100644 index e27f40bbd4e5..000000000000 --- a/trunk/arch/mips/boot/compressed/Makefile +++ /dev/null @@ -1,100 +0,0 @@ -# -# This file is subject to the terms and conditions of the GNU General Public -# License. -# -# Adapted for MIPS Pete Popov, Dan Malek -# -# Copyright (C) 1994 by Linus Torvalds -# Adapted for PowerPC by Gary Thomas -# modified by Cort (cort@cs.nmt.edu) -# -# Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University -# Author: Wu Zhangjin -# - -# compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE -VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1) -VMLINUX_SIZE := $(shell [ -n "$(VMLINUX_SIZE)" ] && echo $$(($(VMLINUX_SIZE) + (65536 - $(VMLINUX_SIZE) % 65536)))) -VMLINUZ_LOAD_ADDRESS := 0x$(shell [ -n "$(VMLINUX_SIZE)" ] && printf %x $$(($(VMLINUX_LOAD_ADDRESS) + $(VMLINUX_SIZE)))) - -# set the default size of the mallocing area for decompressing -BOOT_HEAP_SIZE := 0x400000 - -# Disable Function Tracer -KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//") - -KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \ - -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" \ - -KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ - -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \ - -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) - -obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o - -obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o - -OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S -$(obj)/vmlinux.bin: $(KBUILD_IMAGE) - $(call if_changed,objcopy) - -suffix_$(CONFIG_KERNEL_GZIP) = gz -suffix_$(CONFIG_KERNEL_BZIP2) = bz2 -suffix_$(CONFIG_KERNEL_LZMA) = lzma -tool_$(CONFIG_KERNEL_GZIP) = gzip -tool_$(CONFIG_KERNEL_BZIP2) = bzip2 -tool_$(CONFIG_KERNEL_LZMA) = lzma -$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin - $(call if_changed,$(tool_y)) - -$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o - $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \ - --add-section=.image=$< \ - --set-section-flags=.image=contents,alloc,load,readonly,data \ - $(obj)/dummy.o $@ - -LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T -vmlinuz: $(src)/ld.script $(obj-y) $(obj)/piggy.o - $(call if_changed,ld) - $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap $@ - -# -# Some DECstations need all possible sections of an ECOFF executable -# -ifdef CONFIG_MACH_DECSTATION - E2EFLAGS = -a -else - E2EFLAGS = -endif - -# elf2ecoff can only handle 32bit image - -ifdef CONFIG_32BIT - VMLINUZ = vmlinuz -else - VMLINUZ = vmlinuz.32 -endif - -vmlinuz.32: vmlinuz - $(Q)$(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ - -vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ) - $(Q)$(obj)/../elf2ecoff $(VMLINUZ) vmlinuz.ecoff $(E2EFLAGS) - -$(obj)/../elf2ecoff: $(src)/../elf2ecoff.c - $(Q)$(HOSTCC) -o $@ $^ - -drop-sections = .reginfo .mdebug .comment .note .pdr .options .MIPS.options -strip-flags = $(addprefix --remove-section=,$(drop-sections)) - -OBJCOPYFLAGS_vmlinuz.bin := $(OBJCOPYFLAGS) -O binary $(strip-flags) -vmlinuz.bin: vmlinuz - $(call if_changed,objcopy) - -OBJCOPYFLAGS_vmlinuz.srec := $(OBJCOPYFLAGS) -S -O srec $(strip-flags) -vmlinuz.srec: vmlinuz - $(call if_changed,objcopy) - -clean: -clean-files += *.o \ - vmlinu* diff --git a/trunk/arch/mips/boot/compressed/dbg.c b/trunk/arch/mips/boot/compressed/dbg.c deleted file mode 100644 index ff4dc7a33a9f..000000000000 --- a/trunk/arch/mips/boot/compressed/dbg.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * MIPS-specific debug support for pre-boot environment - * - * NOTE: putc() is board specific, if your board have a 16550 compatible uart, - * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you - * need to implement your own putc(). - */ - -#include -#include - -void __attribute__ ((weak)) putc(char c) -{ -} - -void puts(const char *s) -{ - char c; - while ((c = *s++) != '\0') { - putc(c); - if (c == '\n') - putc('\r'); - } -} - -void puthex(unsigned long long val) -{ - - unsigned char buf[10]; - int i; - for (i = 7; i >= 0; i--) { - buf[i] = "0123456789ABCDEF"[val & 0x0F]; - val >>= 4; - } - buf[8] = '\0'; - puts(buf); -} diff --git a/trunk/arch/mips/boot/compressed/decompress.c b/trunk/arch/mips/boot/compressed/decompress.c deleted file mode 100644 index 67330c2f7318..000000000000 --- a/trunk/arch/mips/boot/compressed/decompress.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Misc. bootloader code for many machines. - * - * Copyright 2001 MontaVista Software Inc. - * Author: Matt Porter Derived from - * arch/ppc/boot/prep/misc.c - * - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology - * Author: Wu Zhangjin - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -#include - -/* These two variables specify the free mem region - * that can be used for temporary malloc area - */ -unsigned long free_mem_ptr; -unsigned long free_mem_end_ptr; -char *zimage_start; - -/* The linker tells us where the image is. */ -extern unsigned char __image_begin, __image_end; -extern unsigned char __ramdisk_begin, __ramdisk_end; -unsigned long initrd_size; - -/* debug interfaces */ -extern void puts(const char *s); -extern void puthex(unsigned long long val); - -void error(char *x) -{ - puts("\n\n"); - puts(x); - puts("\n\n -- System halted"); - - while (1) - ; /* Halt */ -} - -/* activate the code for pre-boot environment */ -#define STATIC static - -#ifdef CONFIG_KERNEL_GZIP -void *memcpy(void *dest, const void *src, size_t n) -{ - int i; - const char *s = src; - char *d = dest; - - for (i = 0; i < n; i++) - d[i] = s[i]; - return dest; -} -#include "../../../../lib/decompress_inflate.c" -#endif - -#ifdef CONFIG_KERNEL_BZIP2 -void *memset(void *s, int c, size_t n) -{ - int i; - char *ss = s; - - for (i = 0; i < n; i++) - ss[i] = c; - return s; -} -#include "../../../../lib/decompress_bunzip2.c" -#endif - -#ifdef CONFIG_KERNEL_LZMA -#include "../../../../lib/decompress_unlzma.c" -#endif - -void decompress_kernel(unsigned long boot_heap_start) -{ - int zimage_size; - - /* - * We link ourself to an arbitrary low address. When we run, we - * relocate outself to that address. __image_beign points to - * the part of the image where the zImage is. -- Tom - */ - zimage_start = (char *)(unsigned long)(&__image_begin); - zimage_size = (unsigned long)(&__image_end) - - (unsigned long)(&__image_begin); - - /* - * The zImage and initrd will be between start and _end, so they've - * already been moved once. We're good to go now. -- Tom - */ - puts("zimage at: "); - puthex((unsigned long)zimage_start); - puts(" "); - puthex((unsigned long)(zimage_size + zimage_start)); - puts("\n"); - - if (initrd_size) { - puts("initrd at: "); - puthex((unsigned long)(&__ramdisk_begin)); - puts(" "); - puthex((unsigned long)(&__ramdisk_end)); - puts("\n"); - } - - /* this area are prepared for mallocing when decompressing */ - free_mem_ptr = boot_heap_start; - free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE; - - /* Display standard Linux/MIPS boot prompt for kernel args */ - puts("Uncompressing Linux at load address "); - puthex(VMLINUX_LOAD_ADDRESS_ULL); - puts("\n"); - /* Decompress the kernel with according algorithm */ - decompress(zimage_start, zimage_size, 0, 0, - (void *)VMLINUX_LOAD_ADDRESS_ULL, 0, error); - /* FIXME: is there a need to flush cache here? */ - puts("Now, booting the kernel...\n"); -} diff --git a/trunk/arch/mips/boot/compressed/dummy.c b/trunk/arch/mips/boot/compressed/dummy.c deleted file mode 100644 index 31dbf45bf99c..000000000000 --- a/trunk/arch/mips/boot/compressed/dummy.c +++ /dev/null @@ -1,4 +0,0 @@ -int main(void) -{ - return 0; -} diff --git a/trunk/arch/mips/boot/compressed/head.S b/trunk/arch/mips/boot/compressed/head.S deleted file mode 100644 index 4e65a8420bee..000000000000 --- a/trunk/arch/mips/boot/compressed/head.S +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994, 1995 Waldorf Electronics - * Written by Ralf Baechle and Andreas Busse - * Copyright (C) 1995 - 1999 Ralf Baechle - * Copyright (C) 1996 Paul M. Antoine - * Modified for DECStation and hence R3000 support by Paul M. Antoine - * Further modifications by David S. Miller and Harald Koerfgen - * Copyright (C) 1999 Silicon Graphics, Inc. - */ - -#include -#include - - .set noreorder - .cprestore - LEAF(start) -start: - /* Save boot rom start args */ - move s0, a0 - move s1, a1 - move s2, a2 - move s3, a3 - - /* Clear BSS */ - PTR_LA a0, _edata - PTR_LA a2, _end -1: sw zero, 0(a0) - bne a2, a0, 1b - addiu a0, a0, 4 - - PTR_LA a0, (.heap) /* heap address */ - PTR_LA sp, (.stack + 8192) /* stack address */ - - PTR_LA ra, 2f - PTR_LA k0, decompress_kernel - jr k0 - nop -2: - move a0, s0 - move a1, s1 - move a2, s2 - move a3, s3 - PTR_LI k0, KERNEL_ENTRY - jr k0 - nop -3: - b 3b - nop - END(start) - - .comm .heap,BOOT_HEAP_SIZE,4 - .comm .stack,4096*2,4 diff --git a/trunk/arch/mips/boot/compressed/ld.script b/trunk/arch/mips/boot/compressed/ld.script deleted file mode 100644 index 29e9f4c0d5d8..000000000000 --- a/trunk/arch/mips/boot/compressed/ld.script +++ /dev/null @@ -1,150 +0,0 @@ -OUTPUT_ARCH(mips) -ENTRY(start) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - .init : { *(.init) } =0 - .text : - { - _ftext = . ; - *(.text) - *(.rodata) - *(.rodata1) - /* .gnu.warning sections are handled specially by elf32.em. */ - *(.gnu.warning) - } =0 - .kstrtab : { *(.kstrtab) } - - . = ALIGN(16); /* Exception table */ - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - __start___dbe_table = .; /* Exception table for data bus errors */ - __dbe_table : { *(__dbe_table) } - __stop___dbe_table = .; - - __start___ksymtab = .; /* Kernel symbol table */ - __ksymtab : { *(__ksymtab) } - __stop___ksymtab = .; - - _etext = .; - - . = ALIGN(8192); - .data.init_task : { *(.data.init_task) } - - /* Startup code */ - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(16); - __setup_start = .; - .setup.init : { *(.setup.init) } - __setup_end = .; - __initcall_start = .; - .initcall.init : { *(.initcall.init) } - __initcall_end = .; - . = ALIGN(4096); /* Align double page for init_task_union */ - __init_end = .; - - . = ALIGN(4096); - .data.page_aligned : { *(.data.idt) } - - . = ALIGN(32); - .data.cacheline_aligned : { *(.data.cacheline_aligned) } - - .fini : { *(.fini) } =0 - .reginfo : { *(.reginfo) } - /* Adjust the address for the data segment. We want to adjust up to - the same address within the page on the next page up. It would - be more correct to do this: - . = .; - The current expression does not correctly handle the case of a - text segment ending precisely at the end of a page; it causes the - data segment to skip a page. The above expression does not have - this problem, but it will currently (2/95) cause BFD to allocate - a single segment, combining both text and data, for this case. - This will prevent the text segment from being shared among - multiple executions of the program; I think that is more - important than losing a page of the virtual address space (note - that no actual memory is lost; the page which is skipped can not - be referenced). */ - . = .; - .data : - { - _fdata = . ; - *(.data) - - /* Put the compressed image here, so bss is on the end. */ - __image_begin = .; - *(.image) - __image_end = .; - /* Align the initial ramdisk image (INITRD) on page boundaries. */ - . = ALIGN(4096); - __ramdisk_begin = .; - *(.initrd) - __ramdisk_end = .; - . = ALIGN(4096); - - CONSTRUCTORS - } - .data1 : { *(.data1) } - _gp = . + 0x8000; - .lit8 : { *(.lit8) } - .lit4 : { *(.lit4) } - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - .got : { *(.got.plt) *(.got) } - .dynamic : { *(.dynamic) } - /* We want the small data sections together, so single-instruction offsets - can access them all, and initialized data all before uninitialized, so - we can shorten the on-disk segment size. */ - .sdata : { *(.sdata) } - . = ALIGN(4); - _edata = .; - PROVIDE (edata = .); - - __bss_start = .; - _fbss = .; - .sbss : { *(.sbss) *(.scommon) } - .bss : - { - *(.dynbss) - *(.bss) - *(COMMON) - . = ALIGN(4); - _end = . ; - PROVIDE (end = .); - } - - /* Sections to be discarded */ - /DISCARD/ : - { - *(.text.exit) - *(.data.exit) - *(.exitcall.exit) - } - - /* This is the MIPS specific mdebug section. */ - .mdebug : { *(.mdebug) } - /* These are needed for ELF backends which have not yet been - converted to the new style linker. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - /* DWARF debug sections. - Symbols in the .debug DWARF section are relative to the beginning of the - section so we begin .debug at 0. It's not clear yet what needs to happen - for the others. */ - .debug 0 : { *(.debug) } - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_sfnames 0 : { *(.debug_sfnames) } - .line 0 : { *(.line) } - /* These must appear regardless of . */ - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - .comment : { *(.comment) } - .note : { *(.note) } -} diff --git a/trunk/arch/mips/boot/compressed/uart-16550.c b/trunk/arch/mips/boot/compressed/uart-16550.c deleted file mode 100644 index c9caaf4fbf60..000000000000 --- a/trunk/arch/mips/boot/compressed/uart-16550.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * 16550 compatible uart based serial debug support for zboot - */ - -#include -#include -#include - -#include - -#if defined(CONFIG_MACH_LOONGSON) || defined(CONFIG_MIPS_MALTA) -#define UART_BASE 0x1fd003f8 -#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) -#endif - -#ifdef CONFIG_AR7 -#include -#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) -#endif - -#ifndef PORT -#error please define the serial port address for your own machine -#endif - -static inline unsigned int serial_in(int offset) -{ - return *((char *)PORT(offset)); -} - -static inline void serial_out(int offset, int value) -{ - *((char *)PORT(offset)) = value; -} - -void putc(char c) -{ - int timeout = 1024; - - while (((serial_in(UART_LSR) & UART_LSR_THRE) == 0) && (timeout-- > 0)) - ; - - serial_out(UART_TX, c); -} diff --git a/trunk/arch/mips/cavium-octeon/Makefile b/trunk/arch/mips/cavium-octeon/Makefile index 3e9876317e61..139436280520 100644 --- a/trunk/arch/mips/cavium-octeon/Makefile +++ b/trunk/arch/mips/cavium-octeon/Makefile @@ -9,7 +9,7 @@ # Copyright (C) 2005-2009 Cavium Networks # -obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o +obj-y := setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o obj-y += dma-octeon.o flash_setup.o obj-y += octeon-memcpy.o diff --git a/trunk/arch/mips/cavium-octeon/cpu.c b/trunk/arch/mips/cavium-octeon/cpu.c deleted file mode 100644 index b6df5387e855..000000000000 --- a/trunk/arch/mips/cavium-octeon/cpu.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2009 Wind River Systems, - * written by Ralf Baechle - */ -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -static int cnmips_cu2_call(struct notifier_block *nfb, unsigned long action, - void *data) -{ - unsigned long flags; - unsigned int status; - - switch (action) { - case CU2_EXCEPTION: - prefetch(¤t->thread.cp2); - local_irq_save(flags); - KSTK_STATUS(current) |= ST0_CU2; - status = read_c0_status(); - write_c0_status(status | ST0_CU2); - octeon_cop2_restore(&(current->thread.cp2)); - write_c0_status(status & ~ST0_CU2); - local_irq_restore(flags); - - return NOTIFY_BAD; /* Don't call default notifier */ - } - - return NOTIFY_OK; /* Let default notifier send signals */ -} - -static struct notifier_block cnmips_cu2_notifier = { - .notifier_call = cnmips_cu2_call, -}; - -static int cnmips_cu2_setup(void) -{ - return register_cu2_notifier(&cnmips_cu2_notifier); -} -early_initcall(cnmips_cu2_setup); diff --git a/trunk/arch/mips/cavium-octeon/octeon-platform.c b/trunk/arch/mips/cavium-octeon/octeon-platform.c index cfdb4c2ac5c3..be711dd2d918 100644 --- a/trunk/arch/mips/cavium-octeon/octeon-platform.c +++ b/trunk/arch/mips/cavium-octeon/octeon-platform.c @@ -159,94 +159,6 @@ static int __init octeon_rng_device_init(void) } device_initcall(octeon_rng_device_init); -/* Octeon SMI/MDIO interface. */ -static int __init octeon_mdiobus_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - - if (octeon_is_simulation()) - return 0; /* No mdio in the simulator. */ - - /* The bus number is the platform_device id. */ - pd = platform_device_alloc("mdio-octeon", 0); - if (!pd) { - ret = -ENOMEM; - goto out; - } - - ret = platform_device_add(pd); - if (ret) - goto fail; - - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mdiobus_device_init); - -/* Octeon mgmt port Ethernet interface. */ -static int __init octeon_mgmt_device_init(void) -{ - struct platform_device *pd; - int ret = 0; - int port, num_ports; - - struct resource mgmt_port_resource = { - .flags = IORESOURCE_IRQ, - .start = -1, - .end = -1 - }; - - if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX)) - return 0; - - if (OCTEON_IS_MODEL(OCTEON_CN56XX)) - num_ports = 1; - else - num_ports = 2; - - for (port = 0; port < num_ports; port++) { - pd = platform_device_alloc("octeon_mgmt", port); - if (!pd) { - ret = -ENOMEM; - goto out; - } - switch (port) { - case 0: - mgmt_port_resource.start = OCTEON_IRQ_MII0; - break; - case 1: - mgmt_port_resource.start = OCTEON_IRQ_MII1; - break; - default: - BUG(); - } - mgmt_port_resource.end = mgmt_port_resource.start; - - ret = platform_device_add_resources(pd, &mgmt_port_resource, 1); - - if (ret) - goto fail; - - ret = platform_device_add(pd); - if (ret) - goto fail; - } - return ret; -fail: - platform_device_put(pd); - -out: - return ret; - -} -device_initcall(octeon_mgmt_device_init); - MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/trunk/arch/mips/configs/ar7_defconfig b/trunk/arch/mips/configs/ar7_defconfig index 5a5b6ba7514e..35648302f7cc 100644 --- a/trunk/arch/mips/configs/ar7_defconfig +++ b/trunk/arch/mips/configs/ar7_defconfig @@ -10,6 +10,7 @@ CONFIG_MIPS=y # # CONFIG_MACH_ALCHEMY is not set CONFIG_AR7=y +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -264,6 +265,7 @@ CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_PROBE_INITRD_HEADER=y # CONFIG_FREEZER is not set # @@ -1051,9 +1053,7 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/bcm47xx_defconfig b/trunk/arch/mips/configs/bcm47xx_defconfig index 267bd46120bc..94b7d57f906d 100644 --- a/trunk/arch/mips/configs/bcm47xx_defconfig +++ b/trunk/arch/mips/configs/bcm47xx_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set CONFIG_BCM47XX=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -1852,7 +1853,7 @@ CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/bcm63xx_defconfig b/trunk/arch/mips/configs/bcm63xx_defconfig index 7fee0273c829..ea00c18d1f7b 100644 --- a/trunk/arch/mips/configs/bcm63xx_defconfig +++ b/trunk/arch/mips/configs/bcm63xx_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set CONFIG_BCM63XX=y # CONFIG_MIPS_COBALT is not set @@ -941,9 +942,7 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyS0,115200" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/bigsur_defconfig b/trunk/arch/mips/configs/bigsur_defconfig index c2f06e38c854..13d9eb4736c0 100644 --- a/trunk/arch/mips/configs/bigsur_defconfig +++ b/trunk/arch/mips/configs/bigsur_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -1236,7 +1237,7 @@ CONFIG_DEBUG_MUTEXES=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_SAMPLES is not set -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_SB1XXX_CORELIS is not set # CONFIG_RUNTIME_DEBUG is not set diff --git a/trunk/arch/mips/configs/capcella_defconfig b/trunk/arch/mips/configs/capcella_defconfig index 72b7e456916e..185df23fd460 100644 --- a/trunk/arch/mips/configs/capcella_defconfig +++ b/trunk/arch/mips/configs/capcella_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -782,9 +783,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="mem=32M console=ttyVR0,38400" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/cavium-octeon_defconfig b/trunk/arch/mips/configs/cavium-octeon_defconfig index c8507bc8e925..7afaa28a3768 100644 --- a/trunk/arch/mips/configs/cavium-octeon_defconfig +++ b/trunk/arch/mips/configs/cavium-octeon_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -268,6 +269,7 @@ CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_CLASSIC_RCU=y +# CONFIG_PROBE_INITRD_HEADER is not set # CONFIG_FREEZER is not set # @@ -820,7 +822,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_RUNTIME_DEBUG is not set diff --git a/trunk/arch/mips/configs/cobalt_defconfig b/trunk/arch/mips/configs/cobalt_defconfig index 49e61312e006..6c8cca8589ba 100644 --- a/trunk/arch/mips/configs/cobalt_defconfig +++ b/trunk/arch/mips/configs/cobalt_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set CONFIG_MIPS_COBALT=y # CONFIG_MACH_DECSTATION is not set @@ -1125,7 +1126,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_SAMPLES is not set -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/db1000_defconfig b/trunk/arch/mips/configs/db1000_defconfig index 68e90cd6b2d4..dbdf3bb1a34a 100644 --- a/trunk/arch/mips/configs/db1000_defconfig +++ b/trunk/arch/mips/configs/db1000_defconfig @@ -23,6 +23,7 @@ CONFIG_MIPS_DB1000=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1089,7 +1090,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/db1100_defconfig b/trunk/arch/mips/configs/db1100_defconfig index 90812830e940..fa6814475898 100644 --- a/trunk/arch/mips/configs/db1100_defconfig +++ b/trunk/arch/mips/configs/db1100_defconfig @@ -23,6 +23,7 @@ CONFIG_MIPS_DB1100=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1089,7 +1090,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/db1200_defconfig b/trunk/arch/mips/configs/db1200_defconfig index dabf03032e06..d73f1de43b5d 100644 --- a/trunk/arch/mips/configs/db1200_defconfig +++ b/trunk/arch/mips/configs/db1200_defconfig @@ -23,6 +23,7 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_MIPS_DB1550 is not set CONFIG_MIPS_DB1200=y # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1171,9 +1172,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="mem=48M" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/db1500_defconfig b/trunk/arch/mips/configs/db1500_defconfig index a15131373138..ec3e028a5b2e 100644 --- a/trunk/arch/mips/configs/db1500_defconfig +++ b/trunk/arch/mips/configs/db1500_defconfig @@ -23,6 +23,7 @@ CONFIG_MIPS_DB1500=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1389,7 +1390,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/db1550_defconfig b/trunk/arch/mips/configs/db1550_defconfig index 6b64339c0014..7631dae51be9 100644 --- a/trunk/arch/mips/configs/db1550_defconfig +++ b/trunk/arch/mips/configs/db1550_defconfig @@ -23,6 +23,7 @@ CONFIG_MACH_ALCHEMY=y CONFIG_MIPS_DB1550=y # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1206,7 +1207,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/decstation_defconfig b/trunk/arch/mips/configs/decstation_defconfig index cbb4d86f2912..9e65e6a2dcb3 100644 --- a/trunk/arch/mips/configs/decstation_defconfig +++ b/trunk/arch/mips/configs/decstation_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set CONFIG_MACH_DECSTATION=y # CONFIG_MACH_JAZZ is not set @@ -881,7 +882,7 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/e55_defconfig b/trunk/arch/mips/configs/e55_defconfig index 52968c46c806..1bd84d42b14f 100644 --- a/trunk/arch/mips/configs/e55_defconfig +++ b/trunk/arch/mips/configs/e55_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -560,9 +561,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x1f0,0x3f6,40 mem=8M" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/excite_defconfig b/trunk/arch/mips/configs/excite_defconfig new file mode 100644 index 000000000000..1995d43a2ed1 --- /dev/null +++ b/trunk/arch/mips/configs/excite_defconfig @@ -0,0 +1,1335 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.20 +# Tue Feb 20 21:47:31 2007 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_ZONE_DMA=y +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +CONFIG_BASLER_EXCITE=y +# CONFIG_BASLER_EXCITE_PROTOTYPE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_WR_PPMC is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_MARKEINS is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM is not set +# CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_TIME=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_DMA_COHERENT=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_IRQ_CPU_RM7K=y +CONFIG_IRQ_CPU_RM9K=y +CONFIG_MIPS_RM9122=y +CONFIG_SERIAL_RM9000=y +CONFIG_GPI_RM9000=y +CONFIG_WDT_RM9000=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +CONFIG_CPU_RM9000=y +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_RM9000=y +CONFIG_WEAK_ORDERING=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +# CONFIG_MIPS_VPE_LOADER is not set +# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_BKL=y +# CONFIG_KEXEC is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_SYSFS_DEPRECATED=y +# CONFIG_RELAY is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +# CONFIG_PCCARD is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_LEGACY is not set +# CONFIG_PM_DEBUG is not set +# CONFIG_PM_SYSFS_DEPRECATED is not set + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETFILTER is not set + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_IEEE80211 is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=m +# CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_VERIFY_WRITE=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_BASLER_EXCITE is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set + +# +# Misc devices +# +CONFIG_SGI_IOC4=m +# CONFIG_TIFM_CORE is not set + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_TGT=m +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set + +# +# SCSI low-level drivers +# +# CONFIG_ISCSI_TCP is not set +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_ACARD is not set +# CONFIG_SCSI_AACRAID is not set +# CONFIG_SCSI_AIC7XXX is not set +# CONFIG_SCSI_AIC7XXX_OLD is not set +# CONFIG_SCSI_AIC79XX is not set +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ARCMSR is not set +# CONFIG_MEGARAID_NEWGEN is not set +# CONFIG_MEGARAID_LEGACY is not set +# CONFIG_MEGARAID_SAS is not set +# CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_DMX3191D is not set +# CONFIG_SCSI_FUTURE_DOMAIN is not set +# CONFIG_SCSI_IPS is not set +# CONFIG_SCSI_INITIO is not set +# CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_STEX is not set +# CONFIG_SCSI_SYM53C8XX_2 is not set +# CONFIG_SCSI_QLOGIC_1280 is not set +# CONFIG_SCSI_QLA_FC is not set +# CONFIG_SCSI_QLA_ISCSI is not set +# CONFIG_SCSI_LPFC is not set +# CONFIG_SCSI_DC395x is not set +# CONFIG_SCSI_DC390T is not set +# CONFIG_SCSI_NSP32 is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_SRP is not set + +# +# Serial ATA (prod) and Parallel ATA (experimental) drivers +# +# CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set +# CONFIG_FUSION_SPI is not set +# CONFIG_FUSION_FC is not set +# CONFIG_FUSION_SAS is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# + +# +# Ethernet (10 or 100Mbit) +# +# CONFIG_NET_ETHERNET is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +CONFIG_QLA3XXX=m +# CONFIG_ATL1 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +CONFIG_CHELSIO_T3=m +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_MYRI10GE is not set +CONFIG_NETXEN_NIC=m + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +# CONFIG_NET_RADIO is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=m +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +CONFIG_INPUT_EVDEV=m +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_WDT_RM9K_GPI=m + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_DRM is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set +# CONFIG_USB_DABUSB is not set + +# +# Graphics support +# +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_SMIVGX is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_VIRTUAL is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=m +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y + +# +# Logo configuration +# +# CONFIG_LOGO is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# HID Devices +# +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_SPLIT_ISO is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# may also be needed; see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# CONFIG_USB_AIPTEK is not set +# CONFIG_USB_WACOM is not set +# CONFIG_USB_ACECAD is not set +# CONFIG_USB_KBTAB is not set +# CONFIG_USB_POWERMATE is not set +# CONFIG_USB_TOUCHSCREEN is not set +# CONFIG_USB_YEALINK is not set +# CONFIG_USB_XPAD is not set +# CONFIG_USB_ATI_REMOTE is not set +# CONFIG_USB_ATI_REMOTE2 is not set +# CONFIG_USB_KEYSPAN_REMOTE is not set +# CONFIG_USB_APPLETOUCH is not set +# CONFIG_USB_GTCO is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET_MII is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_MON is not set + +# +# USB port drivers +# + +# +# USB Serial Converter support +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_AUERSWALD is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_TEST is not set + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# LED devices +# +# CONFIG_NEW_LEDS is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# Auxiliary Display support +# + +# +# Virtualization +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4DEV_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +CONFIG_CONFIGFS_FS=m + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_ROOT_NFS=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Distributed Lock Manager +# +CONFIG_DLM=m +CONFIG_DLM_TCP=y +# CONFIG_DLM_SCTP is not set +# CONFIG_DLM_DEBUG is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_MUST_CHECK=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_HMAC is not set +CONFIG_CRYPTO_XCBC=m +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_LRW=m +# CONFIG_CRYPTO_DES is not set +CONFIG_CRYPTO_FCRYPT=m +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_CRC32C is not set +CONFIG_CRYPTO_CAMELLIA=m +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y diff --git a/trunk/arch/mips/configs/fuloong2e_defconfig b/trunk/arch/mips/configs/fuloong2e_defconfig index a09dd03aa8c8..0197f0de6b3f 100644 --- a/trunk/arch/mips/configs/fuloong2e_defconfig +++ b/trunk/arch/mips/configs/fuloong2e_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc4 -# Fri Oct 16 13:18:01 2009 +# Linux kernel version: 2.6.31-rc1 +# Thu Jul 2 22:37:00 2009 # CONFIG_MIPS=y @@ -10,8 +10,8 @@ CONFIG_MIPS=y # # CONFIG_MACH_ALCHEMY is not set # CONFIG_AR7 is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set -# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -105,8 +105,6 @@ CONFIG_CPU_LOONGSON2E=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y CONFIG_CPU_LOONGSON2=y CONFIG_SYS_HAS_CPU_LOONGSON2E=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y @@ -137,16 +135,12 @@ CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set +CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_HAVE_MEMORY_PRESENT=y +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPARSEMEM_STATIC=y - -# -# Memory hotplug is currently incompatible with Software Suspend -# CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_PHYS_ADDR_T_64BIT=y @@ -154,7 +148,6 @@ CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y @@ -187,12 +180,6 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="-fuloong2e" # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -206,12 +193,11 @@ CONFIG_BSD_PROCESS_ACCT=y # # RCU Subsystem # -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=64 -# CONFIG_RCU_FANOUT_EXACT is not set +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set # CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -249,16 +235,18 @@ CONFIG_SHMEM=y CONFIG_AIO=y # -# Kernel Performance Events And Counters +# Performance Counters # CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set CONFIG_PROFILING=y CONFIG_TRACEPOINTS=y +CONFIG_MARKERS=y CONFIG_OPROFILE=m CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_SYSCALL_WRAPPERS=y @@ -267,8 +255,8 @@ CONFIG_HAVE_SYSCALL_WRAPPERS=y # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 @@ -295,7 +283,7 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -333,14 +321,9 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_PM=y # CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y # CONFIG_SUSPEND is not set -CONFIG_HIBERNATION_NVS=y -CONFIG_HIBERNATION=y -CONFIG_PM_STD_PARTITION="/dev/hda3" -# CONFIG_PM_RUNTIME is not set +# CONFIG_HIBERNATION is not set CONFIG_NET=y -CONFIG_COMPAT_NETLINK_MESSAGES=y # # Networking options @@ -459,7 +442,6 @@ CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -491,7 +473,6 @@ CONFIG_NET_CLS_ROUTE=y # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y @@ -500,6 +481,7 @@ CONFIG_WIRELESS_EXT_SYSFS=y # # CFG80211 needs to be enabled for MAC80211 # +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set CONFIG_NET_9P=m @@ -513,7 +495,6 @@ CONFIG_NET_9P=m # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m @@ -523,9 +504,9 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=m # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set # CONFIG_MTD_PARTITIONS is not set +# CONFIG_MTD_TESTS is not set # # User Modules And Translation Layers @@ -839,7 +820,6 @@ CONFIG_8139TOO=y # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set # CONFIG_ATL2 is not set @@ -887,7 +867,10 @@ CONFIG_CHELSIO_T3_DEPENDS=y # CONFIG_SFC is not set # CONFIG_BE2NET is not set # CONFIG_TR is not set -CONFIG_WLAN=y + +# +# Wireless LAN +# # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set @@ -903,7 +886,6 @@ CONFIG_WLAN=y # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set -# CONFIG_USB_CDC_PHONET is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -951,16 +933,12 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set CONFIG_KEYBOARD_ATKBD=y -# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y @@ -968,7 +946,6 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set CONFIG_MOUSE_SERIAL=y # CONFIG_MOUSE_APPLETOUCH is not set @@ -1038,7 +1015,6 @@ CONFIG_RTC=y CONFIG_DEVPORT=y CONFIG_I2C=m CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_HELPER_AUTO=y @@ -1094,6 +1070,9 @@ CONFIG_I2C_VIAPRO=m # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1109,6 +1088,7 @@ CONFIG_I2C_VIAPRO=m # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -1125,7 +1105,6 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set # CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set @@ -1135,7 +1114,6 @@ CONFIG_SSB_POSSIBLE=y # # Graphics support # -CONFIG_VGA_ARB=y # CONFIG_DRM is not set # CONFIG_VGASTATE is not set CONFIG_VIDEO_OUTPUT_CONTROL=m @@ -1220,7 +1198,6 @@ CONFIG_FONT_8x16=y # CONFIG_LOGO is not set CONFIG_SOUND=y CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -1327,6 +1304,7 @@ CONFIG_SND_USB=y CONFIG_AC97_BUS=m CONFIG_HID_SUPPORT=y CONFIG_HID=y +# CONFIG_HID_DEBUG is not set CONFIG_HIDRAW=y # @@ -1378,7 +1356,6 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set CONFIG_USB_ISP1760_HCD=m -# CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set @@ -1476,7 +1453,6 @@ CONFIG_UIO_CIF=m # CONFIG_UIO_SMX is not set # CONFIG_UIO_AEC is not set # CONFIG_UIO_SERCOS3 is not set -# CONFIG_UIO_PCI_GENERIC is not set # # TI VLYNQ @@ -1493,10 +1469,10 @@ CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set # CONFIG_EXT3_FS_XATTR is not set CONFIG_EXT4_FS=m +CONFIG_EXT4DEV_COMPAT=y CONFIG_EXT4_FS_XATTR=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_DEBUG is not set CONFIG_FS_XIP=y CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set @@ -1513,7 +1489,6 @@ CONFIG_FS_POSIX_ACL=y # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y @@ -1582,6 +1557,7 @@ CONFIG_OMFS_FS=m # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y @@ -1690,7 +1666,6 @@ CONFIG_ENABLE_WARN_DEPRECATED=y # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_FRAME_WARN=2048 # CONFIG_MAGIC_SYSRQ is not set -# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set @@ -1703,14 +1678,13 @@ CONFIG_NOP_TRACER=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_TRACING=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options @@ -1768,13 +1742,11 @@ CONFIG_CRYPTO_XTS=m # CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set -CONFIG_CRYPTO_GHASH=m # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=m # CONFIG_CRYPTO_MICHAEL_MIC is not set diff --git a/trunk/arch/mips/configs/ip22_defconfig b/trunk/arch/mips/configs/ip22_defconfig index 222d7eca2fe4..f14d38ba6034 100644 --- a/trunk/arch/mips/configs/ip22_defconfig +++ b/trunk/arch/mips/configs/ip22_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -1187,7 +1188,7 @@ CONFIG_DEBUG_MEMORY_INIT=y CONFIG_DYNAMIC_PRINTK_DEBUG=y # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/ip27_defconfig b/trunk/arch/mips/configs/ip27_defconfig index ed84b4cb3c8d..1fc73aa7b509 100644 --- a/trunk/arch/mips/configs/ip27_defconfig +++ b/trunk/arch/mips/configs/ip27_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -939,7 +940,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/ip28_defconfig b/trunk/arch/mips/configs/ip28_defconfig index dab2e5aaadaf..539dccb0345d 100644 --- a/trunk/arch/mips/configs/ip28_defconfig +++ b/trunk/arch/mips/configs/ip28_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -815,7 +816,7 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/ip32_defconfig b/trunk/arch/mips/configs/ip32_defconfig index 1841c88d3d24..d934bdefb393 100644 --- a/trunk/arch/mips/configs/ip32_defconfig +++ b/trunk/arch/mips/configs/ip32_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -1125,7 +1126,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/jazz_defconfig b/trunk/arch/mips/configs/jazz_defconfig index 14c2ab3b2674..d22df61833a8 100644 --- a/trunk/arch/mips/configs/jazz_defconfig +++ b/trunk/arch/mips/configs/jazz_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set CONFIG_MACH_JAZZ=y @@ -1373,7 +1374,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/jmr3927_defconfig b/trunk/arch/mips/configs/jmr3927_defconfig index 4d66c44cced8..5380f1f582d9 100644 --- a/trunk/arch/mips/configs/jmr3927_defconfig +++ b/trunk/arch/mips/configs/jmr3927_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -834,7 +835,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y # CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/lasat_defconfig b/trunk/arch/mips/configs/lasat_defconfig index 08d481e3d42a..044074db7e55 100644 --- a/trunk/arch/mips/configs/lasat_defconfig +++ b/trunk/arch/mips/configs/lasat_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -797,7 +798,7 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/lemote2f_defconfig b/trunk/arch/mips/configs/lemote2f_defconfig deleted file mode 100644 index b71a0a4fb95f..000000000000 --- a/trunk/arch/mips/configs/lemote2f_defconfig +++ /dev/null @@ -1,1835 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc6 -# Mon Nov 9 23:42:42 2009 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_AR7 is not set -# CONFIG_BCM47XX is not set -# CONFIG_BCM63XX is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -CONFIG_MACH_LOONGSON=y -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_NEC_MARKEINS is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SNI_RM is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MIKROTIK_RB532 is not set -# CONFIG_WR_PPMC is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set -# CONFIG_ALCHEMY_GPIO_INDIRECT is not set -CONFIG_ARCH_SPARSEMEM_ENABLE=y -# CONFIG_LEMOTE_FULOONG2E is not set -CONFIG_LEMOTE_MACH2F=y -CONFIG_CS5536=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_CEVT_R4K_LIB=y -CONFIG_CEVT_R4K=y -CONFIG_CSRC_R4K_LIB=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_EARLY_PRINTK=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_I8259=y -# CONFIG_NO_IOPORT is not set -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_LOONGSON2E is not set -CONFIG_CPU_LOONGSON2F=y -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -# CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_SYS_SUPPORTS_ZBOOT=y -CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y -CONFIG_CPU_LOONGSON2=y -CONFIG_SYS_HAS_CPU_LOONGSON2F=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -# CONFIG_32BIT is not set -CONFIG_64BIT=y -# CONFIG_PAGE_SIZE_4KB is not set -# CONFIG_PAGE_SIZE_8KB is not set -CONFIG_PAGE_SIZE_16KB=y -# CONFIG_PAGE_SIZE_32KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -CONFIG_CPU_HAS_WB=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_SELECT_MEMORY_MODEL=y -# CONFIG_FLATMEM_MANUAL is not set -# CONFIG_DISCONTIGMEM_MANUAL is not set -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_SPARSEMEM_STATIC=y - -# -# Memory hotplug is currently incompatible with Software Suspend -# -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_256 is not set -# CONFIG_HZ_1000 is not set -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=250 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -# CONFIG_KEXEC is not set -# CONFIG_SECCOMP is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -# CONFIG_TASKSTATS is not set -CONFIG_AUDIT=y - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=64 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=15 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Kernel Performance Events And Counters -# -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_PCI_QUIRKS=y -CONFIG_SLUB_DEBUG=y -CONFIG_COMPAT_BRK=y -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_SYSCALL_WRAPPERS=y - -# -# GCOV-based kernel profiling -# -# CONFIG_SLOW_WORK is not set -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLOCK_COMPAT=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_FREEZER=y - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_PCI_LEGACY=y -# CONFIG_PCI_STUB is not set -# CONFIG_PCI_IOV is not set -CONFIG_ISA=y -CONFIG_MMU=y -# CONFIG_PCCARD is not set -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set -CONFIG_MIPS32_COMPAT=y -CONFIG_COMPAT=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_MIPS32_O32=y -CONFIG_MIPS32_N32=y -CONFIG_BINFMT_ELF32=y - -# -# Power management options -# -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_HIBERNATION_NVS=y -CONFIG_HIBERNATION=y -CONFIG_PM_STD_PARTITION="/dev/hda3" -# CONFIG_PM_RUNTIME is not set -CONFIG_NET=y -CONFIG_COMPAT_NETLINK_MESSAGES=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_LRO=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=y -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_VEGAS is not set -# CONFIG_TCP_CONG_SCALABLE is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_VENO is not set -# CONFIG_TCP_CONG_YEAH is not set -# CONFIG_TCP_CONG_ILLINOIS is not set -CONFIG_DEFAULT_BIC=y -# CONFIG_DEFAULT_CUBIC is not set -# CONFIG_DEFAULT_HTCP is not set -# CONFIG_DEFAULT_VEGAS is not set -# CONFIG_DEFAULT_WESTWOOD is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="bic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=m -CONFIG_IPV6_PRIVACY=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -# CONFIG_INET6_AH is not set -# CONFIG_INET6_ESP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_INET6_XFRM_MODE_TRANSPORT=m -CONFIG_INET6_XFRM_MODE_TUNNEL=m -CONFIG_INET6_XFRM_MODE_BEET=m -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -CONFIG_IPV6_SIT=m -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y - -# -# Core Netfilter Configuration -# -# CONFIG_NETFILTER_NETLINK_QUEUE is not set -# CONFIG_NETFILTER_NETLINK_LOG is not set -# CONFIG_NF_CONNTRACK is not set -# CONFIG_NETFILTER_XTABLES is not set -# CONFIG_IP_VS is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_NF_DEFRAG_IPV4 is not set -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# IPv6: Netfilter Configuration -# -# CONFIG_IP6_NF_QUEUE is not set -# CONFIG_IP6_NF_IPTABLES is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -# CONFIG_NET_SCH_CBQ is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_MULTIQ is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_SCH_DRR is not set -# CONFIG_NET_SCH_INGRESS is not set - -# -# Classification -# -CONFIG_NET_CLS=y -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_TCINDEX is not set -# CONFIG_NET_CLS_ROUTE4 is not set -# CONFIG_NET_CLS_FW is not set -# CONFIG_NET_CLS_U32 is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_CLS_FLOW is not set -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_STACK=32 -# CONFIG_NET_EMATCH_CMP is not set -# CONFIG_NET_EMATCH_NBYTE is not set -# CONFIG_NET_EMATCH_U32 is not set -# CONFIG_NET_EMATCH_META is not set -# CONFIG_NET_EMATCH_TEXT is not set -CONFIG_NET_CLS_ACT=y -# CONFIG_NET_ACT_POLICE is not set -# CONFIG_NET_ACT_GACT is not set -# CONFIG_NET_ACT_MIRRED is not set -# CONFIG_NET_ACT_NAT is not set -# CONFIG_NET_ACT_PEDIT is not set -# CONFIG_NET_ACT_SIMP is not set -# CONFIG_NET_ACT_SKBEDIT is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -# CONFIG_LIB80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -# CONFIG_WIMAX is not set -CONFIG_RFKILL=m -# CONFIG_RFKILL_INPUT is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -# CONFIG_PARPORT is not set -# CONFIG_PNP is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=y -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=8192 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_MISC_DEVICES=y -# CONFIG_PHANTOM is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_CB710_CORE is not set -CONFIG_HAVE_IDE=y -CONFIG_IDE=y - -# -# Please see Documentation/ide/ide.txt for help/info on IDE drives -# -CONFIG_IDE_XFER_MODE=y -CONFIG_IDE_TIMINGS=y -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_IDE_GD=y -CONFIG_IDE_GD_ATA=y -# CONFIG_IDE_GD_ATAPI is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_IDE_TASK_IOCTL=y -CONFIG_IDE_PROC_FS=y - -# -# IDE chipset support/bugfixes -# -# CONFIG_IDE_GENERIC is not set -# CONFIG_BLK_DEV_PLATFORM is not set -CONFIG_BLK_DEV_IDEDMA_SFF=y - -# -# PCI IDE chipsets support -# -CONFIG_BLK_DEV_IDEPCI=y -# CONFIG_IDEPCI_PCIBUS_ORDER is not set -# CONFIG_BLK_DEV_OFFBOARD is not set -CONFIG_BLK_DEV_GENERIC=y -# CONFIG_BLK_DEV_OPTI621 is not set -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -CONFIG_BLK_DEV_AMD74XX=y -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_JMICRON is not set -# CONFIG_BLK_DEV_SC1200 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT8172 is not set -# CONFIG_BLK_DEV_IT8213 is not set -# CONFIG_BLK_DEV_IT821X is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -# CONFIG_BLK_DEV_VIA82CXXX is not set -# CONFIG_BLK_DEV_TC86C001 is not set - -# -# Other IDE chipsets support -# - -# -# Note: most of these also require special kernel boot parameters -# -# CONFIG_BLK_DEV_4DRIVES is not set -# CONFIG_BLK_DEV_ALI14XX is not set -# CONFIG_BLK_DEV_DTC2278 is not set -# CONFIG_BLK_DEV_HT6560B is not set -# CONFIG_BLK_DEV_QD65XX is not set -# CONFIG_BLK_DEV_UMC8672 is not set -CONFIG_BLK_DEV_IDEDMA=y - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=m -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=m -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -CONFIG_CHR_DEV_SG=m -# CONFIG_CHR_DEV_SCH is not set -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# You can enable one or both FireWire driver stacks. -# - -# -# See the help texts for more information. -# -# CONFIG_FIREWIRE is not set -# CONFIG_IEEE1394 is not set -# CONFIG_I2O is not set -CONFIG_NETDEVICES=y -# CONFIG_IFB is not set -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_ARCNET is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ETHOC is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_DNET is not set -# CONFIG_NET_TULIP is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_AC3200 is not set -# CONFIG_APRICOT is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_CS89x0 is not set -# CONFIG_TC35815 is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -CONFIG_8139TOO=y -# CONFIG_8139TOO_PIO is not set -CONFIG_8139TOO_TUNE_TWISTER=y -# CONFIG_8139TOO_8129 is not set -# CONFIG_8139_OLD_RX_RESET is not set -# CONFIG_R6040 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SMSC9420 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_SC92031 is not set -# CONFIG_ATL2 is not set -CONFIG_NETDEV_1000=y -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_E1000E is not set -# CONFIG_IP1000 is not set -# CONFIG_IGB is not set -# CONFIG_IGBVF is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -CONFIG_R8169=y -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_CNIC is not set -# CONFIG_QLA3XXX is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_ATL1C is not set -# CONFIG_JME is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_TR is not set -CONFIG_WLAN=y -CONFIG_WLAN_PRE80211=y -# CONFIG_STRIP is not set -# CONFIG_WAVELAN is not set -CONFIG_WLAN_80211=y -# CONFIG_LIBERTAS is not set -# CONFIG_ATMEL is not set -# CONFIG_PRISM54 is not set -# CONFIG_USB_ZD1201 is not set -# CONFIG_HOSTAP is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_USB_HSO is not set -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -# CONFIG_MOUSE_PS2_ALPS is not set -# CONFIG_MOUSE_PS2_LOGIPS2PP is not set -CONFIG_MOUSE_PS2_SYNAPTICS=y -# CONFIG_MOUSE_PS2_TRACKPOINT is not set -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_INPORT is not set -# CONFIG_MOUSE_LOGIBM is not set -# CONFIG_MOUSE_PC110PAD is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_COMPUTONE is not set -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set -# CONFIG_DIGIEPCA is not set -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -# CONFIG_ISI is not set -# CONFIG_SYNCLINKMP is not set -# CONFIG_SYNCLINK_GT is not set -# CONFIG_N_HDLC is not set -# CONFIG_RISCOM8 is not set -# CONFIG_SPECIALIX is not set -# CONFIG_STALDRV is not set -# CONFIG_NOZOMI is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_PCI is not set -CONFIG_SERIAL_8250_NR_UARTS=16 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_FOURPORT=y -# CONFIG_SERIAL_8250_ACCENT is not set -# CONFIG_SERIAL_8250_BOCA is not set -# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set -# CONFIG_SERIAL_8250_HUB6 is not set -# CONFIG_SERIAL_8250_SHARE_IRQ is not set -# CONFIG_SERIAL_8250_DETECT_IRQ is not set -# CONFIG_SERIAL_8250_RSA is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=16 -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -CONFIG_RTC=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_DEVPORT=y -# CONFIG_I2C is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -CONFIG_THERMAL=y -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set -CONFIG_MEDIA_SUPPORT=m - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -# CONFIG_MEDIA_ATTACH is not set -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_PMS is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_STRADIS is not set -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STV680 is not set -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_PWC is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set -# CONFIG_RADIO_ADAPTERS is not set -# CONFIG_DAB is not set - -# -# Graphics support -# -CONFIG_VGA_ARB=y -# CONFIG_DRM is not set -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=y -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -# CONFIG_FB_DDC is not set -CONFIG_FB_BOOT_VESA_SUPPORT=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -CONFIG_FB_SIS=y -CONFIG_FB_SIS_300=y -CONFIG_FB_SIS_315=y -# CONFIG_FB_VIA is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_FONT_6x11=y -CONFIG_FONT_7x14=y -CONFIG_FONT_PEARL_8x8=y -CONFIG_FONT_ACORN_8x8=y -CONFIG_FONT_MINI_4x6=y -CONFIG_FONT_SUN8x16=y -CONFIG_FONT_SUN12x22=y -CONFIG_FONT_10x18=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=m -# CONFIG_SOUND_OSS_CORE is not set -CONFIG_SND=m -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_RTCTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -# CONFIG_SND_SUPPORT_OLD_API is not set -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_VMASTER=y -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_AC97_CODEC=m -# CONFIG_SND_DRIVERS is not set -CONFIG_SND_PCI=y -# CONFIG_SND_AD1889 is not set -# CONFIG_SND_ALS300 is not set -# CONFIG_SND_ALI5451 is not set -# CONFIG_SND_ATIIXP is not set -# CONFIG_SND_ATIIXP_MODEM is not set -# CONFIG_SND_AU8810 is not set -# CONFIG_SND_AU8820 is not set -# CONFIG_SND_AU8830 is not set -# CONFIG_SND_AW2 is not set -# CONFIG_SND_AZT3328 is not set -# CONFIG_SND_BT87X is not set -# CONFIG_SND_CA0106 is not set -# CONFIG_SND_CMIPCI is not set -# CONFIG_SND_OXYGEN is not set -# CONFIG_SND_CS4281 is not set -# CONFIG_SND_CS46XX is not set -CONFIG_SND_CS5535AUDIO=m -# CONFIG_SND_CTXFI is not set -# CONFIG_SND_DARLA20 is not set -# CONFIG_SND_GINA20 is not set -# CONFIG_SND_LAYLA20 is not set -# CONFIG_SND_DARLA24 is not set -# CONFIG_SND_GINA24 is not set -# CONFIG_SND_LAYLA24 is not set -# CONFIG_SND_MONA is not set -# CONFIG_SND_MIA is not set -# CONFIG_SND_ECHO3G is not set -# CONFIG_SND_INDIGO is not set -# CONFIG_SND_INDIGOIO is not set -# CONFIG_SND_INDIGODJ is not set -# CONFIG_SND_INDIGOIOX is not set -# CONFIG_SND_INDIGODJX is not set -# CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_ENS1370 is not set -# CONFIG_SND_ENS1371 is not set -# CONFIG_SND_ES1938 is not set -# CONFIG_SND_ES1968 is not set -# CONFIG_SND_FM801 is not set -# CONFIG_SND_HDA_INTEL is not set -# CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set -# CONFIG_SND_HIFIER is not set -# CONFIG_SND_ICE1712 is not set -# CONFIG_SND_ICE1724 is not set -# CONFIG_SND_INTEL8X0 is not set -# CONFIG_SND_INTEL8X0M is not set -# CONFIG_SND_KORG1212 is not set -# CONFIG_SND_LX6464ES is not set -# CONFIG_SND_MAESTRO3 is not set -# CONFIG_SND_MIXART is not set -# CONFIG_SND_NM256 is not set -# CONFIG_SND_PCXHR is not set -# CONFIG_SND_RIPTIDE is not set -# CONFIG_SND_RME32 is not set -# CONFIG_SND_RME96 is not set -# CONFIG_SND_RME9652 is not set -# CONFIG_SND_SONICVIBES is not set -# CONFIG_SND_TRIDENT is not set -# CONFIG_SND_VIA82XX is not set -# CONFIG_SND_VIA82XX_MODEM is not set -# CONFIG_SND_VIRTUOSO is not set -# CONFIG_SND_VX222 is not set -# CONFIG_SND_YMFPCI is not set -# CONFIG_SND_MIPS is not set -# CONFIG_SND_USB is not set -# CONFIG_SND_SOC is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_AC97_BUS=m -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -CONFIG_HIDRAW=y - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -CONFIG_USB_HIDDEV=y - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG is not set -CONFIG_USB_OTG_WHITELIST=y -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_XHCI_HCD is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_UHCI_HCD=m -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_WHCI_HCD is not set -# CONFIG_USB_HWA_HCD is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -# CONFIG_USB_PRINTER is not set -CONFIG_USB_WDM=m -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=m -# CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -# CONFIG_USB_EZUSB is not set -CONFIG_USB_SERIAL_GENERIC=y -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP210X is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -# CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_UWB is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -CONFIG_STAGING=y -# CONFIG_STAGING_EXCLUDE_BUILD is not set -# CONFIG_ET131X is not set -# CONFIG_USB_IP_COMMON is not set -# CONFIG_PRISM2_USB is not set -# CONFIG_ECHO is not set -# CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set -# CONFIG_ALTERA_PCIE_CHDMA is not set -# CONFIG_RTL8187SE is not set -# CONFIG_RTL8192SU is not set -# CONFIG_RTL8192E is not set -# CONFIG_INPUT_MIMIO is not set -# CONFIG_TRANZPORT is not set - -# -# Android -# - -# -# Qualcomm MSM Camera And Video -# - -# -# Camera Sensor Selection -# -# CONFIG_INPUT_GPIO is not set -# CONFIG_DST is not set -# CONFIG_POHMELFS is not set -# CONFIG_B3DFG is not set -# CONFIG_PLAN9AUTH is not set -# CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set -# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -# CONFIG_VT6655 is not set -# CONFIG_VT6656 is not set -# CONFIG_FB_UDL is not set -# CONFIG_VME_BUS is not set - -# -# RAR Register Driver -# -# CONFIG_RAR_REGISTER is not set -# CONFIG_IIO is not set -CONFIG_FB_SM7XX=y -CONFIG_FB_SM7XX_ACCEL=y - -# -# File systems -# -# CONFIG_EXT2_FS is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_QUOTA=y -# CONFIG_QUOTA_NETLINK_INTERFACE is not set -CONFIG_PRINT_QUOTA_WARNING=y -# CONFIG_QFMT_V1 is not set -# CONFIG_QFMT_V2 is not set -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=m -# CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -# CONFIG_MISC_FILESYSTEMS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -# CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set -CONFIG_LOCKD=m -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=m -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf-8" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -# CONFIG_MAGIC_SYSRQ is not set -CONFIG_STRIP_ASM_SYMS=y -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_CMDLINE_BOOL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_HIFN_795X is not set -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_AUDIT_GENERIC=y -CONFIG_ZLIB_INFLATE=m -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/mips/configs/malta_defconfig b/trunk/arch/mips/configs/malta_defconfig index d3c601206db2..3f01870b4d65 100644 --- a/trunk/arch/mips/configs/malta_defconfig +++ b/trunk/arch/mips/configs/malta_defconfig @@ -10,6 +10,7 @@ CONFIG_MIPS=y # CONFIG_ZONE_DMA=y # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -1590,7 +1591,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/markeins_defconfig b/trunk/arch/mips/configs/markeins_defconfig index 6a325c02b63c..d001f7e87418 100644 --- a/trunk/arch/mips/configs/markeins_defconfig +++ b/trunk/arch/mips/configs/markeins_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1365,9 +1366,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyS0,115200 mem=192m ip=bootp root=/dev/nfs rw" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/mipssim_defconfig b/trunk/arch/mips/configs/mipssim_defconfig index f77a34e0f938..7358454deaa6 100644 --- a/trunk/arch/mips/configs/mipssim_defconfig +++ b/trunk/arch/mips/configs/mipssim_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -634,9 +635,7 @@ CONFIG_FORCED_INLINING=y # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_FAULT_INJECTION is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp" -# CONFIG_CMDLINE_OVERRIDE is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_RUNTIME_DEBUG is not set diff --git a/trunk/arch/mips/configs/mpc30x_defconfig b/trunk/arch/mips/configs/mpc30x_defconfig index 17203056b22b..8c720e51795b 100644 --- a/trunk/arch/mips/configs/mpc30x_defconfig +++ b/trunk/arch/mips/configs/mpc30x_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -816,9 +817,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="mem=32M console=ttyVR0,19200 ide0=0x170,0x376,73" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/msp71xx_defconfig b/trunk/arch/mips/configs/msp71xx_defconfig index 000d185ddf42..ecbc030b7b6c 100644 --- a/trunk/arch/mips/configs/msp71xx_defconfig +++ b/trunk/arch/mips/configs/msp71xx_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1411,7 +1412,7 @@ CONFIG_FORCED_INLINING=y # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_FAULT_INJECTION is not set CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_RUNTIME_DEBUG is not set # CONFIG_MIPS_UNCACHED is not set diff --git a/trunk/arch/mips/configs/mtx1_defconfig b/trunk/arch/mips/configs/mtx1_defconfig index 144b94d9a6ad..9477f040796d 100644 --- a/trunk/arch/mips/configs/mtx1_defconfig +++ b/trunk/arch/mips/configs/mtx1_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # CONFIG_MACH_ALCHEMY=y +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -3017,7 +3018,7 @@ CONFIG_MAGIC_SYSRQ=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/pb1100_defconfig b/trunk/arch/mips/configs/pb1100_defconfig index ddf67f639194..be8091ef0a79 100644 --- a/trunk/arch/mips/configs/pb1100_defconfig +++ b/trunk/arch/mips/configs/pb1100_defconfig @@ -23,6 +23,7 @@ CONFIG_MIPS_PB1100=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1082,7 +1083,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/pb1500_defconfig b/trunk/arch/mips/configs/pb1500_defconfig index 5ec60836b645..e74ba794c789 100644 --- a/trunk/arch/mips/configs/pb1500_defconfig +++ b/trunk/arch/mips/configs/pb1500_defconfig @@ -23,6 +23,7 @@ CONFIG_MIPS_PB1500=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1199,7 +1200,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/pb1550_defconfig b/trunk/arch/mips/configs/pb1550_defconfig index 6647642b5d97..1d896fd830da 100644 --- a/trunk/arch/mips/configs/pb1550_defconfig +++ b/trunk/arch/mips/configs/pb1550_defconfig @@ -23,6 +23,7 @@ CONFIG_MIPS_PB1550=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1192,7 +1193,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/pnx8335-stb225_defconfig b/trunk/arch/mips/configs/pnx8335-stb225_defconfig index 848344d588d1..fef4d31c2055 100644 --- a/trunk/arch/mips/configs/pnx8335-stb225_defconfig +++ b/trunk/arch/mips/configs/pnx8335-stb225_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -1033,7 +1034,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set # CONFIG_KERNEL_TESTS is not set -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/pnx8550-jbs_defconfig b/trunk/arch/mips/configs/pnx8550-jbs_defconfig index 9d721fdccb30..e10c7116c3c2 100644 --- a/trunk/arch/mips/configs/pnx8550-jbs_defconfig +++ b/trunk/arch/mips/configs/pnx8550-jbs_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1214,9 +1215,7 @@ CONFIG_DEBUG_MUTEXES=y CONFIG_FORCED_INLINING=y # CONFIG_RCU_TORTURE_TEST is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp" -# CONFIG_CMDLINE_OVERRIDE is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_RUNTIME_DEBUG is not set diff --git a/trunk/arch/mips/configs/pnx8550-stb810_defconfig b/trunk/arch/mips/configs/pnx8550-stb810_defconfig index ab07ec08c6fa..5ed3c8dfa0a1 100644 --- a/trunk/arch/mips/configs/pnx8550-stb810_defconfig +++ b/trunk/arch/mips/configs/pnx8550-stb810_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1204,9 +1205,7 @@ CONFIG_DEBUG_SLAB=y CONFIG_FORCED_INLINING=y # CONFIG_RCU_TORTURE_TEST is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp" -# CONFIG_CMDLINE_OVERRIDE is not set # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_RUNTIME_DEBUG is not set diff --git a/trunk/arch/mips/configs/powertv_defconfig b/trunk/arch/mips/configs/powertv_defconfig deleted file mode 100644 index 7291633d81cc..000000000000 --- a/trunk/arch/mips/configs/powertv_defconfig +++ /dev/null @@ -1,1550 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.31-rc5 -# Fri Aug 28 14:49:33 2009 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_AR7 is not set -# CONFIG_BCM47XX is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_NEC_MARKEINS is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -CONFIG_POWERTV=y -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SNI_RM is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MIKROTIK_RB532 is not set -# CONFIG_WR_PPMC is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set -# CONFIG_ALCHEMY_GPIO_INDIRECT is not set -# CONFIG_MIN_RUNTIME_RESOURCES is not set -# CONFIG_BOOTLOADER_DRIVER is not set -CONFIG_BOOTLOADER_FAMILY="R2" -CONFIG_CSRC_POWERTV=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_CEVT_R4K_LIB=y -CONFIG_CEVT_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -# CONFIG_EARLY_PRINTK is not set -CONFIG_SYS_HAS_EARLY_PRINTK=y -# CONFIG_NO_IOPORT is not set -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 - -# -# CPU selection -# -# CONFIG_CPU_LOONGSON2 is not set -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -# CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_CPU_MIPS32=y -CONFIG_CPU_MIPSR2=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_HARDWARE_WATCHPOINTS=y - -# -# Kernel type -# -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set -# CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_32KB is not set -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_MIPSR2_IRQ_VI=y -CONFIG_CPU_MIPSR2_IRQ_EI=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -# CONFIG_HIGHMEM is not set -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -# CONFIG_KEXEC is not set -# CONFIG_SECCOMP is not set -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -# CONFIG_SWAP is not set -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set -# CONFIG_IKCONFIG is not set -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set -CONFIG_RELAY=y -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -# CONFIG_PCSPKR_PLATFORM is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -# CONFIG_EPOLL is not set -# CONFIG_SIGNALFD is not set -CONFIG_TIMERFD=y -# CONFIG_EVENTFD is not set -CONFIG_SHMEM=y -CONFIG_AIO=y - -# -# Performance Counters -# -# CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_PCI_QUIRKS=y -# CONFIG_SLUB_DEBUG is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_COMPAT_BRK=y -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_BLOCK=y -CONFIG_LBDAF=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_DEFAULT_IOSCHED="noop" -# CONFIG_PROBE_INITRD_HEADER is not set -# CONFIG_FREEZER is not set - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCI_LEGACY is not set -# CONFIG_PCI_DEBUG is not set -# CONFIG_PCI_STUB is not set -# CONFIG_PCI_IOV is not set -CONFIG_MMU=y -# CONFIG_PCCARD is not set -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set -CONFIG_TRAD_SIGNALS=y - -# -# Power management options -# -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_PM is not set -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_IPCOMP=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_ASK_IP_FIB_HASH=y -# CONFIG_IP_FIB_TRIE is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_MULTIPLE_TABLES is not set -# CONFIG_IP_ROUTE_MULTIPATH is not set -# CONFIG_IP_ROUTE_VERBOSE is not set -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=y -CONFIG_IPV6_PRIVACY=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -CONFIG_INET6_IPCOMP=y -# CONFIG_IPV6_MIP6 is not set -CONFIG_INET6_XFRM_TUNNEL=y -CONFIG_INET6_TUNNEL=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set -# CONFIG_IPV6_SIT is not set -CONFIG_IPV6_TUNNEL=y -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y -# CONFIG_BRIDGE_NETFILTER is not set - -# -# Core Netfilter Configuration -# -# CONFIG_NETFILTER_NETLINK_QUEUE is not set -# CONFIG_NETFILTER_NETLINK_LOG is not set -# CONFIG_NF_CONNTRACK is not set -CONFIG_NETFILTER_XTABLES=y -# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set -# CONFIG_NETFILTER_XT_TARGET_MARK is not set -# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set -# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set -# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set -# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set -# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set -# CONFIG_NETFILTER_XT_MATCH_DCCP is not set -# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -# CONFIG_NETFILTER_XT_MATCH_ESP is not set -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set -# CONFIG_NETFILTER_XT_MATCH_HL is not set -# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set -# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set -# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set -# CONFIG_NETFILTER_XT_MATCH_MAC is not set -# CONFIG_NETFILTER_XT_MATCH_MARK is not set -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -# CONFIG_NETFILTER_XT_MATCH_OWNER is not set -# CONFIG_NETFILTER_XT_MATCH_POLICY is not set -# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set -# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set -# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set -# CONFIG_NETFILTER_XT_MATCH_REALM is not set -# CONFIG_NETFILTER_XT_MATCH_RECENT is not set -# CONFIG_NETFILTER_XT_MATCH_SCTP is not set -# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set -# CONFIG_NETFILTER_XT_MATCH_STRING is not set -# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set -# CONFIG_NETFILTER_XT_MATCH_TIME is not set -# CONFIG_NETFILTER_XT_MATCH_U32 is not set -# CONFIG_IP_VS is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_NF_DEFRAG_IPV4 is not set -# CONFIG_IP_NF_QUEUE is not set -CONFIG_IP_NF_IPTABLES=y -# CONFIG_IP_NF_MATCH_ADDRTYPE is not set -# CONFIG_IP_NF_MATCH_AH is not set -# CONFIG_IP_NF_MATCH_ECN is not set -# CONFIG_IP_NF_MATCH_TTL is not set -CONFIG_IP_NF_FILTER=y -# CONFIG_IP_NF_TARGET_REJECT is not set -# CONFIG_IP_NF_TARGET_LOG is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -# CONFIG_IP_NF_MANGLE is not set -# CONFIG_IP_NF_TARGET_TTL is not set -# CONFIG_IP_NF_RAW is not set -CONFIG_IP_NF_ARPTABLES=y -CONFIG_IP_NF_ARPFILTER=y -# CONFIG_IP_NF_ARP_MANGLE is not set - -# -# IPv6: Netfilter Configuration -# -# CONFIG_IP6_NF_QUEUE is not set -CONFIG_IP6_NF_IPTABLES=y -# CONFIG_IP6_NF_MATCH_AH is not set -# CONFIG_IP6_NF_MATCH_EUI64 is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_MH is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_TARGET_HL is not set -# CONFIG_IP6_NF_TARGET_LOG is not set -CONFIG_IP6_NF_FILTER=y -# CONFIG_IP6_NF_TARGET_REJECT is not set -# CONFIG_IP6_NF_MANGLE is not set -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -CONFIG_STP=y -CONFIG_BRIDGE=y -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -# CONFIG_NET_SCH_CBQ is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_MULTIQ is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TEQL is not set -CONFIG_NET_SCH_TBF=y -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_SCH_DRR is not set - -# -# Classification -# -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_TCINDEX is not set -# CONFIG_NET_CLS_ROUTE4 is not set -# CONFIG_NET_CLS_FW is not set -# CONFIG_NET_CLS_U32 is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_CLS_FLOW is not set -# CONFIG_NET_EMATCH is not set -# CONFIG_NET_CLS_ACT is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_INTEL_VR_NOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -# CONFIG_MTD_NAND_VERIFY_WRITE is not set -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_CAFE is not set -# CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=32768 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_PROC_FS is not set - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -CONFIG_ATA=y -# CONFIG_ATA_NONSTANDARD is not set -CONFIG_SATA_PMP=y -# CONFIG_SATA_AHCI is not set -# CONFIG_SATA_SIL24 is not set -CONFIG_ATA_SFF=y -# CONFIG_SATA_SVW is not set -# CONFIG_ATA_PIIX is not set -# CONFIG_SATA_MV is not set -# CONFIG_SATA_NV is not set -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set -# CONFIG_SATA_PROMISE is not set -# CONFIG_SATA_SX4 is not set -# CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set -# CONFIG_SATA_INIC162X is not set -# CONFIG_PATA_ALI is not set -# CONFIG_PATA_AMD is not set -# CONFIG_PATA_ARTOP is not set -# CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CS5520 is not set -# CONFIG_PATA_CS5530 is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_ATA_GENERIC is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_OLDPIIX is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_NS87415 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RZ1000 is not set -# CONFIG_PATA_SC1200 is not set -# CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_SCH is not set -# CONFIG_MD is not set -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# You can enable one or both FireWire driver stacks. -# - -# -# See the help texts for more information. -# -# CONFIG_FIREWIRE is not set -# CONFIG_IEEE1394 is not set -# CONFIG_I2O is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_ARCNET is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ETHOC is not set -# CONFIG_DNET is not set -# CONFIG_NET_TULIP is not set -# CONFIG_HP100 is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_NET_PCI is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_ATL2 is not set -CONFIG_NETDEV_1000=y -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_E1000E is not set -# CONFIG_IP1000 is not set -# CONFIG_IGB is not set -# CONFIG_IGBVF is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_CNIC is not set -# CONFIG_QLA3XXX is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_ATL1C is not set -# CONFIG_JME is not set -CONFIG_NETDEV_10000=y -# CONFIG_CHELSIO_T1 is not set -CONFIG_CHELSIO_T3_DEPENDS=y -# CONFIG_CHELSIO_T3 is not set -# CONFIG_ENIC is not set -# CONFIG_IXGBE is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_VXGE is not set -# CONFIG_MYRI10GE is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_NIU is not set -# CONFIG_MLX4_EN is not set -# CONFIG_MLX4_CORE is not set -# CONFIG_TEHUTI is not set -# CONFIG_BNX2X is not set -# CONFIG_QLGE is not set -# CONFIG_SFC is not set -# CONFIG_BE2NET is not set -# CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -CONFIG_USB_RTL8150=y -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NET_FC is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_NOZOMI is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -# CONFIG_LEGACY_PTYS is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_DEVPORT=y -# CONFIG_I2C is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_DRM is not set -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_SOUND is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set -# CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -CONFIG_USB_HIDDEV=y - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_XHCI_HCD is not set -CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -# CONFIG_USB_UHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_WHCI_HCD is not set -# CONFIG_USB_HWA_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_CONSOLE=y -# CONFIG_USB_EZUSB is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -CONFIG_USB_SERIAL_CP210X=y -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -# CONFIG_USB_SERIAL_FTDI_SIO is not set -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -# CONFIG_USB_SERIAL_PL2303 is not set -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -# CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_UWB is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -CONFIG_RTC_LIB=y -# CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=y -# CONFIG_CUSE is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -# CONFIG_MSDOS_FS is not set -# CONFIG_VFAT_FS is not set -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_CRAMFS=y -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set -CONFIG_CMDLINE_BOOL=y -CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M" -# CONFIG_CMDLINE_OVERRIDE is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_RUNTIME_DEBUG is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_AUTHENC=y -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=y -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/mips/configs/rb532_defconfig b/trunk/arch/mips/configs/rb532_defconfig index 57a50483abdf..f40c3a04739d 100644 --- a/trunk/arch/mips/configs/rb532_defconfig +++ b/trunk/arch/mips/configs/rb532_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -1203,7 +1204,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/rbtx49xx_defconfig b/trunk/arch/mips/configs/rbtx49xx_defconfig index 21c2022d46ee..6c6a19aebe1f 100644 --- a/trunk/arch/mips/configs/rbtx49xx_defconfig +++ b/trunk/arch/mips/configs/rbtx49xx_defconfig @@ -10,6 +10,7 @@ CONFIG_MIPS=y # # CONFIG_MACH_ALCHEMY is not set # CONFIG_AR7 is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set @@ -283,6 +284,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_PROBE_INITRD_HEADER is not set # CONFIG_FREEZER is not set # @@ -1061,7 +1063,7 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/rm200_defconfig b/trunk/arch/mips/configs/rm200_defconfig index 790362890033..e53b8d096cfc 100644 --- a/trunk/arch/mips/configs/rm200_defconfig +++ b/trunk/arch/mips/configs/rm200_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -1693,7 +1694,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # # Security options diff --git a/trunk/arch/mips/configs/sb1250-swarm_defconfig b/trunk/arch/mips/configs/sb1250-swarm_defconfig index 7f07bf02b838..7f38c0b956f3 100644 --- a/trunk/arch/mips/configs/sb1250-swarm_defconfig +++ b/trunk/arch/mips/configs/sb1250-swarm_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -960,7 +961,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # CONFIG_SB1XXX_CORELIS is not set # diff --git a/trunk/arch/mips/configs/tb0219_defconfig b/trunk/arch/mips/configs/tb0219_defconfig index c54d1128f9a3..b5059881bc7e 100644 --- a/trunk/arch/mips/configs/tb0219_defconfig +++ b/trunk/arch/mips/configs/tb0219_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -891,9 +892,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/tb0226_defconfig b/trunk/arch/mips/configs/tb0226_defconfig index e7c5cd32a2bd..b06a716bf23f 100644 --- a/trunk/arch/mips/configs/tb0226_defconfig +++ b/trunk/arch/mips/configs/tb0226_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -894,9 +895,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="cca=3 mem=32M console=ttyVR0,115200" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/tb0287_defconfig b/trunk/arch/mips/configs/tb0287_defconfig index b50032ba4d01..46512cf7ce04 100644 --- a/trunk/arch/mips/configs/tb0287_defconfig +++ b/trunk/arch/mips/configs/tb0287_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set @@ -1076,9 +1077,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SAMPLES is not set -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="cca=3 mem=64M console=ttyVR0,115200 ip=any root=/dev/nfs" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/workpad_defconfig b/trunk/arch/mips/configs/workpad_defconfig index c02ba08b69ab..b437eb7f8672 100644 --- a/trunk/arch/mips/configs/workpad_defconfig +++ b/trunk/arch/mips/configs/workpad_defconfig @@ -9,6 +9,7 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -754,9 +755,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyVR0,19200 ide0=0x170,0x376,49 mem=16M" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/wrppmc_defconfig b/trunk/arch/mips/configs/wrppmc_defconfig index a35bc41389e5..06acc7482e4c 100644 --- a/trunk/arch/mips/configs/wrppmc_defconfig +++ b/trunk/arch/mips/configs/wrppmc_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -886,9 +887,7 @@ CONFIG_ENABLE_MUST_CHECK=y # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyS0,115200n8" -# CONFIG_CMDLINE_OVERRIDE is not set # # Security options diff --git a/trunk/arch/mips/configs/yosemite_defconfig b/trunk/arch/mips/configs/yosemite_defconfig index e3d68d651e7d..69feaf88b510 100644 --- a/trunk/arch/mips/configs/yosemite_defconfig +++ b/trunk/arch/mips/configs/yosemite_defconfig @@ -22,6 +22,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MIPS_DB1550 is not set # CONFIG_MIPS_DB1200 is not set # CONFIG_MIPS_MIRAGE is not set +# CONFIG_BASLER_EXCITE is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set @@ -823,7 +824,7 @@ CONFIG_DEBUG_MUTEXES=y CONFIG_FORCED_INLINING=y # CONFIG_RCU_TORTURE_TEST is not set CONFIG_CROSSCOMPILE=y -# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE="" # CONFIG_DEBUG_STACK_USAGE is not set # CONFIG_RUNTIME_DEBUG is not set diff --git a/trunk/arch/mips/fw/arc/cmdline.c b/trunk/arch/mips/fw/arc/cmdline.c index 5c8603c85f20..4ca4eef934a5 100644 --- a/trunk/arch/mips/fw/arc/cmdline.c +++ b/trunk/arch/mips/fw/arc/cmdline.c @@ -16,6 +16,11 @@ #undef DEBUG_CMDLINE +char * __init prom_getcmdline(void) +{ + return arcs_cmdline; +} + static char *ignored[] = { "ConsoleIn=", "ConsoleOut=", diff --git a/trunk/arch/mips/include/asm/asm-offsets.h b/trunk/arch/mips/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/mips/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/mips/include/asm/bootinfo.h b/trunk/arch/mips/include/asm/bootinfo.h index 09eee09780f2..f5dfaf6a1606 100644 --- a/trunk/arch/mips/include/asm/bootinfo.h +++ b/trunk/arch/mips/include/asm/bootinfo.h @@ -67,9 +67,9 @@ #define MACH_LEMOTE_ML2F7 3 #define MACH_LEMOTE_YL2F89 4 #define MACH_DEXXON_GDIUM2F10 5 -#define MACH_LEMOTE_NAS 6 -#define MACH_LEMOTE_LL2F 7 -#define MACH_LOONGSON_END 8 +#define MACH_LOONGSON_END 6 + +#define CL_SIZE COMMAND_LINE_SIZE extern char *system_type; const char *get_system_type(void); @@ -107,7 +107,7 @@ extern void free_init_pages(const char *what, /* * Initial kernel command line, usually setup by prom_init() */ -extern char arcs_cmdline[COMMAND_LINE_SIZE]; +extern char arcs_cmdline[CL_SIZE]; /* * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware diff --git a/trunk/arch/mips/include/asm/clock.h b/trunk/arch/mips/include/asm/clock.h deleted file mode 100644 index 83894aa7932c..000000000000 --- a/trunk/arch/mips/include/asm/clock.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef __ASM_MIPS_CLOCK_H -#define __ASM_MIPS_CLOCK_H - -#include -#include -#include -#include - -extern void (*cpu_wait) (void); - -struct clk; - -struct clk_ops { - void (*init) (struct clk *clk); - void (*enable) (struct clk *clk); - void (*disable) (struct clk *clk); - void (*recalc) (struct clk *clk); - int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id); - long (*round_rate) (struct clk *clk, unsigned long rate); -}; - -struct clk { - struct list_head node; - const char *name; - int id; - struct module *owner; - - struct clk *parent; - struct clk_ops *ops; - - struct kref kref; - - unsigned long rate; - unsigned long flags; -}; - -#define CLK_ALWAYS_ENABLED (1 << 0) -#define CLK_RATE_PROPAGATES (1 << 1) - -/* Should be defined by processor-specific code */ -void arch_init_clk_ops(struct clk_ops **, int type); - -int clk_init(void); - -int __clk_enable(struct clk *); -void __clk_disable(struct clk *); - -void clk_recalc_rate(struct clk *); - -int clk_register(struct clk *); -void clk_unregister(struct clk *); - -/* the exported API, in addition to clk_set_rate */ -/** - * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter - * @clk: clock source - * @rate: desired clock rate in Hz - * @algo_id: algorithm id to be passed down to ops->set_rate - * - * Returns success (0) or negative errno. - */ -int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id); - -#endif /* __ASM_MIPS_CLOCK_H */ diff --git a/trunk/arch/mips/include/asm/cop2.h b/trunk/arch/mips/include/asm/cop2.h deleted file mode 100644 index 6b04c98b7fad..000000000000 --- a/trunk/arch/mips/include/asm/cop2.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2009 Wind River Systems, - * written by Ralf Baechle - */ -#ifndef __ASM_COP2_H -#define __ASM_COP2_H - -enum cu2_ops { - CU2_EXCEPTION, - CU2_LWC2_OP, - CU2_LDC2_OP, - CU2_SWC2_OP, - CU2_SDC2_OP, -}; - -extern int register_cu2_notifier(struct notifier_block *nb); -extern int cu2_notifier_call_chain(unsigned long val, void *v); - -#endif /* __ASM_COP2_H */ diff --git a/trunk/arch/mips/include/asm/cpu.h b/trunk/arch/mips/include/asm/cpu.h index cf373a95fe4a..4b96d1a36056 100644 --- a/trunk/arch/mips/include/asm/cpu.h +++ b/trunk/arch/mips/include/asm/cpu.h @@ -154,8 +154,6 @@ #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ #define PRID_REV_VR4130 0x0080 #define PRID_REV_34K_V1_0_2 0x0022 -#define PRID_REV_LOONGSON2E 0x0002 -#define PRID_REV_LOONGSON2F 0x0003 /* * Older processors used to encode processor version and revision in two diff --git a/trunk/arch/mips/include/asm/elf.h b/trunk/arch/mips/include/asm/elf.h index 7a6a35dbe529..7990694cda22 100644 --- a/trunk/arch/mips/include/asm/elf.h +++ b/trunk/arch/mips/include/asm/elf.h @@ -326,6 +326,7 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ dump_task_fpu(tsk, elf_fpregs) +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This yields a mask that user programs can use to figure out what diff --git a/trunk/arch/mips/include/asm/fcntl.h b/trunk/arch/mips/include/asm/fcntl.h index e482fe90fe88..7c6681aa2ab8 100644 --- a/trunk/arch/mips/include/asm/fcntl.h +++ b/trunk/arch/mips/include/asm/fcntl.h @@ -19,7 +19,7 @@ #define FASYNC 0x1000 /* fcntl, for BSD compatibility */ #define O_LARGEFILE 0x2000 /* allow large file opens */ /* - * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using + * Before Linux 2.6.32 only O_DSYNC semantics were implemented, but using * the O_SYNC flag. We continue to use the existing numerical value * for O_DSYNC semantics now, but using the correct symbolic name for it. * This new value is used to request true Posix O_SYNC semantics. It is diff --git a/trunk/arch/mips/include/asm/fpu.h b/trunk/arch/mips/include/asm/fpu.h index 7fcef8ef3fab..8a3ef247659a 100644 --- a/trunk/arch/mips/include/asm/fpu.h +++ b/trunk/arch/mips/include/asm/fpu.h @@ -28,7 +28,15 @@ struct sigcontext; struct sigcontext32; +extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); +extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); + +extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); +extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); + extern void fpu_emulator_init_fpu(void); +extern int fpu_emulator_save_context(struct sigcontext __user *sc); +extern int fpu_emulator_restore_context(struct sigcontext __user *sc); extern void _init_fpu(void); extern void _save_fp(struct task_struct *); extern void _restore_fp(struct task_struct *); diff --git a/trunk/arch/mips/include/asm/fpu_emulator.h b/trunk/arch/mips/include/asm/fpu_emulator.h index aecada6f6117..e5189572956c 100644 --- a/trunk/arch/mips/include/asm/fpu_emulator.h +++ b/trunk/arch/mips/include/asm/fpu_emulator.h @@ -25,27 +25,17 @@ #include #include -#include - -#ifdef CONFIG_DEBUG_FS struct mips_fpu_emulator_stats { - local_t emulated; - local_t loads; - local_t stores; - local_t cp1ops; - local_t cp1xops; - local_t errors; + unsigned int emulated; + unsigned int loads; + unsigned int stores; + unsigned int cp1ops; + unsigned int cp1xops; + unsigned int errors; }; -DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); - -#define MIPS_FPU_EMU_INC_STATS(M) \ - cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M)) - -#else -#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0) -#endif /* CONFIG_DEBUG_FS */ +extern struct mips_fpu_emulator_stats fpuemustats; extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); diff --git a/trunk/arch/mips/include/asm/ftrace.h b/trunk/arch/mips/include/asm/ftrace.h index 3986cd8704f3..40a8c178f10d 100644 --- a/trunk/arch/mips/include/asm/ftrace.h +++ b/trunk/arch/mips/include/asm/ftrace.h @@ -1,90 +1 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive for - * more details. - * - * Copyright (C) 2009 DSLab, Lanzhou University, China - * Author: Wu Zhangjin - */ - -#ifndef _ASM_MIPS_FTRACE_H -#define _ASM_MIPS_FTRACE_H - -#ifdef CONFIG_FUNCTION_TRACER - -#define MCOUNT_ADDR ((unsigned long)(_mcount)) -#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ - -#ifndef __ASSEMBLY__ -extern void _mcount(void); -#define mcount _mcount - -#define safe_load(load, src, dst, error) \ -do { \ - asm volatile ( \ - "1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\ - " li %[" STR(error) "], 0\n" \ - "2:\n" \ - \ - ".section .fixup, \"ax\"\n" \ - "3: li %[" STR(error) "], 1\n" \ - " j 2b\n" \ - ".previous\n" \ - \ - ".section\t__ex_table,\"a\"\n\t" \ - STR(PTR) "\t1b, 3b\n\t" \ - ".previous\n" \ - \ - : [dst] "=&r" (dst), [error] "=r" (error)\ - : [src] "r" (src) \ - : "memory" \ - ); \ -} while (0) - -#define safe_store(store, src, dst, error) \ -do { \ - asm volatile ( \ - "1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\ - " li %[" STR(error) "], 0\n" \ - "2:\n" \ - \ - ".section .fixup, \"ax\"\n" \ - "3: li %[" STR(error) "], 1\n" \ - " j 2b\n" \ - ".previous\n" \ - \ - ".section\t__ex_table,\"a\"\n\t"\ - STR(PTR) "\t1b, 3b\n\t" \ - ".previous\n" \ - \ - : [error] "=r" (error) \ - : [dst] "r" (dst), [src] "r" (src)\ - : "memory" \ - ); \ -} while (0) - -#define safe_load_code(dst, src, error) \ - safe_load(STR(lw), src, dst, error) -#define safe_store_code(src, dst, error) \ - safe_store(STR(sw), src, dst, error) - -#define safe_load_stack(dst, src, error) \ - safe_load(STR(PTR_L), src, dst, error) - -#define safe_store_stack(src, dst, error) \ - safe_store(STR(PTR_S), src, dst, error) - - -#ifdef CONFIG_DYNAMIC_FTRACE -static inline unsigned long ftrace_call_adjust(unsigned long addr) -{ - return addr; -} - -struct dyn_arch_ftrace { -}; - -#endif /* CONFIG_DYNAMIC_FTRACE */ -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_FUNCTION_TRACER */ -#endif /* _ASM_MIPS_FTRACE_H */ +/* empty */ diff --git a/trunk/arch/mips/include/asm/irq.h b/trunk/arch/mips/include/asm/irq.h index 06960364c96b..09b08d05ff72 100644 --- a/trunk/arch/mips/include/asm/irq.h +++ b/trunk/arch/mips/include/asm/irq.h @@ -113,11 +113,36 @@ do { \ #endif -extern void do_IRQ(unsigned int irq); +/* + * do_IRQ handles all normal device IRQ's (the special + * SMP cross-CPU interrupts have their own specific + * handlers). + * + * Ideally there should be away to get this into kernel/irq/handle.c to + * avoid the overhead of a call for just a tiny function ... + */ +#define do_IRQ(irq) \ +do { \ + irq_enter(); \ + __DO_IRQ_SMTC_HOOK(irq); \ + generic_handle_irq(irq); \ + irq_exit(); \ +} while (0) #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF +/* + * To avoid inefficient and in some cases pathological re-checking of + * IRQ affinity, we have this variant that skips the affinity check. + */ + -extern void do_IRQ_no_affinity(unsigned int irq); +#define do_IRQ_no_affinity(irq) \ +do { \ + irq_enter(); \ + __NO_AFFINITY_IRQ_SMTC_HOOK(irq); \ + generic_handle_irq(irq); \ + irq_exit(); \ +} while (0) #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/trunk/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h b/trunk/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h new file mode 100644 index 000000000000..107104c3cd12 --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-excite/cpu-feature-overrides.h @@ -0,0 +1,48 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 Thomas Koeller + * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) + */ +#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H + +/* + * Basler eXcite has an RM9122 processor. + */ +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_dsp 0 +#define cpu_icache_snoops_remote_store 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_inclusive_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + +#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */ diff --git a/trunk/arch/mips/include/asm/mach-excite/excite.h b/trunk/arch/mips/include/asm/mach-excite/excite.h new file mode 100644 index 000000000000..4c29ba44992c --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-excite/excite.h @@ -0,0 +1,154 @@ +#ifndef __EXCITE_H__ +#define __EXCITE_H__ + +#include +#include +#include + +#define EXCITE_CPU_EXT_CLOCK 100000000 + +#if !defined(__ASSEMBLY__) +void __init excite_kgdb_init(void); +void excite_procfs_init(void); +extern unsigned long memsize; +extern char modetty[]; +extern u32 unit_id; +#endif + +/* Base name for XICAP devices */ +#define XICAP_NAME "xicap_gpi" + +/* OCD register offsets */ +#define LKB0 0x0038 +#define LKB5 0x0128 +#define LKM5 0x012C +#define LKB7 0x0138 +#define LKM7 0x013c +#define LKB8 0x0140 +#define LKM8 0x0144 +#define LKB9 0x0148 +#define LKM9 0x014c +#define LKB10 0x0150 +#define LKM10 0x0154 +#define LKB11 0x0158 +#define LKM11 0x015c +#define LKB12 0x0160 +#define LKM12 0x0164 +#define LKB13 0x0168 +#define LKM13 0x016c +#define LDP0 0x0200 +#define LDP1 0x0210 +#define LDP2 0x0220 +#define LDP3 0x0230 +#define INTPIN0 0x0A40 +#define INTPIN1 0x0A44 +#define INTPIN2 0x0A48 +#define INTPIN3 0x0A4C +#define INTPIN4 0x0A50 +#define INTPIN5 0x0A54 +#define INTPIN6 0x0A58 +#define INTPIN7 0x0A5C + + + + +/* TITAN register offsets */ +#define CPRR 0x0004 +#define CPDSR 0x0008 +#define CPTC0R 0x000c +#define CPTC1R 0x0010 +#define CPCFG0 0x0020 +#define CPCFG1 0x0024 +#define CPDST0A 0x0028 +#define CPDST0B 0x002c +#define CPDST1A 0x0030 +#define CPDST1B 0x0034 +#define CPXDSTA 0x0038 +#define CPXDSTB 0x003c +#define CPXCISRA 0x0048 +#define CPXCISRB 0x004c +#define CPGIG0ER 0x0050 +#define CPGIG1ER 0x0054 +#define CPGRWL 0x0068 +#define CPURSLMT 0x00f8 +#define UACFG 0x0200 +#define UAINTS 0x0204 +#define SDRXFCIE 0x4828 +#define SDTXFCIE 0x4928 +#define INTP0Status0 0x1B00 +#define INTP0Mask0 0x1B04 +#define INTP0Set0 0x1B08 +#define INTP0Clear0 0x1B0C +#define GXCFG 0x5000 +#define GXDMADRPFX 0x5018 +#define GXDMA_DESCADR 0x501c +#define GXCH0TDESSTRT 0x5054 + +/* IRQ definitions */ +#define NMICONFIG 0xac0 +#define TITAN_MSGINT 0xc4 +#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2) +#define FPGA0_MSGINT 0x5a +#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2) +#define FPGA1_MSGINT 0x7b +#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2) +#define PHY_MSGINT 0x9c +#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2) + +#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE) +/* Pre-release units used interrupt pin #9 */ +#define USB_IRQ 11 +#else +/* Re-designed units use interrupt pin #1 */ +#define USB_MSGINT 0x39 +#define USB_IRQ ((USB_MSGINT / 0x20) + 2) +#endif +#define TIMER_IRQ 12 + + +/* Device address ranges */ +#define EXCITE_OFFS_OCD 0x1fffc000 +#define EXCITE_SIZE_OCD (16 * 1024) +#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD) +#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD) + +#define EXCITE_OFFS_SCRAM 0x1fffa000 +#define EXCITE_SIZE_SCRAM (8 << 10) +#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM) +#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM) + +#define EXCITE_OFFS_PCI_IO 0x1fff8000 +#define EXCITE_SIZE_PCI_IO (8 << 10) +#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO) +#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO) + +#define EXCITE_OFFS_TITAN 0x1fff0000 +#define EXCITE_SIZE_TITAN (32 << 10) +#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN) +#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN) + +#define EXCITE_OFFS_PCI_MEM 0x1ffe0000 +#define EXCITE_SIZE_PCI_MEM (64 << 10) +#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM) +#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM) + +#define EXCITE_OFFS_FPGA 0x1ffdc000 +#define EXCITE_SIZE_FPGA (16 << 10) +#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA) +#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA) + +#define EXCITE_OFFS_NAND 0x1ffd8000 +#define EXCITE_SIZE_NAND (16 << 10) +#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND) +#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND) + +#define EXCITE_OFFS_BOOTROM 0x1f000000 +#define EXCITE_SIZE_BOOTROM (8 << 20) +#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM) +#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM) + +/* FPGA address offsets */ +#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */ +#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */ + +#endif /* __EXCITE_H__ */ diff --git a/trunk/arch/mips/include/asm/mach-excite/excite_fpga.h b/trunk/arch/mips/include/asm/mach-excite/excite_fpga.h new file mode 100644 index 000000000000..0a1ef69bece7 --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-excite/excite_fpga.h @@ -0,0 +1,80 @@ +#ifndef EXCITE_FPGA_H_INCLUDED +#define EXCITE_FPGA_H_INCLUDED + + +/** + * Address alignment of the individual FPGA bytes. + * The address arrangement of the individual bytes of the FPGA is two + * byte aligned at the embedded MK2 platform. + */ +#ifdef EXCITE_CCI_FPGA_MK2 +typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2))); +#else +typedef unsigned char excite_cci_fpga_align_t; +#endif + + +/** + * Size of Dual Ported RAM. + */ +#define EXCITE_DPR_SIZE 263 + + +/** + * Size of Reserved Status Fields in Dual Ported RAM. + */ +#define EXCITE_DPR_STATUS_SIZE 7 + + + +/** + * FPGA. + * Hardware register layout of the FPGA interface. The FPGA must accessed + * byte wise solely. + * @see EXCITE_CCI_DPR_MK2 + */ +typedef struct excite_fpga { + + /** + * Dual Ported RAM. + */ + excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE]; + + /** + * Status. + */ + excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE]; + +#ifdef EXCITE_CCI_FPGA_MK2 + /** + * RM9000 Interrupt. + * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite. + */ + excite_cci_fpga_align_t rm9k_int; +#else + /** + * MK2 Interrupt. + * Write access initiates interrupt at the ARM processor of the MK2. + */ + excite_cci_fpga_align_t mk2_int; + + excite_cci_fpga_align_t gap[0x1000-0x10f]; + + /** + * IRQ Source/Acknowledge. + */ + excite_cci_fpga_align_t rm9k_irq_src; + + /** + * IRQ Mask. + * Set bits enable the related interrupt. + */ + excite_cci_fpga_align_t rm9k_irq_mask; +#endif + + +} excite_fpga; + + + +#endif /* ndef EXCITE_FPGA_H_INCLUDED */ diff --git a/trunk/arch/mips/include/asm/mach-excite/excite_nandflash.h b/trunk/arch/mips/include/asm/mach-excite/excite_nandflash.h new file mode 100644 index 000000000000..c4cf6140622e --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-excite/excite_nandflash.h @@ -0,0 +1,7 @@ +#ifndef __EXCITE_NANDFLASH_H__ +#define __EXCITE_NANDFLASH_H__ + +/* Resource names */ +#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs" + +#endif /* __EXCITE_NANDFLASH_H__ */ diff --git a/trunk/arch/mips/include/asm/mach-excite/rm9k_eth.h b/trunk/arch/mips/include/asm/mach-excite/rm9k_eth.h new file mode 100644 index 000000000000..94705a46f72e --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-excite/rm9k_eth.h @@ -0,0 +1,23 @@ +#if !defined(__RM9K_ETH_H__) +#define __RM9K_ETH_H__ + +#define RM9K_GE_NAME "rm9k_ge" + +/* Resource names */ +#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac" +#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat" +#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc" +#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma" +#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx" +#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx" +#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx" +#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx" +#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy" +#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx" +#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx" +#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main" +#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy" +#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice" +#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel" + +#endif /* !defined(__RM9K_ETH_H__) */ diff --git a/trunk/arch/mips/include/asm/mach-excite/rm9k_wdt.h b/trunk/arch/mips/include/asm/mach-excite/rm9k_wdt.h new file mode 100644 index 000000000000..3fa3c08d2da7 --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-excite/rm9k_wdt.h @@ -0,0 +1,12 @@ +#ifndef __RM9K_WDT_H__ +#define __RM9K_WDT_H__ + +/* Device name */ +#define WDT_NAME "wdt_gpi" + +/* Resource names */ +#define WDT_RESOURCE_REGS "excite_watchdog_regs" +#define WDT_RESOURCE_IRQ "excite_watchdog_irq" +#define WDT_RESOURCE_COUNTER "excite_watchdog_counter" + +#endif /* __RM9K_WDT_H__ */ diff --git a/trunk/arch/mips/include/asm/mach-excite/rm9k_xicap.h b/trunk/arch/mips/include/asm/mach-excite/rm9k_xicap.h new file mode 100644 index 000000000000..009577734a8d --- /dev/null +++ b/trunk/arch/mips/include/asm/mach-excite/rm9k_xicap.h @@ -0,0 +1,16 @@ +#ifndef __EXCITE_XICAP_H__ +#define __EXCITE_XICAP_H__ + + +/* Resource names */ +#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx" +#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx" +#define XICAP_RESOURCE_XDMA "xicap_xdma" +#define XICAP_RESOURCE_DMADESC "xicap_dmadesc" +#define XICAP_RESOURCE_PKTPROC "xicap_pktproc" +#define XICAP_RESOURCE_IRQ "xicap_irq" +#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice" +#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks" +#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream" + +#endif /* __EXCITE_XICAP_H__ */ diff --git a/trunk/arch/mips/include/asm/mach-powertv/war.h b/trunk/arch/mips/include/asm/mach-excite/war.h similarity index 56% rename from trunk/arch/mips/include/asm/mach-powertv/war.h rename to trunk/arch/mips/include/asm/mach-excite/war.h index 7ac05ecc512b..1f82180c1598 100644 --- a/trunk/arch/mips/include/asm/mach-powertv/war.h +++ b/trunk/arch/mips/include/asm/mach-excite/war.h @@ -3,13 +3,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * This version for the PowerTV platform copied from the Malta version. - * * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - * Portions copyright (C) 2009 Cisco Systems, Inc. */ -#ifndef __ASM_MACH_POWERTV_WAR_H -#define __ASM_MACH_POWERTV_WAR_H +#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H +#define __ASM_MIPS_MACH_EXCITE_WAR_H #define R4600_V1_INDEX_ICACHEOP_WAR 0 #define R4600_V1_HIT_CACHEOP_WAR 0 @@ -17,12 +14,12 @@ #define R5432_CP0_INTERRUPT_WAR 0 #define BCM1250_M3_WAR 0 #define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 1 -#define MIPS_CACHE_SYNC_WAR 1 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 #define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define RM9000_CDEX_SMP_WAR 1 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 #define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 -#endif /* __ASM_MACH_POWERTV_WAR_H */ +#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ diff --git a/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h deleted file mode 100644 index 021f77ca59ec..000000000000 --- a/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * The header file of cs5536 sourth bridge. - * - * Copyright (C) 2007 Lemote, Inc. - * Author : jlliu - */ - -#ifndef _CS5536_H -#define _CS5536_H - -#include - -extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); -extern void _wrmsr(u32 msr, u32 hi, u32 lo); - -/* - * MSR module base - */ -#define CS5536_SB_MSR_BASE (0x00000000) -#define CS5536_GLIU_MSR_BASE (0x10000000) -#define CS5536_ILLEGAL_MSR_BASE (0x20000000) -#define CS5536_USB_MSR_BASE (0x40000000) -#define CS5536_IDE_MSR_BASE (0x60000000) -#define CS5536_DIVIL_MSR_BASE (0x80000000) -#define CS5536_ACC_MSR_BASE (0xa0000000) -#define CS5536_UNUSED_MSR_BASE (0xc0000000) -#define CS5536_GLCP_MSR_BASE (0xe0000000) - -#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) -#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) -#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) -#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) -#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) -#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) -#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) -#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) -#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) - -/* - * BAR SPACE OF VIRTUAL PCI : - * range for pci probe use, length is the actual size. - */ -/* IO space for all DIVIL modules */ -#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ -#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ -#define CS5536_SMB_RANGE 0xfffffff8 -#define CS5536_SMB_LENGTH 0x08 -#define CS5536_GPIO_RANGE 0xffffff00 -#define CS5536_GPIO_LENGTH 0x100 -#define CS5536_MFGPT_RANGE 0xffffffc0 -#define CS5536_MFGPT_LENGTH 0x40 -#define CS5536_ACPI_RANGE 0xffffffe0 -#define CS5536_ACPI_LENGTH 0x20 -#define CS5536_PMS_RANGE 0xffffff80 -#define CS5536_PMS_LENGTH 0x80 -/* IO space for IDE */ -#define CS5536_IDE_RANGE 0xfffffff0 -#define CS5536_IDE_LENGTH 0x10 -/* IO space for ACC */ -#define CS5536_ACC_RANGE 0xffffff80 -#define CS5536_ACC_LENGTH 0x80 -/* MEM space for ALL USB modules */ -#define CS5536_OHCI_RANGE 0xfffff000 -#define CS5536_OHCI_LENGTH 0x1000 -#define CS5536_EHCI_RANGE 0xfffff000 -#define CS5536_EHCI_LENGTH 0x1000 - -/* - * PCI MSR ACCESS - */ -#define PCI_MSR_CTRL 0xF0 -#define PCI_MSR_ADDR 0xF4 -#define PCI_MSR_DATA_LO 0xF8 -#define PCI_MSR_DATA_HI 0xFC - -/**************** MSR *****************************/ - -/* - * GLIU STANDARD MSR - */ -#define GLIU_CAP 0x00 -#define GLIU_CONFIG 0x01 -#define GLIU_SMI 0x02 -#define GLIU_ERROR 0x03 -#define GLIU_PM 0x04 -#define GLIU_DIAG 0x05 - -/* - * GLIU SPEC. MSR - */ -#define GLIU_P2D_BM0 0x20 -#define GLIU_P2D_BM1 0x21 -#define GLIU_P2D_BM2 0x22 -#define GLIU_P2D_BMK0 0x23 -#define GLIU_P2D_BMK1 0x24 -#define GLIU_P2D_BM3 0x25 -#define GLIU_P2D_BM4 0x26 -#define GLIU_COH 0x80 -#define GLIU_PAE 0x81 -#define GLIU_ARB 0x82 -#define GLIU_ASMI 0x83 -#define GLIU_AERR 0x84 -#define GLIU_DEBUG 0x85 -#define GLIU_PHY_CAP 0x86 -#define GLIU_NOUT_RESP 0x87 -#define GLIU_NOUT_WDATA 0x88 -#define GLIU_WHOAMI 0x8B -#define GLIU_SLV_DIS 0x8C -#define GLIU_IOD_BM0 0xE0 -#define GLIU_IOD_BM1 0xE1 -#define GLIU_IOD_BM2 0xE2 -#define GLIU_IOD_BM3 0xE3 -#define GLIU_IOD_BM4 0xE4 -#define GLIU_IOD_BM5 0xE5 -#define GLIU_IOD_BM6 0xE6 -#define GLIU_IOD_BM7 0xE7 -#define GLIU_IOD_BM8 0xE8 -#define GLIU_IOD_BM9 0xE9 -#define GLIU_IOD_SC0 0xEA -#define GLIU_IOD_SC1 0xEB -#define GLIU_IOD_SC2 0xEC -#define GLIU_IOD_SC3 0xED -#define GLIU_IOD_SC4 0xEE -#define GLIU_IOD_SC5 0xEF -#define GLIU_IOD_SC6 0xF0 -#define GLIU_IOD_SC7 0xF1 - -/* - * SB STANDARD - */ -#define SB_CAP 0x00 -#define SB_CONFIG 0x01 -#define SB_SMI 0x02 -#define SB_ERROR 0x03 -#define SB_MAR_ERR_EN 0x00000001 -#define SB_TAR_ERR_EN 0x00000002 -#define SB_RSVD_BIT1 0x00000004 -#define SB_EXCEP_ERR_EN 0x00000008 -#define SB_SYSE_ERR_EN 0x00000010 -#define SB_PARE_ERR_EN 0x00000020 -#define SB_TAS_ERR_EN 0x00000040 -#define SB_MAR_ERR_FLAG 0x00010000 -#define SB_TAR_ERR_FLAG 0x00020000 -#define SB_RSVD_BIT2 0x00040000 -#define SB_EXCEP_ERR_FLAG 0x00080000 -#define SB_SYSE_ERR_FLAG 0x00100000 -#define SB_PARE_ERR_FLAG 0x00200000 -#define SB_TAS_ERR_FLAG 0x00400000 -#define SB_PM 0x04 -#define SB_DIAG 0x05 - -/* - * SB SPEC. - */ -#define SB_CTRL 0x10 -#define SB_R0 0x20 -#define SB_R1 0x21 -#define SB_R2 0x22 -#define SB_R3 0x23 -#define SB_R4 0x24 -#define SB_R5 0x25 -#define SB_R6 0x26 -#define SB_R7 0x27 -#define SB_R8 0x28 -#define SB_R9 0x29 -#define SB_R10 0x2A -#define SB_R11 0x2B -#define SB_R12 0x2C -#define SB_R13 0x2D -#define SB_R14 0x2E -#define SB_R15 0x2F - -/* - * GLCP STANDARD - */ -#define GLCP_CAP 0x00 -#define GLCP_CONFIG 0x01 -#define GLCP_SMI 0x02 -#define GLCP_ERROR 0x03 -#define GLCP_PM 0x04 -#define GLCP_DIAG 0x05 - -/* - * GLCP SPEC. - */ -#define GLCP_CLK_DIS_DELAY 0x08 -#define GLCP_PM_CLK_DISABLE 0x09 -#define GLCP_GLB_PM 0x0B -#define GLCP_DBG_OUT 0x0C -#define GLCP_RSVD1 0x0D -#define GLCP_SOFT_COM 0x0E -#define SOFT_BAR_SMB_FLAG 0x00000001 -#define SOFT_BAR_GPIO_FLAG 0x00000002 -#define SOFT_BAR_MFGPT_FLAG 0x00000004 -#define SOFT_BAR_IRQ_FLAG 0x00000008 -#define SOFT_BAR_PMS_FLAG 0x00000010 -#define SOFT_BAR_ACPI_FLAG 0x00000020 -#define SOFT_BAR_IDE_FLAG 0x00000400 -#define SOFT_BAR_ACC_FLAG 0x00000800 -#define SOFT_BAR_OHCI_FLAG 0x00001000 -#define SOFT_BAR_EHCI_FLAG 0x00002000 -#define GLCP_RSVD2 0x0F -#define GLCP_CLK_OFF 0x10 -#define GLCP_CLK_ACTIVE 0x11 -#define GLCP_CLK_DISABLE 0x12 -#define GLCP_CLK4ACK 0x13 -#define GLCP_SYS_RST 0x14 -#define GLCP_RSVD3 0x15 -#define GLCP_DBG_CLK_CTRL 0x16 -#define GLCP_CHIP_REV_ID 0x17 - -/* PIC */ -#define PIC_YSEL_LOW 0x20 -#define PIC_YSEL_LOW_USB_SHIFT 8 -#define PIC_YSEL_LOW_ACC_SHIFT 16 -#define PIC_YSEL_LOW_FLASH_SHIFT 24 -#define PIC_YSEL_HIGH 0x21 -#define PIC_ZSEL_LOW 0x22 -#define PIC_ZSEL_HIGH 0x23 -#define PIC_IRQM_PRIM 0x24 -#define PIC_IRQM_LPC 0x25 -#define PIC_XIRR_STS_LOW 0x26 -#define PIC_XIRR_STS_HIGH 0x27 -#define PCI_SHDW 0x34 - -/* - * DIVIL STANDARD - */ -#define DIVIL_CAP 0x00 -#define DIVIL_CONFIG 0x01 -#define DIVIL_SMI 0x02 -#define DIVIL_ERROR 0x03 -#define DIVIL_PM 0x04 -#define DIVIL_DIAG 0x05 - -/* - * DIVIL SPEC. - */ -#define DIVIL_LBAR_IRQ 0x08 -#define DIVIL_LBAR_KEL 0x09 -#define DIVIL_LBAR_SMB 0x0B -#define DIVIL_LBAR_GPIO 0x0C -#define DIVIL_LBAR_MFGPT 0x0D -#define DIVIL_LBAR_ACPI 0x0E -#define DIVIL_LBAR_PMS 0x0F -#define DIVIL_LEG_IO 0x14 -#define DIVIL_BALL_OPTS 0x15 -#define DIVIL_SOFT_IRQ 0x16 -#define DIVIL_SOFT_RESET 0x17 - -/* MFGPT */ -#define MFGPT_IRQ 0x28 - -/* - * IDE STANDARD - */ -#define IDE_CAP 0x00 -#define IDE_CONFIG 0x01 -#define IDE_SMI 0x02 -#define IDE_ERROR 0x03 -#define IDE_PM 0x04 -#define IDE_DIAG 0x05 - -/* - * IDE SPEC. - */ -#define IDE_IO_BAR 0x08 -#define IDE_CFG 0x10 -#define IDE_DTC 0x12 -#define IDE_CAST 0x13 -#define IDE_ETC 0x14 -#define IDE_INTERNAL_PM 0x15 - -/* - * ACC STANDARD - */ -#define ACC_CAP 0x00 -#define ACC_CONFIG 0x01 -#define ACC_SMI 0x02 -#define ACC_ERROR 0x03 -#define ACC_PM 0x04 -#define ACC_DIAG 0x05 - -/* - * USB STANDARD - */ -#define USB_CAP 0x00 -#define USB_CONFIG 0x01 -#define USB_SMI 0x02 -#define USB_ERROR 0x03 -#define USB_PM 0x04 -#define USB_DIAG 0x05 - -/* - * USB SPEC. - */ -#define USB_OHCI 0x08 -#define USB_EHCI 0x09 - -/****************** NATIVE ***************************/ -/* GPIO : I/O SPACE; REG : 32BITS */ -#define GPIOL_OUT_VAL 0x00 -#define GPIOL_OUT_EN 0x04 - -#endif /* _CS5536_H */ diff --git a/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h deleted file mode 100644 index 4b493d6772c2..000000000000 --- a/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * cs5536 mfgpt header file - */ - -#ifndef _CS5536_MFGPT_H -#define _CS5536_MFGPT_H - -#include -#include - -#ifdef CONFIG_CS5536_MFGPT -extern void setup_mfgpt0_timer(void); -extern void disable_mfgpt0_counter(void); -extern void enable_mfgpt0_counter(void); -#else -static inline void __maybe_unused setup_mfgpt0_timer(void) -{ -} -static inline void __maybe_unused disable_mfgpt0_counter(void) -{ -} -static inline void __maybe_unused enable_mfgpt0_counter(void) -{ -} -#endif - -#define MFGPT_TICK_RATE 14318000 -#define COMPARE ((MFGPT_TICK_RATE + HZ/2) / HZ) - -#define MFGPT_BASE mfgpt_base -#define MFGPT0_CMP2 (MFGPT_BASE + 2) -#define MFGPT0_CNT (MFGPT_BASE + 4) -#define MFGPT0_SETUP (MFGPT_BASE + 6) - -#endif /*!_CS5536_MFGPT_H */ diff --git a/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h deleted file mode 100644 index 0dca9c89ee7c..000000000000 --- a/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * the definition file of cs5536 Virtual Support Module(VSM). - * pci configuration space can be accessed through the VSM, so - * there is no need of the MSR read/write now, except the spec. - * MSR registers which are not implemented yet. - * - * Copyright (C) 2007 Lemote Inc. - * Author : jlliu, liujl@lemote.com - */ - -#ifndef _CS5536_PCI_H -#define _CS5536_PCI_H - -#include -#include - -extern void cs5536_pci_conf_write4(int function, int reg, u32 value); -extern u32 cs5536_pci_conf_read4(int function, int reg); - -#define CS5536_ACC_INTR 9 -#define CS5536_IDE_INTR 14 -#define CS5536_USB_INTR 11 -#define CS5536_MFGPT_INTR 5 -#define CS5536_UART1_INTR 4 -#define CS5536_UART2_INTR 3 - -/************** PCI BUS DEVICE FUNCTION ***************/ - -/* - * PCI bus device function - */ -#define PCI_BUS_CS5536 0 -#define PCI_IDSEL_CS5536 14 - -/********** STANDARD PCI-2.2 EXPANSION ****************/ - -/* - * PCI configuration space - * we have to virtualize the PCI configure space head, so we should - * define the necessary IDs and some others. - */ - -/* CONFIG of PCI VENDOR ID*/ -#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ - (((mod_dev_id) << 16) | (sys_vendor_id)) - -/* VENDOR ID */ -#define CS5536_VENDOR_ID 0x1022 - -/* DEVICE ID */ -#define CS5536_ISA_DEVICE_ID 0x2090 -#define CS5536_IDE_DEVICE_ID 0x209a -#define CS5536_ACC_DEVICE_ID 0x2093 -#define CS5536_OHCI_DEVICE_ID 0x2094 -#define CS5536_EHCI_DEVICE_ID 0x2095 - -/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ -#define CS5536_ISA_CLASS_CODE 0x060100 -#define CS5536_IDE_CLASS_CODE 0x010180 -#define CS5536_ACC_CLASS_CODE 0x040100 -#define CS5536_OHCI_CLASS_CODE 0x0C0310 -#define CS5536_EHCI_CLASS_CODE 0x0C0320 - -/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ - -#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ - ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ - | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); - -#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ -#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ -#define PCI_NORMAL_HEADER_TYPE 0x00 -#define PCI_NORMAL_LATENCY_TIMER 0x00 -#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ - -/* BAR */ -#define PCI_BAR0_REG 0x10 -#define PCI_BAR1_REG 0x14 -#define PCI_BAR2_REG 0x18 -#define PCI_BAR3_REG 0x1c -#define PCI_BAR4_REG 0x20 -#define PCI_BAR5_REG 0x24 -#define PCI_BAR_COUNT 6 -#define PCI_BAR_RANGE_MASK 0xFFFFFFFF - -/* CARDBUS CIS POINTER */ -#define PCI_CARDBUS_CIS_POINTER 0x00000000 - -/* SUBSYSTEM VENDOR ID */ -#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID - -/* SUBSYSTEM ID */ -#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID -#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID -#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID -#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID -#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID - -/* EXPANSION ROM BAR */ -#define PCI_EXPANSION_ROM_BAR 0x00000000 - -/* CAPABILITIES POINTER */ -#define PCI_CAPLIST_POINTER 0x00000000 -#define PCI_CAPLIST_USB_POINTER 0x40 -/* INTERRUPT */ - -#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ - ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ - ((pin) << 8) | (mod_intr)) - -#define PCI_MAX_LATENCY 0x40 -#define PCI_MIN_GRANT 0x00 -#define PCI_DEFAULT_PIN 0x01 - -/*********** EXPANSION PCI REG ************************/ - -/* - * ISA EXPANSION - */ -#define PCI_UART1_INT_REG 0x50 -#define PCI_UART2_INT_REG 0x54 -#define PCI_ISA_FIXUP_REG 0x58 - -/* - * IDE EXPANSION - */ -#define PCI_IDE_CFG_REG 0x40 -#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF -#define PCI_IDE_DTC_REG 0x48 -#define PCI_IDE_CAST_REG 0x4C -#define PCI_IDE_ETC_REG 0x50 -#define PCI_IDE_PM_REG 0x54 -#define PCI_IDE_INT_REG 0x60 - -/* - * ACC EXPANSION - */ -#define PCI_ACC_INT_REG 0x50 - -/* - * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI - */ -#define PCI_OHCI_PM_REG 0x40 -#define PCI_OHCI_INT_REG 0x50 - -/* - * EHCI EXPANSION - */ -#define PCI_EHCI_LEGSMIEN_REG 0x50 -#define PCI_EHCI_LEGSMISTS_REG 0x54 -#define PCI_EHCI_FLADJ_REG 0x60 - -#endif /* _CS5536_PCI_H_ */ diff --git a/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h deleted file mode 100644 index 6305bea7e18e..000000000000 --- a/trunk/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * the read/write interfaces for Virtual Support Module(VSM) - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin - */ - -#ifndef _CS5536_VSM_H -#define _CS5536_VSM_H - -#include - -typedef void (*cs5536_pci_vsm_write)(int reg, u32 value); -typedef u32 (*cs5536_pci_vsm_read)(int reg); - -#define DECLARE_CS5536_MODULE(name) \ -extern void pci_##name##_write_reg(int reg, u32 value); \ -extern u32 pci_##name##_read_reg(int reg); - -/* ide module */ -DECLARE_CS5536_MODULE(ide) -/* acc module */ -DECLARE_CS5536_MODULE(acc) -/* ohci module */ -DECLARE_CS5536_MODULE(ohci) -/* isa module */ -DECLARE_CS5536_MODULE(isa) -/* ehci module */ -DECLARE_CS5536_MODULE(ehci) - -#endif /* _CS5536_VSM_H */ diff --git a/trunk/arch/mips/include/asm/mach-loongson/dma-coherence.h b/trunk/arch/mips/include/asm/mach-loongson/dma-coherence.h index 981c75f91a7d..71a6851ba833 100644 --- a/trunk/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/trunk/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -28,11 +28,7 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { -#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) - return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); -#else return dma_addr & 0x7fffffff; -#endif } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, diff --git a/trunk/arch/mips/include/asm/mach-loongson/loongson.h b/trunk/arch/mips/include/asm/mach-loongson/loongson.h index ee8bc8376972..da70bcf2304e 100644 --- a/trunk/arch/mips/include/asm/mach-loongson/loongson.h +++ b/trunk/arch/mips/include/asm/mach-loongson/loongson.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote, Inc. + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it @@ -15,6 +15,9 @@ #include #include +/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */ +#include + /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); @@ -29,19 +32,7 @@ extern unsigned long memsize, highmemsize; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); -extern void __init prom_init_machtype(void); extern void __init prom_init_env(void); -#ifdef CONFIG_LOONGSON_UART_BASE -extern unsigned long _loongson_uart_base, loongson_uart_base; -extern void prom_init_loongson_uart_base(void); -#endif - -static inline void prom_init_uart_base(void) -{ -#ifdef CONFIG_LOONGSON_UART_BASE - prom_init_loongson_uart_base(); -#endif -} /* irq operation functions */ extern void bonito_irqdispatch(void); @@ -49,276 +40,25 @@ extern void __init bonito_irq_init(void); extern void __init set_irq_trigger_mode(void); extern void __init mach_init_irq(void); extern void mach_irq_dispatch(unsigned int pending); -extern int mach_i8259_irq(void); - -/* We need this in some places... */ -#define delay() ({ \ - int x; \ - for (x = 0; x < 100000; x++) \ - __asm__ __volatile__(""); \ -}) - -#define LOONGSON_REG(x) \ - (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) - -#define LOONGSON_IRQ_BASE 32 -#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ - -#define LOONGSON_FLASH_BASE 0x1c000000 -#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */ -#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1) - -#define LOONGSON_LIO0_BASE 0x1e000000 -#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */ -#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1) - -#define LOONGSON_BOOT_BASE 0x1fc00000 -#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */ -#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) -#define LOONGSON_REG_BASE 0x1fe00000 -#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ -#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) - -#define LOONGSON_LIO1_BASE 0x1ff00000 -#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ -#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) - -#define LOONGSON_PCILO0_BASE 0x10000000 -#define LOONGSON_PCILO1_BASE 0x14000000 -#define LOONGSON_PCILO2_BASE 0x18000000 -#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE -#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */ -#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1) - -#define LOONGSON_PCICFG_BASE 0x1fe80000 -#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ -#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) -#define LOONGSON_PCIIO_BASE 0x1fd00000 -#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ -#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) - -/* Loongson Register Bases */ - -#define LOONGSON_PCICONFIGBASE 0x00 -#define LOONGSON_REGBASE 0x100 /* PCI Configuration Registers */ - -#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) -#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) -#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) -#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) -#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) -#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) -#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) -#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) -#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) -#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) -#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) -#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) - -#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c) - -#define LOONGSON_PCICMD_PERR_CLR 0x80000000 -#define LOONGSON_PCICMD_SERR_CLR 0x40000000 -#define LOONGSON_PCICMD_MABORT_CLR 0x20000000 -#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 -#define LOONGSON_PCICMD_TABORT_CLR 0x08000000 -#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 -#define LOONGSON_PCICMD_PERRRESPEN 0x00000040 -#define LOONGSON_PCICMD_ASTEPEN 0x00000080 -#define LOONGSON_PCICMD_SERREN 0x00000100 -#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00 -#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8 - -/* Loongson h/w Configuration */ - -#define LOONGSON_GENCFG_OFFSET 0x4 -#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) - -#define LOONGSON_GENCFG_DEBUGMODE 0x00000001 -#define LOONGSON_GENCFG_SNOOPEN 0x00000002 -#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004 - -#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008 -#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010 -#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020 -#define LOONGSON_GENCFG_BYTESWAP 0x00000040 - -#define LOONGSON_GENCFG_UNCACHED 0x00000080 -#define LOONGSON_GENCFG_PREFETCHEN 0x00000100 -#define LOONGSON_GENCFG_WBEHINDEN 0x00000200 -#define LOONGSON_GENCFG_CACHEALG 0x00000c00 -#define LOONGSON_GENCFG_CACHEALG_SHIFT 10 -#define LOONGSON_GENCFG_PCIQUEUE 0x00001000 -#define LOONGSON_GENCFG_CACHESTOP 0x00002000 -#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000 -#define LOONGSON_GENCFG_BUSERREN 0x00008000 -#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000 -#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000 - -/* PCI address map control */ - -#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10) -#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14) -#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18) - -/* GPIO Regs - r/w */ - -#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) -#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) - -/* ICU Configuration Regs - r/w */ - -#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) -#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) -#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) - -/* ICU Enable Regs - IntEn & IntISR are r/o. */ - -#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) -#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) -#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) -#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) - -/* ICU */ -#define LOONGSON_ICU_MBOXES 0x0000000f -#define LOONGSON_ICU_MBOXES_SHIFT 0 -#define LOONGSON_ICU_DMARDY 0x00000010 -#define LOONGSON_ICU_DMAEMPTY 0x00000020 -#define LOONGSON_ICU_COPYRDY 0x00000040 -#define LOONGSON_ICU_COPYEMPTY 0x00000080 -#define LOONGSON_ICU_COPYERR 0x00000100 -#define LOONGSON_ICU_PCIIRQ 0x00000200 -#define LOONGSON_ICU_MASTERERR 0x00000400 -#define LOONGSON_ICU_SYSTEMERR 0x00000800 -#define LOONGSON_ICU_DRAMPERR 0x00001000 -#define LOONGSON_ICU_RETRYERR 0x00002000 -#define LOONGSON_ICU_GPIOS 0x01ff0000 -#define LOONGSON_ICU_GPIOS_SHIFT 16 -#define LOONGSON_ICU_GPINS 0x7e000000 -#define LOONGSON_ICU_GPINS_SHIFT 25 -#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N))) -#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N))) -#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N))) - -/* PCI prefetch window base & mask */ - -#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) -#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) -#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) -#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) +#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) /* PCI_Hit*_Sel_* */ -#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50) -#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54) -#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58) -#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c) -#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60) -#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64) +#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) +#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) +#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) +#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) +#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) +#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) /* PXArb Config & Status */ -#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) -#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) - -/* pcimap */ - -#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f -#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0 -#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0 -#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6 -#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000 -#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12 -#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000 -#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ - ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) - -#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ -#include -extern void loongson2_cpu_wait(void); -extern struct cpufreq_frequency_table loongson2_clockmod_table[]; - -/* Chip Config */ -#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) -#endif - -/* - * address windows configuration module - * - * loongson2e do not have this module - */ -#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG - -/* address window config module base address */ -#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul -#define LOONGSON_ADDRWINCFG_SIZE 0x180 - -extern unsigned long _loongson_addrwincfg_base; -#define LOONGSON_ADDRWINCFG(offset) \ - (*(volatile u64 *)(_loongson_addrwincfg_base + (offset))) - -#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) -#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) -#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) -#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) - -#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) -#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) -#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) -#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) - -#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) -#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) -#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) -#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) - -#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) -#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) -#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) -#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) - -#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) -#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) -#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) -#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) - -#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) -#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) -#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) -#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) - -#define ADDRWIN_WIN0 0 -#define ADDRWIN_WIN1 1 -#define ADDRWIN_WIN2 2 -#define ADDRWIN_WIN3 3 - -#define ADDRWIN_MAP_DST_DDR 0 -#define ADDRWIN_MAP_DST_PCI 1 -#define ADDRWIN_MAP_DST_LIO 1 - -/* - * s: CPU, PCIDMA - * d: DDR, PCI, LIO - * win: 0, 1, 2, 3 - * src: map source - * dst: map destination - * size: ~mask + 1 - */ -#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ - s##_WIN##w##_BASE = (src); \ - s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ - s##_WIN##w##_MASK = ~(size-1); \ -} while (0) - -#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ - LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) -#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ - LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) -#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ - LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) +#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) +#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) -#endif /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */ +/* loongson2-specific perf counter IRQ */ +#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/trunk/arch/mips/include/asm/mach-loongson/machine.h b/trunk/arch/mips/include/asm/mach-loongson/machine.h index acf8359cb135..206ea2067916 100644 --- a/trunk/arch/mips/include/asm/mach-loongson/machine.h +++ b/trunk/arch/mips/include/asm/mach-loongson/machine.h @@ -13,14 +13,9 @@ #ifdef CONFIG_LEMOTE_FULOONG2E -#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E - -#endif +#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8) -/* use fuloong2f as the default machine of LEMOTE_MACH2F */ -#ifdef CONFIG_LEMOTE_MACH2F - -#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F +#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E #endif diff --git a/trunk/arch/mips/include/asm/mach-loongson/mem.h b/trunk/arch/mips/include/asm/mach-loongson/mem.h index e9960f341b96..bd7b3cba7e35 100644 --- a/trunk/arch/mips/include/asm/mach-loongson/mem.h +++ b/trunk/arch/mips/include/asm/mach-loongson/mem.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote, Inc. + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it @@ -12,30 +12,19 @@ #define __ASM_MACH_LOONGSON_MEM_H /* - * high memory space + * On Lemote Loongson 2e * - * in loongson2e, starts from 512M - * in loongson2f, starts from 2G 256M + * the high memory space starts from 512M. + * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. */ -#ifdef CONFIG_CPU_LOONGSON2E -#define LOONGSON_HIGHMEM_START 0x20000000 -#else -#define LOONGSON_HIGHMEM_START 0x90000000 -#endif -/* - * the peripheral registers(MMIO): - * - * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. - * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. - */ +#ifdef CONFIG_LEMOTE_FULOONG2E + +#define LOONGSON_HIGHMEM_START 0x20000000 #define LOONGSON_MMIO_MEM_START 0x10000000 +#define LOONGSON_MMIO_MEM_END 0x20000000 -#ifdef CONFIG_CPU_LOONGSON2E -#define LOONGSON_MMIO_MEM_END 0x20000000 -#else -#define LOONGSON_MMIO_MEM_END 0x80000000 #endif #endif /* __ASM_MACH_LOONGSON_MEM_H */ diff --git a/trunk/arch/mips/include/asm/mach-loongson/pci.h b/trunk/arch/mips/include/asm/mach-loongson/pci.h index a199a4f6de4e..f1663ca81da0 100644 --- a/trunk/arch/mips/include/asm/mach-loongson/pci.h +++ b/trunk/arch/mips/include/asm/mach-loongson/pci.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2008 Zhang Le - * Copyright (c) 2009 Wu Zhangjin * * This program is free software; you can redistribute it * and/or modify it under the terms of the GNU General @@ -23,39 +22,16 @@ #ifndef __ASM_MACH_LOONGSON_PCI_H_ #define __ASM_MACH_LOONGSON_PCI_H_ -extern struct pci_ops loongson_pci_ops; +extern struct pci_ops bonito64_pci_ops; -/* this is an offset from mips_io_port_base */ -#define LOONGSON_PCI_IO_START 0x00004000UL - -#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG - -/* - * we use address window2 to map cpu address space to pci space - * window2: cpu [1G, 2G] -> pci [1G, 2G] - * why not use window 0 & 1? because they are used by cpu when booting. - * window0: cpu [0, 256M] -> ddr [0, 256M] - * window1: cpu [256M, 512M] -> pci [256M, 512M] - */ - -/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ -#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ -#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC - -#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST -#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ - -#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ - LOONGSON_PCI_MEM_START + 1) - -#else /* loongson2f/32bit & loongson2e */ +#ifdef CONFIG_LEMOTE_FULOONG2E /* this pci memory space is mapped by pcimap in pci.c */ -#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE -#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2) +#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE +#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) /* this is an offset from mips_io_port_base */ #define LOONGSON_PCI_IO_START 0x00004000UL -#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */ +#endif #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ diff --git a/trunk/arch/mips/include/asm/mach-powertv/asic.h b/trunk/arch/mips/include/asm/mach-powertv/asic.h deleted file mode 100644 index bcad43a93ebf..000000000000 --- a/trunk/arch/mips/include/asm/mach-powertv/asic.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_ASIC_H -#define _ASM_MACH_POWERTV_ASIC_H - -#include -#include - -#define DVR_CAPABLE (1<<0) -#define PCIE_CAPABLE (1<<1) -#define FFS_CAPABLE (1<<2) -#define DISPLAY_CAPABLE (1<<3) - -/* Platform Family types - * For compitability, the new value must be added in the end */ -enum family_type { - FAMILY_8500, - FAMILY_8500RNG, - FAMILY_4500, - FAMILY_1500, - FAMILY_8600, - FAMILY_4600, - FAMILY_4600VZA, - FAMILY_8600VZB, - FAMILY_1500VZE, - FAMILY_1500VZF, - FAMILIES -}; - -/* Register maps for each ASIC */ -extern const struct register_map calliope_register_map; -extern const struct register_map cronus_register_map; -extern const struct register_map zeus_register_map; - -extern struct resource dvr_cronus_resources[]; -extern struct resource dvr_zeus_resources[]; -extern struct resource non_dvr_calliope_resources[]; -extern struct resource non_dvr_cronus_resources[]; -extern struct resource non_dvr_cronuslite_resources[]; -extern struct resource non_dvr_vz_calliope_resources[]; -extern struct resource non_dvr_vze_calliope_resources[]; -extern struct resource non_dvr_vzf_calliope_resources[]; -extern struct resource non_dvr_zeus_resources[]; - -extern void powertv_platform_init(void); -extern void platform_alloc_bootmem(void); -extern enum asic_type platform_get_asic(void); -extern enum family_type platform_get_family(void); -extern int platform_supports_dvr(void); -extern int platform_supports_ffs(void); -extern int platform_supports_pcie(void); -extern int platform_supports_display(void); -extern void configure_platform(void); -extern void platform_configure_usb_ehci(void); -extern void platform_unconfigure_usb_ehci(void); -extern void platform_configure_usb_ohci(void); -extern void platform_unconfigure_usb_ohci(void); - -/* Platform Resources */ -#define ASIC_RESOURCE_GET_EXISTS 1 -extern struct resource *asic_resource_get(const char *name); -extern void platform_release_memory(void *baddr, int size); - -/* Reboot Cause */ -extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); -extern void set_locked_reboot_cause(char code, unsigned int data, - unsigned int data2); - -enum sys_reboot_type { - sys_unknown_reboot = 0x00, /* Unknown reboot cause */ - sys_davic_change = 0x01, /* Reboot due to change in DAVIC - * mode */ - sys_user_reboot = 0x02, /* Reboot initiated by user */ - sys_system_reboot = 0x03, /* Reboot initiated by OS */ - sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */ - sys_silent_reboot = 0x05, /* Silent reboot */ - sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */ - sys_power_up_reboot = 0x07, /* Power on bootup. Older - * drivers may report as - * userReboot. */ - sys_code_change = 0x08, /* Reboot to take code change. - * Older drivers may report as - * userReboot. */ - sys_hardware_reset = 0x09, /* HW watchdog or front-panel - * reset button reset. Older - * drivers may report as - * userReboot. */ - sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ -}; - -#endif /* _ASM_MACH_POWERTV_ASIC_H */ diff --git a/trunk/arch/mips/include/asm/mach-powertv/asic_regs.h b/trunk/arch/mips/include/asm/mach-powertv/asic_regs.h deleted file mode 100644 index 9a65c93782f9..000000000000 --- a/trunk/arch/mips/include/asm/mach-powertv/asic_regs.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __ASM_MACH_POWERTV_ASIC_H_ -#define __ASM_MACH_POWERTV_ASIC_H_ -#include - -/* ASIC types */ -enum asic_type { - ASIC_UNKNOWN, - ASIC_ZEUS, - ASIC_CALLIOPE, - ASIC_CRONUS, - ASIC_CRONUSLITE, - ASICS -}; - -/* hardcoded values read from Chip Version registers */ -#define CRONUS_10 0x0B4C1C20 -#define CRONUS_11 0x0B4C1C21 -#define CRONUSLITE_10 0x0B4C1C40 - -#define NAND_FLASH_BASE 0x03000000 -#define ZEUS_IO_BASE 0x09000000 -#define CALLIOPE_IO_BASE 0x08000000 -#define CRONUS_IO_BASE 0x09000000 -#define ASIC_IO_SIZE 0x01000000 - -/* Definitions for backward compatibility */ -#define UART1_INTSTAT uart1_intstat -#define UART1_INTEN uart1_inten -#define UART1_CONFIG1 uart1_config1 -#define UART1_CONFIG2 uart1_config2 -#define UART1_DIVISORHI uart1_divisorhi -#define UART1_DIVISORLO uart1_divisorlo -#define UART1_DATA uart1_data -#define UART1_STATUS uart1_status - -/* ASIC register enumeration */ -struct register_map { - u32 eic_slow0_strt_add; - u32 eic_cfg_bits; - u32 eic_ready_status; - - u32 chipver3; - u32 chipver2; - u32 chipver1; - u32 chipver0; - - u32 uart1_intstat; - u32 uart1_inten; - u32 uart1_config1; - u32 uart1_config2; - u32 uart1_divisorhi; - u32 uart1_divisorlo; - u32 uart1_data; - u32 uart1_status; - - u32 int_stat_3; - u32 int_stat_2; - u32 int_stat_1; - u32 int_stat_0; - u32 int_config; - u32 int_int_scan; - u32 ien_int_3; - u32 ien_int_2; - u32 ien_int_1; - u32 ien_int_0; - u32 int_level_3_3; - u32 int_level_3_2; - u32 int_level_3_1; - u32 int_level_3_0; - u32 int_level_2_3; - u32 int_level_2_2; - u32 int_level_2_1; - u32 int_level_2_0; - u32 int_level_1_3; - u32 int_level_1_2; - u32 int_level_1_1; - u32 int_level_1_0; - u32 int_level_0_3; - u32 int_level_0_2; - u32 int_level_0_1; - u32 int_level_0_0; - u32 int_docsis_en; - - u32 mips_pll_setup; - u32 usb_fs; - u32 test_bus; - u32 crt_spare; - u32 usb2_ohci_int_mask; - u32 usb2_strap; - u32 ehci_hcapbase; - u32 ohci_hc_revision; - u32 bcm1_bs_lmi_steer; - u32 usb2_control; - u32 usb2_stbus_obc; - u32 usb2_stbus_mess_size; - u32 usb2_stbus_chunk_size; - - u32 pcie_regs; - u32 tim_ch; - u32 tim_cl; - u32 gpio_dout; - u32 gpio_din; - u32 gpio_dir; - u32 watchdog; - u32 front_panel; - - u32 register_maps; -}; - -extern enum asic_type asic; -extern const struct register_map *register_map; -extern unsigned long asic_phy_base; /* Physical address of ASIC */ -extern unsigned long asic_base; /* Virtual address of ASIC */ - -/* - * Macros to interface to registers through their ioremapped address - * asic_reg_offset Returns the offset of a given register from the start - * of the ASIC address space - * asic_reg_phys_addr Returns the physical address of the given register - * asic_reg_addr Returns the iomapped virtual address of the given - * register. - */ -#define asic_reg_offset(x) (register_map->x) -#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x)) -#define asic_reg_addr(x) \ - ((unsigned int *) (asic_base + asic_reg_offset(x))) - -/* - * The asic_reg macro is gone. It should be replaced by either asic_read or - * asic_write, as appropriate. - */ - -#define asic_read(x) readl(asic_reg_addr(x)) -#define asic_write(v, x) writel(v, asic_reg_addr(x)) - -extern void asic_irq_init(void); -#endif diff --git a/trunk/arch/mips/include/asm/mach-powertv/dma-coherence.h b/trunk/arch/mips/include/asm/mach-powertv/dma-coherence.h deleted file mode 100644 index 5b8d5ebeb838..000000000000 --- a/trunk/arch/mips/include/asm/mach-powertv/dma-coherence.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Version from mach-generic modified to support PowerTV port - * Portions Copyright (C) 2009 Cisco Systems, Inc. - * Copyright (C) 2006 Ralf Baechle - * - */ - -#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H -#define __ASM_MACH_POWERTV_DMA_COHERENCE_H - -#include -#include -#include -#include - -static inline bool is_kseg2(void *addr) -{ - return (unsigned long)addr >= KSEG2; -} - -static inline unsigned long virt_to_phys_from_pte(void *addr) -{ - pgd_t *pgd; - pud_t *pud; - pmd_t *pmd; - pte_t *ptep, pte; - - unsigned long virt_addr = (unsigned long)addr; - unsigned long phys_addr = 0UL; - - /* get the page global directory. */ - pgd = pgd_offset_k(virt_addr); - - if (!pgd_none(*pgd)) { - /* get the page upper directory */ - pud = pud_offset(pgd, virt_addr); - if (!pud_none(*pud)) { - /* get the page middle directory */ - pmd = pmd_offset(pud, virt_addr); - if (!pmd_none(*pmd)) { - /* get a pointer to the page table entry */ - ptep = pte_offset(pmd, virt_addr); - pte = *ptep; - /* check for a valid page */ - if (pte_present(pte)) { - /* get the physical address the page is - * refering to */ - phys_addr = (unsigned long) - page_to_phys(pte_page(pte)); - /* add the offset within the page */ - phys_addr |= (virt_addr & ~PAGE_MASK); - } - } - } - } - - return phys_addr; -} - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - if (is_kseg2(addr)) - return phys_to_bus(virt_to_phys_from_pte(addr)); - else - return phys_to_bus(virt_to_phys(addr)); -} - -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return phys_to_bus(page_to_phys(page)); -} - -static inline unsigned long plat_dma_addr_to_phys(struct device *dev, - dma_addr_t dma_addr) -{ - return bus_to_phys(dma_addr); -} - -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction) -{ -} - -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 0; -} - -#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */ diff --git a/trunk/arch/mips/include/asm/mach-powertv/interrupts.h b/trunk/arch/mips/include/asm/mach-powertv/interrupts.h deleted file mode 100644 index 629a57413657..000000000000 --- a/trunk/arch/mips/include/asm/mach-powertv/interrupts.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ -#define _ASM_MACH_POWERTV_INTERRUPTS_H_ - -/* - * Defines for all of the interrupt lines - */ - -/* Definitions for backward compatibility */ -#define kIrq_Uart1 irq_uart1 - -#define ibase 0 - -/*------------- Register: int_stat_3 */ -/* 126 unused (bit 31) */ -#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */ -#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */ -#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */ -#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */ -#define irq_fdma_gp (ibase+122) /* FDMA GP Output */ -#define irq_mips_pic (ibase+121) /* MIPS Performance Counter - * Interrupt */ -#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */ -#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt - * -- Ored by glue logic inside - * SPARC ILC (see - * INT_MEM_PROT_STAT, below, - * for individual interrupts) - */ -/* 118 unused (bit 22) */ -#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by - * glue logic inside SPARC ILC - * (see INT_SBAG_STAT, below, - * for individual interrupts) */ -#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ -#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ -/* 114 unused (bit 18) */ -#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- - * Ored by glue logic inside - * SPARC ILC (see - * INT_MAILBOX_STAT, below, for - * individual interrupts) */ -#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */ -#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */ -#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse - * Status 3 */ -#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse - * Status 3 */ -#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0 - * Interrupt */ -#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1 - * Interrupt */ -#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE - * Interrupt */ -#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0 - * Interrupt */ -#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1 - * Interrupt */ -#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE - * Interrupt */ -#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */ -#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA - * Interrupt */ -#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */ -#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */ -#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */ -#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */ -#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */ -#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */ -/*------------- Register: int_stat_2 */ -#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */ -#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */ -#define irq_timer2 (ibase+93) /* Programmable Timer - * Interrupt 2 */ -#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */ -#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */ -#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */ -#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */ -#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */ -#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */ -#define irq_sata (ibase+87) /* SATA 1 Interrupt */ -#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ -#define irq_dtcp (ibase+86) /* DTCP Interrupt */ -#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ -/* 84 unused (bit 20) */ -/* 83 unused (bit 19) */ -/* 82 unused (bit 18) */ -#define irq_sata2 (ibase+81) /* SATA2 Interrupt */ -#define irq_uart2 (ibase+80) /* UART2 Interrupt */ -#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 - * Host module) */ -#define irq_pod (ibase+78) /* POD Interrupt */ -#define irq_slave_usb (ibase+77) /* Slave USB */ -#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */ -#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */ -#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */ -#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */ -#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */ -#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */ -#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ -#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ -#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ -/* 67 unused (bit 03) */ -/* 66 unused (bit 02) */ -/* 65 unused (bit 01) */ -/* 64 unused (bit 00) */ -/*------------- Register: int_stat_1 */ -/* 63 unused (bit 31) */ -/* 62 unused (bit 30) */ -/* 61 unused (bit 29) */ -/* 60 unused (bit 28) */ -/* 59 unused (bit 27) */ -/* 58 unused (bit 26) */ -/* 57 unused (bit 25) */ -/* 56 unused (bit 24) */ -#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory - * Interrupt */ -#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit - * Interrupt */ -#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit - * Interrupt */ -#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error - * Interrupt */ -#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive - * Interrupt */ -#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive - * Interrupt */ -#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error - * Interrupt */ -#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play - * Interrupt */ -#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error - * Interrupt */ -#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High - * (Chans 63-32) */ -#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low - * (Chans 31-0) */ -#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High - * (Chans 63-32) */ -#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low - * (Chans 31-0) */ -#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error - * Interrupt */ -#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */ -#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready - * Interrupt */ -#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */ -#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O - * Module */ -#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O - * Module (ABE_intN) */ -#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or - * Discontinuity 1 */ -#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or - * Discontinuity 2 */ -#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect - * (PEI) */ -#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error - * detect */ -#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */ -/*------------- Register: int_stat_0 */ -#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O - * Module */ -#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O - * Module */ -#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha - * (chan 3) Transmission - * Completed OK */ -#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2) - * Transmission Completed OK */ -#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation - * (chan 1) Transmission - * Completed OK */ -#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha - * (chan 3)Transmission - * completed with Errors. */ -#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2) - * Transmission completed with - * Errors. */ -#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation - * (chan 1) Transmission - * completed with Errors */ -#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha - * for N times. Aloha retry - * timeout for channel 3. */ -#define irq_timer1 (ibase+22) /* Programmable Timer - * Interrupt */ -#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */ -#define irq_i2c (ibase+20) /* I2C Module Interrupt */ -#define irq_spi (ibase+19) /* SPI Module Interrupt */ -#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */ -#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or - * Splice Detect Interrupt */ -#define irq_se_micro (ibase+16) /* Secure Micro I/F Module - * Interrupt */ -#define irq_uart1 (ibase+15) /* UART Interrupt */ -#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */ -#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */ -#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */ -#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ -#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error - * Interrupt */ -/* 9 unused (bit 09) */ -/* 8 unused (bit 08) */ -#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error - * Interrupt */ -#define irq_psilength_err (ibase+6) /* QAM PSI Length Error - * Interrupt */ -#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From - * Forward Path Reference - - * every 3ms when forward Mbits - * and forward slot control - * bytes are updated. */ -#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from - * Reverse Path Reference - - * delayed from forward mark by - * the ranging delay plus a - * fixed amount. When reverse - * Mbits and reverse slot - * control bytes are updated. - * Occurs every 3ms for 3.0M and - * 1.554 M upstream rates and - * every 6 ms for 256K upstream - * rate. */ -#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on - * Channel 1. */ -#define irq_reservation (ibase+2) /* Partial (or Incremental) - * Reservation Message Completed - * or Slotted aloha verify for - * channel 1. */ -#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify - * Interrupt or Reservation - * increment completed for - * channel 3. */ -#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ -#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ - diff --git a/trunk/arch/mips/include/asm/mach-powertv/ioremap.h b/trunk/arch/mips/include/asm/mach-powertv/ioremap.h deleted file mode 100644 index e6276d5146e8..000000000000 --- a/trunk/arch/mips/include/asm/mach-powertv/ioremap.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Portions Copyright (C) Cisco Systems, Inc. - */ -#ifndef __ASM_MACH_POWERTV_IOREMAP_H -#define __ASM_MACH_POWERTV_IOREMAP_H - -#include - -#define LOW_MEM_BOUNDARY_PHYS 0x20000000 -#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1)) - -/* - * The bus addresses are different than the physical addresses that - * the processor sees by an offset. This offset varies by ASIC - * version. Define a variable to hold the offset and some macros to - * make the conversion simpler. */ -extern unsigned long phys_to_bus_offset; - -#ifdef CONFIG_HIGHMEM -#define MEM_GAP_PHYS 0x60000000 -/* - * TODO: We will use the hard code for conversion between physical and - * bus until the bootloader releases their device tree to us. - */ -#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \ - ((x) + phys_to_bus_offset) : (x)) -#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \ - ((x) - phys_to_bus_offset) : (x)) -#else -#define phys_to_bus(x) ((x) + phys_to_bus_offset) -#define bus_to_phys(x) ((x) - phys_to_bus_offset) -#endif - -/* - * Determine whether the address we are given is for an ASIC device - * Params: addr Address to check - * Returns: Zero if the address is not for ASIC devices, non-zero - * if it is. - */ -static inline int asic_is_device_addr(phys_t addr) -{ - return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK); -} - -/* - * Determine whether the address we are given is external RAM mappable - * into KSEG1. - * Params: addr Address to check - * Returns: Zero if the address is not for external RAM and - */ -static inline int asic_is_lowmem_ram_addr(phys_t addr) -{ - /* - * The RAM always starts at the following address in the processor's - * physical address space - */ - static const phys_t phys_ram_base = 0x10000000; - phys_t bus_ram_base; - - bus_ram_base = phys_to_bus_offset + phys_ram_base; - - return addr >= bus_ram_base && - addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base)); -} - -/* - * Allow physical addresses to be fixed up to help peripherals located - * outside the low 32-bit range -- generic pass-through version. - */ -static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) -{ - return phys_addr; -} - -static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, - unsigned long flags) -{ - return NULL; -} - -static inline int plat_iounmap(const volatile void __iomem *addr) -{ - return 0; -} -#endif /* __ASM_MACH_POWERTV_IOREMAP_H */ diff --git a/trunk/arch/mips/include/asm/mach-powertv/irq.h b/trunk/arch/mips/include/asm/mach-powertv/irq.h deleted file mode 100644 index 4bd5d0c61a91..000000000000 --- a/trunk/arch/mips/include/asm/mach-powertv/irq.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _ASM_MACH_POWERTV_IRQ_H -#define _ASM_MACH_POWERTV_IRQ_H -#include - -#define MIPS_CPU_IRQ_BASE ibase -#define NR_IRQS 127 -#endif diff --git a/trunk/arch/mips/include/asm/mach-powertv/powertv-clock.h b/trunk/arch/mips/include/asm/mach-powertv/powertv-clock.h deleted file mode 100644 index 6f3e9a0fcf8c..000000000000 --- a/trunk/arch/mips/include/asm/mach-powertv/powertv-clock.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -/* - * Local definitions for the powertv PCI code - */ - -#ifndef _POWERTV_PCI_POWERTV_PCI_H_ -#define _POWERTV_PCI_POWERTV_PCI_H_ -extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -extern int asic_pcie_init(void); -extern int asic_pcie_init(void); - -extern int log_level; -#endif diff --git a/trunk/arch/mips/include/asm/mips-boards/bonito64.h b/trunk/arch/mips/include/asm/mips-boards/bonito64.h index d14e2adc4be5..a576ce044c3c 100644 --- a/trunk/arch/mips/include/asm/mips-boards/bonito64.h +++ b/trunk/arch/mips/include/asm/mips-boards/bonito64.h @@ -26,6 +26,11 @@ /* offsets from base register */ #define BONITO(x) (x) +#elif defined(CONFIG_LEMOTE_FULOONG2E) + +#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) +#define BONITO_IRQ_BASE 32 + #else /* diff --git a/trunk/arch/mips/include/asm/mmu_context.h b/trunk/arch/mips/include/asm/mmu_context.h index 145bb81ccaa5..6083db586500 100644 --- a/trunk/arch/mips/include/asm/mmu_context.h +++ b/trunk/arch/mips/include/asm/mmu_context.h @@ -24,33 +24,6 @@ #endif /* SMTC */ #include -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - -#define TLBMISS_HANDLER_SETUP_PGD(pgd) \ - tlbmiss_handler_setup_pgd((unsigned long)(pgd)) - -static inline void tlbmiss_handler_setup_pgd(unsigned long pgd) -{ - /* Check for swapper_pg_dir and convert to physical address. */ - if ((pgd & CKSEG3) == CKSEG0) - pgd = CPHYSADDR(pgd); - write_c0_context(pgd << 11); -} - -#define TLBMISS_HANDLER_SETUP() \ - do { \ - TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ - write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ - } while (0) - - -static inline unsigned long get_current_pgd(void) -{ - return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL); -} - -#else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ - /* * For the fast tlb miss handlers, we keep a per cpu array of pointers * to the current pgd for each processor. Also, the proc. id is stuffed @@ -73,7 +46,7 @@ extern unsigned long pgd_current[]; back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif -#endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ + #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) #define ASID_INC 0x40 diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h deleted file mode 100644 index ec94b9ab7be1..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-agl-defs.h +++ /dev/null @@ -1,1194 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_AGL_DEFS_H__ -#define __CVMX_AGL_DEFS_H__ - -#define CVMX_AGL_GMX_BAD_REG \ - CVMX_ADD_IO_SEG(0x00011800E0000518ull) -#define CVMX_AGL_GMX_BIST \ - CVMX_ADD_IO_SEG(0x00011800E0000400ull) -#define CVMX_AGL_GMX_DRV_CTL \ - CVMX_ADD_IO_SEG(0x00011800E00007F0ull) -#define CVMX_AGL_GMX_INF_MODE \ - CVMX_ADD_IO_SEG(0x00011800E00007F8ull) -#define CVMX_AGL_GMX_PRTX_CFG(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000010ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000180ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000188ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000190ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000198ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00001A0ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00001A8ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000108ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000100ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_DECISION(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000040ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000020ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000018ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000030ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000028ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_IFG(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000058ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_INT_EN(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000008ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_INT_REG(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000000ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_JABBER(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000038ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000068ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000050ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000088ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000098ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00000A8ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00000B8ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000080ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00000C0ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000090ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00000A0ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00000B0ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000048ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_RX_BP_DROPX(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000420ull + (((offset) & 1) * 8)) -#define CVMX_AGL_GMX_RX_BP_OFFX(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000460ull + (((offset) & 1) * 8)) -#define CVMX_AGL_GMX_RX_BP_ONX(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000440ull + (((offset) & 1) * 8)) -#define CVMX_AGL_GMX_RX_PRT_INFO \ - CVMX_ADD_IO_SEG(0x00011800E00004E8ull) -#define CVMX_AGL_GMX_RX_TX_STATUS \ - CVMX_ADD_IO_SEG(0x00011800E00007E8ull) -#define CVMX_AGL_GMX_SMACX(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000230ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_STAT_BP \ - CVMX_ADD_IO_SEG(0x00011800E0000520ull) -#define CVMX_AGL_GMX_TXX_APPEND(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000218ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_CTL(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000270ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000240ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000248ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000238ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000258ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000260ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000250ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT0(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000280ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT1(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000288ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT2(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000290ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT3(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000298ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT4(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00002A0ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT5(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00002A8ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT6(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00002B0ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT7(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00002B8ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT8(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00002C0ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STAT9(offset) \ - CVMX_ADD_IO_SEG(0x00011800E00002C8ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000268ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TXX_THRESH(offset) \ - CVMX_ADD_IO_SEG(0x00011800E0000210ull + (((offset) & 1) * 2048)) -#define CVMX_AGL_GMX_TX_BP \ - CVMX_ADD_IO_SEG(0x00011800E00004D0ull) -#define CVMX_AGL_GMX_TX_COL_ATTEMPT \ - CVMX_ADD_IO_SEG(0x00011800E0000498ull) -#define CVMX_AGL_GMX_TX_IFG \ - CVMX_ADD_IO_SEG(0x00011800E0000488ull) -#define CVMX_AGL_GMX_TX_INT_EN \ - CVMX_ADD_IO_SEG(0x00011800E0000508ull) -#define CVMX_AGL_GMX_TX_INT_REG \ - CVMX_ADD_IO_SEG(0x00011800E0000500ull) -#define CVMX_AGL_GMX_TX_JAM \ - CVMX_ADD_IO_SEG(0x00011800E0000490ull) -#define CVMX_AGL_GMX_TX_LFSR \ - CVMX_ADD_IO_SEG(0x00011800E00004F8ull) -#define CVMX_AGL_GMX_TX_OVR_BP \ - CVMX_ADD_IO_SEG(0x00011800E00004C8ull) -#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC \ - CVMX_ADD_IO_SEG(0x00011800E00004A0ull) -#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE \ - CVMX_ADD_IO_SEG(0x00011800E00004A8ull) - -union cvmx_agl_gmx_bad_reg { - uint64_t u64; - struct cvmx_agl_gmx_bad_reg_s { - uint64_t reserved_38_63:26; - uint64_t txpsh1:1; - uint64_t txpop1:1; - uint64_t ovrflw1:1; - uint64_t txpsh:1; - uint64_t txpop:1; - uint64_t ovrflw:1; - uint64_t reserved_27_31:5; - uint64_t statovr:1; - uint64_t reserved_23_25:3; - uint64_t loststat:1; - uint64_t reserved_4_21:18; - uint64_t out_ovr:2; - uint64_t reserved_0_1:2; - } s; - struct cvmx_agl_gmx_bad_reg_s cn52xx; - struct cvmx_agl_gmx_bad_reg_s cn52xxp1; - struct cvmx_agl_gmx_bad_reg_cn56xx { - uint64_t reserved_35_63:29; - uint64_t txpsh:1; - uint64_t txpop:1; - uint64_t ovrflw:1; - uint64_t reserved_27_31:5; - uint64_t statovr:1; - uint64_t reserved_23_25:3; - uint64_t loststat:1; - uint64_t reserved_3_21:19; - uint64_t out_ovr:1; - uint64_t reserved_0_1:2; - } cn56xx; - struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1; -}; - -union cvmx_agl_gmx_bist { - uint64_t u64; - struct cvmx_agl_gmx_bist_s { - uint64_t reserved_10_63:54; - uint64_t status:10; - } s; - struct cvmx_agl_gmx_bist_s cn52xx; - struct cvmx_agl_gmx_bist_s cn52xxp1; - struct cvmx_agl_gmx_bist_s cn56xx; - struct cvmx_agl_gmx_bist_s cn56xxp1; -}; - -union cvmx_agl_gmx_drv_ctl { - uint64_t u64; - struct cvmx_agl_gmx_drv_ctl_s { - uint64_t reserved_49_63:15; - uint64_t byp_en1:1; - uint64_t reserved_45_47:3; - uint64_t pctl1:5; - uint64_t reserved_37_39:3; - uint64_t nctl1:5; - uint64_t reserved_17_31:15; - uint64_t byp_en:1; - uint64_t reserved_13_15:3; - uint64_t pctl:5; - uint64_t reserved_5_7:3; - uint64_t nctl:5; - } s; - struct cvmx_agl_gmx_drv_ctl_s cn52xx; - struct cvmx_agl_gmx_drv_ctl_s cn52xxp1; - struct cvmx_agl_gmx_drv_ctl_cn56xx { - uint64_t reserved_17_63:47; - uint64_t byp_en:1; - uint64_t reserved_13_15:3; - uint64_t pctl:5; - uint64_t reserved_5_7:3; - uint64_t nctl:5; - } cn56xx; - struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1; -}; - -union cvmx_agl_gmx_inf_mode { - uint64_t u64; - struct cvmx_agl_gmx_inf_mode_s { - uint64_t reserved_2_63:62; - uint64_t en:1; - uint64_t reserved_0_0:1; - } s; - struct cvmx_agl_gmx_inf_mode_s cn52xx; - struct cvmx_agl_gmx_inf_mode_s cn52xxp1; - struct cvmx_agl_gmx_inf_mode_s cn56xx; - struct cvmx_agl_gmx_inf_mode_s cn56xxp1; -}; - -union cvmx_agl_gmx_prtx_cfg { - uint64_t u64; - struct cvmx_agl_gmx_prtx_cfg_s { - uint64_t reserved_6_63:58; - uint64_t tx_en:1; - uint64_t rx_en:1; - uint64_t slottime:1; - uint64_t duplex:1; - uint64_t speed:1; - uint64_t en:1; - } s; - struct cvmx_agl_gmx_prtx_cfg_s cn52xx; - struct cvmx_agl_gmx_prtx_cfg_s cn52xxp1; - struct cvmx_agl_gmx_prtx_cfg_s cn56xx; - struct cvmx_agl_gmx_prtx_cfg_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_adr_cam0 { - uint64_t u64; - struct cvmx_agl_gmx_rxx_adr_cam0_s { - uint64_t adr:64; - } s; - struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx; - struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1; - struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx; - struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_adr_cam1 { - uint64_t u64; - struct cvmx_agl_gmx_rxx_adr_cam1_s { - uint64_t adr:64; - } s; - struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx; - struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1; - struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx; - struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_adr_cam2 { - uint64_t u64; - struct cvmx_agl_gmx_rxx_adr_cam2_s { - uint64_t adr:64; - } s; - struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx; - struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1; - struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx; - struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_adr_cam3 { - uint64_t u64; - struct cvmx_agl_gmx_rxx_adr_cam3_s { - uint64_t adr:64; - } s; - struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx; - struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1; - struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx; - struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_adr_cam4 { - uint64_t u64; - struct cvmx_agl_gmx_rxx_adr_cam4_s { - uint64_t adr:64; - } s; - struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx; - struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1; - struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx; - struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_adr_cam5 { - uint64_t u64; - struct cvmx_agl_gmx_rxx_adr_cam5_s { - uint64_t adr:64; - } s; - struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx; - struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1; - struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx; - struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_adr_cam_en { - uint64_t u64; - struct cvmx_agl_gmx_rxx_adr_cam_en_s { - uint64_t reserved_8_63:56; - uint64_t en:8; - } s; - struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx; - struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1; - struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx; - struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_adr_ctl { - uint64_t u64; - struct cvmx_agl_gmx_rxx_adr_ctl_s { - uint64_t reserved_4_63:60; - uint64_t cam_mode:1; - uint64_t mcst:2; - uint64_t bcst:1; - } s; - struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx; - struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1; - struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx; - struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_decision { - uint64_t u64; - struct cvmx_agl_gmx_rxx_decision_s { - uint64_t reserved_5_63:59; - uint64_t cnt:5; - } s; - struct cvmx_agl_gmx_rxx_decision_s cn52xx; - struct cvmx_agl_gmx_rxx_decision_s cn52xxp1; - struct cvmx_agl_gmx_rxx_decision_s cn56xx; - struct cvmx_agl_gmx_rxx_decision_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_frm_chk { - uint64_t u64; - struct cvmx_agl_gmx_rxx_frm_chk_s { - uint64_t reserved_9_63:55; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t reserved_1_1:1; - uint64_t minerr:1; - } s; - struct cvmx_agl_gmx_rxx_frm_chk_s cn52xx; - struct cvmx_agl_gmx_rxx_frm_chk_s cn52xxp1; - struct cvmx_agl_gmx_rxx_frm_chk_s cn56xx; - struct cvmx_agl_gmx_rxx_frm_chk_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_frm_ctl { - uint64_t u64; - struct cvmx_agl_gmx_rxx_frm_ctl_s { - uint64_t reserved_10_63:54; - uint64_t pre_align:1; - uint64_t pad_len:1; - uint64_t vlan_len:1; - uint64_t pre_free:1; - uint64_t ctl_smac:1; - uint64_t ctl_mcst:1; - uint64_t ctl_bck:1; - uint64_t ctl_drp:1; - uint64_t pre_strp:1; - uint64_t pre_chk:1; - } s; - struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xx; - struct cvmx_agl_gmx_rxx_frm_ctl_s cn52xxp1; - struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xx; - struct cvmx_agl_gmx_rxx_frm_ctl_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_frm_max { - uint64_t u64; - struct cvmx_agl_gmx_rxx_frm_max_s { - uint64_t reserved_16_63:48; - uint64_t len:16; - } s; - struct cvmx_agl_gmx_rxx_frm_max_s cn52xx; - struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1; - struct cvmx_agl_gmx_rxx_frm_max_s cn56xx; - struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_frm_min { - uint64_t u64; - struct cvmx_agl_gmx_rxx_frm_min_s { - uint64_t reserved_16_63:48; - uint64_t len:16; - } s; - struct cvmx_agl_gmx_rxx_frm_min_s cn52xx; - struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1; - struct cvmx_agl_gmx_rxx_frm_min_s cn56xx; - struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_ifg { - uint64_t u64; - struct cvmx_agl_gmx_rxx_ifg_s { - uint64_t reserved_4_63:60; - uint64_t ifg:4; - } s; - struct cvmx_agl_gmx_rxx_ifg_s cn52xx; - struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1; - struct cvmx_agl_gmx_rxx_ifg_s cn56xx; - struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_int_en { - uint64_t u64; - struct cvmx_agl_gmx_rxx_int_en_s { - uint64_t reserved_20_63:44; - uint64_t pause_drp:1; - uint64_t reserved_16_18:3; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t reserved_9_9:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t reserved_1_1:1; - uint64_t minerr:1; - } s; - struct cvmx_agl_gmx_rxx_int_en_s cn52xx; - struct cvmx_agl_gmx_rxx_int_en_s cn52xxp1; - struct cvmx_agl_gmx_rxx_int_en_s cn56xx; - struct cvmx_agl_gmx_rxx_int_en_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_int_reg { - uint64_t u64; - struct cvmx_agl_gmx_rxx_int_reg_s { - uint64_t reserved_20_63:44; - uint64_t pause_drp:1; - uint64_t reserved_16_18:3; - uint64_t ifgerr:1; - uint64_t coldet:1; - uint64_t falerr:1; - uint64_t rsverr:1; - uint64_t pcterr:1; - uint64_t ovrerr:1; - uint64_t reserved_9_9:1; - uint64_t skperr:1; - uint64_t rcverr:1; - uint64_t lenerr:1; - uint64_t alnerr:1; - uint64_t fcserr:1; - uint64_t jabber:1; - uint64_t maxerr:1; - uint64_t reserved_1_1:1; - uint64_t minerr:1; - } s; - struct cvmx_agl_gmx_rxx_int_reg_s cn52xx; - struct cvmx_agl_gmx_rxx_int_reg_s cn52xxp1; - struct cvmx_agl_gmx_rxx_int_reg_s cn56xx; - struct cvmx_agl_gmx_rxx_int_reg_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_jabber { - uint64_t u64; - struct cvmx_agl_gmx_rxx_jabber_s { - uint64_t reserved_16_63:48; - uint64_t cnt:16; - } s; - struct cvmx_agl_gmx_rxx_jabber_s cn52xx; - struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1; - struct cvmx_agl_gmx_rxx_jabber_s cn56xx; - struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_pause_drop_time { - uint64_t u64; - struct cvmx_agl_gmx_rxx_pause_drop_time_s { - uint64_t reserved_16_63:48; - uint64_t status:16; - } s; - struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx; - struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1; - struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx; - struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_ctl { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_ctl_s { - uint64_t reserved_1_63:63; - uint64_t rd_clr:1; - } s; - struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_octs { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_octs_s { - uint64_t reserved_48_63:16; - uint64_t cnt:48; - } s; - struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_octs_ctl { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s { - uint64_t reserved_48_63:16; - uint64_t cnt:48; - } s; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_octs_dmac { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s { - uint64_t reserved_48_63:16; - uint64_t cnt:48; - } s; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_octs_drp { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s { - uint64_t reserved_48_63:16; - uint64_t cnt:48; - } s; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_pkts { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_pkts_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_pkts_bad { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_pkts_ctl { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_pkts_dmac { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_stats_pkts_drp { - uint64_t u64; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s { - uint64_t reserved_32_63:32; - uint64_t cnt:32; - } s; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx; - struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1; -}; - -union cvmx_agl_gmx_rxx_udd_skp { - uint64_t u64; - struct cvmx_agl_gmx_rxx_udd_skp_s { - uint64_t reserved_9_63:55; - uint64_t fcssel:1; - uint64_t reserved_7_7:1; - uint64_t len:7; - } s; - struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx; - struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1; - struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx; - struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1; -}; - -union cvmx_agl_gmx_rx_bp_dropx { - uint64_t u64; - struct cvmx_agl_gmx_rx_bp_dropx_s { - uint64_t reserved_6_63:58; - uint64_t mark:6; - } s; - struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx; - struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1; - struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx; - struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1; -}; - -union cvmx_agl_gmx_rx_bp_offx { - uint64_t u64; - struct cvmx_agl_gmx_rx_bp_offx_s { - uint64_t reserved_6_63:58; - uint64_t mark:6; - } s; - struct cvmx_agl_gmx_rx_bp_offx_s cn52xx; - struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1; - struct cvmx_agl_gmx_rx_bp_offx_s cn56xx; - struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1; -}; - -union cvmx_agl_gmx_rx_bp_onx { - uint64_t u64; - struct cvmx_agl_gmx_rx_bp_onx_s { - uint64_t reserved_9_63:55; - uint64_t mark:9; - } s; - struct cvmx_agl_gmx_rx_bp_onx_s cn52xx; - struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1; - struct cvmx_agl_gmx_rx_bp_onx_s cn56xx; - struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1; -}; - -union cvmx_agl_gmx_rx_prt_info { - uint64_t u64; - struct cvmx_agl_gmx_rx_prt_info_s { - uint64_t reserved_18_63:46; - uint64_t drop:2; - uint64_t reserved_2_15:14; - uint64_t commit:2; - } s; - struct cvmx_agl_gmx_rx_prt_info_s cn52xx; - struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1; - struct cvmx_agl_gmx_rx_prt_info_cn56xx { - uint64_t reserved_17_63:47; - uint64_t drop:1; - uint64_t reserved_1_15:15; - uint64_t commit:1; - } cn56xx; - struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1; -}; - -union cvmx_agl_gmx_rx_tx_status { - uint64_t u64; - struct cvmx_agl_gmx_rx_tx_status_s { - uint64_t reserved_6_63:58; - uint64_t tx:2; - uint64_t reserved_2_3:2; - uint64_t rx:2; - } s; - struct cvmx_agl_gmx_rx_tx_status_s cn52xx; - struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1; - struct cvmx_agl_gmx_rx_tx_status_cn56xx { - uint64_t reserved_5_63:59; - uint64_t tx:1; - uint64_t reserved_1_3:3; - uint64_t rx:1; - } cn56xx; - struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1; -}; - -union cvmx_agl_gmx_smacx { - uint64_t u64; - struct cvmx_agl_gmx_smacx_s { - uint64_t reserved_48_63:16; - uint64_t smac:48; - } s; - struct cvmx_agl_gmx_smacx_s cn52xx; - struct cvmx_agl_gmx_smacx_s cn52xxp1; - struct cvmx_agl_gmx_smacx_s cn56xx; - struct cvmx_agl_gmx_smacx_s cn56xxp1; -}; - -union cvmx_agl_gmx_stat_bp { - uint64_t u64; - struct cvmx_agl_gmx_stat_bp_s { - uint64_t reserved_17_63:47; - uint64_t bp:1; - uint64_t cnt:16; - } s; - struct cvmx_agl_gmx_stat_bp_s cn52xx; - struct cvmx_agl_gmx_stat_bp_s cn52xxp1; - struct cvmx_agl_gmx_stat_bp_s cn56xx; - struct cvmx_agl_gmx_stat_bp_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_append { - uint64_t u64; - struct cvmx_agl_gmx_txx_append_s { - uint64_t reserved_4_63:60; - uint64_t force_fcs:1; - uint64_t fcs:1; - uint64_t pad:1; - uint64_t preamble:1; - } s; - struct cvmx_agl_gmx_txx_append_s cn52xx; - struct cvmx_agl_gmx_txx_append_s cn52xxp1; - struct cvmx_agl_gmx_txx_append_s cn56xx; - struct cvmx_agl_gmx_txx_append_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_ctl { - uint64_t u64; - struct cvmx_agl_gmx_txx_ctl_s { - uint64_t reserved_2_63:62; - uint64_t xsdef_en:1; - uint64_t xscol_en:1; - } s; - struct cvmx_agl_gmx_txx_ctl_s cn52xx; - struct cvmx_agl_gmx_txx_ctl_s cn52xxp1; - struct cvmx_agl_gmx_txx_ctl_s cn56xx; - struct cvmx_agl_gmx_txx_ctl_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_min_pkt { - uint64_t u64; - struct cvmx_agl_gmx_txx_min_pkt_s { - uint64_t reserved_8_63:56; - uint64_t min_size:8; - } s; - struct cvmx_agl_gmx_txx_min_pkt_s cn52xx; - struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1; - struct cvmx_agl_gmx_txx_min_pkt_s cn56xx; - struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_pause_pkt_interval { - uint64_t u64; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s { - uint64_t reserved_16_63:48; - uint64_t interval:16; - } s; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx; - struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_pause_pkt_time { - uint64_t u64; - struct cvmx_agl_gmx_txx_pause_pkt_time_s { - uint64_t reserved_16_63:48; - uint64_t time:16; - } s; - struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx; - struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1; - struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx; - struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_pause_togo { - uint64_t u64; - struct cvmx_agl_gmx_txx_pause_togo_s { - uint64_t reserved_16_63:48; - uint64_t time:16; - } s; - struct cvmx_agl_gmx_txx_pause_togo_s cn52xx; - struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1; - struct cvmx_agl_gmx_txx_pause_togo_s cn56xx; - struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_pause_zero { - uint64_t u64; - struct cvmx_agl_gmx_txx_pause_zero_s { - uint64_t reserved_1_63:63; - uint64_t send:1; - } s; - struct cvmx_agl_gmx_txx_pause_zero_s cn52xx; - struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1; - struct cvmx_agl_gmx_txx_pause_zero_s cn56xx; - struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_soft_pause { - uint64_t u64; - struct cvmx_agl_gmx_txx_soft_pause_s { - uint64_t reserved_16_63:48; - uint64_t time:16; - } s; - struct cvmx_agl_gmx_txx_soft_pause_s cn52xx; - struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1; - struct cvmx_agl_gmx_txx_soft_pause_s cn56xx; - struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat0 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat0_s { - uint64_t xsdef:32; - uint64_t xscol:32; - } s; - struct cvmx_agl_gmx_txx_stat0_s cn52xx; - struct cvmx_agl_gmx_txx_stat0_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat0_s cn56xx; - struct cvmx_agl_gmx_txx_stat0_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat1 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat1_s { - uint64_t scol:32; - uint64_t mcol:32; - } s; - struct cvmx_agl_gmx_txx_stat1_s cn52xx; - struct cvmx_agl_gmx_txx_stat1_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat1_s cn56xx; - struct cvmx_agl_gmx_txx_stat1_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat2 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat2_s { - uint64_t reserved_48_63:16; - uint64_t octs:48; - } s; - struct cvmx_agl_gmx_txx_stat2_s cn52xx; - struct cvmx_agl_gmx_txx_stat2_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat2_s cn56xx; - struct cvmx_agl_gmx_txx_stat2_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat3 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat3_s { - uint64_t reserved_32_63:32; - uint64_t pkts:32; - } s; - struct cvmx_agl_gmx_txx_stat3_s cn52xx; - struct cvmx_agl_gmx_txx_stat3_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat3_s cn56xx; - struct cvmx_agl_gmx_txx_stat3_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat4 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat4_s { - uint64_t hist1:32; - uint64_t hist0:32; - } s; - struct cvmx_agl_gmx_txx_stat4_s cn52xx; - struct cvmx_agl_gmx_txx_stat4_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat4_s cn56xx; - struct cvmx_agl_gmx_txx_stat4_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat5 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat5_s { - uint64_t hist3:32; - uint64_t hist2:32; - } s; - struct cvmx_agl_gmx_txx_stat5_s cn52xx; - struct cvmx_agl_gmx_txx_stat5_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat5_s cn56xx; - struct cvmx_agl_gmx_txx_stat5_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat6 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat6_s { - uint64_t hist5:32; - uint64_t hist4:32; - } s; - struct cvmx_agl_gmx_txx_stat6_s cn52xx; - struct cvmx_agl_gmx_txx_stat6_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat6_s cn56xx; - struct cvmx_agl_gmx_txx_stat6_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat7 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat7_s { - uint64_t hist7:32; - uint64_t hist6:32; - } s; - struct cvmx_agl_gmx_txx_stat7_s cn52xx; - struct cvmx_agl_gmx_txx_stat7_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat7_s cn56xx; - struct cvmx_agl_gmx_txx_stat7_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat8 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat8_s { - uint64_t mcst:32; - uint64_t bcst:32; - } s; - struct cvmx_agl_gmx_txx_stat8_s cn52xx; - struct cvmx_agl_gmx_txx_stat8_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat8_s cn56xx; - struct cvmx_agl_gmx_txx_stat8_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stat9 { - uint64_t u64; - struct cvmx_agl_gmx_txx_stat9_s { - uint64_t undflw:32; - uint64_t ctl:32; - } s; - struct cvmx_agl_gmx_txx_stat9_s cn52xx; - struct cvmx_agl_gmx_txx_stat9_s cn52xxp1; - struct cvmx_agl_gmx_txx_stat9_s cn56xx; - struct cvmx_agl_gmx_txx_stat9_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_stats_ctl { - uint64_t u64; - struct cvmx_agl_gmx_txx_stats_ctl_s { - uint64_t reserved_1_63:63; - uint64_t rd_clr:1; - } s; - struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx; - struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1; - struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx; - struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1; -}; - -union cvmx_agl_gmx_txx_thresh { - uint64_t u64; - struct cvmx_agl_gmx_txx_thresh_s { - uint64_t reserved_6_63:58; - uint64_t cnt:6; - } s; - struct cvmx_agl_gmx_txx_thresh_s cn52xx; - struct cvmx_agl_gmx_txx_thresh_s cn52xxp1; - struct cvmx_agl_gmx_txx_thresh_s cn56xx; - struct cvmx_agl_gmx_txx_thresh_s cn56xxp1; -}; - -union cvmx_agl_gmx_tx_bp { - uint64_t u64; - struct cvmx_agl_gmx_tx_bp_s { - uint64_t reserved_2_63:62; - uint64_t bp:2; - } s; - struct cvmx_agl_gmx_tx_bp_s cn52xx; - struct cvmx_agl_gmx_tx_bp_s cn52xxp1; - struct cvmx_agl_gmx_tx_bp_cn56xx { - uint64_t reserved_1_63:63; - uint64_t bp:1; - } cn56xx; - struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1; -}; - -union cvmx_agl_gmx_tx_col_attempt { - uint64_t u64; - struct cvmx_agl_gmx_tx_col_attempt_s { - uint64_t reserved_5_63:59; - uint64_t limit:5; - } s; - struct cvmx_agl_gmx_tx_col_attempt_s cn52xx; - struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1; - struct cvmx_agl_gmx_tx_col_attempt_s cn56xx; - struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1; -}; - -union cvmx_agl_gmx_tx_ifg { - uint64_t u64; - struct cvmx_agl_gmx_tx_ifg_s { - uint64_t reserved_8_63:56; - uint64_t ifg2:4; - uint64_t ifg1:4; - } s; - struct cvmx_agl_gmx_tx_ifg_s cn52xx; - struct cvmx_agl_gmx_tx_ifg_s cn52xxp1; - struct cvmx_agl_gmx_tx_ifg_s cn56xx; - struct cvmx_agl_gmx_tx_ifg_s cn56xxp1; -}; - -union cvmx_agl_gmx_tx_int_en { - uint64_t u64; - struct cvmx_agl_gmx_tx_int_en_s { - uint64_t reserved_18_63:46; - uint64_t late_col:2; - uint64_t reserved_14_15:2; - uint64_t xsdef:2; - uint64_t reserved_10_11:2; - uint64_t xscol:2; - uint64_t reserved_4_7:4; - uint64_t undflw:2; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } s; - struct cvmx_agl_gmx_tx_int_en_s cn52xx; - struct cvmx_agl_gmx_tx_int_en_s cn52xxp1; - struct cvmx_agl_gmx_tx_int_en_cn56xx { - uint64_t reserved_17_63:47; - uint64_t late_col:1; - uint64_t reserved_13_15:3; - uint64_t xsdef:1; - uint64_t reserved_9_11:3; - uint64_t xscol:1; - uint64_t reserved_3_7:5; - uint64_t undflw:1; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } cn56xx; - struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1; -}; - -union cvmx_agl_gmx_tx_int_reg { - uint64_t u64; - struct cvmx_agl_gmx_tx_int_reg_s { - uint64_t reserved_18_63:46; - uint64_t late_col:2; - uint64_t reserved_14_15:2; - uint64_t xsdef:2; - uint64_t reserved_10_11:2; - uint64_t xscol:2; - uint64_t reserved_4_7:4; - uint64_t undflw:2; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } s; - struct cvmx_agl_gmx_tx_int_reg_s cn52xx; - struct cvmx_agl_gmx_tx_int_reg_s cn52xxp1; - struct cvmx_agl_gmx_tx_int_reg_cn56xx { - uint64_t reserved_17_63:47; - uint64_t late_col:1; - uint64_t reserved_13_15:3; - uint64_t xsdef:1; - uint64_t reserved_9_11:3; - uint64_t xscol:1; - uint64_t reserved_3_7:5; - uint64_t undflw:1; - uint64_t reserved_1_1:1; - uint64_t pko_nxa:1; - } cn56xx; - struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1; -}; - -union cvmx_agl_gmx_tx_jam { - uint64_t u64; - struct cvmx_agl_gmx_tx_jam_s { - uint64_t reserved_8_63:56; - uint64_t jam:8; - } s; - struct cvmx_agl_gmx_tx_jam_s cn52xx; - struct cvmx_agl_gmx_tx_jam_s cn52xxp1; - struct cvmx_agl_gmx_tx_jam_s cn56xx; - struct cvmx_agl_gmx_tx_jam_s cn56xxp1; -}; - -union cvmx_agl_gmx_tx_lfsr { - uint64_t u64; - struct cvmx_agl_gmx_tx_lfsr_s { - uint64_t reserved_16_63:48; - uint64_t lfsr:16; - } s; - struct cvmx_agl_gmx_tx_lfsr_s cn52xx; - struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1; - struct cvmx_agl_gmx_tx_lfsr_s cn56xx; - struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1; -}; - -union cvmx_agl_gmx_tx_ovr_bp { - uint64_t u64; - struct cvmx_agl_gmx_tx_ovr_bp_s { - uint64_t reserved_10_63:54; - uint64_t en:2; - uint64_t reserved_6_7:2; - uint64_t bp:2; - uint64_t reserved_2_3:2; - uint64_t ign_full:2; - } s; - struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx; - struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1; - struct cvmx_agl_gmx_tx_ovr_bp_cn56xx { - uint64_t reserved_9_63:55; - uint64_t en:1; - uint64_t reserved_5_7:3; - uint64_t bp:1; - uint64_t reserved_1_3:3; - uint64_t ign_full:1; - } cn56xx; - struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1; -}; - -union cvmx_agl_gmx_tx_pause_pkt_dmac { - uint64_t u64; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s { - uint64_t reserved_48_63:16; - uint64_t dmac:48; - } s; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx; - struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1; -}; - -union cvmx_agl_gmx_tx_pause_pkt_type { - uint64_t u64; - struct cvmx_agl_gmx_tx_pause_pkt_type_s { - uint64_t reserved_16_63:48; - uint64_t type:16; - } s; - struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx; - struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1; - struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx; - struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h deleted file mode 100644 index dab6dca492f9..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-mixx-defs.h +++ /dev/null @@ -1,248 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_MIXX_DEFS_H__ -#define __CVMX_MIXX_DEFS_H__ - -#define CVMX_MIXX_BIST(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100078ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_CTL(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100020ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_INTENA(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100050ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_IRCNT(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100030ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_IRHWM(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100028ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_IRING1(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100010ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_IRING2(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100018ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_ISR(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100048ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_ORCNT(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100040ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_ORHWM(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100038ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_ORING1(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100000ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_ORING2(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100008ull + (((offset) & 1) * 2048)) -#define CVMX_MIXX_REMCNT(offset) \ - CVMX_ADD_IO_SEG(0x0001070000100058ull + (((offset) & 1) * 2048)) - -union cvmx_mixx_bist { - uint64_t u64; - struct cvmx_mixx_bist_s { - uint64_t reserved_4_63:60; - uint64_t mrqdat:1; - uint64_t ipfdat:1; - uint64_t irfdat:1; - uint64_t orfdat:1; - } s; - struct cvmx_mixx_bist_s cn52xx; - struct cvmx_mixx_bist_s cn52xxp1; - struct cvmx_mixx_bist_s cn56xx; - struct cvmx_mixx_bist_s cn56xxp1; -}; - -union cvmx_mixx_ctl { - uint64_t u64; - struct cvmx_mixx_ctl_s { - uint64_t reserved_8_63:56; - uint64_t crc_strip:1; - uint64_t busy:1; - uint64_t en:1; - uint64_t reset:1; - uint64_t lendian:1; - uint64_t nbtarb:1; - uint64_t mrq_hwm:2; - } s; - struct cvmx_mixx_ctl_s cn52xx; - struct cvmx_mixx_ctl_s cn52xxp1; - struct cvmx_mixx_ctl_s cn56xx; - struct cvmx_mixx_ctl_s cn56xxp1; -}; - -union cvmx_mixx_intena { - uint64_t u64; - struct cvmx_mixx_intena_s { - uint64_t reserved_7_63:57; - uint64_t orunena:1; - uint64_t irunena:1; - uint64_t data_drpena:1; - uint64_t ithena:1; - uint64_t othena:1; - uint64_t ivfena:1; - uint64_t ovfena:1; - } s; - struct cvmx_mixx_intena_s cn52xx; - struct cvmx_mixx_intena_s cn52xxp1; - struct cvmx_mixx_intena_s cn56xx; - struct cvmx_mixx_intena_s cn56xxp1; -}; - -union cvmx_mixx_ircnt { - uint64_t u64; - struct cvmx_mixx_ircnt_s { - uint64_t reserved_20_63:44; - uint64_t ircnt:20; - } s; - struct cvmx_mixx_ircnt_s cn52xx; - struct cvmx_mixx_ircnt_s cn52xxp1; - struct cvmx_mixx_ircnt_s cn56xx; - struct cvmx_mixx_ircnt_s cn56xxp1; -}; - -union cvmx_mixx_irhwm { - uint64_t u64; - struct cvmx_mixx_irhwm_s { - uint64_t reserved_40_63:24; - uint64_t ibplwm:20; - uint64_t irhwm:20; - } s; - struct cvmx_mixx_irhwm_s cn52xx; - struct cvmx_mixx_irhwm_s cn52xxp1; - struct cvmx_mixx_irhwm_s cn56xx; - struct cvmx_mixx_irhwm_s cn56xxp1; -}; - -union cvmx_mixx_iring1 { - uint64_t u64; - struct cvmx_mixx_iring1_s { - uint64_t reserved_60_63:4; - uint64_t isize:20; - uint64_t reserved_36_39:4; - uint64_t ibase:33; - uint64_t reserved_0_2:3; - } s; - struct cvmx_mixx_iring1_s cn52xx; - struct cvmx_mixx_iring1_s cn52xxp1; - struct cvmx_mixx_iring1_s cn56xx; - struct cvmx_mixx_iring1_s cn56xxp1; -}; - -union cvmx_mixx_iring2 { - uint64_t u64; - struct cvmx_mixx_iring2_s { - uint64_t reserved_52_63:12; - uint64_t itlptr:20; - uint64_t reserved_20_31:12; - uint64_t idbell:20; - } s; - struct cvmx_mixx_iring2_s cn52xx; - struct cvmx_mixx_iring2_s cn52xxp1; - struct cvmx_mixx_iring2_s cn56xx; - struct cvmx_mixx_iring2_s cn56xxp1; -}; - -union cvmx_mixx_isr { - uint64_t u64; - struct cvmx_mixx_isr_s { - uint64_t reserved_7_63:57; - uint64_t orun:1; - uint64_t irun:1; - uint64_t data_drp:1; - uint64_t irthresh:1; - uint64_t orthresh:1; - uint64_t idblovf:1; - uint64_t odblovf:1; - } s; - struct cvmx_mixx_isr_s cn52xx; - struct cvmx_mixx_isr_s cn52xxp1; - struct cvmx_mixx_isr_s cn56xx; - struct cvmx_mixx_isr_s cn56xxp1; -}; - -union cvmx_mixx_orcnt { - uint64_t u64; - struct cvmx_mixx_orcnt_s { - uint64_t reserved_20_63:44; - uint64_t orcnt:20; - } s; - struct cvmx_mixx_orcnt_s cn52xx; - struct cvmx_mixx_orcnt_s cn52xxp1; - struct cvmx_mixx_orcnt_s cn56xx; - struct cvmx_mixx_orcnt_s cn56xxp1; -}; - -union cvmx_mixx_orhwm { - uint64_t u64; - struct cvmx_mixx_orhwm_s { - uint64_t reserved_20_63:44; - uint64_t orhwm:20; - } s; - struct cvmx_mixx_orhwm_s cn52xx; - struct cvmx_mixx_orhwm_s cn52xxp1; - struct cvmx_mixx_orhwm_s cn56xx; - struct cvmx_mixx_orhwm_s cn56xxp1; -}; - -union cvmx_mixx_oring1 { - uint64_t u64; - struct cvmx_mixx_oring1_s { - uint64_t reserved_60_63:4; - uint64_t osize:20; - uint64_t reserved_36_39:4; - uint64_t obase:33; - uint64_t reserved_0_2:3; - } s; - struct cvmx_mixx_oring1_s cn52xx; - struct cvmx_mixx_oring1_s cn52xxp1; - struct cvmx_mixx_oring1_s cn56xx; - struct cvmx_mixx_oring1_s cn56xxp1; -}; - -union cvmx_mixx_oring2 { - uint64_t u64; - struct cvmx_mixx_oring2_s { - uint64_t reserved_52_63:12; - uint64_t otlptr:20; - uint64_t reserved_20_31:12; - uint64_t odbell:20; - } s; - struct cvmx_mixx_oring2_s cn52xx; - struct cvmx_mixx_oring2_s cn52xxp1; - struct cvmx_mixx_oring2_s cn56xx; - struct cvmx_mixx_oring2_s cn56xxp1; -}; - -union cvmx_mixx_remcnt { - uint64_t u64; - struct cvmx_mixx_remcnt_s { - uint64_t reserved_52_63:12; - uint64_t iremcnt:20; - uint64_t reserved_20_31:12; - uint64_t oremcnt:20; - } s; - struct cvmx_mixx_remcnt_s cn52xx; - struct cvmx_mixx_remcnt_s cn52xxp1; - struct cvmx_mixx_remcnt_s cn56xx; - struct cvmx_mixx_remcnt_s cn56xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h b/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h deleted file mode 100644 index 9ae45fcbe3e3..000000000000 --- a/trunk/arch/mips/include/asm/octeon/cvmx-smix-defs.h +++ /dev/null @@ -1,178 +0,0 @@ -/***********************license start*************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2008 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information - ***********************license end**************************************/ - -#ifndef __CVMX_SMIX_DEFS_H__ -#define __CVMX_SMIX_DEFS_H__ - -#define CVMX_SMIX_CLK(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_CMD(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_EN(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_RD_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256)) -#define CVMX_SMIX_WR_DAT(offset) \ - CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256)) - -union cvmx_smix_clk { - uint64_t u64; - struct cvmx_smix_clk_s { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t sample_mode:1; - uint64_t reserved_14_14:1; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } s; - struct cvmx_smix_clk_cn30xx { - uint64_t reserved_21_63:43; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn30xx; - struct cvmx_smix_clk_cn30xx cn31xx; - struct cvmx_smix_clk_cn30xx cn38xx; - struct cvmx_smix_clk_cn30xx cn38xxp2; - struct cvmx_smix_clk_cn50xx { - uint64_t reserved_25_63:39; - uint64_t mode:1; - uint64_t reserved_21_23:3; - uint64_t sample_hi:5; - uint64_t reserved_14_15:2; - uint64_t clk_idle:1; - uint64_t preamble:1; - uint64_t sample:4; - uint64_t phase:8; - } cn50xx; - struct cvmx_smix_clk_s cn52xx; - struct cvmx_smix_clk_cn50xx cn52xxp1; - struct cvmx_smix_clk_s cn56xx; - struct cvmx_smix_clk_cn50xx cn56xxp1; - struct cvmx_smix_clk_cn30xx cn58xx; - struct cvmx_smix_clk_cn30xx cn58xxp1; -}; - -union cvmx_smix_cmd { - uint64_t u64; - struct cvmx_smix_cmd_s { - uint64_t reserved_18_63:46; - uint64_t phy_op:2; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } s; - struct cvmx_smix_cmd_cn30xx { - uint64_t reserved_17_63:47; - uint64_t phy_op:1; - uint64_t reserved_13_15:3; - uint64_t phy_adr:5; - uint64_t reserved_5_7:3; - uint64_t reg_adr:5; - } cn30xx; - struct cvmx_smix_cmd_cn30xx cn31xx; - struct cvmx_smix_cmd_cn30xx cn38xx; - struct cvmx_smix_cmd_cn30xx cn38xxp2; - struct cvmx_smix_cmd_s cn50xx; - struct cvmx_smix_cmd_s cn52xx; - struct cvmx_smix_cmd_s cn52xxp1; - struct cvmx_smix_cmd_s cn56xx; - struct cvmx_smix_cmd_s cn56xxp1; - struct cvmx_smix_cmd_cn30xx cn58xx; - struct cvmx_smix_cmd_cn30xx cn58xxp1; -}; - -union cvmx_smix_en { - uint64_t u64; - struct cvmx_smix_en_s { - uint64_t reserved_1_63:63; - uint64_t en:1; - } s; - struct cvmx_smix_en_s cn30xx; - struct cvmx_smix_en_s cn31xx; - struct cvmx_smix_en_s cn38xx; - struct cvmx_smix_en_s cn38xxp2; - struct cvmx_smix_en_s cn50xx; - struct cvmx_smix_en_s cn52xx; - struct cvmx_smix_en_s cn52xxp1; - struct cvmx_smix_en_s cn56xx; - struct cvmx_smix_en_s cn56xxp1; - struct cvmx_smix_en_s cn58xx; - struct cvmx_smix_en_s cn58xxp1; -}; - -union cvmx_smix_rd_dat { - uint64_t u64; - struct cvmx_smix_rd_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_rd_dat_s cn30xx; - struct cvmx_smix_rd_dat_s cn31xx; - struct cvmx_smix_rd_dat_s cn38xx; - struct cvmx_smix_rd_dat_s cn38xxp2; - struct cvmx_smix_rd_dat_s cn50xx; - struct cvmx_smix_rd_dat_s cn52xx; - struct cvmx_smix_rd_dat_s cn52xxp1; - struct cvmx_smix_rd_dat_s cn56xx; - struct cvmx_smix_rd_dat_s cn56xxp1; - struct cvmx_smix_rd_dat_s cn58xx; - struct cvmx_smix_rd_dat_s cn58xxp1; -}; - -union cvmx_smix_wr_dat { - uint64_t u64; - struct cvmx_smix_wr_dat_s { - uint64_t reserved_18_63:46; - uint64_t pending:1; - uint64_t val:1; - uint64_t dat:16; - } s; - struct cvmx_smix_wr_dat_s cn30xx; - struct cvmx_smix_wr_dat_s cn31xx; - struct cvmx_smix_wr_dat_s cn38xx; - struct cvmx_smix_wr_dat_s cn38xxp2; - struct cvmx_smix_wr_dat_s cn50xx; - struct cvmx_smix_wr_dat_s cn52xx; - struct cvmx_smix_wr_dat_s cn52xxp1; - struct cvmx_smix_wr_dat_s cn56xx; - struct cvmx_smix_wr_dat_s cn56xxp1; - struct cvmx_smix_wr_dat_s cn58xx; - struct cvmx_smix_wr_dat_s cn58xxp1; -}; - -#endif diff --git a/trunk/arch/mips/include/asm/octeon/octeon.h b/trunk/arch/mips/include/asm/octeon/octeon.h index 4d0a8c61fc3e..cac9b1a206fc 100644 --- a/trunk/arch/mips/include/asm/octeon/octeon.h +++ b/trunk/arch/mips/include/asm/octeon/octeon.h @@ -47,7 +47,6 @@ struct octeon_cop2_state; extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); extern void octeon_crypto_disable(struct octeon_cop2_state *state, unsigned long flags); -extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); extern void octeon_init_cvmcount(void); diff --git a/trunk/arch/mips/include/asm/pgtable.h b/trunk/arch/mips/include/asm/pgtable.h index 1854336e56a2..d6eb6134abec 100644 --- a/trunk/arch/mips/include/asm/pgtable.h +++ b/trunk/arch/mips/include/asm/pgtable.h @@ -389,19 +389,6 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma, #include -/* - * uncached accelerated TLB map for video memory access - */ -#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED -#define __HAVE_PHYS_MEM_ACCESS_PROT - -struct file; -pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, - unsigned long size, pgprot_t vma_prot); -int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn, - unsigned long size, pgprot_t *vma_prot); -#endif - /* * We provide our own get_unmapped area to cope with the virtual aliasing * constraints placed on us by the cache architecture. diff --git a/trunk/arch/mips/include/asm/sgialib.h b/trunk/arch/mips/include/asm/sgialib.h index 63741ca1e422..bfce5c786f1c 100644 --- a/trunk/arch/mips/include/asm/sgialib.h +++ b/trunk/arch/mips/include/asm/sgialib.h @@ -85,7 +85,8 @@ extern void prom_identify_arch(void); extern PCHAR ArcGetEnvironmentVariable(PCHAR name); extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); -/* ARCS command line parsing. */ +/* ARCS command line acquisition and parsing. */ +extern char *prom_getcmdline(void); extern void prom_init_cmdline(void); /* Acquiring info about the current time, etc. */ diff --git a/trunk/arch/mips/include/asm/stackframe.h b/trunk/arch/mips/include/asm/stackframe.h index 3b6da3330e32..db0fa7b5aeaf 100644 --- a/trunk/arch/mips/include/asm/stackframe.h +++ b/trunk/arch/mips/include/asm/stackframe.h @@ -51,6 +51,9 @@ LONG_S v1, PT_ACX(sp) #else mfhi v1 + LONG_S v1, PT_HI(sp) + mflo v1 + LONG_S v1, PT_LO(sp) #endif #ifdef CONFIG_32BIT LONG_S $8, PT_R8(sp) @@ -59,17 +62,10 @@ LONG_S $10, PT_R10(sp) LONG_S $11, PT_R11(sp) LONG_S $12, PT_R12(sp) -#ifndef CONFIG_CPU_HAS_SMARTMIPS - LONG_S v1, PT_HI(sp) - mflo v1 -#endif LONG_S $13, PT_R13(sp) LONG_S $14, PT_R14(sp) LONG_S $15, PT_R15(sp) LONG_S $24, PT_R24(sp) -#ifndef CONFIG_CPU_HAS_SMARTMIPS - LONG_S v1, PT_LO(sp) -#endif .endm .macro SAVE_STATIC @@ -87,19 +83,15 @@ #ifdef CONFIG_SMP #ifdef CONFIG_MIPS_MT_SMTC #define PTEBASE_SHIFT 19 /* TCBIND */ -#define CPU_ID_REG CP0_TCBIND -#define CPU_ID_MFC0 mfc0 -#elif defined(CONFIG_MIPS_PGD_C0_CONTEXT) -#define PTEBASE_SHIFT 48 /* XCONTEXT */ -#define CPU_ID_REG CP0_XCONTEXT -#define CPU_ID_MFC0 MFC0 #else #define PTEBASE_SHIFT 23 /* CONTEXT */ -#define CPU_ID_REG CP0_CONTEXT -#define CPU_ID_MFC0 MFC0 #endif .macro get_saved_sp /* SMP variation */ - CPU_ID_MFC0 k0, CPU_ID_REG +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 k0, CP0_TCBIND +#else + MFC0 k0, CP0_CONTEXT +#endif #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) lui k1, %hi(kernelsp) #else @@ -115,7 +107,11 @@ .endm .macro set_saved_sp stackp temp temp2 - CPU_ID_MFC0 \temp, CPU_ID_REG +#ifdef CONFIG_MIPS_MT_SMTC + mfc0 \temp, CP0_TCBIND +#else + MFC0 \temp, CP0_CONTEXT +#endif LONG_SRL \temp, PTEBASE_SHIFT LONG_S \stackp, kernelsp(\temp) .endm @@ -170,6 +166,7 @@ LONG_S $0, PT_R0(sp) mfc0 v1, CP0_STATUS LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) #ifdef CONFIG_MIPS_MT_SMTC /* * Ideally, these instructions would be shuffled in @@ -181,21 +178,20 @@ LONG_S v1, PT_TCSTATUS(sp) #endif /* CONFIG_MIPS_MT_SMTC */ LONG_S $4, PT_R4(sp) - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_STATUS(sp) mfc0 v1, CP0_CAUSE - LONG_S $6, PT_R6(sp) - LONG_S $7, PT_R7(sp) + LONG_S $5, PT_R5(sp) LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) #ifdef CONFIG_64BIT LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) #endif + LONG_S v1, PT_EPC(sp) LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) - LONG_S v1, PT_EPC(sp) ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON diff --git a/trunk/arch/mips/kernel/Makefile b/trunk/arch/mips/kernel/Makefile index 9326af5186fe..eecd2a9f155c 100644 --- a/trunk/arch/mips/kernel/Makefile +++ b/trunk/arch/mips/kernel/Makefile @@ -2,17 +2,14 @@ # Makefile for the Linux/MIPS kernel. # +CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) + extra-y := head.o init_task.o vmlinux.lds obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ ptrace.o reset.o setup.o signal.o syscall.o \ time.o topology.o traps.o unaligned.o watch.o -ifdef CONFIG_FUNCTION_TRACER -CFLAGS_REMOVE_ftrace.o = -pg -CFLAGS_REMOVE_early_printk.o = -pg -endif - obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o @@ -22,7 +19,6 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o -obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o @@ -30,8 +26,6 @@ obj-$(CONFIG_SYNC_R4K) += sync-r4k.o obj-$(CONFIG_STACKTRACE) += stacktrace.o obj-$(CONFIG_MODULES) += mips_ksyms.o module.o -obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o - obj-$(CONFIG_CPU_LOONGSON2) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o @@ -98,8 +92,4 @@ CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/n obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o -obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/ - EXTRA_CFLAGS += -Werror - -CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c index 80e202eca056..7a51866068a4 100644 --- a/trunk/arch/mips/kernel/cpu-probe.c +++ b/trunk/arch/mips/kernel/cpu-probe.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include @@ -33,7 +32,6 @@ * the CPU very much. */ void (*cpu_wait)(void); -EXPORT_SYMBOL(cpu_wait); static void r3081_wait(void) { diff --git a/trunk/arch/mips/kernel/cpufreq/Kconfig b/trunk/arch/mips/kernel/cpufreq/Kconfig deleted file mode 100644 index 58c601eee6fd..000000000000 --- a/trunk/arch/mips/kernel/cpufreq/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -# -# CPU Frequency scaling -# - -config MIPS_EXTERNAL_TIMER - bool - -config MIPS_CPUFREQ - bool - default y - depends on CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER - -if MIPS_CPUFREQ - -menu "CPU Frequency scaling" - -source "drivers/cpufreq/Kconfig" - -if CPU_FREQ - -comment "CPUFreq processor drivers" - -config LOONGSON2_CPUFREQ - tristate "Loongson2 CPUFreq Driver" - select CPU_FREQ_TABLE - depends on MIPS_CPUFREQ - help - This option adds a CPUFreq driver for loongson processors which - support software configurable cpu frequency. - - Loongson2F and it's successors support this feature. - - For details, take a look at . - - If in doubt, say N. - -endif # CPU_FREQ - -endmenu - -endif # MIPS_CPUFREQ diff --git a/trunk/arch/mips/kernel/cpufreq/Makefile b/trunk/arch/mips/kernel/cpufreq/Makefile deleted file mode 100644 index c3479a432efe..000000000000 --- a/trunk/arch/mips/kernel/cpufreq/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the Linux/MIPS cpufreq. -# - -obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o diff --git a/trunk/arch/mips/kernel/cpufreq/loongson2_clock.c b/trunk/arch/mips/kernel/cpufreq/loongson2_clock.c deleted file mode 100644 index d7ca256e33ef..000000000000 --- a/trunk/arch/mips/kernel/cpufreq/loongson2_clock.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology - * Author: Yanhua, yanh@lemote.com - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include -#include - -#include - -#include - -static LIST_HEAD(clock_list); -static DEFINE_SPINLOCK(clock_lock); -static DEFINE_MUTEX(clock_list_sem); - -/* Minimum CLK support */ -enum { - DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT, - DC_87PT, DC_DISABLE, DC_RESV -}; - -struct cpufreq_frequency_table loongson2_clockmod_table[] = { - {DC_RESV, CPUFREQ_ENTRY_INVALID}, - {DC_ZERO, CPUFREQ_ENTRY_INVALID}, - {DC_25PT, 0}, - {DC_37PT, 0}, - {DC_50PT, 0}, - {DC_62PT, 0}, - {DC_75PT, 0}, - {DC_87PT, 0}, - {DC_DISABLE, 0}, - {DC_RESV, CPUFREQ_TABLE_END}, -}; -EXPORT_SYMBOL_GPL(loongson2_clockmod_table); - -static struct clk cpu_clk = { - .name = "cpu_clk", - .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES, - .rate = 800000000, -}; - -struct clk *clk_get(struct device *dev, const char *id) -{ - return &cpu_clk; -} -EXPORT_SYMBOL(clk_get); - -static void propagate_rate(struct clk *clk) -{ - struct clk *clkp; - - list_for_each_entry(clkp, &clock_list, node) { - if (likely(clkp->parent != clk)) - continue; - if (likely(clkp->ops && clkp->ops->recalc)) - clkp->ops->recalc(clkp); - if (unlikely(clkp->flags & CLK_RATE_PROPAGATES)) - propagate_rate(clkp); - } -} - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk->rate; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - -int clk_set_rate(struct clk *clk, unsigned long rate) -{ - return clk_set_rate_ex(clk, rate, 0); -} -EXPORT_SYMBOL_GPL(clk_set_rate); - -int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) -{ - int ret = 0; - int regval; - int i; - - if (likely(clk->ops && clk->ops->set_rate)) { - unsigned long flags; - - spin_lock_irqsave(&clock_lock, flags); - ret = clk->ops->set_rate(clk, rate, algo_id); - spin_unlock_irqrestore(&clock_lock, flags); - } - - if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) - propagate_rate(clk); - - for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END; - i++) { - if (loongson2_clockmod_table[i].frequency == - CPUFREQ_ENTRY_INVALID) - continue; - if (rate == loongson2_clockmod_table[i].frequency) - break; - } - if (rate != loongson2_clockmod_table[i].frequency) - return -ENOTSUPP; - - clk->rate = rate; - - regval = LOONGSON_CHIPCFG0; - regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1); - LOONGSON_CHIPCFG0 = regval; - - return ret; -} -EXPORT_SYMBOL_GPL(clk_set_rate_ex); - -long clk_round_rate(struct clk *clk, unsigned long rate) -{ - if (likely(clk->ops && clk->ops->round_rate)) { - unsigned long flags, rounded; - - spin_lock_irqsave(&clock_lock, flags); - rounded = clk->ops->round_rate(clk, rate); - spin_unlock_irqrestore(&clock_lock, flags); - - return rounded; - } - - return rate; -} -EXPORT_SYMBOL_GPL(clk_round_rate); - -/* - * This is the simple version of Loongson-2 wait, Maybe we need do this in - * interrupt disabled content - */ - -DEFINE_SPINLOCK(loongson2_wait_lock); -void loongson2_cpu_wait(void) -{ - u32 cpu_freq; - unsigned long flags; - - spin_lock_irqsave(&loongson2_wait_lock, flags); - cpu_freq = LOONGSON_CHIPCFG0; - LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */ - LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */ - spin_unlock_irqrestore(&loongson2_wait_lock, flags); -} -EXPORT_SYMBOL_GPL(loongson2_cpu_wait); diff --git a/trunk/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/trunk/arch/mips/kernel/cpufreq/loongson2_cpufreq.c deleted file mode 100644 index 2f6a0b147ab8..000000000000 --- a/trunk/arch/mips/kernel/cpufreq/loongson2_cpufreq.c +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Cpufreq driver for the loongson-2 processors - * - * The 2E revision of loongson processor not support this feature. - * - * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology - * Author: Yanhua, yanh@lemote.com - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#include -#include -#include -#include /* set_cpus_allowed() */ -#include -#include - -#include - -#include - -static uint nowait; - -static struct clk *cpuclk; - -static void (*saved_cpu_wait) (void); - -static int loongson2_cpu_freq_notifier(struct notifier_block *nb, - unsigned long val, void *data); - -static struct notifier_block loongson2_cpufreq_notifier_block = { - .notifier_call = loongson2_cpu_freq_notifier -}; - -static int loongson2_cpu_freq_notifier(struct notifier_block *nb, - unsigned long val, void *data) -{ - if (val == CPUFREQ_POSTCHANGE) - current_cpu_data.udelay_val = loops_per_jiffy; - - return 0; -} - -static unsigned int loongson2_cpufreq_get(unsigned int cpu) -{ - return clk_get_rate(cpuclk); -} - -/* - * Here we notify other drivers of the proposed change and the final change. - */ -static int loongson2_cpufreq_target(struct cpufreq_policy *policy, - unsigned int target_freq, - unsigned int relation) -{ - unsigned int cpu = policy->cpu; - unsigned int newstate = 0; - cpumask_t cpus_allowed; - struct cpufreq_freqs freqs; - unsigned int freq; - - if (!cpu_online(cpu)) - return -ENODEV; - - cpus_allowed = current->cpus_allowed; - set_cpus_allowed(current, cpumask_of_cpu(cpu)); - - if (cpufreq_frequency_table_target - (policy, &loongson2_clockmod_table[0], target_freq, relation, - &newstate)) - return -EINVAL; - - freq = - ((cpu_clock_freq / 1000) * - loongson2_clockmod_table[newstate].index) / 8; - if (freq < policy->min || freq > policy->max) - return -EINVAL; - - pr_debug("cpufreq: requested frequency %u Hz\n", target_freq * 1000); - - freqs.cpu = cpu; - freqs.old = loongson2_cpufreq_get(cpu); - freqs.new = freq; - freqs.flags = 0; - - if (freqs.new == freqs.old) - return 0; - - /* notifiers */ - cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); - - set_cpus_allowed(current, cpus_allowed); - - /* setting the cpu frequency */ - clk_set_rate(cpuclk, freq); - - /* notifiers */ - cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); - - pr_debug("cpufreq: set frequency %u kHz\n", freq); - - return 0; -} - -static int loongson2_cpufreq_cpu_init(struct cpufreq_policy *policy) -{ - int i; - - if (!cpu_online(policy->cpu)) - return -ENODEV; - - cpuclk = clk_get(NULL, "cpu_clk"); - if (IS_ERR(cpuclk)) { - printk(KERN_ERR "cpufreq: couldn't get CPU clk\n"); - return PTR_ERR(cpuclk); - } - - cpuclk->rate = cpu_clock_freq / 1000; - if (!cpuclk->rate) - return -EINVAL; - - /* clock table init */ - for (i = 2; - (loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END); - i++) - loongson2_clockmod_table[i].frequency = (cpuclk->rate * i) / 8; - - policy->cur = loongson2_cpufreq_get(policy->cpu); - - cpufreq_frequency_table_get_attr(&loongson2_clockmod_table[0], - policy->cpu); - - return cpufreq_frequency_table_cpuinfo(policy, - &loongson2_clockmod_table[0]); -} - -static int loongson2_cpufreq_verify(struct cpufreq_policy *policy) -{ - return cpufreq_frequency_table_verify(policy, - &loongson2_clockmod_table[0]); -} - -static int loongson2_cpufreq_exit(struct cpufreq_policy *policy) -{ - clk_put(cpuclk); - return 0; -} - -static struct freq_attr *loongson2_table_attr[] = { - &cpufreq_freq_attr_scaling_available_freqs, - NULL, -}; - -static struct cpufreq_driver loongson2_cpufreq_driver = { - .owner = THIS_MODULE, - .name = "loongson2", - .init = loongson2_cpufreq_cpu_init, - .verify = loongson2_cpufreq_verify, - .target = loongson2_cpufreq_target, - .get = loongson2_cpufreq_get, - .exit = loongson2_cpufreq_exit, - .attr = loongson2_table_attr, -}; - -static struct platform_device_id platform_device_ids[] = { - { - .name = "loongson2_cpufreq", - }, - {} -}; - -MODULE_DEVICE_TABLE(platform, platform_device_ids); - -static struct platform_driver platform_driver = { - .driver = { - .name = "loongson2_cpufreq", - .owner = THIS_MODULE, - }, - .id_table = platform_device_ids, -}; - -static int __init cpufreq_init(void) -{ - int ret; - - /* Register platform stuff */ - ret = platform_driver_register(&platform_driver); - if (ret) - return ret; - - pr_info("cpufreq: Loongson-2F CPU frequency driver.\n"); - - cpufreq_register_notifier(&loongson2_cpufreq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); - - ret = cpufreq_register_driver(&loongson2_cpufreq_driver); - - if (!ret && !nowait) { - saved_cpu_wait = cpu_wait; - cpu_wait = loongson2_cpu_wait; - } - - return ret; -} - -static void __exit cpufreq_exit(void) -{ - if (!nowait && saved_cpu_wait) - cpu_wait = saved_cpu_wait; - cpufreq_unregister_driver(&loongson2_cpufreq_driver); - cpufreq_unregister_notifier(&loongson2_cpufreq_notifier_block, - CPUFREQ_TRANSITION_NOTIFIER); - - platform_driver_unregister(&platform_driver); -} - -module_init(cpufreq_init); -module_exit(cpufreq_exit); - -module_param(nowait, uint, 0644); -MODULE_PARM_DESC(nowait, "Disable Loongson-2F specific wait"); - -MODULE_AUTHOR("Yanhua "); -MODULE_DESCRIPTION("cpufreq driver for Loongson2F"); -MODULE_LICENSE("GPL"); diff --git a/trunk/arch/mips/kernel/csrc-powertv.c b/trunk/arch/mips/kernel/csrc-powertv.c deleted file mode 100644 index a27c16c8690e..000000000000 --- a/trunk/arch/mips/kernel/csrc-powertv.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (C) 2008 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - */ -/* - * The file comes from kernel/csrc-r4k.c - */ -#include -#include - -#include /* Not included in linux/time.h */ - -#include -#include "powertv-clock.h" - -/* MIPS PLL Register Definitions */ -#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF) -#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF) -#define PLL_GET_P(x) (((x) >> 24) & 0x00000007) - -/* - * returns: Clock frequency in kHz - */ -unsigned int __init mips_get_pll_freq(void) -{ - unsigned int pll_reg, m, n, p; - unsigned int fin = 54000; /* Base frequency in kHz */ - unsigned int fout; - - /* Read PLL register setting */ - pll_reg = asic_read(mips_pll_setup); - m = PLL_GET_M(pll_reg); - n = PLL_GET_N(pll_reg); - p = PLL_GET_P(pll_reg); - pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); - - /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ - fout = ((2 * n * fin) / (m * (0x01 << p))); - - pr_info("MIPS Clock Freq=%d kHz\n", fout); - - return fout; -} - -static cycle_t c0_hpt_read(struct clocksource *cs) -{ - return read_c0_count(); -} - -static struct clocksource clocksource_mips = { - .name = "powertv-counter", - .read = c0_hpt_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -static void __init powertv_c0_hpt_clocksource_init(void) -{ - unsigned int pll_freq = mips_get_pll_freq(); - - pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000, - (pll_freq % 1000) * 100 / 1000); - - mips_hpt_frequency = pll_freq / 2 * 1000; - - clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; - - clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); - - clocksource_register(&clocksource_mips); -} - -/** - * struct tim_c - free running counter - * @hi: High 16 bits of the counter - * @lo: Low 32 bits of the counter - * - * Lays out the structure of the free running counter in memory. This counter - * increments at a rate of 27 MHz/8 on all platforms. - */ -struct tim_c { - unsigned int hi; - unsigned int lo; -}; - -static struct tim_c *tim_c; - -static cycle_t tim_c_read(struct clocksource *cs) -{ - unsigned int hi; - unsigned int next_hi; - unsigned int lo; - - hi = readl(&tim_c->hi); - - for (;;) { - lo = readl(&tim_c->lo); - next_hi = readl(&tim_c->hi); - if (next_hi == hi) - break; - hi = next_hi; - } - -pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo); - return ((u64) hi << 32) | lo; -} - -#define TIM_C_SIZE 48 /* # bits in the timer */ - -static struct clocksource clocksource_tim_c = { - .name = "powertv-tim_c", - .read = tim_c_read, - .mask = CLOCKSOURCE_MASK(TIM_C_SIZE), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/** - * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock - * - * The hard part here is coming up with a constant k and shift s such that - * the 48-bit TIM_C value multiplied by k doesn't overflow and that value, - * when shifted right by s, yields the corresponding number of nanoseconds. - * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to - * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the - * number of nanoseconds. Since the TIM_C value has 48 bits and the math is - * done in 64 bits, avoiding an overflow means that k must be less than - * 64 - 48 = 16 bits. - */ -static void __init powertv_tim_c_clocksource_init(void) -{ - int prescale; - unsigned long dividend; - unsigned long k; - int s; - const int max_k_bits = (64 - 48) - 1; - const unsigned long billion = 1000000000; - const unsigned long counts_per_second = 27000000 / 8; - - prescale = BITS_PER_LONG - ilog2(billion) - 1; - dividend = billion << prescale; - k = dividend / counts_per_second; - s = ilog2(k) - max_k_bits; - - if (s < 0) - s = prescale; - - else { - k >>= s; - s += prescale; - } - - clocksource_tim_c.mult = k; - clocksource_tim_c.shift = s; - clocksource_tim_c.rating = 200; - - clocksource_register(&clocksource_tim_c); - tim_c = (struct tim_c *) asic_reg_addr(tim_ch); -} - -/** - powertv_clocksource_init - initialize all clocksources - */ -void __init powertv_clocksource_init(void) -{ - powertv_c0_hpt_clocksource_init(); - powertv_tim_c_clocksource_init(); -} diff --git a/trunk/arch/mips/kernel/ftrace.c b/trunk/arch/mips/kernel/ftrace.c deleted file mode 100644 index 68b067040d8b..000000000000 --- a/trunk/arch/mips/kernel/ftrace.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Code for replacing ftrace calls with jumps. - * - * Copyright (C) 2007-2008 Steven Rostedt - * Copyright (C) 2009 DSLab, Lanzhou University, China - * Author: Wu Zhangjin - * - * Thanks goes to Steven Rostedt for writing the original x86 version. - */ - -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_DYNAMIC_FTRACE - -#define JAL 0x0c000000 /* jump & link: ip --> ra, jump to target */ -#define ADDR_MASK 0x03ffffff /* op_code|addr : 31...26|25 ....0 */ -#define jump_insn_encode(op_code, addr) \ - ((unsigned int)((op_code) | (((addr) >> 2) & ADDR_MASK))) - -static unsigned int ftrace_nop = 0x00000000; - -static int ftrace_modify_code(unsigned long ip, unsigned int new_code) -{ - int faulted; - - /* *(unsigned int *)ip = new_code; */ - safe_store_code(new_code, ip, faulted); - - if (unlikely(faulted)) - return -EFAULT; - - flush_icache_range(ip, ip + 8); - - return 0; -} - -static int lui_v1; -static int jal_mcount; - -int ftrace_make_nop(struct module *mod, - struct dyn_ftrace *rec, unsigned long addr) -{ - unsigned int new; - int faulted; - unsigned long ip = rec->ip; - - /* We have compiled module with -mlong-calls, but compiled the kernel - * without it, we need to cope with them respectively. */ - if (ip & 0x40000000) { - /* record it for ftrace_make_call */ - if (lui_v1 == 0) { - /* lui_v1 = *(unsigned int *)ip; */ - safe_load_code(lui_v1, ip, faulted); - - if (unlikely(faulted)) - return -EFAULT; - } - - /* lui v1, hi_16bit_of_mcount --> b 1f (0x10000004) - * addiu v1, v1, low_16bit_of_mcount - * move at, ra - * jalr v1 - * nop - * 1f: (ip + 12) - */ - new = 0x10000004; - } else { - /* record/calculate it for ftrace_make_call */ - if (jal_mcount == 0) { - /* We can record it directly like this: - * jal_mcount = *(unsigned int *)ip; - * Herein, jump over the first two nop instructions */ - jal_mcount = jump_insn_encode(JAL, (MCOUNT_ADDR + 8)); - } - - /* move at, ra - * jalr v1 --> nop - */ - new = ftrace_nop; - } - return ftrace_modify_code(ip, new); -} - -static int modified; /* initialized as 0 by default */ - -int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) -{ - unsigned int new; - unsigned long ip = rec->ip; - - /* We just need to remove the "b ftrace_stub" at the fist time! */ - if (modified == 0) { - modified = 1; - ftrace_modify_code(addr, ftrace_nop); - } - /* ip, module: 0xc0000000, kernel: 0x80000000 */ - new = (ip & 0x40000000) ? lui_v1 : jal_mcount; - - return ftrace_modify_code(ip, new); -} - -#define FTRACE_CALL_IP ((unsigned long)(&ftrace_call)) - -int ftrace_update_ftrace_func(ftrace_func_t func) -{ - unsigned int new; - - new = jump_insn_encode(JAL, (unsigned long)func); - - return ftrace_modify_code(FTRACE_CALL_IP, new); -} - -int __init ftrace_dyn_arch_init(void *data) -{ - /* The return code is retured via data */ - *(unsigned long *)data = 0; - - return 0; -} -#endif /* CONFIG_DYNAMIC_FTRACE */ - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER - -#ifdef CONFIG_DYNAMIC_FTRACE - -extern void ftrace_graph_call(void); -#define JMP 0x08000000 /* jump to target directly */ -#define CALL_FTRACE_GRAPH_CALLER \ - jump_insn_encode(JMP, (unsigned long)(&ftrace_graph_caller)) -#define FTRACE_GRAPH_CALL_IP ((unsigned long)(&ftrace_graph_call)) - -int ftrace_enable_ftrace_graph_caller(void) -{ - return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, - CALL_FTRACE_GRAPH_CALLER); -} - -int ftrace_disable_ftrace_graph_caller(void) -{ - return ftrace_modify_code(FTRACE_GRAPH_CALL_IP, ftrace_nop); -} - -#endif /* !CONFIG_DYNAMIC_FTRACE */ - -#ifndef KBUILD_MCOUNT_RA_ADDRESS -#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */ -#define S_R_SP (0xafb0 << 16) /* s{d,w} R, offset(sp) */ -#define OFFSET_MASK 0xffff /* stack offset range: 0 ~ PT_SIZE */ - -unsigned long ftrace_get_parent_addr(unsigned long self_addr, - unsigned long parent, - unsigned long parent_addr, - unsigned long fp) -{ - unsigned long sp, ip, ra; - unsigned int code; - int faulted; - - /* in module or kernel? */ - if (self_addr & 0x40000000) { - /* module: move to the instruction "lui v1, HI_16BIT_OF_MCOUNT" */ - ip = self_addr - 20; - } else { - /* kernel: move to the instruction "move ra, at" */ - ip = self_addr - 12; - } - - /* search the text until finding the non-store instruction or "s{d,w} - * ra, offset(sp)" instruction */ - do { - ip -= 4; - - /* get the code at "ip": code = *(unsigned int *)ip; */ - safe_load_code(code, ip, faulted); - - if (unlikely(faulted)) - return 0; - - /* If we hit the non-store instruction before finding where the - * ra is stored, then this is a leaf function and it does not - * store the ra on the stack. */ - if ((code & S_R_SP) != S_R_SP) - return parent_addr; - - } while (((code & S_RA_SP) != S_RA_SP)); - - sp = fp + (code & OFFSET_MASK); - - /* ra = *(unsigned long *)sp; */ - safe_load_stack(ra, sp, faulted); - if (unlikely(faulted)) - return 0; - - if (ra == parent) - return sp; - return 0; -} - -#endif - -/* - * Hook the return address and push it in the stack of return addrs - * in current thread info. - */ -void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, - unsigned long fp) -{ - unsigned long old; - struct ftrace_graph_ent trace; - unsigned long return_hooker = (unsigned long) - &return_to_handler; - int faulted; - - if (unlikely(atomic_read(¤t->tracing_graph_pause))) - return; - - /* "parent" is the stack address saved the return address of the caller - * of _mcount. - * - * if the gcc < 4.5, a leaf function does not save the return address - * in the stack address, so, we "emulate" one in _mcount's stack space, - * and hijack it directly, but for a non-leaf function, it save the - * return address to the its own stack space, we can not hijack it - * directly, but need to find the real stack address, - * ftrace_get_parent_addr() does it! - * - * if gcc>= 4.5, with the new -mmcount-ra-address option, for a - * non-leaf function, the location of the return address will be saved - * to $12 for us, and for a leaf function, only put a zero into $12. we - * do it in ftrace_graph_caller of mcount.S. - */ - - /* old = *parent; */ - safe_load_stack(old, parent, faulted); - if (unlikely(faulted)) - goto out; -#ifndef KBUILD_MCOUNT_RA_ADDRESS - parent = (unsigned long *)ftrace_get_parent_addr(self_addr, old, - (unsigned long)parent, - fp); - /* If fails when getting the stack address of the non-leaf function's - * ra, stop function graph tracer and return */ - if (parent == 0) - goto out; -#endif - /* *parent = return_hooker; */ - safe_store_stack(return_hooker, parent, faulted); - if (unlikely(faulted)) - goto out; - - if (ftrace_push_return_trace(old, self_addr, &trace.depth, fp) == - -EBUSY) { - *parent = old; - return; - } - - trace.func = self_addr; - - /* Only trace if the calling function expects to */ - if (!ftrace_graph_entry(&trace)) { - current->curr_ret_stack--; - *parent = old; - } - return; -out: - ftrace_graph_stop(); - WARN_ON(1); -} -#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ diff --git a/trunk/arch/mips/kernel/irq.c b/trunk/arch/mips/kernel/irq.c index 981f86c26168..8b0b4181219f 100644 --- a/trunk/arch/mips/kernel/irq.c +++ b/trunk/arch/mips/kernel/irq.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include @@ -151,32 +150,3 @@ void __init init_IRQ(void) kgdb_early_setup = 1; #endif } - -/* - * do_IRQ handles all normal device IRQ's (the special - * SMP cross-CPU interrupts have their own specific - * handlers). - */ -void __irq_entry do_IRQ(unsigned int irq) -{ - irq_enter(); - __DO_IRQ_SMTC_HOOK(irq); - generic_handle_irq(irq); - irq_exit(); -} - -#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF -/* - * To avoid inefficient and in some cases pathological re-checking of - * IRQ affinity, we have this variant that skips the affinity check. - */ - -void __irq_entry do_IRQ_no_affinity(unsigned int irq) -{ - irq_enter(); - __NO_AFFINITY_IRQ_SMTC_HOOK(irq); - generic_handle_irq(irq); - irq_exit(); -} - -#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */ diff --git a/trunk/arch/mips/kernel/mcount.S b/trunk/arch/mips/kernel/mcount.S deleted file mode 100644 index 0a9cfdb271dd..000000000000 --- a/trunk/arch/mips/kernel/mcount.S +++ /dev/null @@ -1,189 +0,0 @@ -/* - * MIPS specific _mcount support - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive for - * more details. - * - * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China - * Author: Wu Zhangjin - */ - -#include -#include -#include - - .text - .set noreorder - .set noat - - .macro MCOUNT_SAVE_REGS - PTR_SUBU sp, PT_SIZE - PTR_S ra, PT_R31(sp) - PTR_S AT, PT_R1(sp) - PTR_S a0, PT_R4(sp) - PTR_S a1, PT_R5(sp) - PTR_S a2, PT_R6(sp) - PTR_S a3, PT_R7(sp) -#ifdef CONFIG_64BIT - PTR_S a4, PT_R8(sp) - PTR_S a5, PT_R9(sp) - PTR_S a6, PT_R10(sp) - PTR_S a7, PT_R11(sp) -#endif - .endm - - .macro MCOUNT_RESTORE_REGS - PTR_L ra, PT_R31(sp) - PTR_L AT, PT_R1(sp) - PTR_L a0, PT_R4(sp) - PTR_L a1, PT_R5(sp) - PTR_L a2, PT_R6(sp) - PTR_L a3, PT_R7(sp) -#ifdef CONFIG_64BIT - PTR_L a4, PT_R8(sp) - PTR_L a5, PT_R9(sp) - PTR_L a6, PT_R10(sp) - PTR_L a7, PT_R11(sp) -#endif -#ifdef CONFIG_64BIT - PTR_ADDIU sp, PT_SIZE -#else - PTR_ADDIU sp, (PT_SIZE + 8) -#endif -.endm - - .macro RETURN_BACK - jr ra - move ra, AT - .endm - -#ifdef CONFIG_DYNAMIC_FTRACE - -NESTED(ftrace_caller, PT_SIZE, ra) - .globl _mcount -_mcount: - b ftrace_stub - nop - lw t1, function_trace_stop - bnez t1, ftrace_stub - nop - - MCOUNT_SAVE_REGS -#ifdef KBUILD_MCOUNT_RA_ADDRESS - PTR_S t0, PT_R12(sp) /* t0 saved the location of the return address(at) by -mmcount-ra-address */ -#endif - - move a0, ra /* arg1: next ip, selfaddr */ - .globl ftrace_call -ftrace_call: - nop /* a placeholder for the call to a real tracing function */ - move a1, AT /* arg2: the caller's next ip, parent */ - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER - .globl ftrace_graph_call -ftrace_graph_call: - nop - nop -#endif - - MCOUNT_RESTORE_REGS - .globl ftrace_stub -ftrace_stub: - RETURN_BACK - END(ftrace_caller) - -#else /* ! CONFIG_DYNAMIC_FTRACE */ - -NESTED(_mcount, PT_SIZE, ra) - lw t1, function_trace_stop - bnez t1, ftrace_stub - nop - PTR_LA t1, ftrace_stub - PTR_L t2, ftrace_trace_function /* Prepare t2 for (1) */ - bne t1, t2, static_trace - nop - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER - PTR_L t3, ftrace_graph_return - bne t1, t3, ftrace_graph_caller - nop - PTR_LA t1, ftrace_graph_entry_stub - PTR_L t3, ftrace_graph_entry - bne t1, t3, ftrace_graph_caller - nop -#endif - b ftrace_stub - nop - -static_trace: - MCOUNT_SAVE_REGS - - move a0, ra /* arg1: next ip, selfaddr */ - jalr t2 /* (1) call *ftrace_trace_function */ - move a1, AT /* arg2: the caller's next ip, parent */ - - MCOUNT_RESTORE_REGS - .globl ftrace_stub -ftrace_stub: - RETURN_BACK - END(_mcount) - -#endif /* ! CONFIG_DYNAMIC_FTRACE */ - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER - -NESTED(ftrace_graph_caller, PT_SIZE, ra) -#ifdef CONFIG_DYNAMIC_FTRACE - PTR_L a1, PT_R31(sp) /* load the original ra from the stack */ -#ifdef KBUILD_MCOUNT_RA_ADDRESS - PTR_L t0, PT_R12(sp) /* load the original t0 from the stack */ -#endif -#else - MCOUNT_SAVE_REGS - move a1, ra /* arg2: next ip, selfaddr */ -#endif - -#ifdef KBUILD_MCOUNT_RA_ADDRESS - bnez t0, 1f /* non-leaf func: t0 saved the location of the return address */ - nop - PTR_LA t0, PT_R1(sp) /* leaf func: get the location of at(old ra) from our own stack */ -1: move a0, t0 /* arg1: the location of the return address */ -#else - PTR_LA a0, PT_R1(sp) /* arg1: &AT -> a0 */ -#endif - jal prepare_ftrace_return -#ifdef CONFIG_FRAME_POINTER - move a2, fp /* arg3: frame pointer */ -#else -#ifdef CONFIG_64BIT - PTR_LA a2, PT_SIZE(sp) -#else - PTR_LA a2, (PT_SIZE+8)(sp) -#endif -#endif - - MCOUNT_RESTORE_REGS - RETURN_BACK - END(ftrace_graph_caller) - - .align 2 - .globl return_to_handler -return_to_handler: - PTR_SUBU sp, PT_SIZE - PTR_S v0, PT_R2(sp) - - jal ftrace_return_to_handler - PTR_S v1, PT_R3(sp) - - /* restore the real parent address: v0 -> ra */ - move ra, v0 - - PTR_L v0, PT_R2(sp) - PTR_L v1, PT_R3(sp) - jr ra - PTR_ADDIU sp, PT_SIZE -#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ - - .set at - .set reorder diff --git a/trunk/arch/mips/kernel/mips_ksyms.c b/trunk/arch/mips/kernel/mips_ksyms.c index 1d04807874db..225755d0c1f6 100644 --- a/trunk/arch/mips/kernel/mips_ksyms.c +++ b/trunk/arch/mips/kernel/mips_ksyms.c @@ -13,7 +13,6 @@ #include #include #include -#include extern void *__bzero(void *__s, size_t __count); extern long __strncpy_from_user_nocheck_asm(char *__to, @@ -52,7 +51,3 @@ EXPORT_SYMBOL(csum_partial_copy_nocheck); EXPORT_SYMBOL(__csum_partial_copy_user); EXPORT_SYMBOL(invalid_pte_table); -#ifdef CONFIG_FUNCTION_TRACER -/* _mcount is defined in arch/mips/kernel/mcount.S */ -EXPORT_SYMBOL(_mcount); -#endif diff --git a/trunk/arch/mips/kernel/setup.c b/trunk/arch/mips/kernel/setup.c index f9513f9e61d3..2b290d70083e 100644 --- a/trunk/arch/mips/kernel/setup.c +++ b/trunk/arch/mips/kernel/setup.c @@ -58,12 +58,8 @@ EXPORT_SYMBOL(mips_machtype); struct boot_mem_map boot_mem_map; -static char __initdata command_line[COMMAND_LINE_SIZE]; -char __initdata arcs_cmdline[COMMAND_LINE_SIZE]; - -#ifdef CONFIG_CMDLINE_BOOL -static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE; -#endif +static char command_line[CL_SIZE]; + char arcs_cmdline[CL_SIZE]=CONFIG_CMDLINE; /* * mips_io_port_base is the begin of the address space to which x86 style @@ -170,8 +166,26 @@ static unsigned long __init init_initrd(void) * already set up initrd_start and initrd_end. In these cases * perfom sanity checks and use them if all looks good. */ - if (!initrd_start || initrd_end <= initrd_start) + if (!initrd_start || initrd_end <= initrd_start) { +#ifdef CONFIG_PROBE_INITRD_HEADER + u32 *initrd_header; + + /* + * See if initrd has been added to the kernel image by + * arch/mips/boot/addinitrd.c. In that case a header is + * prepended to initrd and is made up by 8 bytes. The first + * word is a magic number and the second one is the size of + * initrd. Initrd start must be page aligned in any cases. + */ + initrd_header = __va(PAGE_ALIGN(__pa_symbol(&_end) + 8)) - 8; + if (initrd_header[0] != 0x494E5244) + goto disable; + initrd_start = (unsigned long)(initrd_header + 2); + initrd_end = initrd_start + initrd_header[1]; +#else goto disable; +#endif + } if (initrd_start & ~PAGE_MASK) { pr_err("initrd start must be page aligned\n"); @@ -462,20 +476,8 @@ static void __init arch_mem_init(char **cmdline_p) pr_info("Determined physical RAM map:\n"); print_memory_map(); -#ifdef CONFIG_CMDLINE_BOOL -#ifdef CONFIG_CMDLINE_OVERRIDE - strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE); -#else - if (builtin_cmdline[0]) { - strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); - strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE); - } - strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE); -#endif -#else - strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE); -#endif - strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); + strlcpy(command_line, arcs_cmdline, sizeof(command_line)); + strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); *cmdline_p = command_line; diff --git a/trunk/arch/mips/kernel/signal.c b/trunk/arch/mips/kernel/signal.c index d0c68b5d717b..6254041b942f 100644 --- a/trunk/arch/mips/kernel/signal.c +++ b/trunk/arch/mips/kernel/signal.c @@ -35,15 +35,6 @@ #include "signal-common.h" -static int (*save_fp_context)(struct sigcontext __user *sc); -static int (*restore_fp_context)(struct sigcontext __user *sc); - -extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); -extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); - -extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); -extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); - /* * Horribly complicated - with the bloody RM9000 workarounds enabled * the signal trampolines is moving to the end of the structure so we can @@ -718,40 +709,3 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused, key_replace_session_keyring(); } } - -#ifdef CONFIG_SMP -static int smp_save_fp_context(struct sigcontext __user *sc) -{ - return raw_cpu_has_fpu - ? _save_fp_context(sc) - : fpu_emulator_save_context(sc); -} - -static int smp_restore_fp_context(struct sigcontext __user *sc) -{ - return raw_cpu_has_fpu - ? _restore_fp_context(sc) - : fpu_emulator_restore_context(sc); -} -#endif - -static int signal_setup(void) -{ -#ifdef CONFIG_SMP - /* For now just do the cpu_has_fpu check when the functions are invoked */ - save_fp_context = smp_save_fp_context; - restore_fp_context = smp_restore_fp_context; -#else - if (cpu_has_fpu) { - save_fp_context = _save_fp_context; - restore_fp_context = _restore_fp_context; - } else { - save_fp_context = fpu_emulator_save_context; - restore_fp_context = fpu_emulator_restore_context; - } -#endif - - return 0; -} - -arch_initcall(signal_setup); diff --git a/trunk/arch/mips/kernel/signal32.c b/trunk/arch/mips/kernel/signal32.c index 03abaf048f09..2e74075ac0ca 100644 --- a/trunk/arch/mips/kernel/signal32.c +++ b/trunk/arch/mips/kernel/signal32.c @@ -35,15 +35,6 @@ #include "signal-common.h" -static int (*save_fp_context32)(struct sigcontext32 __user *sc); -static int (*restore_fp_context32)(struct sigcontext32 __user *sc); - -extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); -extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); - -extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); -extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); - /* * Including would give use the 64-bit syscall numbers ... */ @@ -837,18 +828,3 @@ SYSCALL_DEFINE5(32_waitid, int, which, compat_pid_t, pid, info.si_code |= __SI_CHLD; return copy_siginfo_to_user32(uinfo, &info); } - -static int signal32_init(void) -{ - if (cpu_has_fpu) { - save_fp_context32 = _save_fp_context32; - restore_fp_context32 = _restore_fp_context32; - } else { - save_fp_context32 = fpu_emulator_save_context32; - restore_fp_context32 = fpu_emulator_restore_context32; - } - - return 0; -} - -arch_initcall(signal32_init); diff --git a/trunk/arch/mips/kernel/smp.c b/trunk/arch/mips/kernel/smp.c index 6cdca1956b77..e72e6844d134 100644 --- a/trunk/arch/mips/kernel/smp.c +++ b/trunk/arch/mips/kernel/smp.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include @@ -131,7 +130,7 @@ asmlinkage __cpuinit void start_secondary(void) /* * Call into both interrupt handlers, as we share the IPI for them */ -void __irq_entry smp_call_function_interrupt(void) +void smp_call_function_interrupt(void) { irq_enter(); generic_smp_call_function_single_interrupt(); diff --git a/trunk/arch/mips/kernel/smtc.c b/trunk/arch/mips/kernel/smtc.c index 23499b5bd9c3..a38e3ee95515 100644 --- a/trunk/arch/mips/kernel/smtc.c +++ b/trunk/arch/mips/kernel/smtc.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -940,29 +939,23 @@ static void ipi_call_interrupt(void) DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device); -static void __irq_entry smtc_clock_tick_interrupt(void) +void ipi_decode(struct smtc_ipi *pipi) { unsigned int cpu = smp_processor_id(); struct clock_event_device *cd; - int irq = MIPS_CPU_IRQ_BASE + 1; - - irq_enter(); - kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); - cd = &per_cpu(mips_clockevent_device, cpu); - cd->event_handler(cd); - irq_exit(); -} - -void ipi_decode(struct smtc_ipi *pipi) -{ void *arg_copy = pipi->arg; int type_copy = pipi->type; + int irq = MIPS_CPU_IRQ_BASE + 1; smtc_ipi_nq(&freeIPIq, pipi); switch (type_copy) { case SMTC_CLOCK_TICK: - smtc_clock_tick_interrupt(); + irq_enter(); + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); + cd = &per_cpu(mips_clockevent_device, cpu); + cd->event_handler(cd); + irq_exit(); break; case LINUX_SMP_IPI: diff --git a/trunk/arch/mips/kernel/traps.c b/trunk/arch/mips/kernel/traps.c index 308e43460864..0a18b4c62afb 100644 --- a/trunk/arch/mips/kernel/traps.c +++ b/trunk/arch/mips/kernel/traps.c @@ -25,12 +25,10 @@ #include #include #include -#include #include #include #include -#include #include #include #include @@ -81,6 +79,10 @@ extern asmlinkage void handle_reserved(void); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, int has_fpu); +#ifdef CONFIG_CPU_CAVIUM_OCTEON +extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task); +#endif + void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); void (*board_nmi_handler_setup)(void); @@ -855,44 +857,6 @@ static void mt_ase_fp_affinity(void) #endif /* CONFIG_MIPS_MT_FPAFF */ } -/* - * No lock; only written during early bootup by CPU 0. - */ -static RAW_NOTIFIER_HEAD(cu2_chain); - -int __ref register_cu2_notifier(struct notifier_block *nb) -{ - return raw_notifier_chain_register(&cu2_chain, nb); -} - -int cu2_notifier_call_chain(unsigned long val, void *v) -{ - return raw_notifier_call_chain(&cu2_chain, val, v); -} - -static int default_cu2_call(struct notifier_block *nfb, unsigned long action, - void *data) -{ - struct pt_regs *regs = data; - - switch (action) { - default: - die_if_kernel("Unhandled kernel unaligned access or invalid " - "instruction", regs); - /* Fall through */ - - case CU2_EXCEPTION: - force_sig(SIGILL, current); - } - - return NOTIFY_OK; -} - -static struct notifier_block default_cu2_notifier = { - .notifier_call = default_cu2_call, - .priority = 0x80000000, /* Run last */ -}; - asmlinkage void do_cpu(struct pt_regs *regs) { unsigned int __user *epc; @@ -956,9 +920,17 @@ asmlinkage void do_cpu(struct pt_regs *regs) return; case 2: - raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); - break; - +#ifdef CONFIG_CPU_CAVIUM_OCTEON + prefetch(¤t->thread.cp2); + local_irq_save(flags); + KSTK_STATUS(current) |= ST0_CU2; + status = read_c0_status(); + write_c0_status(status | ST0_CU2); + octeon_cop2_restore(&(current->thread.cp2)); + write_c0_status(status & ~ST0_CU2); + local_irq_restore(flags); + return; +#endif case 3: break; } @@ -1395,6 +1367,77 @@ void *set_vi_handler(int n, vi_handler_t addr) return set_vi_srs_handler(n, addr, 0); } +/* + * This is used by native signal handling + */ +asmlinkage int (*save_fp_context)(struct sigcontext __user *sc); +asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc); + +extern asmlinkage int _save_fp_context(struct sigcontext __user *sc); +extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); + +extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); +extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); + +#ifdef CONFIG_SMP +static int smp_save_fp_context(struct sigcontext __user *sc) +{ + return raw_cpu_has_fpu + ? _save_fp_context(sc) + : fpu_emulator_save_context(sc); +} + +static int smp_restore_fp_context(struct sigcontext __user *sc) +{ + return raw_cpu_has_fpu + ? _restore_fp_context(sc) + : fpu_emulator_restore_context(sc); +} +#endif + +static inline void signal_init(void) +{ +#ifdef CONFIG_SMP + /* For now just do the cpu_has_fpu check when the functions are invoked */ + save_fp_context = smp_save_fp_context; + restore_fp_context = smp_restore_fp_context; +#else + if (cpu_has_fpu) { + save_fp_context = _save_fp_context; + restore_fp_context = _restore_fp_context; + } else { + save_fp_context = fpu_emulator_save_context; + restore_fp_context = fpu_emulator_restore_context; + } +#endif +} + +#ifdef CONFIG_MIPS32_COMPAT + +/* + * This is used by 32-bit signal stuff on the 64-bit kernel + */ +asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc); +asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc); + +extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc); +extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc); + +extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc); +extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc); + +static inline void signal32_init(void) +{ + if (cpu_has_fpu) { + save_fp_context32 = _save_fp_context32; + restore_fp_context32 = _restore_fp_context32; + } else { + save_fp_context32 = fpu_emulator_save_context32; + restore_fp_context32 = fpu_emulator_restore_context32; + } +} +#endif + extern void cpu_cache_init(void); extern void tlb_init(void); extern void flush_tlb_handlers(void); @@ -1708,10 +1751,13 @@ void __init trap_init(void) else memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); + signal_init(); +#ifdef CONFIG_MIPS32_COMPAT + signal32_init(); +#endif + local_flush_icache_range(ebase, ebase + 0x400); flush_tlb_handlers(); sort_extable(__start___dbe_table, __stop___dbe_table); - - register_cu2_notifier(&default_cu2_notifier); } diff --git a/trunk/arch/mips/kernel/unaligned.c b/trunk/arch/mips/kernel/unaligned.c index 69b039ca8d83..67bd626942ab 100644 --- a/trunk/arch/mips/kernel/unaligned.c +++ b/trunk/arch/mips/kernel/unaligned.c @@ -81,7 +81,6 @@ #include #include #include -#include #include #include #include @@ -452,27 +451,17 @@ static void emulate_load_store_insn(struct pt_regs *regs, */ goto sigbus; - /* - * COP2 is available to implementor for application specific use. - * It's up to applications to register a notifier chain and do - * whatever they have to do, including possible sending of signals. - */ case lwc2_op: - cu2_notifier_call_chain(CU2_LWC2_OP, regs); - break; - case ldc2_op: - cu2_notifier_call_chain(CU2_LDC2_OP, regs); - break; - case swc2_op: - cu2_notifier_call_chain(CU2_SWC2_OP, regs); - break; - case sdc2_op: - cu2_notifier_call_chain(CU2_SDC2_OP, regs); - break; - + /* + * These are the coprocessor 2 load/stores. The current + * implementations don't use cp2 and cp2 should always be + * disabled in c0_status. So send SIGILL. + * (No longer true: The Sony Praystation uses cp2 for + * 3D matrix operations. Dunno if that thingy has a MMU ...) + */ default: /* * Pheeee... We encountered an yet unknown instruction or diff --git a/trunk/arch/mips/kernel/vmlinux.lds.S b/trunk/arch/mips/kernel/vmlinux.lds.S index f25df73db923..162b29954baa 100644 --- a/trunk/arch/mips/kernel/vmlinux.lds.S +++ b/trunk/arch/mips/kernel/vmlinux.lds.S @@ -46,7 +46,6 @@ SECTIONS SCHED_TEXT LOCK_TEXT KPROBES_TEXT - IRQENTRY_TEXT *(.text.*) *(.fixup) *(.gnu.warning) diff --git a/trunk/arch/mips/lasat/picvue_proc.c b/trunk/arch/mips/lasat/picvue_proc.c index 8e388da1926f..0bb6037afba3 100644 --- a/trunk/arch/mips/lasat/picvue_proc.c +++ b/trunk/arch/mips/lasat/picvue_proc.c @@ -4,14 +4,12 @@ * Brian Murphy * */ -#include #include #include #include #include #include -#include #include #include @@ -40,9 +38,12 @@ static void pvc_display(unsigned long data) static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0); -static int pvc_line_proc_show(struct seq_file *m, void *v) +static int pvc_proc_read_line(char *page, char **start, + off_t off, int count, + int *eof, void *data) { - int lineno = *(int *)m->private; + char *origpage = page; + int lineno = *(int *)data; if (lineno < 0 || lineno > PVC_NLINES) { printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno); @@ -50,66 +51,45 @@ static int pvc_line_proc_show(struct seq_file *m, void *v) } mutex_lock(&pvc_mutex); - seq_printf(m, "%s\n", pvc_lines[lineno]); + page += sprintf(page, "%s\n", pvc_lines[lineno]); mutex_unlock(&pvc_mutex); - return 0; -} - -static int pvc_line_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, pvc_line_proc_show, PDE(inode)->data); + return page - origpage; } -static ssize_t pvc_line_proc_write(struct file *file, const char __user *buf, - size_t count, loff_t *pos) +static int pvc_proc_write_line(struct file *file, const char *buffer, + unsigned long count, void *data) { - int lineno = *(int *)PDE(file->f_path.dentry->d_inode)->data; - char kbuf[PVC_LINELEN]; - size_t len; + int origcount = count; + int lineno = *(int *)data; - BUG_ON(lineno < 0 || lineno > PVC_NLINES); + if (lineno < 0 || lineno > PVC_NLINES) { + printk(KERN_WARNING "proc_write_line: invalid lineno %d\n", + lineno); + return origcount; + } - len = min(count, sizeof(kbuf) - 1); - if (copy_from_user(kbuf, buf, len)) - return -EFAULT; - kbuf[len] = '\0'; + if (count > PVC_LINELEN) + count = PVC_LINELEN; - if (len > 0 && kbuf[len - 1] == '\n') - len--; + if (buffer[count-1] == '\n') + count--; mutex_lock(&pvc_mutex); - strncpy(pvc_lines[lineno], kbuf, len); - pvc_lines[lineno][len] = '\0'; + strncpy(pvc_lines[lineno], buffer, count); + pvc_lines[lineno][count] = '\0'; mutex_unlock(&pvc_mutex); tasklet_schedule(&pvc_display_tasklet); - return count; + return origcount; } -static const struct file_operations pvc_line_proc_fops = { - .owner = THIS_MODULE, - .open = pvc_line_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .write = pvc_line_proc_write, -}; - -static ssize_t pvc_scroll_proc_write(struct file *file, const char __user *buf, - size_t count, loff_t *pos) +static int pvc_proc_write_scroll(struct file *file, const char *buffer, + unsigned long count, void *data) { - char kbuf[42]; - size_t len; - int cmd; - - len = min(count, sizeof(kbuf) - 1); - if (copy_from_user(kbuf, buf, len)) - return -EFAULT; - kbuf[len] = '\0'; - - cmd = simple_strtol(kbuf, NULL, 10); + int origcount = count; + int cmd = simple_strtol(buffer, NULL, 10); mutex_lock(&pvc_mutex); if (scroll_interval != 0) @@ -130,31 +110,22 @@ static ssize_t pvc_scroll_proc_write(struct file *file, const char __user *buf, } mutex_unlock(&pvc_mutex); - return count; + return origcount; } -static int pvc_scroll_proc_show(struct seq_file *m, void *v) +static int pvc_proc_read_scroll(char *page, char **start, + off_t off, int count, + int *eof, void *data) { + char *origpage = page; + mutex_lock(&pvc_mutex); - seq_printf(m, "%d\n", scroll_dir * scroll_interval); + page += sprintf(page, "%d\n", scroll_dir * scroll_interval); mutex_unlock(&pvc_mutex); - return 0; + return page - origpage; } -static int pvc_scroll_proc_open(struct inode *inode, struct file *file) -{ - return single_open(file, pvc_scroll_proc_show, NULL); -} - -static const struct file_operations pvc_scroll_proc_fops = { - .owner = THIS_MODULE, - .open = pvc_scroll_proc_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, - .write = pvc_scroll_proc_write, -}; void pvc_proc_timerfunc(unsigned long data) { @@ -192,16 +163,22 @@ static int __init pvc_proc_init(void) pvc_linedata[i] = i; } for (i = 0; i < PVC_NLINES; i++) { - proc_entry = proc_create_data(pvc_linename[i], 0644, pvc_display_dir, - &pvc_line_proc_fops, &pvc_linedata[i]); + proc_entry = create_proc_entry(pvc_linename[i], 0644, + pvc_display_dir); if (proc_entry == NULL) goto error; + + proc_entry->read_proc = pvc_proc_read_line; + proc_entry->write_proc = pvc_proc_write_line; + proc_entry->data = &pvc_linedata[i]; } - proc_entry = proc_create("scroll", 0644, pvc_display_dir, - &pvc_scroll_proc_fops); + proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir); if (proc_entry == NULL) goto error; + proc_entry->write_proc = pvc_proc_write_scroll; + proc_entry->read_proc = pvc_proc_read_scroll; + init_timer(&timer); timer.function = pvc_proc_timerfunc; diff --git a/trunk/arch/mips/lasat/prom.c b/trunk/arch/mips/lasat/prom.c index 20fde19a5fbf..6acc6cb85f0a 100644 --- a/trunk/arch/mips/lasat/prom.c +++ b/trunk/arch/mips/lasat/prom.c @@ -100,8 +100,8 @@ void __init prom_init(void) /* Get the command line */ if (argc > 0) { - strncpy(arcs_cmdline, argv[0], COMMAND_LINE_SIZE-1); - arcs_cmdline[COMMAND_LINE_SIZE-1] = '\0'; + strncpy(arcs_cmdline, argv[0], CL_SIZE-1); + arcs_cmdline[CL_SIZE-1] = '\0'; } /* Set the I/O base address */ diff --git a/trunk/arch/mips/lasat/sysctl.c b/trunk/arch/mips/lasat/sysctl.c index d87ffd04cb0a..14b9a28a4aec 100644 --- a/trunk/arch/mips/lasat/sysctl.c +++ b/trunk/arch/mips/lasat/sysctl.c @@ -204,7 +204,7 @@ static ctl_table lasat_table[] = { .maxlen = sizeof(int), .mode = 0644, .proc_handler = proc_lasat_prid, - }, +. }, #ifdef CONFIG_INET { .procname = "ipaddr", diff --git a/trunk/arch/mips/loongson/Kconfig b/trunk/arch/mips/loongson/Kconfig index 3df1967dea08..d45092505fa1 100644 --- a/trunk/arch/mips/loongson/Kconfig +++ b/trunk/arch/mips/loongson/Kconfig @@ -1,85 +1,31 @@ choice - prompt "Machine Type" - depends on MACH_LOONGSON + prompt "Machine Type" + depends on MACH_LOONGSON config LEMOTE_FULOONG2E - bool "Lemote Fuloong(2e) mini-PC" - select ARCH_SPARSEMEM_ENABLE - select CEVT_R4K - select CSRC_R4K - select SYS_HAS_CPU_LOONGSON2E - select DMA_NONCOHERENT - select BOOT_ELF32 - select BOARD_SCACHE - select HW_HAS_PCI - select I8259 - select ISA - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_HAS_EARLY_PRINTK - select GENERIC_HARDIRQS_NO__DO_IRQ - select GENERIC_ISA_DMA_SUPPORT_BROKEN - select CPU_HAS_WB - help - Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and - an FPGA northbridge - - Lemote Fuloong(2e) mini PC have a VIA686B south bridge. - -config LEMOTE_MACH2F - bool "Lemote Loongson 2F family machines" - select ARCH_SPARSEMEM_ENABLE - select BOARD_SCACHE - select BOOT_ELF32 - select CEVT_R4K if ! MIPS_EXTERNAL_TIMER - select CPU_HAS_WB - select CS5536 - select CSRC_R4K if ! MIPS_EXTERNAL_TIMER - select DMA_NONCOHERENT - select GENERIC_HARDIRQS_NO__DO_IRQ - select GENERIC_ISA_DMA_SUPPORT_BROKEN - select HW_HAS_PCI - select I8259 - select IRQ_CPU - select ISA - select SYS_HAS_CPU_LOONGSON2F - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_HIGHMEM - select SYS_SUPPORTS_LITTLE_ENDIAN - help - Lemote Loongson 2F family machines utilize the 2F revision of - Loongson processor and the AMD CS5536 south bridge. - - These family machines include fuloong2f mini PC, yeeloong2f notebook, - LingLoong allinone PC and so forth. + bool "Lemote Fuloong(2e) mini-PC" + select ARCH_SPARSEMEM_ENABLE + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON2E + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select CPU_HAS_WB + help + Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and + an FPGA northbridge + + Lemote Fuloong(2e) mini PC have a VIA686B south bridge. endchoice - -config CS5536 - bool - -config CS5536_MFGPT - bool "CS5536 MFGPT Timer" - depends on CS5536 - select MIPS_EXTERNAL_TIMER - help - This option enables the mfgpt0 timer of AMD CS5536. - - If you want to enable the Loongson2 CPUFreq Driver, Please enable - this option at first, otherwise, You will get wrong system time. - - If unsure, say Yes. - -config LOONGSON_SUSPEND - bool - default y - depends on CPU_SUPPORTS_CPUFREQ && SUSPEND - -config LOONGSON_UART_BASE - bool - default y - depends on EARLY_PRINTK || SERIAL_8250 diff --git a/trunk/arch/mips/loongson/Makefile b/trunk/arch/mips/loongson/Makefile index 2b76cb0fb07d..39048c455d7d 100644 --- a/trunk/arch/mips/loongson/Makefile +++ b/trunk/arch/mips/loongson/Makefile @@ -9,9 +9,3 @@ obj-$(CONFIG_MACH_LOONGSON) += common/ # obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ - -# -# Lemote loongson2f family machines -# - -obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/ diff --git a/trunk/arch/mips/loongson/common/Makefile b/trunk/arch/mips/loongson/common/Makefile index 7668c4de1151..656b3cc0a2a6 100644 --- a/trunk/arch/mips/loongson/common/Makefile +++ b/trunk/arch/mips/loongson/common/Makefile @@ -3,23 +3,9 @@ # obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ - pci.o bonito-irq.o mem.o machtype.o platform.o + pci.o bonito-irq.o mem.o machtype.o # -# Serial port support +# Early printk support # obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -obj-$(CONFIG_SERIAL_8250) += serial.o -obj-$(CONFIG_LOONGSON_UART_BASE) += uart_base.o - -# -# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure -# space -# -obj-$(CONFIG_CS5536) += cs5536/ - -# -# Suspend Support -# - -obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o diff --git a/trunk/arch/mips/loongson/common/bonito-irq.c b/trunk/arch/mips/loongson/common/bonito-irq.c index 2dc2a4cc632a..3e31e7ad713e 100644 --- a/trunk/arch/mips/loongson/common/bonito-irq.c +++ b/trunk/arch/mips/loongson/common/bonito-irq.c @@ -12,19 +12,18 @@ * option) any later version. */ #include -#include #include static inline void bonito_irq_enable(unsigned int irq) { - LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE)); + BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); mmiowb(); } static inline void bonito_irq_disable(unsigned int irq) { - LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE)); + BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); mmiowb(); } @@ -36,7 +35,7 @@ static struct irq_chip bonito_irq_type = { .unmask = bonito_irq_enable, }; -static struct irqaction __maybe_unused dma_timeout_irqaction = { +static struct irqaction dma_timeout_irqaction = { .handler = no_action, .name = "dma_timeout", }; @@ -45,10 +44,8 @@ void bonito_irq_init(void) { u32 i; - for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) + for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); -#ifdef CONFIG_CPU_LOONGSON2E - setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); -#endif + setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); } diff --git a/trunk/arch/mips/loongson/common/cmdline.c b/trunk/arch/mips/loongson/common/cmdline.c index 7ad47f227477..75f1b243ee4e 100644 --- a/trunk/arch/mips/loongson/common/cmdline.c +++ b/trunk/arch/mips/loongson/common/cmdline.c @@ -9,7 +9,7 @@ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology * Author: Fuxin Zhang, zhangfx@lemote.com * - * Copyright (C) 2009 Lemote Inc. + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology * Author: Wu Zhangjin, wuzj@lemote.com * * This program is free software; you can redistribute it and/or modify it @@ -49,6 +49,4 @@ void __init prom_init_cmdline(void) strcat(arcs_cmdline, " console=ttyS0,115200"); if ((strstr(arcs_cmdline, "root=")) == NULL) strcat(arcs_cmdline, " root=/dev/hda1"); - - prom_init_machtype(); } diff --git a/trunk/arch/mips/loongson/common/cs5536/Makefile b/trunk/arch/mips/loongson/common/cs5536/Makefile deleted file mode 100644 index 510d4cdc2378..000000000000 --- a/trunk/arch/mips/loongson/common/cs5536/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Makefile for CS5536 support. -# - -obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \ - cs5536_isa.o cs5536_ehci.o - -# -# Enable cs5536 mfgpt Timer -# -obj-$(CONFIG_CS5536_MFGPT) += cs5536_mfgpt.o - -EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/loongson/common/cs5536/cs5536_acc.c b/trunk/arch/mips/loongson/common/cs5536/cs5536_acc.c deleted file mode 100644 index b49485f187e0..000000000000 --- a/trunk/arch/mips/loongson/common/cs5536/cs5536_acc.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * the ACC Virtual Support Module of AMD CS5536 - * - * Copyright (C) 2007 Lemote, Inc. - * Author : jlliu, liujl@lemote.com - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -void pci_acc_write_reg(int reg, u32 value) -{ - u32 hi = 0, lo = value; - - switch (reg) { - case PCI_COMMAND: - _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); - if (value & PCI_COMMAND_MASTER) - lo |= (0x03 << 8); - else - lo &= ~(0x03 << 8); - _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); - break; - case PCI_STATUS: - if (value & PCI_STATUS_PARITY) { - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) { - lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; - _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); - } - } - break; - case PCI_BAR0_REG: - if (value == PCI_BAR_RANGE_MASK) { - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - lo |= SOFT_BAR_ACC_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else if (value & 0x01) { - value &= 0xfffffffc; - hi = 0xA0000000 | ((value & 0x000ff000) >> 12); - lo = 0x000fff80 | ((value & 0x00000fff) << 20); - _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo); - } - break; - case PCI_ACC_INT_REG: - _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); - /* disable all the usb interrupt in PIC */ - lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT); - if (value) /* enable all the acc interrupt in PIC */ - lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT); - _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); - break; - default: - break; - } -} - -u32 pci_acc_read_reg(int reg) -{ - u32 hi, lo; - u32 conf_data = 0; - - switch (reg) { - case PCI_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); - if (((lo & 0xfff00000) || (hi & 0x000000ff)) - && ((hi & 0xf0000000) == 0xa0000000)) - conf_data |= PCI_COMMAND_IO; - _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); - if ((lo & 0x300) == 0x300) - conf_data |= PCI_COMMAND_MASTER; - break; - case PCI_STATUS: - conf_data |= PCI_STATUS_66MHZ; - conf_data |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) - conf_data |= PCI_STATUS_PARITY; - conf_data |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo); - conf_data = lo & 0x000000ff; - conf_data |= (CS5536_ACC_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: - conf_data = - CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, - PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_ACC_FLAG) { - conf_data = CS5536_ACC_RANGE | - PCI_BASE_ADDRESS_SPACE_IO; - lo &= ~SOFT_BAR_ACC_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); - conf_data = (hi & 0x000000ff) << 12; - conf_data |= (lo & 0xfff00000) >> 20; - conf_data |= 0x01; - conf_data &= ~0x02; - } - break; - case PCI_CARDBUS_CIS: - conf_data = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: - conf_data = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: - conf_data = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: - conf_data = - CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); - break; - default: - break; - } - - return conf_data; -} diff --git a/trunk/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/trunk/arch/mips/loongson/common/cs5536/cs5536_ehci.c deleted file mode 100644 index 74f9c59d36af..000000000000 --- a/trunk/arch/mips/loongson/common/cs5536/cs5536_ehci.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * the EHCI Virtual Support Module of AMD CS5536 - * - * Copyright (C) 2007 Lemote, Inc. - * Author : jlliu, liujl@lemote.com - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -void pci_ehci_write_reg(int reg, u32 value) -{ - u32 hi = 0, lo = value; - - switch (reg) { - case PCI_COMMAND: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - if (value & PCI_COMMAND_MASTER) - hi |= PCI_COMMAND_MASTER; - else - hi &= ~PCI_COMMAND_MASTER; - - if (value & PCI_COMMAND_MEMORY) - hi |= PCI_COMMAND_MEMORY; - else - hi &= ~PCI_COMMAND_MEMORY; - _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); - break; - case PCI_STATUS: - if (value & PCI_STATUS_PARITY) { - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) { - lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; - _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); - } - } - break; - case PCI_BAR0_REG: - if (value == PCI_BAR_RANGE_MASK) { - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - lo |= SOFT_BAR_EHCI_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else if ((value & 0x01) == 0x00) { - _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); - - value &= 0xfffffff0; - hi = 0x40000000 | ((value & 0xff000000) >> 24); - lo = 0x000fffff | ((value & 0x00fff000) << 8); - _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo); - } - break; - case PCI_EHCI_LEGSMIEN_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - hi &= 0x003f0000; - hi |= (value & 0x3f) << 16; - _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); - break; - case PCI_EHCI_FLADJ_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - hi &= ~0x00003f00; - hi |= value & 0x00003f00; - _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); - break; - default: - break; - } -} - -u32 pci_ehci_read_reg(int reg) -{ - u32 conf_data = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - if (hi & PCI_COMMAND_MASTER) - conf_data |= PCI_COMMAND_MASTER; - if (hi & PCI_COMMAND_MEMORY) - conf_data |= PCI_COMMAND_MEMORY; - break; - case PCI_STATUS: - conf_data |= PCI_STATUS_66MHZ; - conf_data |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) - conf_data |= PCI_STATUS_PARITY; - conf_data |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); - conf_data = lo & 0x000000ff; - conf_data |= (CS5536_EHCI_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: - conf_data = - CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, - PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_EHCI_FLAG) { - conf_data = CS5536_EHCI_RANGE | - PCI_BASE_ADDRESS_SPACE_MEMORY; - lo &= ~SOFT_BAR_EHCI_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - conf_data = lo & 0xfffff000; - } - break; - case PCI_CARDBUS_CIS: - conf_data = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: - conf_data = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: - conf_data = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: - conf_data = - CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); - break; - case PCI_EHCI_LEGSMIEN_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - conf_data = (hi & 0x003f0000) >> 16; - break; - case PCI_EHCI_LEGSMISTS_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - conf_data = (hi & 0x3f000000) >> 24; - break; - case PCI_EHCI_FLADJ_REG: - _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); - conf_data = hi & 0x00003f00; - break; - default: - break; - } - - return conf_data; -} diff --git a/trunk/arch/mips/loongson/common/cs5536/cs5536_ide.c b/trunk/arch/mips/loongson/common/cs5536/cs5536_ide.c deleted file mode 100644 index 3f61594b3884..000000000000 --- a/trunk/arch/mips/loongson/common/cs5536/cs5536_ide.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * the IDE Virtual Support Module of AMD CS5536 - * - * Copyright (C) 2007 Lemote, Inc. - * Author : jlliu, liujl@lemote.com - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -void pci_ide_write_reg(int reg, u32 value) -{ - u32 hi = 0, lo = value; - - switch (reg) { - case PCI_COMMAND: - _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); - if (value & PCI_COMMAND_MASTER) - lo |= (0x03 << 4); - else - lo &= ~(0x03 << 4); - _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); - break; - case PCI_STATUS: - if (value & PCI_STATUS_PARITY) { - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) { - lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; - _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); - } - } - break; - case PCI_CACHE_LINE_SIZE: - value &= 0x0000ff00; - _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); - hi &= 0xffffff00; - hi |= (value >> 8); - _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); - break; - case PCI_BAR4_REG: - if (value == PCI_BAR_RANGE_MASK) { - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - lo |= SOFT_BAR_IDE_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else if (value & 0x01) { - lo = (value & 0xfffffff0) | 0x1; - _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo); - - value &= 0xfffffffc; - hi = 0x60000000 | ((value & 0x000ff000) >> 12); - lo = 0x000ffff0 | ((value & 0x00000fff) << 20); - _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo); - } - break; - case PCI_IDE_CFG_REG: - if (value == CS5536_IDE_FLASH_SIGNATURE) { - _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); - lo |= 0x01; - _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); - } else - _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); - break; - case PCI_IDE_DTC_REG: - _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); - break; - case PCI_IDE_CAST_REG: - _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); - break; - case PCI_IDE_ETC_REG: - _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); - break; - case PCI_IDE_PM_REG: - _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); - break; - default: - break; - } -} - -u32 pci_ide_read_reg(int reg) -{ - u32 conf_data = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); - if (lo & 0xfffffff0) - conf_data |= PCI_COMMAND_IO; - _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); - if ((lo & 0x30) == 0x30) - conf_data |= PCI_COMMAND_MASTER; - break; - case PCI_STATUS: - conf_data |= PCI_STATUS_66MHZ; - conf_data |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) - conf_data |= PCI_STATUS_PARITY; - conf_data |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo); - conf_data = lo & 0x000000ff; - conf_data |= (CS5536_IDE_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: - _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); - hi &= 0x000000f8; - conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); - break; - case PCI_BAR4_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_IDE_FLAG) { - conf_data = CS5536_IDE_RANGE | - PCI_BASE_ADDRESS_SPACE_IO; - lo &= ~SOFT_BAR_IDE_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); - conf_data = lo & 0xfffffff0; - conf_data |= 0x01; - conf_data &= ~0x02; - } - break; - case PCI_CARDBUS_CIS: - conf_data = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: - conf_data = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: - conf_data = PCI_CAPLIST_POINTER; - break; - case PCI_INTERRUPT_LINE: - conf_data = - CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); - break; - case PCI_IDE_CFG_REG: - _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo); - conf_data = lo; - break; - case PCI_IDE_DTC_REG: - _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); - conf_data = lo; - break; - case PCI_IDE_CAST_REG: - _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); - conf_data = lo; - break; - case PCI_IDE_ETC_REG: - _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); - conf_data = lo; - case PCI_IDE_PM_REG: - _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); - conf_data = lo; - break; - default: - break; - } - - return conf_data; -} diff --git a/trunk/arch/mips/loongson/common/cs5536/cs5536_isa.c b/trunk/arch/mips/loongson/common/cs5536/cs5536_isa.c deleted file mode 100644 index b6f17f538e48..000000000000 --- a/trunk/arch/mips/loongson/common/cs5536/cs5536_isa.c +++ /dev/null @@ -1,316 +0,0 @@ -/* - * the ISA Virtual Support Module of AMD CS5536 - * - * Copyright (C) 2007 Lemote, Inc. - * Author : jlliu, liujl@lemote.com - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -/* common variables for PCI_ISA_READ/WRITE_BAR */ -static const u32 divil_msr_reg[6] = { - DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO), - DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ), - DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI), -}; - -static const u32 soft_bar_flag[6] = { - SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG, - SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG, -}; - -static const u32 sb_msr_reg[6] = { - SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2), - SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5), -}; - -static const u32 bar_space_range[6] = { - CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE, - CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE, -}; - -static const int bar_space_len[6] = { - CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH, - CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH, -}; - -/* - * enable the divil module bar space. - * - * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg - * and the RCONFx(0~5) reg to use the modules. - */ -static void divil_lbar_enable(void) -{ - u32 hi, lo; - int offset; - - /* - * The DIVIL IRQ is not used yet. and make the RCONF0 reserved. - */ - - for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { - _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); - hi |= 0x01; - _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); - } -} - -/* - * disable the divil module bar space. - */ -static void divil_lbar_disable(void) -{ - u32 hi, lo; - int offset; - - for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { - _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); - hi &= ~0x01; - _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); - } -} - -/* - * BAR write: write value to the n BAR - */ - -void pci_isa_write_bar(int n, u32 value) -{ - u32 hi = 0, lo = value; - - if (value == PCI_BAR_RANGE_MASK) { - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - lo |= soft_bar_flag[n]; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else if (value & 0x01) { - /* NATIVE reg */ - hi = 0x0000f001; - lo &= bar_space_range[n]; - _wrmsr(divil_msr_reg[n], hi, lo); - - /* RCONFx is 4bytes in units for I/O space */ - hi = ((value & 0x000ffffc) << 12) | - ((bar_space_len[n] - 4) << 12) | 0x01; - lo = ((value & 0x000ffffc) << 12) | 0x01; - _wrmsr(sb_msr_reg[n], hi, lo); - } -} - -/* - * BAR read: read the n BAR - */ - -u32 pci_isa_read_bar(int n) -{ - u32 conf_data = 0; - u32 hi, lo; - - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & soft_bar_flag[n]) { - conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO; - lo &= ~soft_bar_flag[n]; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(divil_msr_reg[n], &hi, &lo); - conf_data = lo & bar_space_range[n]; - conf_data |= 0x01; - conf_data &= ~0x02; - } - return conf_data; -} - -/* - * isa_write: ISA write transfer - * - * We assume that this is not a bus master transfer. - */ -void pci_isa_write_reg(int reg, u32 value) -{ - u32 hi = 0, lo = value; - u32 temp; - - switch (reg) { - case PCI_COMMAND: - if (value & PCI_COMMAND_IO) - divil_lbar_enable(); - else - divil_lbar_disable(); - break; - case PCI_STATUS: - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - temp = lo & 0x0000ffff; - if ((value & PCI_STATUS_SIG_TARGET_ABORT) && - (lo & SB_TAS_ERR_EN)) - temp |= SB_TAS_ERR_FLAG; - - if ((value & PCI_STATUS_REC_TARGET_ABORT) && - (lo & SB_TAR_ERR_EN)) - temp |= SB_TAR_ERR_FLAG; - - if ((value & PCI_STATUS_REC_MASTER_ABORT) - && (lo & SB_MAR_ERR_EN)) - temp |= SB_MAR_ERR_FLAG; - - if ((value & PCI_STATUS_DETECTED_PARITY) - && (lo & SB_PARE_ERR_EN)) - temp |= SB_PARE_ERR_FLAG; - - lo = temp; - _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); - break; - case PCI_CACHE_LINE_SIZE: - value &= 0x0000ff00; - _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); - hi &= 0xffffff00; - hi |= (value >> 8); - _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); - break; - case PCI_BAR0_REG: - pci_isa_write_bar(0, value); - break; - case PCI_BAR1_REG: - pci_isa_write_bar(1, value); - break; - case PCI_BAR2_REG: - pci_isa_write_bar(2, value); - break; - case PCI_BAR3_REG: - pci_isa_write_bar(3, value); - break; - case PCI_BAR4_REG: - pci_isa_write_bar(4, value); - break; - case PCI_BAR5_REG: - pci_isa_write_bar(5, value); - break; - case PCI_UART1_INT_REG: - _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); - /* disable uart1 interrupt in PIC */ - lo &= ~(0xf << 24); - if (value) /* enable uart1 interrupt in PIC */ - lo |= (CS5536_UART1_INTR << 24); - _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); - break; - case PCI_UART2_INT_REG: - _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); - /* disable uart2 interrupt in PIC */ - lo &= ~(0xf << 28); - if (value) /* enable uart2 interrupt in PIC */ - lo |= (CS5536_UART2_INTR << 28); - _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); - break; - case PCI_ISA_FIXUP_REG: - if (value) { - /* enable the TARGET ABORT/MASTER ABORT etc. */ - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - lo |= 0x00000063; - _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); - } - - default: - /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */ - break; - } -} - -/* - * isa_read: ISA read transfers - * - * We assume that this is not a bus master transfer. - */ -u32 pci_isa_read_reg(int reg) -{ - u32 conf_data = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - /* we just check the first LBAR for the IO enable bit, */ - /* maybe we should changed later. */ - _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo); - if (hi & 0x01) - conf_data |= PCI_COMMAND_IO; - break; - case PCI_STATUS: - conf_data |= PCI_STATUS_66MHZ; - conf_data |= PCI_STATUS_DEVSEL_MEDIUM; - conf_data |= PCI_STATUS_FAST_BACK; - - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_TAS_ERR_FLAG) - conf_data |= PCI_STATUS_SIG_TARGET_ABORT; - if (lo & SB_TAR_ERR_FLAG) - conf_data |= PCI_STATUS_REC_TARGET_ABORT; - if (lo & SB_MAR_ERR_FLAG) - conf_data |= PCI_STATUS_REC_MASTER_ABORT; - if (lo & SB_PARE_ERR_FLAG) - conf_data |= PCI_STATUS_DETECTED_PARITY; - break; - case PCI_CLASS_REVISION: - _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo); - conf_data = lo & 0x000000ff; - conf_data |= (CS5536_ISA_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: - _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); - hi &= 0x000000f8; - conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi); - break; - /* - * we only use the LBAR of DIVIL, no RCONF used. - * all of them are IO space. - */ - case PCI_BAR0_REG: - return pci_isa_read_bar(0); - break; - case PCI_BAR1_REG: - return pci_isa_read_bar(1); - break; - case PCI_BAR2_REG: - return pci_isa_read_bar(2); - break; - case PCI_BAR3_REG: - break; - case PCI_BAR4_REG: - return pci_isa_read_bar(4); - break; - case PCI_BAR5_REG: - return pci_isa_read_bar(5); - break; - case PCI_CARDBUS_CIS: - conf_data = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: - conf_data = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: - conf_data = PCI_CAPLIST_POINTER; - break; - case PCI_INTERRUPT_LINE: - /* no interrupt used here */ - conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00); - break; - default: - break; - } - - return conf_data; -} diff --git a/trunk/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/trunk/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c deleted file mode 100644 index 6cb44dbaeec2..000000000000 --- a/trunk/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c +++ /dev/null @@ -1,217 +0,0 @@ -/* - * CS5536 General timer functions - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Yanhua, yanh@lemote.com - * - * Copyright (C) 2009 Lemote Inc. - * Author: Wu zhangjin, wuzj@lemote.com - * - * Reference: AMD Geode(TM) CS5536 Companion Device Data Book - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -DEFINE_SPINLOCK(mfgpt_lock); -EXPORT_SYMBOL(mfgpt_lock); - -static u32 mfgpt_base; - -/* - * Initialize the MFGPT timer. - * - * This is also called after resume to bring the MFGPT into operation again. - */ - -/* disable counter */ -void disable_mfgpt0_counter(void) -{ - outw(inw(MFGPT0_SETUP) & 0x7fff, MFGPT0_SETUP); -} -EXPORT_SYMBOL(disable_mfgpt0_counter); - -/* enable counter, comparator2 to event mode, 14.318MHz clock */ -void enable_mfgpt0_counter(void) -{ - outw(0xe310, MFGPT0_SETUP); -} -EXPORT_SYMBOL(enable_mfgpt0_counter); - -static void init_mfgpt_timer(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - spin_lock(&mfgpt_lock); - - switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - outw(COMPARE, MFGPT0_CMP2); /* set comparator2 */ - outw(0, MFGPT0_CNT); /* set counter to 0 */ - enable_mfgpt0_counter(); - break; - - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_UNUSED: - if (evt->mode == CLOCK_EVT_MODE_PERIODIC || - evt->mode == CLOCK_EVT_MODE_ONESHOT) - disable_mfgpt0_counter(); - break; - - case CLOCK_EVT_MODE_ONESHOT: - /* The oneshot mode have very high deviation, Not use it! */ - break; - - case CLOCK_EVT_MODE_RESUME: - /* Nothing to do here */ - break; - } - spin_unlock(&mfgpt_lock); -} - -static struct clock_event_device mfgpt_clockevent = { - .name = "mfgpt", - .features = CLOCK_EVT_FEAT_PERIODIC, - .set_mode = init_mfgpt_timer, - .irq = CS5536_MFGPT_INTR, -}; - -static irqreturn_t timer_interrupt(int irq, void *dev_id) -{ - u32 basehi; - - /* - * get MFGPT base address - * - * NOTE: do not remove me, it's need for the value of mfgpt_base is - * variable - */ - _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); - - /* ack */ - outw(inw(MFGPT0_SETUP) | 0x4000, MFGPT0_SETUP); - - mfgpt_clockevent.event_handler(&mfgpt_clockevent); - - return IRQ_HANDLED; -} - -static struct irqaction irq5 = { - .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, - .name = "timer" -}; - -/* - * Initialize the conversion factor and the min/max deltas of the clock event - * structure and register the clock event source with the framework. - */ -void __init setup_mfgpt0_timer(void) -{ - u32 basehi; - struct clock_event_device *cd = &mfgpt_clockevent; - unsigned int cpu = smp_processor_id(); - - cd->cpumask = cpumask_of(cpu); - clockevent_set_clock(cd, MFGPT_TICK_RATE); - cd->max_delta_ns = clockevent_delta2ns(0xffff, cd); - cd->min_delta_ns = clockevent_delta2ns(0xf, cd); - - /* Enable MFGPT0 Comparator 2 Output to the Interrupt Mapper */ - _wrmsr(DIVIL_MSR_REG(MFGPT_IRQ), 0, 0x100); - - /* Enable Interrupt Gate 5 */ - _wrmsr(DIVIL_MSR_REG(PIC_ZSEL_LOW), 0, 0x50000); - - /* get MFGPT base address */ - _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), &basehi, &mfgpt_base); - - clockevents_register_device(cd); - - setup_irq(CS5536_MFGPT_INTR, &irq5); -} - -/* - * Since the MFGPT overflows every tick, its not very useful - * to just read by itself. So use jiffies to emulate a free - * running counter: - */ -static cycle_t mfgpt_read(struct clocksource *cs) -{ - unsigned long flags; - int count; - u32 jifs; - static int old_count; - static u32 old_jifs; - - spin_lock_irqsave(&mfgpt_lock, flags); - /* - * Although our caller may have the read side of xtime_lock, - * this is now a seqlock, and we are cheating in this routine - * by having side effects on state that we cannot undo if - * there is a collision on the seqlock and our caller has to - * retry. (Namely, old_jifs and old_count.) So we must treat - * jiffies as volatile despite the lock. We read jiffies - * before latching the timer count to guarantee that although - * the jiffies value might be older than the count (that is, - * the counter may underflow between the last point where - * jiffies was incremented and the point where we latch the - * count), it cannot be newer. - */ - jifs = jiffies; - /* read the count */ - count = inw(MFGPT0_CNT); - - /* - * It's possible for count to appear to go the wrong way for this - * reason: - * - * The timer counter underflows, but we haven't handled the resulting - * interrupt and incremented jiffies yet. - * - * Previous attempts to handle these cases intelligently were buggy, so - * we just do the simple thing now. - */ - if (count < old_count && jifs == old_jifs) - count = old_count; - - old_count = count; - old_jifs = jifs; - - spin_unlock_irqrestore(&mfgpt_lock, flags); - - return (cycle_t) (jifs * COMPARE) + count; -} - -static struct clocksource clocksource_mfgpt = { - .name = "mfgpt", - .rating = 120, /* Functional for real use, but not desired */ - .read = mfgpt_read, - .mask = CLOCKSOURCE_MASK(32), - .mult = 0, - .shift = 22, -}; - -int __init init_mfgpt_clocksource(void) -{ - if (num_possible_cpus() > 1) /* MFGPT does not scale! */ - return 0; - - clocksource_mfgpt.mult = clocksource_hz2mult(MFGPT_TICK_RATE, 22); - return clocksource_register(&clocksource_mfgpt); -} - -arch_initcall(init_mfgpt_clocksource); diff --git a/trunk/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/trunk/arch/mips/loongson/common/cs5536/cs5536_ohci.c deleted file mode 100644 index 8fdb02b6e90f..000000000000 --- a/trunk/arch/mips/loongson/common/cs5536/cs5536_ohci.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * the OHCI Virtual Support Module of AMD CS5536 - * - * Copyright (C) 2007 Lemote, Inc. - * Author : jlliu, liujl@lemote.com - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -void pci_ohci_write_reg(int reg, u32 value) -{ - u32 hi = 0, lo = value; - - switch (reg) { - case PCI_COMMAND: - _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); - if (value & PCI_COMMAND_MASTER) - hi |= PCI_COMMAND_MASTER; - else - hi &= ~PCI_COMMAND_MASTER; - - if (value & PCI_COMMAND_MEMORY) - hi |= PCI_COMMAND_MEMORY; - else - hi &= ~PCI_COMMAND_MEMORY; - _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); - break; - case PCI_STATUS: - if (value & PCI_STATUS_PARITY) { - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) { - lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; - _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); - } - } - break; - case PCI_BAR0_REG: - if (value == PCI_BAR_RANGE_MASK) { - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - lo |= SOFT_BAR_OHCI_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else if ((value & 0x01) == 0x00) { - _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); - - value &= 0xfffffff0; - hi = 0x40000000 | ((value & 0xff000000) >> 24); - lo = 0x000fffff | ((value & 0x00fff000) << 8); - _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo); - } - break; - case PCI_OHCI_INT_REG: - _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); - lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT); - if (value) /* enable all the usb interrupt in PIC */ - lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT); - _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); - break; - default: - break; - } -} - -u32 pci_ohci_read_reg(int reg) -{ - u32 conf_data = 0; - u32 hi, lo; - - switch (reg) { - case PCI_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID); - break; - case PCI_COMMAND: - _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); - if (hi & PCI_COMMAND_MASTER) - conf_data |= PCI_COMMAND_MASTER; - if (hi & PCI_COMMAND_MEMORY) - conf_data |= PCI_COMMAND_MEMORY; - break; - case PCI_STATUS: - conf_data |= PCI_STATUS_66MHZ; - conf_data |= PCI_STATUS_FAST_BACK; - _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); - if (lo & SB_PARE_ERR_FLAG) - conf_data |= PCI_STATUS_PARITY; - conf_data |= PCI_STATUS_DEVSEL_MEDIUM; - break; - case PCI_CLASS_REVISION: - _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); - conf_data = lo & 0x000000ff; - conf_data |= (CS5536_OHCI_CLASS_CODE << 8); - break; - case PCI_CACHE_LINE_SIZE: - conf_data = - CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, - PCI_NORMAL_LATENCY_TIMER); - break; - case PCI_BAR0_REG: - _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); - if (lo & SOFT_BAR_OHCI_FLAG) { - conf_data = CS5536_OHCI_RANGE | - PCI_BASE_ADDRESS_SPACE_MEMORY; - lo &= ~SOFT_BAR_OHCI_FLAG; - _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); - } else { - _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); - conf_data = lo & 0xffffff00; - conf_data &= ~0x0000000f; /* 32bit mem */ - } - break; - case PCI_CARDBUS_CIS: - conf_data = PCI_CARDBUS_CIS_POINTER; - break; - case PCI_SUBSYSTEM_VENDOR_ID: - conf_data = - CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID); - break; - case PCI_ROM_ADDRESS: - conf_data = PCI_EXPANSION_ROM_BAR; - break; - case PCI_CAPABILITY_LIST: - conf_data = PCI_CAPLIST_USB_POINTER; - break; - case PCI_INTERRUPT_LINE: - conf_data = - CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); - break; - case PCI_OHCI_INT_REG: - _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); - if ((lo & 0x00000f00) == CS5536_USB_INTR) - conf_data = 1; - break; - default: - break; - } - - return conf_data; -} diff --git a/trunk/arch/mips/loongson/common/cs5536/cs5536_pci.c b/trunk/arch/mips/loongson/common/cs5536/cs5536_pci.c deleted file mode 100644 index e23f3d7d2c1d..000000000000 --- a/trunk/arch/mips/loongson/common/cs5536/cs5536_pci.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * read/write operation to the PCI config space of CS5536 - * - * Copyright (C) 2007 Lemote, Inc. - * Author : jlliu, liujl@lemote.com - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * the Virtual Support Module(VSM) for virtulizing the PCI - * configure space are defined in cs5536_modulename.c respectively, - * - * after this virtulizing, user can access the PCI configure space - * directly as a normal multi-function PCI device which follows - * the PCI-2.2 spec. - */ - -#include -#include - -enum { - CS5536_FUNC_START = -1, - CS5536_ISA_FUNC, - reserved_func, - CS5536_IDE_FUNC, - CS5536_ACC_FUNC, - CS5536_OHCI_FUNC, - CS5536_EHCI_FUNC, - CS5536_FUNC_END, -}; - -static const cs5536_pci_vsm_write vsm_conf_write[] = { - [CS5536_ISA_FUNC] pci_isa_write_reg, - [reserved_func] NULL, - [CS5536_IDE_FUNC] pci_ide_write_reg, - [CS5536_ACC_FUNC] pci_acc_write_reg, - [CS5536_OHCI_FUNC] pci_ohci_write_reg, - [CS5536_EHCI_FUNC] pci_ehci_write_reg, -}; - -static const cs5536_pci_vsm_read vsm_conf_read[] = { - [CS5536_ISA_FUNC] pci_isa_read_reg, - [reserved_func] NULL, - [CS5536_IDE_FUNC] pci_ide_read_reg, - [CS5536_ACC_FUNC] pci_acc_read_reg, - [CS5536_OHCI_FUNC] pci_ohci_read_reg, - [CS5536_EHCI_FUNC] pci_ehci_read_reg, -}; - -/* - * write to PCI config space and transfer it to MSR write. - */ -void cs5536_pci_conf_write4(int function, int reg, u32 value) -{ - if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END)) - return; - if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) - return; - - if (vsm_conf_write[function] != NULL) - vsm_conf_write[function](reg, value); -} - -/* - * read PCI config space and transfer it to MSR access. - */ -u32 cs5536_pci_conf_read4(int function, int reg) -{ - u32 data = 0; - - if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END)) - return 0; - if ((reg < 0) || ((reg & 0x03) != 0)) - return 0; - if (reg > 0x100) - return 0xffffffff; - - if (vsm_conf_read[function] != NULL) - data = vsm_conf_read[function](reg); - - return data; -} diff --git a/trunk/arch/mips/loongson/common/early_printk.c b/trunk/arch/mips/loongson/common/early_printk.c index 23e7a8f8897f..bc73edc0cfd8 100644 --- a/trunk/arch/mips/loongson/common/early_printk.c +++ b/trunk/arch/mips/loongson/common/early_printk.c @@ -1,7 +1,7 @@ /* early printk support * * Copyright (c) 2009 Philippe Vachon - * Copyright (c) 2009 Lemote Inc. + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology * Author: Wu Zhangjin, wuzj@lemote.com * * This program is free software; you can redistribute it and/or modify it @@ -12,29 +12,26 @@ #include #include +#include #define PORT(base, offset) (u8 *)(base + offset) -static inline unsigned int serial_in(unsigned char *base, int offset) +static inline unsigned int serial_in(phys_addr_t base, int offset) { return readb(PORT(base, offset)); } -static inline void serial_out(unsigned char *base, int offset, int value) +static inline void serial_out(phys_addr_t base, int offset, int value) { writeb(value, PORT(base, offset)); } void prom_putchar(char c) { - int timeout; - unsigned char *uart_base; + phys_addr_t uart_base = + (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); - uart_base = (unsigned char *)_loongson_uart_base; - timeout = 1024; - - while (((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) && - (timeout-- > 0)) + while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) ; serial_out(uart_base, UART_TX, c); diff --git a/trunk/arch/mips/loongson/common/env.c b/trunk/arch/mips/loongson/common/env.c index 196d947d929a..b9ef50385541 100644 --- a/trunk/arch/mips/loongson/common/env.c +++ b/trunk/arch/mips/loongson/common/env.c @@ -17,14 +17,11 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include - #include #include unsigned long bus_clock, cpu_clock_freq; -EXPORT_SYMBOL(cpu_clock_freq); unsigned long memsize, highmemsize; /* pmon passes arguments in 32bit pointers */ diff --git a/trunk/arch/mips/loongson/common/init.c b/trunk/arch/mips/loongson/common/init.c index a2abd9355737..3abe927422a3 100644 --- a/trunk/arch/mips/loongson/common/init.c +++ b/trunk/arch/mips/loongson/common/init.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote Inc. + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology * Author: Wu Zhangjin, wuzj@lemote.com * * This program is free software; you can redistribute it and/or modify it @@ -10,28 +10,19 @@ #include -#include +#include -/* Loongson CPU address windows config space base address */ -unsigned long __maybe_unused _loongson_addrwincfg_base; +#include void __init prom_init(void) { - /* init base address of io space */ + /* init base address of io space */ set_io_port_base((unsigned long) - ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); - -#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG - _loongson_addrwincfg_base = (unsigned long) - ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); -#endif + ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); prom_init_cmdline(); prom_init_env(); prom_init_memory(); - - /*init the uart base address */ - prom_init_uart_base(); } void __init prom_free_prom_memory(void) diff --git a/trunk/arch/mips/loongson/common/irq.c b/trunk/arch/mips/loongson/common/irq.c index 20e732831978..b32b4a3e5137 100644 --- a/trunk/arch/mips/loongson/common/irq.c +++ b/trunk/arch/mips/loongson/common/irq.c @@ -20,21 +20,21 @@ void bonito_irqdispatch(void) int i; /* workaround the IO dma problem: let cpu looping to allow DMA finish */ - int_status = LOONGSON_INTISR; + int_status = BONITO_INTISR; if (int_status & (1 << 10)) { while (int_status & (1 << 10)) { udelay(1); - int_status = LOONGSON_INTISR; + int_status = BONITO_INTISR; } } /* Get pending sources, masked by current enables */ - int_status = LOONGSON_INTISR & LOONGSON_INTEN; + int_status = BONITO_INTISR & BONITO_INTEN; if (int_status != 0) { i = __ffs(int_status); int_status &= ~(1 << i); - do_IRQ(LOONGSON_IRQ_BASE + i); + do_IRQ(BONITO_IRQ_BASE + i); } } @@ -60,13 +60,13 @@ void __init arch_init_irq(void) set_irq_trigger_mode(); /* no steer */ - LOONGSON_INTSTEER = 0; + BONITO_INTSTEER = 0; /* * Mask out all interrupt by writing "1" to all bit position in * the interrupt reset reg. */ - LOONGSON_INTENCLR = ~0; + BONITO_INTENCLR = ~0; /* machine specific irq init */ mach_init_irq(); diff --git a/trunk/arch/mips/loongson/common/machtype.c b/trunk/arch/mips/loongson/common/machtype.c index 0ed52b3f5314..7b348248de7d 100644 --- a/trunk/arch/mips/loongson/common/machtype.c +++ b/trunk/arch/mips/loongson/common/machtype.c @@ -15,9 +15,6 @@ #include #include -/* please ensure the length of the machtype string is less than 50 */ -#define MACHTYPE_LEN 50 - static const char *system_types[] = { [MACH_LOONGSON_UNKNOWN] "unknown loongson machine", [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box", @@ -25,35 +22,29 @@ static const char *system_types[] = { [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches", [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches", [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches", - [MACH_LEMOTE_NAS] "lemote-nas-2f", - [MACH_LEMOTE_LL2F] "lemote-lynloong-2f", [MACH_LOONGSON_END] NULL, }; const char *get_system_type(void) { + if (mips_machtype == MACH_UNKNOWN) + mips_machtype = LOONGSON_MACHTYPE; + return system_types[mips_machtype]; } -void __init prom_init_machtype(void) +static __init int machtype_setup(char *str) { - char *p, str[MACHTYPE_LEN]; int machtype = MACH_LEMOTE_FL2E; - mips_machtype = LOONGSON_MACHTYPE; - - p = strstr(arcs_cmdline, "machtype="); - if (!p) - return; - p += strlen("machtype="); - strncpy(str, p, MACHTYPE_LEN); - p = strstr(str, " "); - if (p) - *p = '\0'; + if (!str) + return -EINVAL; for (; system_types[machtype]; machtype++) if (strstr(system_types[machtype], str)) { mips_machtype = machtype; break; } + return 0; } +__setup("machtype=", machtype_setup); diff --git a/trunk/arch/mips/loongson/common/mem.c b/trunk/arch/mips/loongson/common/mem.c index ceacd092b446..e94ef158f980 100644 --- a/trunk/arch/mips/loongson/common/mem.c +++ b/trunk/arch/mips/loongson/common/mem.c @@ -12,40 +12,15 @@ #include #include -#include void __init prom_init_memory(void) { add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); - - add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize << - 20), BOOT_MEM_RESERVED); -#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG - { - int bit; - - bit = fls(memsize + highmemsize); - if (bit != ffs(memsize + highmemsize)) - bit += 20; - else - bit = bit + 20 - 1; - - /* set cpu window3 to map CPU to DDR: 2G -> 2G */ - LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul, - 0x80000000ul, (1 << bit)); - mmiowb(); - } -#endif /* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */ - #ifdef CONFIG_64BIT - if (highmemsize > 0) - add_memory_region(LOONGSON_HIGHMEM_START, - highmemsize << 20, BOOT_MEM_RAM); - - add_memory_region(LOONGSON_PCI_MEM_END + 1, LOONGSON_HIGHMEM_START - - LOONGSON_PCI_MEM_END - 1, BOOT_MEM_RESERVED); - -#endif /* !CONFIG_64BIT */ + if (highmemsize > 0) + add_memory_region(LOONGSON_HIGHMEM_START, + highmemsize << 20, BOOT_MEM_RAM); +#endif /* CONFIG_64BIT */ } /* override of arch/mips/mm/cache.c: __uncached_access */ @@ -58,61 +33,3 @@ int __uncached_access(struct file *file, unsigned long addr) ((addr >= LOONGSON_MMIO_MEM_START) && (addr < LOONGSON_MMIO_MEM_END)); } - -#ifdef CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED - -#include -#include -#include - -static unsigned long uca_start, uca_end; - -pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, - unsigned long size, pgprot_t vma_prot) -{ - unsigned long offset = pfn << PAGE_SHIFT; - unsigned long end = offset + size; - - if (__uncached_access(file, offset)) { - if (((uca_start && offset) >= uca_start) && - (end <= uca_end)) - return __pgprot((pgprot_val(vma_prot) & - ~_CACHE_MASK) | - _CACHE_UNCACHED_ACCELERATED); - else - return pgprot_noncached(vma_prot); - } - return vma_prot; -} - -static int __init find_vga_mem_init(void) -{ - struct pci_dev *dev = 0; - struct resource *r; - int idx; - - if (uca_start) - return 0; - - for_each_pci_dev(dev) { - if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) { - for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) { - r = &dev->resource[idx]; - if (!r->start && r->end) - continue; - if (r->flags & IORESOURCE_IO) - continue; - if (r->flags & IORESOURCE_MEM) { - uca_start = r->start; - uca_end = r->end; - return 0; - } - } - } - } - - return 0; -} - -late_initcall(find_vga_mem_init); -#endif /* !CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED */ diff --git a/trunk/arch/mips/loongson/common/pci.c b/trunk/arch/mips/loongson/common/pci.c index 31d8c5ecd16c..a3a4abfb6c9a 100644 --- a/trunk/arch/mips/loongson/common/pci.c +++ b/trunk/arch/mips/loongson/common/pci.c @@ -27,7 +27,7 @@ static struct resource loongson_pci_io_resource = { }; static struct pci_controller loongson_pci_controller = { - .pci_ops = &loongson_pci_ops, + .pci_ops = &bonito64_pci_ops, .io_resource = &loongson_pci_io_resource, .mem_resource = &loongson_pci_mem_resource, .mem_offset = 0x00000000UL, @@ -44,15 +44,15 @@ static void __init setup_pcimap(void) * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 * [<2G] [384M,448M] [320M,384M] [0M,64M] */ - LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 | - LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) | - LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) | - LOONGSON_PCIMAP_WIN(0, 0); + BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | + BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | + BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | + BONITO_PCIMAP_WIN(0, 0); /* * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] */ - LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ + BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ /* size: 256M, burst transmission, pre-fetch enable, 64bit */ LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; @@ -67,14 +67,6 @@ static void __init setup_pcimap(void) /* can not change gnt to break pci transfer when device's gnt not deassert for some broken device */ LOONGSON_PXARB_CFG = 0x00fe0105ul; - -#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG - /* - * set cpu addr window2 to map CPU address space to PCI address space - */ - LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC, - LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE); -#endif } static int __init pcibios_init(void) diff --git a/trunk/arch/mips/loongson/common/platform.c b/trunk/arch/mips/loongson/common/platform.c deleted file mode 100644 index be81777eb94d..000000000000 --- a/trunk/arch/mips/loongson/common/platform.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -static struct platform_device loongson2_cpufreq_device = { - .name = "loongson2_cpufreq", - .id = -1, -}; - -static int __init loongson2_cpufreq_init(void) -{ - struct cpuinfo_mips *c = ¤t_cpu_data; - - /* Only 2F revision and it's successors support CPUFreq */ - if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON2F) - return platform_device_register(&loongson2_cpufreq_device); - - return -ENODEV; -} - -arch_initcall(loongson2_cpufreq_init); diff --git a/trunk/arch/mips/loongson/common/pm.c b/trunk/arch/mips/loongson/common/pm.c deleted file mode 100644 index b625fec8a4d5..000000000000 --- a/trunk/arch/mips/loongson/common/pm.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * loongson-specific suspend support - * - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ -#include -#include -#include - -#include -#include - -#include - -static unsigned int __maybe_unused cached_master_mask; /* i8259A */ -static unsigned int __maybe_unused cached_slave_mask; -static unsigned int __maybe_unused cached_bonito_irq_mask; /* bonito */ - -void arch_suspend_disable_irqs(void) -{ - /* disable all mips events */ - local_irq_disable(); - -#ifdef CONFIG_I8259 - /* disable all events of i8259A */ - cached_slave_mask = inb(PIC_SLAVE_IMR); - cached_master_mask = inb(PIC_MASTER_IMR); - - outb(0xff, PIC_SLAVE_IMR); - inb(PIC_SLAVE_IMR); - outb(0xff, PIC_MASTER_IMR); - inb(PIC_MASTER_IMR); -#endif - /* disable all events of bonito */ - cached_bonito_irq_mask = LOONGSON_INTEN; - LOONGSON_INTENCLR = 0xffff; - (void)LOONGSON_INTENCLR; -} - -void arch_suspend_enable_irqs(void) -{ - /* enable all mips events */ - local_irq_enable(); -#ifdef CONFIG_I8259 - /* only enable the cached events of i8259A */ - outb(cached_slave_mask, PIC_SLAVE_IMR); - outb(cached_master_mask, PIC_MASTER_IMR); -#endif - /* enable all cached events of bonito */ - LOONGSON_INTENSET = cached_bonito_irq_mask; - (void)LOONGSON_INTENSET; -} - -/* - * Setup the board-specific events for waking up loongson from wait mode - */ -void __weak setup_wakeup_events(void) -{ -} - -/* - * Check wakeup events - */ -int __weak wakeup_loongson(void) -{ - return 1; -} - -/* - * If the events are really what we want to wakeup the CPU, wake it up - * otherwise put the CPU asleep again. - */ -static void wait_for_wakeup_events(void) -{ - while (!wakeup_loongson()) - LOONGSON_CHIPCFG0 &= ~0x7; -} - -/* - * Stop all perf counters - * - * $24 is the control register of Loongson perf counter - */ -static inline void stop_perf_counters(void) -{ - __write_64bit_c0_register($24, 0, 0); -} - - -static void loongson_suspend_enter(void) -{ - static unsigned int cached_cpu_freq; - - /* setup wakeup events via enabling the IRQs */ - setup_wakeup_events(); - - stop_perf_counters(); - - cached_cpu_freq = LOONGSON_CHIPCFG0; - - /* Put CPU into wait mode */ - LOONGSON_CHIPCFG0 &= ~0x7; - - /* wait for the given events to wakeup cpu from wait mode */ - wait_for_wakeup_events(); - - LOONGSON_CHIPCFG0 = cached_cpu_freq; - mmiowb(); -} - -void __weak mach_suspend(void) -{ -} - -void __weak mach_resume(void) -{ -} - -static int loongson_pm_enter(suspend_state_t state) -{ - mach_suspend(); - - /* processor specific suspend */ - loongson_suspend_enter(); - - mach_resume(); - - return 0; -} - -static int loongson_pm_valid_state(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_ON: - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: - return 1; - - default: - return 0; - } -} - -static struct platform_suspend_ops loongson_pm_ops = { - .valid = loongson_pm_valid_state, - .enter = loongson_pm_enter, -}; - -static int __init loongson_pm_init(void) -{ - suspend_set_ops(&loongson_pm_ops); - - return 0; -} -arch_initcall(loongson_pm_init); diff --git a/trunk/arch/mips/loongson/common/reset.c b/trunk/arch/mips/loongson/common/reset.c index d57f1719da95..97e918251edd 100644 --- a/trunk/arch/mips/loongson/common/reset.c +++ b/trunk/arch/mips/loongson/common/reset.c @@ -22,7 +22,7 @@ static void loongson_restart(char *command) mach_prepare_reboot(); /* reboot via jumping to boot base address */ - ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); + ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); } static void loongson_halt(void) diff --git a/trunk/arch/mips/loongson/common/serial.c b/trunk/arch/mips/loongson/common/serial.c deleted file mode 100644 index 23b66a5f88cb..000000000000 --- a/trunk/arch/mips/loongson/common/serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - * - * Copyright (C) 2009 Lemote, Inc. - * Author: Yan hua (yanhua@lemote.com) - * Author: Wu Zhangjin (wuzj@lemote.com) - */ - -#include -#include -#include - -#include - -#include -#include - -#define PORT(int) \ -{ \ - .irq = int, \ - .uartclk = 1843200, \ - .iotype = UPIO_PORT, \ - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ - .regshift = 0, \ -} - -#define PORT_M(int) \ -{ \ - .irq = MIPS_CPU_IRQ_BASE + (int), \ - .uartclk = 3686400, \ - .iotype = UPIO_MEM, \ - .membase = (void __iomem *)NULL, \ - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ - .regshift = 0, \ -} - -static struct plat_serial8250_port uart8250_data[][2] = { - [MACH_LOONGSON_UNKNOWN] {}, - [MACH_LEMOTE_FL2E] {PORT(4), {} }, - [MACH_LEMOTE_FL2F] {PORT(3), {} }, - [MACH_LEMOTE_ML2F7] {PORT_M(3), {} }, - [MACH_LEMOTE_YL2F89] {PORT_M(3), {} }, - [MACH_DEXXON_GDIUM2F10] {PORT_M(3), {} }, - [MACH_LEMOTE_NAS] {PORT_M(3), {} }, - [MACH_LEMOTE_LL2F] {PORT(3), {} }, - [MACH_LOONGSON_END] {}, -}; - -static struct platform_device uart8250_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, -}; - -static int __init serial_init(void) -{ - unsigned char iotype; - - iotype = uart8250_data[mips_machtype][0].iotype; - - if (UPIO_MEM == iotype) - uart8250_data[mips_machtype][0].membase = - (void __iomem *)_loongson_uart_base; - else if (UPIO_PORT == iotype) - uart8250_data[mips_machtype][0].iobase = - loongson_uart_base - LOONGSON_PCIIO_BASE; - - uart8250_device.dev.platform_data = uart8250_data[mips_machtype]; - - return platform_device_register(&uart8250_device); -} - -device_initcall(serial_init); diff --git a/trunk/arch/mips/loongson/common/time.c b/trunk/arch/mips/loongson/common/time.c index 35f0b66a94f5..6e08c8270abe 100644 --- a/trunk/arch/mips/loongson/common/time.c +++ b/trunk/arch/mips/loongson/common/time.c @@ -14,14 +14,11 @@ #include #include -#include void __init plat_time_init(void) { /* setup mips r4k timer */ mips_hpt_frequency = cpu_clock_freq / 2; - - setup_mfgpt0_timer(); } void read_persistent_clock(struct timespec *ts) diff --git a/trunk/arch/mips/loongson/common/uart_base.c b/trunk/arch/mips/loongson/common/uart_base.c deleted file mode 100644 index 78ff66ae749e..000000000000 --- a/trunk/arch/mips/loongson/common/uart_base.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -#include - -/* ioremapped */ -unsigned long _loongson_uart_base; -EXPORT_SYMBOL(_loongson_uart_base); -/* raw */ -unsigned long loongson_uart_base; -EXPORT_SYMBOL(loongson_uart_base); - -void prom_init_loongson_uart_base(void) -{ - switch (mips_machtype) { - case MACH_LEMOTE_FL2E: - loongson_uart_base = LOONGSON_PCIIO_BASE + 0x3f8; - break; - case MACH_LEMOTE_FL2F: - case MACH_LEMOTE_LL2F: - loongson_uart_base = LOONGSON_PCIIO_BASE + 0x2f8; - break; - case MACH_LEMOTE_ML2F7: - case MACH_LEMOTE_YL2F89: - case MACH_DEXXON_GDIUM2F10: - case MACH_LEMOTE_NAS: - default: - /* The CPU provided serial port */ - loongson_uart_base = LOONGSON_LIO1_BASE + 0x3f8; - break; - } - - _loongson_uart_base = - (unsigned long)ioremap_nocache(loongson_uart_base, 8); -} diff --git a/trunk/arch/mips/loongson/fuloong-2e/irq.c b/trunk/arch/mips/loongson/fuloong-2e/irq.c index 320e9379bdd7..7888cf69424a 100644 --- a/trunk/arch/mips/loongson/fuloong-2e/irq.c +++ b/trunk/arch/mips/loongson/fuloong-2e/irq.c @@ -47,8 +47,8 @@ static struct irqaction cascade_irqaction = { void __init set_irq_trigger_mode(void) { /* most bonito irq should be level triggered */ - LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | - LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; + BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | + BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; } void __init mach_init_irq(void) diff --git a/trunk/arch/mips/loongson/fuloong-2e/reset.c b/trunk/arch/mips/loongson/fuloong-2e/reset.c index fc16c677d476..677fe186db95 100644 --- a/trunk/arch/mips/loongson/fuloong-2e/reset.c +++ b/trunk/arch/mips/loongson/fuloong-2e/reset.c @@ -14,8 +14,8 @@ void mach_prepare_reboot(void) { - LOONGSON_GENCFG &= ~(1 << 2); - LOONGSON_GENCFG |= (1 << 2); + BONITO_BONGENCFG &= ~(1 << 2); + BONITO_BONGENCFG |= (1 << 2); } void mach_prepare_shutdown(void) diff --git a/trunk/arch/mips/loongson/lemote-2f/Makefile b/trunk/arch/mips/loongson/lemote-2f/Makefile deleted file mode 100644 index 4d84b27dc41b..000000000000 --- a/trunk/arch/mips/loongson/lemote-2f/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# Makefile for lemote loongson2f family machines -# - -obj-y += irq.o reset.o ec_kb3310b.o - -# -# Suspend Support -# - -obj-$(CONFIG_LOONGSON_SUSPEND) += pm.o diff --git a/trunk/arch/mips/loongson/lemote-2f/ec_kb3310b.c b/trunk/arch/mips/loongson/lemote-2f/ec_kb3310b.c deleted file mode 100644 index 4d84111a2cd4..000000000000 --- a/trunk/arch/mips/loongson/lemote-2f/ec_kb3310b.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Basic KB3310B Embedded Controller support for the YeeLoong 2F netbook - * - * Copyright (C) 2008 Lemote Inc. - * Author: liujl , 2008-04-20 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include - -#include "ec_kb3310b.h" - -static DEFINE_SPINLOCK(index_access_lock); -static DEFINE_SPINLOCK(port_access_lock); - -unsigned char ec_read(unsigned short addr) -{ - unsigned char value; - unsigned long flags; - - spin_lock_irqsave(&index_access_lock, flags); - outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH); - outb((addr & 0x00ff), EC_IO_PORT_LOW); - value = inb(EC_IO_PORT_DATA); - spin_unlock_irqrestore(&index_access_lock, flags); - - return value; -} -EXPORT_SYMBOL_GPL(ec_read); - -void ec_write(unsigned short addr, unsigned char val) -{ - unsigned long flags; - - spin_lock_irqsave(&index_access_lock, flags); - outb((addr & 0xff00) >> 8, EC_IO_PORT_HIGH); - outb((addr & 0x00ff), EC_IO_PORT_LOW); - outb(val, EC_IO_PORT_DATA); - /* flush the write action */ - inb(EC_IO_PORT_DATA); - spin_unlock_irqrestore(&index_access_lock, flags); - - return; -} -EXPORT_SYMBOL_GPL(ec_write); - -/* - * This function is used for EC command writes and corresponding status queries. - */ -int ec_query_seq(unsigned char cmd) -{ - int timeout; - unsigned char status; - unsigned long flags; - int ret = 0; - - spin_lock_irqsave(&port_access_lock, flags); - - /* make chip goto reset mode */ - udelay(EC_REG_DELAY); - outb(cmd, EC_CMD_PORT); - udelay(EC_REG_DELAY); - - /* check if the command is received by ec */ - timeout = EC_CMD_TIMEOUT; - status = inb(EC_STS_PORT); - while (timeout-- && (status & (1 << 1))) { - status = inb(EC_STS_PORT); - udelay(EC_REG_DELAY); - } - - if (timeout <= 0) { - printk(KERN_ERR "%s: deadable error : timeout...\n", __func__); - ret = -EINVAL; - } else - printk(KERN_INFO - "(%x/%d)ec issued command %d status : 0x%x\n", - timeout, EC_CMD_TIMEOUT - timeout, cmd, status); - - spin_unlock_irqrestore(&port_access_lock, flags); - - return ret; -} -EXPORT_SYMBOL_GPL(ec_query_seq); - -/* - * Send query command to EC to get the proper event number - */ -int ec_query_event_num(void) -{ - return ec_query_seq(CMD_GET_EVENT_NUM); -} -EXPORT_SYMBOL(ec_query_event_num); - -/* - * Get event number from EC - * - * NOTE: This routine must follow the query_event_num function in the - * interrupt. - */ -int ec_get_event_num(void) -{ - int timeout = 100; - unsigned char value; - unsigned char status; - - udelay(EC_REG_DELAY); - status = inb(EC_STS_PORT); - udelay(EC_REG_DELAY); - while (timeout-- && !(status & (1 << 0))) { - status = inb(EC_STS_PORT); - udelay(EC_REG_DELAY); - } - if (timeout <= 0) { - pr_info("%s: get event number timeout.\n", __func__); - - return -EINVAL; - } - value = inb(EC_DAT_PORT); - udelay(EC_REG_DELAY); - - return value; -} -EXPORT_SYMBOL(ec_get_event_num); diff --git a/trunk/arch/mips/loongson/lemote-2f/ec_kb3310b.h b/trunk/arch/mips/loongson/lemote-2f/ec_kb3310b.h deleted file mode 100644 index 1595a21b315b..000000000000 --- a/trunk/arch/mips/loongson/lemote-2f/ec_kb3310b.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * KB3310B Embedded Controller - * - * Copyright (C) 2008 Lemote Inc. - * Author: liujl , 2008-03-14 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef _EC_KB3310B_H -#define _EC_KB3310B_H - -extern unsigned char ec_read(unsigned short addr); -extern void ec_write(unsigned short addr, unsigned char val); -extern int ec_query_seq(unsigned char cmd); -extern int ec_query_event_num(void); -extern int ec_get_event_num(void); - -typedef int (*sci_handler) (int status); -extern sci_handler yeeloong_report_lid_status; - -#define SCI_IRQ_NUM 0x0A - -/* - * The following registers are determined by the EC index configuration. - * 1, fill the PORT_HIGH as EC register high part. - * 2, fill the PORT_LOW as EC register low part. - * 3, fill the PORT_DATA as EC register write data or get the data from it. - */ -#define EC_IO_PORT_HIGH 0x0381 -#define EC_IO_PORT_LOW 0x0382 -#define EC_IO_PORT_DATA 0x0383 - -/* - * EC delay time is 500us for register and status access - */ -#define EC_REG_DELAY 500 /* unit : us */ -#define EC_CMD_TIMEOUT 0x1000 - -/* - * EC access port for SCI communication - */ -#define EC_CMD_PORT 0x66 -#define EC_STS_PORT 0x66 -#define EC_DAT_PORT 0x62 -#define CMD_INIT_IDLE_MODE 0xdd -#define CMD_EXIT_IDLE_MODE 0xdf -#define CMD_INIT_RESET_MODE 0xd8 -#define CMD_REBOOT_SYSTEM 0x8c -#define CMD_GET_EVENT_NUM 0x84 -#define CMD_PROGRAM_PIECE 0xda - -/* temperature & fan registers */ -#define REG_TEMPERATURE_VALUE 0xF458 -#define REG_FAN_AUTO_MAN_SWITCH 0xF459 -#define BIT_FAN_AUTO 0 -#define BIT_FAN_MANUAL 1 -#define REG_FAN_CONTROL 0xF4D2 -#define BIT_FAN_CONTROL_ON (1 << 0) -#define BIT_FAN_CONTROL_OFF (0 << 0) -#define REG_FAN_STATUS 0xF4DA -#define BIT_FAN_STATUS_ON (1 << 0) -#define BIT_FAN_STATUS_OFF (0 << 0) -#define REG_FAN_SPEED_HIGH 0xFE22 -#define REG_FAN_SPEED_LOW 0xFE23 -#define REG_FAN_SPEED_LEVEL 0xF4CC -/* fan speed divider */ -#define FAN_SPEED_DIVIDER 480000 /* (60*1000*1000/62.5/2)*/ - -/* battery registers */ -#define REG_BAT_DESIGN_CAP_HIGH 0xF77D -#define REG_BAT_DESIGN_CAP_LOW 0xF77E -#define REG_BAT_FULLCHG_CAP_HIGH 0xF780 -#define REG_BAT_FULLCHG_CAP_LOW 0xF781 -#define REG_BAT_DESIGN_VOL_HIGH 0xF782 -#define REG_BAT_DESIGN_VOL_LOW 0xF783 -#define REG_BAT_CURRENT_HIGH 0xF784 -#define REG_BAT_CURRENT_LOW 0xF785 -#define REG_BAT_VOLTAGE_HIGH 0xF786 -#define REG_BAT_VOLTAGE_LOW 0xF787 -#define REG_BAT_TEMPERATURE_HIGH 0xF788 -#define REG_BAT_TEMPERATURE_LOW 0xF789 -#define REG_BAT_RELATIVE_CAP_HIGH 0xF492 -#define REG_BAT_RELATIVE_CAP_LOW 0xF493 -#define REG_BAT_VENDOR 0xF4C4 -#define FLAG_BAT_VENDOR_SANYO 0x01 -#define FLAG_BAT_VENDOR_SIMPLO 0x02 -#define REG_BAT_CELL_COUNT 0xF4C6 -#define FLAG_BAT_CELL_3S1P 0x03 -#define FLAG_BAT_CELL_3S2P 0x06 -#define REG_BAT_CHARGE 0xF4A2 -#define FLAG_BAT_CHARGE_DISCHARGE 0x01 -#define FLAG_BAT_CHARGE_CHARGE 0x02 -#define FLAG_BAT_CHARGE_ACPOWER 0x00 -#define REG_BAT_STATUS 0xF4B0 -#define BIT_BAT_STATUS_LOW (1 << 5) -#define BIT_BAT_STATUS_DESTROY (1 << 2) -#define BIT_BAT_STATUS_FULL (1 << 1) -#define BIT_BAT_STATUS_IN (1 << 0) -#define REG_BAT_CHARGE_STATUS 0xF4B1 -#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2) -#define BIT_BAT_CHARGE_STATUS_PRECHG (1 << 1) -#define REG_BAT_STATE 0xF482 -#define BIT_BAT_STATE_CHARGING (1 << 1) -#define BIT_BAT_STATE_DISCHARGING (1 << 0) -#define REG_BAT_POWER 0xF440 -#define BIT_BAT_POWER_S3 (1 << 2) -#define BIT_BAT_POWER_ON (1 << 1) -#define BIT_BAT_POWER_ACIN (1 << 0) - -/* other registers */ -/* Audio: rd/wr */ -#define REG_AUDIO_VOLUME 0xF46C -#define REG_AUDIO_MUTE 0xF4E7 -#define REG_AUDIO_BEEP 0xF4D0 -/* USB port power or not: rd/wr */ -#define REG_USB0_FLAG 0xF461 -#define REG_USB1_FLAG 0xF462 -#define REG_USB2_FLAG 0xF463 -#define BIT_USB_FLAG_ON 1 -#define BIT_USB_FLAG_OFF 0 -/* LID */ -#define REG_LID_DETECT 0xF4BD -#define BIT_LID_DETECT_ON 1 -#define BIT_LID_DETECT_OFF 0 -/* CRT */ -#define REG_CRT_DETECT 0xF4AD -#define BIT_CRT_DETECT_PLUG 1 -#define BIT_CRT_DETECT_UNPLUG 0 -/* LCD backlight brightness adjust: 9 levels */ -#define REG_DISPLAY_BRIGHTNESS 0xF4F5 -/* Black screen Status */ -#define BIT_DISPLAY_LCD_ON 1 -#define BIT_DISPLAY_LCD_OFF 0 -/* LCD backlight control: off/restore */ -#define REG_BACKLIGHT_CTRL 0xF7BD -#define BIT_BACKLIGHT_ON 1 -#define BIT_BACKLIGHT_OFF 0 -/* Reset the machine auto-clear: rd/wr */ -#define REG_RESET 0xF4EC -#define BIT_RESET_ON 1 -/* Light the led: rd/wr */ -#define REG_LED 0xF4C8 -#define BIT_LED_RED_POWER (1 << 0) -#define BIT_LED_ORANGE_POWER (1 << 1) -#define BIT_LED_GREEN_CHARGE (1 << 2) -#define BIT_LED_RED_CHARGE (1 << 3) -#define BIT_LED_NUMLOCK (1 << 4) -/* Test led mode, all led on/off */ -#define REG_LED_TEST 0xF4C2 -#define BIT_LED_TEST_IN 1 -#define BIT_LED_TEST_OUT 0 -/* Camera on/off */ -#define REG_CAMERA_STATUS 0xF46A -#define BIT_CAMERA_STATUS_ON 1 -#define BIT_CAMERA_STATUS_OFF 0 -#define REG_CAMERA_CONTROL 0xF7B7 -#define BIT_CAMERA_CONTROL_OFF 0 -#define BIT_CAMERA_CONTROL_ON 1 -/* Wlan Status */ -#define REG_WLAN 0xF4FA -#define BIT_WLAN_ON 1 -#define BIT_WLAN_OFF 0 -#define REG_DISPLAY_LCD 0xF79F - -/* SCI Event Number from EC */ -enum { - EVENT_LID = 0x23, /* LID open/close */ - EVENT_DISPLAY_TOGGLE, /* Fn+F3 for display switch */ - EVENT_SLEEP, /* Fn+F1 for entering sleep mode */ - EVENT_OVERTEMP, /* Over-temperature happened */ - EVENT_CRT_DETECT, /* CRT is connected */ - EVENT_CAMERA, /* Camera on/off */ - EVENT_USB_OC2, /* USB2 Over Current occurred */ - EVENT_USB_OC0, /* USB0 Over Current occurred */ - EVENT_BLACK_SCREEN, /* Turn on/off backlight */ - EVENT_AUDIO_MUTE, /* Mute on/off */ - EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */ - EVENT_AC_BAT, /* AC & Battery relative issue */ - EVENT_AUDIO_VOLUME, /* Volume adjust */ - EVENT_WLAN, /* Wlan on/off */ - EVENT_END -}; - -#endif /* !_EC_KB3310B_H */ diff --git a/trunk/arch/mips/loongson/lemote-2f/irq.c b/trunk/arch/mips/loongson/lemote-2f/irq.c deleted file mode 100644 index 77d32f9cf31e..000000000000 --- a/trunk/arch/mips/loongson/lemote-2f/irq.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (C) 2007 Lemote Inc. - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -#include -#include -#include - -#include -#include - -#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ -#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ -#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ -#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ -#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ - -#define LOONGSON_INT_BIT_INT0 (1 << 11) -#define LOONGSON_INT_BIT_INT1 (1 << 12) - -/* - * The generic i8259_irq() make the kernel hang on booting. Since we cannot - * get the irq via the IRR directly, we access the ISR instead. - */ -int mach_i8259_irq(void) -{ - int irq, isr; - - irq = -1; - - if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { - spin_lock(&i8259A_lock); - isr = inb(PIC_MASTER_CMD) & - ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR); - if (!isr) - isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8; - irq = ffs(isr) - 1; - if (unlikely(irq == 7)) { - /* - * This may be a spurious interrupt. - * - * Read the interrupt status register (ISR). If the most - * significant bit is not set then there is no valid - * interrupt. - */ - outb(0x0B, PIC_MASTER_ISR); /* ISR register */ - if (~inb(PIC_MASTER_ISR) & 0x80) - irq = -1; - } - spin_unlock(&i8259A_lock); - } - - return irq; -} -EXPORT_SYMBOL(mach_i8259_irq); - -static void i8259_irqdispatch(void) -{ - int irq; - - irq = mach_i8259_irq(); - if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); -} - -void mach_irq_dispatch(unsigned int pending) -{ - if (pending & CAUSEF_IP7) - do_IRQ(LOONGSON_TIMER_IRQ); - else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */ -#ifdef CONFIG_OPROFILE - do_IRQ(LOONGSON2_PERFCNT_IRQ); -#endif - bonito_irqdispatch(); - } else if (pending & CAUSEF_IP3) /* CPU UART */ - do_IRQ(LOONGSON_UART_IRQ); - else if (pending & CAUSEF_IP2) /* South Bridge */ - i8259_irqdispatch(); - else - spurious_interrupt(); -} - -void __init set_irq_trigger_mode(void) -{ - /* setup cs5536 as high level trigger */ - LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; - LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); -} - -static irqreturn_t ip6_action(int cpl, void *dev_id) -{ - return IRQ_HANDLED; -} - -struct irqaction ip6_irqaction = { - .handler = ip6_action, - .name = "cascade", - .flags = IRQF_SHARED, -}; - -struct irqaction cascade_irqaction = { - .handler = no_action, - .name = "cascade", -}; - -void __init mach_init_irq(void) -{ - /* init all controller - * 0-15 ------> i8259 interrupt - * 16-23 ------> mips cpu interrupt - * 32-63 ------> bonito irq - */ - - /* Sets the first-level interrupt dispatcher. */ - mips_cpu_irq_init(); - init_i8259_irqs(); - bonito_irq_init(); - - /* setup north bridge irq (bonito) */ - setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); - /* setup source bridge irq (i8259) */ - setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); -} diff --git a/trunk/arch/mips/loongson/lemote-2f/pm.c b/trunk/arch/mips/loongson/lemote-2f/pm.c deleted file mode 100644 index d7af2e616592..000000000000 --- a/trunk/arch/mips/loongson/lemote-2f/pm.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Lemote loongson2f family machines' specific suspend support - * - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include -#include "ec_kb3310b.h" - -#define I8042_KBD_IRQ 1 -#define I8042_CTR_KBDINT 0x01 -#define I8042_CTR_KBDDIS 0x10 - -static unsigned char i8042_ctr; - -static int i8042_enable_kbd_port(void) -{ - if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { - pr_err("i8042.c: Can't read CTR while enabling i8042 kbd port." - "\n"); - return -EIO; - } - - i8042_ctr &= ~I8042_CTR_KBDDIS; - i8042_ctr |= I8042_CTR_KBDINT; - - if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { - i8042_ctr &= ~I8042_CTR_KBDINT; - i8042_ctr |= I8042_CTR_KBDDIS; - pr_err("i8042.c: Failed to enable KBD port.\n"); - - return -EIO; - } - - return 0; -} - -void setup_wakeup_events(void) -{ - int irq_mask; - - switch (mips_machtype) { - case MACH_LEMOTE_ML2F7: - case MACH_LEMOTE_YL2F89: - /* open the keyboard irq in i8259A */ - outb((0xff & ~(1 << I8042_KBD_IRQ)), PIC_MASTER_IMR); - irq_mask = inb(PIC_MASTER_IMR); - - /* enable keyboard port */ - i8042_enable_kbd_port(); - - /* Wakeup CPU via SCI lid open event */ - outb(irq_mask & ~(1 << PIC_CASCADE_IR), PIC_MASTER_IMR); - inb(PIC_MASTER_IMR); - outb(0xff & ~(1 << (SCI_IRQ_NUM - 8)), PIC_SLAVE_IMR); - inb(PIC_SLAVE_IMR); - - break; - - default: - break; - } -} - -static struct delayed_work lid_task; -static int initialized; -/* yeeloong_report_lid_status will be implemented in yeeloong_laptop.c */ -sci_handler yeeloong_report_lid_status; -EXPORT_SYMBOL(yeeloong_report_lid_status); -static void yeeloong_lid_update_task(struct work_struct *work) -{ - if (yeeloong_report_lid_status) - yeeloong_report_lid_status(BIT_LID_DETECT_ON); -} - -int wakeup_loongson(void) -{ - int irq; - - /* query the interrupt number */ - irq = mach_i8259_irq(); - if (irq < 0) - return 0; - - printk(KERN_INFO "%s: irq = %d\n", __func__, irq); - - if (irq == I8042_KBD_IRQ) - return 1; - else if (irq == SCI_IRQ_NUM) { - int ret, sci_event; - /* query the event number */ - ret = ec_query_seq(CMD_GET_EVENT_NUM); - if (ret < 0) - return 0; - sci_event = ec_get_event_num(); - if (sci_event < 0) - return 0; - if (sci_event == EVENT_LID) { - int lid_status; - /* check the LID status */ - lid_status = ec_read(REG_LID_DETECT); - /* wakeup cpu when people open the LID */ - if (lid_status == BIT_LID_DETECT_ON) { - /* If we call it directly here, the WARNING - * will be sent out by getnstimeofday - * via "WARN_ON(timekeeping_suspended);" - * because we can not schedule in suspend mode. - */ - if (initialized == 0) { - INIT_DELAYED_WORK(&lid_task, - yeeloong_lid_update_task); - initialized = 1; - } - schedule_delayed_work(&lid_task, 1); - return 1; - } - } - } - - return 0; -} - -void __weak mach_suspend(void) -{ - disable_mfgpt0_counter(); -} - -void __weak mach_resume(void) -{ - enable_mfgpt0_counter(); -} diff --git a/trunk/arch/mips/loongson/lemote-2f/reset.c b/trunk/arch/mips/loongson/lemote-2f/reset.c deleted file mode 100644 index 51d1a60d5349..000000000000 --- a/trunk/arch/mips/loongson/lemote-2f/reset.c +++ /dev/null @@ -1,159 +0,0 @@ -/* Board-specific reboot/shutdown routines - * - * Copyright (c) 2009 Philippe Vachon - * - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include - -#include - -#include - -#include -#include "ec_kb3310b.h" - -static void reset_cpu(void) -{ - /* - * reset cpu to full speed, this is needed when enabling cpu frequency - * scalling - */ - LOONGSON_CHIPCFG0 |= 0x7; -} - -/* reset support for fuloong2f */ - -static void fl2f_reboot(void) -{ - reset_cpu(); - - /* send a reset signal to south bridge. - * - * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset - * normally with this reset operation and it will not work in PMON, but - * you can type halt command and then reboot, seems the hardware reset - * logic not work normally. - */ - { - u32 hi, lo; - _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); - lo |= 0x00000001; - _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); - } -} - -static void fl2f_shutdown(void) -{ - u32 hi, lo, val; - int gpio_base; - - /* get gpio base */ - _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); - gpio_base = lo & 0xff00; - - /* make cs5536 gpio13 output enable */ - val = inl(gpio_base + GPIOL_OUT_EN); - val &= ~(1 << (16 + 13)); - val |= (1 << 13); - outl(val, gpio_base + GPIOL_OUT_EN); - mmiowb(); - /* make cs5536 gpio13 output low level voltage. */ - val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13)); - val |= (1 << (16 + 13)); - outl(val, gpio_base + GPIOL_OUT_VAL); - mmiowb(); -} - -/* reset support for yeeloong2f and mengloong2f notebook */ - -void ml2f_reboot(void) -{ - reset_cpu(); - - /* sending an reset signal to EC(embedded controller) */ - ec_write(REG_RESET, BIT_RESET_ON); -} - -#define yl2f89_reboot ml2f_reboot - -/* menglong(7inches) laptop has different shutdown logic from 8.9inches */ -#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d -#define EC_SHUTDOWN_IO_PORT_LOW 0xff2e -#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f -#define REG_SHUTDOWN_HIGH 0xFC -#define REG_SHUTDOWN_LOW 0x29 -#define BIT_SHUTDOWN_ON (1 << 1) - -static void ml2f_shutdown(void) -{ - u8 val; - u64 i; - - outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH); - outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW); - mmiowb(); - val = inb(EC_SHUTDOWN_IO_PORT_DATA); - outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA); - mmiowb(); - /* need enough wait here... how many microseconds needs? */ - for (i = 0; i < 0x10000; i++) - delay(); - outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA); - mmiowb(); -} - -static void yl2f89_shutdown(void) -{ - /* cpu-gpio0 output low */ - LOONGSON_GPIODATA &= ~0x00000001; - /* cpu-gpio0 as output */ - LOONGSON_GPIOIE &= ~0x00000001; -} - -void mach_prepare_reboot(void) -{ - switch (mips_machtype) { - case MACH_LEMOTE_FL2F: - case MACH_LEMOTE_NAS: - case MACH_LEMOTE_LL2F: - fl2f_reboot(); - break; - case MACH_LEMOTE_ML2F7: - ml2f_reboot(); - break; - case MACH_LEMOTE_YL2F89: - yl2f89_reboot(); - break; - default: - break; - } -} - -void mach_prepare_shutdown(void) -{ - switch (mips_machtype) { - case MACH_LEMOTE_FL2F: - case MACH_LEMOTE_NAS: - case MACH_LEMOTE_LL2F: - fl2f_shutdown(); - break; - case MACH_LEMOTE_ML2F7: - ml2f_shutdown(); - break; - case MACH_LEMOTE_YL2F89: - yl2f89_shutdown(); - break; - default: - break; - } -} diff --git a/trunk/arch/mips/math-emu/cp1emu.c b/trunk/arch/mips/math-emu/cp1emu.c index 8f2f8e9d8b21..454b53924490 100644 --- a/trunk/arch/mips/math-emu/cp1emu.c +++ b/trunk/arch/mips/math-emu/cp1emu.c @@ -35,7 +35,6 @@ * better performance by compiling with -msoft-float! */ #include -#include #include #include @@ -69,9 +68,7 @@ static int fpux_emu(struct pt_regs *, /* Further private data for which no space exists in mips_fpu_struct */ -#ifdef CONFIG_DEBUG_FS -DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); -#endif +struct mips_fpu_emulator_stats fpuemustats; /* Control registers */ @@ -212,7 +209,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) unsigned int cond; if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } @@ -243,7 +240,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) return SIGILL; } if (get_user(ir, (mips_instruction __user *) emulpc)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } /* __compute_return_epc() will have updated cp0_epc */ @@ -256,16 +253,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) } emul: - MIPS_FPU_EMU_INC_STATS(emulated); + fpuemustats.emulated++; switch (MIPSInst_OPCODE(ir)) { case ldc1_op:{ u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u64 val; - MIPS_FPU_EMU_INC_STATS(loads); + fpuemustats.loads++; if (get_user(val, va)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_RT(ir)); @@ -277,10 +274,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u64 val; - MIPS_FPU_EMU_INC_STATS(stores); + fpuemustats.stores++; DIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } break; @@ -291,9 +288,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u32 val; - MIPS_FPU_EMU_INC_STATS(loads); + fpuemustats.loads++; if (get_user(val, va)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } SITOREG(val, MIPSInst_RT(ir)); @@ -305,10 +302,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u32 val; - MIPS_FPU_EMU_INC_STATS(stores); + fpuemustats.stores++; SIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } break; @@ -432,7 +429,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } @@ -598,7 +595,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, { unsigned rcsr = 0; /* resulting csr */ - MIPS_FPU_EMU_INC_STATS(cp1xops); + fpuemustats.cp1xops++; switch (MIPSInst_FMA_FFMT(ir)) { case s_fmt:{ /* 0 */ @@ -613,9 +610,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - MIPS_FPU_EMU_INC_STATS(loads); + fpuemustats.loads++; if (get_user(val, va)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } SITOREG(val, MIPSInst_FD(ir)); @@ -625,11 +622,11 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - MIPS_FPU_EMU_INC_STATS(stores); + fpuemustats.stores++; SIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } break; @@ -690,9 +687,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - MIPS_FPU_EMU_INC_STATS(loads); + fpuemustats.loads++; if (get_user(val, va)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } DITOREG(val, MIPSInst_FD(ir)); @@ -702,10 +699,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - MIPS_FPU_EMU_INC_STATS(stores); + fpuemustats.stores++; DIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } break; @@ -772,7 +769,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, #endif } rv; /* resulting value */ - MIPS_FPU_EMU_INC_STATS(cp1ops); + fpuemustats.cp1ops++; switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { case s_fmt:{ /* 0 */ union { @@ -1243,7 +1240,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, prevepc = xcp->cp0_epc; if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } if (insn == 0) @@ -1279,50 +1276,33 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, } #ifdef CONFIG_DEBUG_FS - -static int fpuemu_stat_get(void *data, u64 *val) -{ - int cpu; - unsigned long sum = 0; - for_each_online_cpu(cpu) { - struct mips_fpu_emulator_stats *ps; - local_t *pv; - ps = &per_cpu(fpuemustats, cpu); - pv = (void *)ps + (unsigned long)data; - sum += local_read(pv); - } - *val = sum; - return 0; -} -DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n"); - extern struct dentry *mips_debugfs_dir; static int __init debugfs_fpuemu(void) { struct dentry *d, *dir; + int i; + static struct { + const char *name; + unsigned int *v; + } vars[] __initdata = { + { "emulated", &fpuemustats.emulated }, + { "loads", &fpuemustats.loads }, + { "stores", &fpuemustats.stores }, + { "cp1ops", &fpuemustats.cp1ops }, + { "cp1xops", &fpuemustats.cp1xops }, + { "errors", &fpuemustats.errors }, + }; if (!mips_debugfs_dir) return -ENODEV; dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); if (!dir) return -ENOMEM; - -#define FPU_STAT_CREATE(M) \ - do { \ - d = debugfs_create_file(#M , S_IRUGO, dir, \ - (void *)offsetof(struct mips_fpu_emulator_stats, M), \ - &fops_fpuemu_stat); \ - if (!d) \ - return -ENOMEM; \ - } while (0) - - FPU_STAT_CREATE(emulated); - FPU_STAT_CREATE(loads); - FPU_STAT_CREATE(stores); - FPU_STAT_CREATE(cp1ops); - FPU_STAT_CREATE(cp1xops); - FPU_STAT_CREATE(errors); - + for (i = 0; i < ARRAY_SIZE(vars); i++) { + d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v); + if (!d) + return -ENOMEM; + } return 0; } __initcall(debugfs_fpuemu); diff --git a/trunk/arch/mips/math-emu/dsemul.c b/trunk/arch/mips/math-emu/dsemul.c index 36d975ae08f8..df7b9d928efc 100644 --- a/trunk/arch/mips/math-emu/dsemul.c +++ b/trunk/arch/mips/math-emu/dsemul.c @@ -98,7 +98,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) err |= __put_user(cpc, &fr->epc); if (unlikely(err)) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return SIGBUS; } @@ -136,7 +136,7 @@ int do_dsemulret(struct pt_regs *xcp) err |= __get_user(cookie, &fr->cookie); if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { - MIPS_FPU_EMU_INC_STATS(errors); + fpuemustats.errors++; return 0; } diff --git a/trunk/arch/mips/mipssim/Makefile b/trunk/arch/mips/mipssim/Makefile index 41b96571315e..57f43c1c7882 100644 --- a/trunk/arch/mips/mipssim/Makefile +++ b/trunk/arch/mips/mipssim/Makefile @@ -17,7 +17,8 @@ # 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. # -obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o +obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \ + sim_cmdline.o obj-$(CONFIG_EARLY_PRINTK) += sim_console.o obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o diff --git a/trunk/arch/mips/powertv/time.c b/trunk/arch/mips/mipssim/sim_cmdline.c similarity index 60% rename from trunk/arch/mips/powertv/time.c rename to trunk/arch/mips/mipssim/sim_cmdline.c index 1e0a5ef4c8c7..74240e1ce5a5 100644 --- a/trunk/arch/mips/powertv/time.c +++ b/trunk/arch/mips/mipssim/sim_cmdline.c @@ -1,7 +1,5 @@ /* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -16,22 +14,19 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * Setting up the clock on the MIPS boards. */ - #include -#include -#include +#include +#include -#include "powertv-clock.h" +extern char arcs_cmdline[]; -unsigned int __cpuinit get_c0_compare_int(void) +char * __init prom_getcmdline(void) { - return irq_mips_timer; + return arcs_cmdline; } -void __init plat_time_init(void) +void __init prom_init_cmdline(void) { - powertv_clocksource_init(); - r4k_clockevent_init(); + /* XXX: Get boot line from environment? */ } diff --git a/trunk/arch/mips/mipssim/sim_setup.c b/trunk/arch/mips/mipssim/sim_setup.c index 0824f6af4777..2877675c5f0d 100644 --- a/trunk/arch/mips/mipssim/sim_setup.c +++ b/trunk/arch/mips/mipssim/sim_setup.c @@ -61,6 +61,7 @@ void __init prom_init(void) set_io_port_base(0xbfd00000); pr_info("\nLINUX started...\n"); + prom_init_cmdline(); prom_meminit(); #ifdef CONFIG_MIPS_MT_SMP diff --git a/trunk/arch/mips/mm/cerr-sb1.c b/trunk/arch/mips/mm/cerr-sb1.c index 3571090ba178..1bd1f18ac23c 100644 --- a/trunk/arch/mips/mm/cerr-sb1.c +++ b/trunk/arch/mips/mm/cerr-sb1.c @@ -567,10 +567,13 @@ static uint32_t extract_dc(unsigned short addr, int data) datalo = ((unsigned long long)datalohi << 32) | datalolo; ecc = dc_ecc(datalo); if (ecc != datahi) { - int bits; + int bits = 0; bad_ecc |= 1 << (3-offset); ecc ^= datahi; - bits = hweight8(ecc); + while (ecc) { + if (ecc & 1) bits++; + ecc >>= 1; + } res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; } printk(" %02X-%016llX", datahi, datalo); diff --git a/trunk/arch/mips/mm/init.c b/trunk/arch/mips/mm/init.c index 9e8d00389eef..8d1f4f363049 100644 --- a/trunk/arch/mips/mm/init.c +++ b/trunk/arch/mips/mm/init.c @@ -462,9 +462,7 @@ void __init_refok free_initmem(void) __pa_symbol(&__init_end)); } -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT unsigned long pgd_current[NR_CPUS]; -#endif /* * On 64-bit we've got three-level pagetables with a slightly * different layout ... diff --git a/trunk/arch/mips/mm/tlbex.c b/trunk/arch/mips/mm/tlbex.c index 3d0baa4a842d..bb1719a55d22 100644 --- a/trunk/arch/mips/mm/tlbex.c +++ b/trunk/arch/mips/mm/tlbex.c @@ -160,12 +160,6 @@ static u32 tlb_handler[128] __cpuinitdata; static struct uasm_label labels[128] __cpuinitdata; static struct uasm_reloc relocs[128] __cpuinitdata; -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT -/* - * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, - * we cannot do r3000 under these circumstances. - */ - /* * The R3000 TLB handler is simple. */ @@ -205,7 +199,6 @@ static void __cpuinit build_r3000_tlb_refill_handler(void) dump_handler((u32 *)ebase, 32); } -#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ /* * The R4000 TLB handler is much more complicated. We have two @@ -504,9 +497,8 @@ static void __cpuinit build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, unsigned int tmp, unsigned int ptr) { -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT long pgdc = (long)pgd_current; -#endif + /* * The vmalloc handling is not in the hotpath. */ @@ -514,15 +506,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, uasm_il_bltz(p, r, tmp, label_vmalloc); /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ -#ifdef CONFIG_MIPS_PGD_C0_CONTEXT - /* - * &pgd << 11 stored in CONTEXT [23..63]. - */ - UASM_i_MFC0(p, ptr, C0_CONTEXT); - uasm_i_dins(p, ptr, 0, 0, 23); /* Clear lower 23 bits of context. */ - uasm_i_ori(p, ptr, ptr, 0x540); /* 1 0 1 0 1 << 6 xkphys cached */ - uasm_i_drotr(p, ptr, ptr, 11); -#elif defined(CONFIG_SMP) +#ifdef CONFIG_SMP # ifdef CONFIG_MIPS_MT_SMTC /* * SMTC uses TCBind value as "CPU" index @@ -536,7 +520,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, */ uasm_i_dmfc0(p, ptr, C0_CONTEXT); uasm_i_dsrl(p, ptr, ptr, 23); -# endif +#endif UASM_i_LA_mostly(p, tmp, pgdc); uasm_i_daddu(p, ptr, ptr, tmp); uasm_i_dmfc0(p, tmp, C0_BADVADDR); @@ -1049,7 +1033,6 @@ build_pte_modifiable(u32 **p, struct uasm_reloc **r, iPTE_LW(p, pte, ptr); } -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT /* * R3000 style TLB load/store/modify handlers. */ @@ -1201,7 +1184,6 @@ static void __cpuinit build_r3000_tlb_modify_handler(void) dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); } -#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ /* * R4000 style TLB load/store/modify handlers. @@ -1418,7 +1400,6 @@ void __cpuinit build_tlb_refill_handler(void) case CPU_TX3912: case CPU_TX3922: case CPU_TX3927: -#ifndef CONFIG_MIPS_PGD_C0_CONTEXT build_r3000_tlb_refill_handler(); if (!run_once) { build_r3000_tlb_load_handler(); @@ -1426,9 +1407,6 @@ void __cpuinit build_tlb_refill_handler(void) build_r3000_tlb_modify_handler(); run_once++; } -#else - panic("No R3000 TLB refill handler"); -#endif break; case CPU_R6000: diff --git a/trunk/arch/mips/mm/uasm.c b/trunk/arch/mips/mm/uasm.c index 0a165c5179a1..f467199676a8 100644 --- a/trunk/arch/mips/mm/uasm.c +++ b/trunk/arch/mips/mm/uasm.c @@ -60,11 +60,11 @@ enum opcode { insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl, insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0, insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl, - insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, - insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, + insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, + insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, - insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins + insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori }; struct insn { @@ -104,7 +104,6 @@ static struct insn insn_table[] __cpuinitdata = { { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE }, { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE }, { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE }, - { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE }, { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD }, { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 }, { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, @@ -133,7 +132,6 @@ static struct insn insn_table[] __cpuinitdata = { { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, - { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, { insn_invalid, 0, 0 } }; @@ -306,12 +304,6 @@ Ip_u2u1s3(op) \ build_insn(buf, insn##op, b, a, c); \ } -#define I_u2u1msbu3(op) \ -Ip_u2u1msbu3(op) \ -{ \ - build_insn(buf, insn##op, b, a, c+d-1, c); \ -} - #define I_u1u2(op) \ Ip_u1u2(op) \ { \ @@ -357,7 +349,6 @@ I_u2u1u3(_dsll32) I_u2u1u3(_dsra) I_u2u1u3(_dsrl) I_u2u1u3(_dsrl32) -I_u2u1u3(_drotr) I_u3u1u2(_dsubu) I_0(_eret) I_u1(_j) @@ -386,7 +377,6 @@ I_0(_tlbwi) I_0(_tlbwr) I_u3u1u2(_xor) I_u2u1u3(_xori) -I_u2u1msbu3(_dins); /* Handle labels. */ void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) diff --git a/trunk/arch/mips/mm/uasm.h b/trunk/arch/mips/mm/uasm.h index 3d153edaa51e..c6d1e3dd82d4 100644 --- a/trunk/arch/mips/mm/uasm.h +++ b/trunk/arch/mips/mm/uasm.h @@ -34,11 +34,6 @@ uasm_i##op(u32 **buf, unsigned int a, signed int b, unsigned int c) void __cpuinit \ uasm_i##op(u32 **buf, unsigned int a, unsigned int b, signed int c) -#define Ip_u2u1msbu3(op) \ -void __cpuinit \ -uasm_i##op(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \ - unsigned int d) - #define Ip_u1u2(op) \ void __cpuinit uasm_i##op(u32 **buf, unsigned int a, unsigned int b) @@ -70,7 +65,6 @@ Ip_u2u1u3(_dsll32); Ip_u2u1u3(_dsra); Ip_u2u1u3(_dsrl); Ip_u2u1u3(_dsrl32); -Ip_u2u1u3(_drotr); Ip_u3u1u2(_dsubu); Ip_0(_eret); Ip_u1(_j); @@ -99,7 +93,6 @@ Ip_0(_tlbwi); Ip_0(_tlbwr); Ip_u3u1u2(_xor); Ip_u2u1u3(_xori); -Ip_u2u1msbu3(_dins); /* Handle labels. */ struct uasm_label { diff --git a/trunk/arch/mips/mti-malta/malta-memory.c b/trunk/arch/mips/mti-malta/malta-memory.c index b27419c84919..9035c64bc5ed 100644 --- a/trunk/arch/mips/mti-malta/malta-memory.c +++ b/trunk/arch/mips/mti-malta/malta-memory.c @@ -55,7 +55,7 @@ static struct prom_pmemblock * __init prom_getmdesc(void) char *memsize_str; unsigned int memsize; char *ptr; - static char cmdline[COMMAND_LINE_SIZE] __initdata; + static char cmdline[CL_SIZE] __initdata; /* otherwise look in the environment */ memsize_str = prom_getenv("memsize"); diff --git a/trunk/arch/mips/nxp/pnx833x/common/interrupts.c b/trunk/arch/mips/nxp/pnx833x/common/interrupts.c index 3a467c04f811..30533ba200e2 100644 --- a/trunk/arch/mips/nxp/pnx833x/common/interrupts.c +++ b/trunk/arch/mips/nxp/pnx833x/common/interrupts.c @@ -295,7 +295,7 @@ static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type) } static struct irq_chip pnx833x_pic_irq_type = { - .name = "PNX-PIC", + .typename = "PNX-PIC", .startup = pnx833x_startup_pic_irq, .shutdown = pnx833x_shutdown_pic_irq, .enable = pnx833x_enable_pic_irq, @@ -305,7 +305,7 @@ static struct irq_chip pnx833x_pic_irq_type = { }; static struct irq_chip pnx833x_gpio_irq_type = { - .name = "PNX-GPIO", + .typename = "PNX-GPIO", .startup = pnx833x_startup_gpio_irq, .shutdown = pnx833x_disable_gpio_irq, .enable = pnx833x_enable_gpio_irq, diff --git a/trunk/arch/mips/oprofile/op_model_loongson2.c b/trunk/arch/mips/oprofile/op_model_loongson2.c index 475ff46712ab..575cd1473475 100644 --- a/trunk/arch/mips/oprofile/op_model_loongson2.c +++ b/trunk/arch/mips/oprofile/op_model_loongson2.c @@ -1,7 +1,7 @@ /* * Loongson2 performance counter driver for oprofile * - * Copyright (C) 2009 Lemote Inc. + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology * Author: Yanhua * Author: Wu Zhangjin * @@ -125,9 +125,6 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) */ /* Check whether the irq belongs to me */ - enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; - if (!enabled) - return IRQ_NONE; enabled = reg.cnt1_enabled | reg.cnt2_enabled; if (!enabled) return IRQ_NONE; diff --git a/trunk/arch/mips/pci/Makefile b/trunk/arch/mips/pci/Makefile index c9209ca6c8e7..91bfe73a7f60 100644 --- a/trunk/arch/mips/pci/Makefile +++ b/trunk/arch/mips/pci/Makefile @@ -22,13 +22,13 @@ obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ # # These are still pretty much in the old state, watch, go blind. # +obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o -obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o -obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o +obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/trunk/arch/mips/pci/fixup-excite.c b/trunk/arch/mips/pci/fixup-excite.c new file mode 100644 index 000000000000..cd64d9f177c4 --- /dev/null +++ b/trunk/arch/mips/pci/fixup-excite.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if (pin == 0) + return -1; + + return USB_IRQ; /* USB controller is the only PCI device */ +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/trunk/arch/mips/pci/fixup-fuloong2e.c b/trunk/arch/mips/pci/fixup-fuloong2e.c index 4f6d8da07f93..0c4c7a81213f 100644 --- a/trunk/arch/mips/pci/fixup-fuloong2e.c +++ b/trunk/arch/mips/pci/fixup-fuloong2e.c @@ -13,8 +13,7 @@ */ #include #include - -#include +#include /* South bridge slot number is set by the pci probe process */ static u8 sb_slot = 5; @@ -36,7 +35,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) break; } } else { - irq = LOONGSON_IRQ_BASE + 25 + pin; + irq = BONITO_IRQ_BASE + 25 + pin; } return irq; diff --git a/trunk/arch/mips/pci/fixup-lemote2f.c b/trunk/arch/mips/pci/fixup-lemote2f.c deleted file mode 100644 index caf2edeb02f0..000000000000 --- a/trunk/arch/mips/pci/fixup-lemote2f.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (C) 2008 Lemote Technology - * Copyright (C) 2004 ICT CAS - * Author: Li xiaoyu, lixy@ict.ac.cn - * - * Copyright (C) 2007 Lemote, Inc. - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include - -#include -#include -#include - -/* PCI interrupt pins - * - * These should not be changed, or you should consider loongson2f interrupt - * register and your pci card dispatch - */ - -#define PCIA 4 -#define PCIB 5 -#define PCIC 6 -#define PCID 7 - -/* all the pci device has the PCIA pin, check the datasheet. */ -static char irq_tab[][5] __initdata = { - /* INTA INTB INTC INTD */ - {0, 0, 0, 0, 0}, /* 11: Unused */ - {0, 0, 0, 0, 0}, /* 12: Unused */ - {0, 0, 0, 0, 0}, /* 13: Unused */ - {0, 0, 0, 0, 0}, /* 14: Unused */ - {0, 0, 0, 0, 0}, /* 15: Unused */ - {0, 0, 0, 0, 0}, /* 16: Unused */ - {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */ - {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */ - {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */ - {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */ - {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */ - {0, 0, 0, 0, 0}, /* 22: Unused */ - {0, 0, 0, 0, 0}, /* 23: Unused */ - {0, 0, 0, 0, 0}, /* 24: Unused */ - {0, 0, 0, 0, 0}, /* 25: Unused */ - {0, 0, 0, 0, 0}, /* 26: Unused */ - {0, 0, 0, 0, 0}, /* 27: Unused */ -}; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int virq; - - if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536) - && (PCI_SLOT(dev->devfn) < 32)) { - virq = irq_tab[slot][pin]; - printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin, - virq + LOONGSON_IRQ_BASE); - if (virq != 0) - return LOONGSON_IRQ_BASE + virq; - else - return 0; - } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */ - switch (PCI_FUNC(dev->devfn)) { - case 2: - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, - CS5536_IDE_INTR); - return CS5536_IDE_INTR; /* for IDE */ - case 3: - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, - CS5536_ACC_INTR); - return CS5536_ACC_INTR; /* for AUDIO */ - case 4: /* for OHCI */ - case 5: /* for EHCI */ - case 6: /* for UDC */ - case 7: /* for OTG */ - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, - CS5536_USB_INTR); - return CS5536_USB_INTR; - } - return dev->irq; - } else { - printk(KERN_INFO " strange pci slot number.\n"); - return 0; - } -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -/* CS5536 SPEC. fixup */ -static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev) -{ - /* the uart1 and uart2 interrupt in PIC is enabled as default */ - pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1); - pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1); -} - -static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev) -{ - /* setting the mutex pin as IDE function */ - pci_write_config_dword(pdev, PCI_IDE_CFG_REG, - CS5536_IDE_FLASH_SIGNATURE); -} - -static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) -{ - /* enable the AUDIO interrupt in PIC */ - pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1); - - pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); -} - -static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev) -{ - /* enable the OHCI interrupt in PIC */ - /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ - pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1); -} - -static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) -{ - u32 hi, lo; - - /* Serial short detect enable */ - _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo); - _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo); - - /* setting the USB2.0 micro frame length */ - pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000); -} - -static void __init loongson_nec_fixup(struct pci_dev *pdev) -{ - unsigned int val; - - pci_read_config_dword(pdev, 0xe0, &val); - /* Only 2 port be used */ - pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2); -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, - loongson_cs5536_isa_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC, - loongson_cs5536_ohci_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC, - loongson_cs5536_ehci_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO, - loongson_cs5536_acc_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, - loongson_cs5536_ide_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, - loongson_nec_fixup); diff --git a/trunk/arch/mips/pci/ops-bonito64.c b/trunk/arch/mips/pci/ops-bonito64.c index 1b3e03f20c54..54e55e7a2431 100644 --- a/trunk/arch/mips/pci/ops-bonito64.c +++ b/trunk/arch/mips/pci/ops-bonito64.c @@ -29,8 +29,13 @@ #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 +#ifdef CONFIG_LEMOTE_FULOONG2E +#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset)) +#define ID_SEL_BEGIN 11 +#else #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) #define ID_SEL_BEGIN 10 +#endif #define MAX_DEV_NUM (31 - ID_SEL_BEGIN) @@ -72,8 +77,10 @@ static int bonito64_pcibios_config_access(unsigned char access_type, addrp = CFG_SPACE_REG(addr & 0xffff); if (access_type == PCI_ACCESS_WRITE) { writel(cpu_to_le32(*data), addrp); +#ifndef CONFIG_LEMOTE_FULOONG2E /* Wait till done */ while (BONITO_PCIMSTAT & 0xF); +#endif } else { *data = le32_to_cpu(readl(addrp)); } diff --git a/trunk/arch/mips/pci/ops-loongson2.c b/trunk/arch/mips/pci/ops-loongson2.c deleted file mode 100644 index aa5d3da27212..000000000000 --- a/trunk/arch/mips/pci/ops-loongson2.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * fuloong2e specific PCI support. - * - * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include - -#include - -#ifdef CONFIG_CS5536 -#include -#include -#endif - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -#define CFG_SPACE_REG(offset) \ - (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) -#define ID_SEL_BEGIN 11 -#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) - - -static int loongson_pcibios_config_access(unsigned char access_type, - struct pci_bus *bus, - unsigned int devfn, int where, - u32 *data) -{ - u32 busnum = bus->number; - u32 addr, type; - u32 dummy; - void *addrp; - int device = PCI_SLOT(devfn); - int function = PCI_FUNC(devfn); - int reg = where & ~3; - - if (busnum == 0) { - /* board-specific part,currently,only fuloong2f,yeeloong2f - * use CS5536, fuloong2e use via686b, gdium has no - * south bridge - */ -#ifdef CONFIG_CS5536 - /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to - * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO, - * PCI_MSR_DATA_HI, which is bigger than PCI_MSR_CTRL, so, it - * will not go this branch, but the others. so, no calling dead - * loop here. - */ - if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) { - switch (access_type) { - case PCI_ACCESS_READ: - *data = cs5536_pci_conf_read4(function, reg); - break; - case PCI_ACCESS_WRITE: - cs5536_pci_conf_write4(function, reg, *data); - break; - } - return 0; - } -#endif - /* Type 0 configuration for onboard PCI bus */ - if (device > MAX_DEV_NUM) - return -1; - - addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; - type = 0; - } else { - /* Type 1 configuration for offboard PCI bus */ - addr = (busnum << 16) | (device << 11) | (function << 8) | reg; - type = 0x10000; - } - - /* Clear aborts */ - LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ - LOONGSON_PCICMD_MTABORT_CLR; - - LOONGSON_PCIMAP_CFG = (addr >> 16) | type; - - /* Flush Bonito register block */ - dummy = LOONGSON_PCIMAP_CFG; - mmiowb(); - - addrp = CFG_SPACE_REG(addr & 0xffff); - if (access_type == PCI_ACCESS_WRITE) - writel(cpu_to_le32(*data), addrp); - else - *data = le32_to_cpu(readl(addrp)); - - /* Detect Master/Target abort */ - if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | - LOONGSON_PCICMD_MTABORT_CLR)) { - /* Error occurred */ - - /* Clear bits */ - LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | - LOONGSON_PCICMD_MTABORT_CLR); - - return -1; - } - - return 0; - -} - - -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 data = 0; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data)) - return -1; - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - -static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data = 0; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (size == 4) - data = val; - else { - if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, - where, &data)) - return -1; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - } - - if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, - &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops loongson_pci_ops = { - .read = loongson_pcibios_read, - .write = loongson_pcibios_write -}; - -#ifdef CONFIG_CS5536 -void _rdmsr(u32 msr, u32 *hi, u32 *lo) -{ - struct pci_bus bus = { - .number = PCI_BUS_CS5536 - }; - u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); - loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); - loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); - loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); -} -EXPORT_SYMBOL(_rdmsr); - -void _wrmsr(u32 msr, u32 hi, u32 lo) -{ - struct pci_bus bus = { - .number = PCI_BUS_CS5536 - }; - u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); - loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); - loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); - loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); -} -EXPORT_SYMBOL(_wrmsr); -#endif diff --git a/trunk/arch/mips/pci/pci-excite.c b/trunk/arch/mips/pci/pci-excite.c new file mode 100644 index 000000000000..8a56876afcc6 --- /dev/null +++ b/trunk/arch/mips/pci/pci-excite.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2004 by Basler Vision Technologies AG + * Author: Thomas Koeller + * Based on the PMC-Sierra Yosemite board support by Ralf Baechle. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include + + +extern struct pci_ops titan_pci_ops; + + +static struct resource + mem_resource = { + .name = "PCI memory", + .start = EXCITE_PHYS_PCI_MEM, + .end = EXCITE_PHYS_PCI_MEM + EXCITE_SIZE_PCI_MEM - 1, + .flags = IORESOURCE_MEM + }, + io_resource = { + .name = "PCI I/O", + .start = EXCITE_PHYS_PCI_IO, + .end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1, + .flags = IORESOURCE_IO + }; + + +static struct pci_controller bx_controller = { + .pci_ops = &titan_pci_ops, + .mem_resource = &mem_resource, + .mem_offset = 0x00000000UL, + .io_resource = &io_resource, + .io_offset = 0x00000000UL +}; + + +static char + iopage_failed[] __initdata = "Cannot allocate PCI I/O page", + modebits_no_pci[] __initdata = "PCI is not configured in mode bits"; + +#define RM9000x2_OCD_HTSC 0x0604 +#define RM9000x2_OCD_HTBHL 0x060c +#define RM9000x2_OCD_PCIHRST 0x078c + +#define RM9K_OCD_MODEBIT1 0x00d4 /* (MODEBIT1) Mode Bit 1 */ +#define RM9K_OCD_CPHDCR 0x00f4 /* CPU-PCI/HT Data Control. */ + +#define PCISC_FB2B 0x00000200 +#define PCISC_MWICG 0x00000010 +#define PCISC_EMC 0x00000004 +#define PCISC_ERMA 0x00000002 + + + +static int __init basler_excite_pci_setup(void) +{ + const unsigned int fullbars = memsize / (256 << 20); + unsigned int i; + + /* Check modebits to see if PCI is really enabled. */ + if (!((ocd_readl(RM9K_OCD_MODEBIT1) >> (47-32)) & 0x1)) + panic(modebits_no_pci); + + if (NULL == request_mem_region(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO, + "Memory-mapped PCI I/O page")) + panic(iopage_failed); + + /* Enable PCI 0 as master for config cycles */ + ocd_writel(PCISC_EMC | PCISC_ERMA, RM9000x2_OCD_HTSC); + + + /* Set up latency timer */ + ocd_writel(0x8008, RM9000x2_OCD_HTBHL); + + /* Setup host IO and Memory space */ + ocd_writel((EXCITE_PHYS_PCI_IO >> 4) | 1, LKB7); + ocd_writel(((EXCITE_SIZE_PCI_IO >> 4) & 0x7fffff00) - 0x100, LKM7); + ocd_writel((EXCITE_PHYS_PCI_MEM >> 4) | 1, LKB8); + ocd_writel(((EXCITE_SIZE_PCI_MEM >> 4) & 0x7fffff00) - 0x100, LKM8); + + /* Set up PCI BARs to map all installed memory */ + for (i = 0; i < 6; i++) { + const unsigned int bar = 0x610 + i * 4; + + if (i < fullbars) { + ocd_writel(0x10000000 * i, bar); + ocd_writel(0x01000000 * i, bar + 0x140); + ocd_writel(0x0ffff029, bar + 0x100); + continue; + } + + if (i == fullbars) { + int o; + u32 mask; + + const unsigned long rem = memsize - i * 0x10000000; + if (!rem) { + ocd_writel(0x00000000, bar + 0x100); + continue; + } + + o = ffs(rem) - 1; + if (rem & ~(0x1 << o)) + o++; + mask = ((0x1 << o) & 0x0ffff000) - 0x1000; + ocd_writel(0x10000000 * i, bar); + ocd_writel(0x01000000 * i, bar + 0x140); + ocd_writel(0x00000029 | mask, bar + 0x100); + continue; + } + + ocd_writel(0x00000000, bar + 0x100); + } + + /* Finally, enable the PCI interrupt */ +#if USB_IRQ > 7 + set_c0_intcontrol(1 << USB_IRQ); +#else + set_c0_status(1 << (USB_IRQ + 8)); +#endif + + ioport_resource.start = EXCITE_PHYS_PCI_IO; + ioport_resource.end = EXCITE_PHYS_PCI_IO + EXCITE_SIZE_PCI_IO - 1; + set_io_port_base((unsigned long) ioremap_nocache(EXCITE_PHYS_PCI_IO, EXCITE_SIZE_PCI_IO)); + register_pci_controller(&bx_controller); + return 0; +} + + +arch_initcall(basler_excite_pci_setup); diff --git a/trunk/arch/mips/powertv/Kconfig b/trunk/arch/mips/powertv/Kconfig deleted file mode 100644 index ff0e7e3e6954..000000000000 --- a/trunk/arch/mips/powertv/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -source "arch/mips/powertv/asic/Kconfig" - -config BOOTLOADER_DRIVER - bool "PowerTV Bootloader Driver Support" - default n - depends on POWERTV - help - Use this option if you want to load bootloader driver. - -config BOOTLOADER_FAMILY - string "POWERTV Bootloader Family string" - default "85" - depends on POWERTV && !BOOTLOADER_DRIVER - help - This value should be specified when the bootloader driver is disabled - and must be exactly two characters long. Families supported are: - R1 - RNG-100 R2 - RNG-200 - A1 - Class A B1 - Class B - E1 - Class E F1 - Class F - 44 - 45xx 46 - 46xx - 85 - 85xx 86 - 86xx diff --git a/trunk/arch/mips/powertv/Makefile b/trunk/arch/mips/powertv/Makefile deleted file mode 100644 index 2c516718affe..000000000000 --- a/trunk/arch/mips/powertv/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. -# -# Carsten Langgaard, carstenl@mips.com -# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. -# Portions copyright (C) 2009 Cisco Systems, Inc. -# -# This program is free software; you can distribute it and/or modify it -# under the terms of the GNU General Public License (Version 2) as -# published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -# for more details. -# -# You should have received a copy of the GNU General Public License along -# with this program; if not, write to the Free Software Foundation, Inc., -# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -# -# Makefile for the Cisco PowerTV-specific kernel interface routines -# under Linux. -# - -obj-y += cmdline.o init.o memory.o reset.o time.o powertv_setup.o asic/ pci/ - -EXTRA_CFLAGS += -Wall -Werror diff --git a/trunk/arch/mips/powertv/asic/Kconfig b/trunk/arch/mips/powertv/asic/Kconfig deleted file mode 100644 index 2016bfe94d66..000000000000 --- a/trunk/arch/mips/powertv/asic/Kconfig +++ /dev/null @@ -1,28 +0,0 @@ -config MIN_RUNTIME_RESOURCES - bool "Support for minimum runtime resources" - default n - depends on POWERTV - help - Enables support for minimizing the number of (SA asic) runtime - resources that are preallocated by the kernel. - -config MIN_RUNTIME_DOCSIS - bool "Support for minimum DOCSIS resource" - default y - depends on MIN_RUNTIME_RESOURCES - help - Enables support for the preallocated DOCSIS resource. - -config MIN_RUNTIME_PMEM - bool "Support for minimum PMEM resource" - default y - depends on MIN_RUNTIME_RESOURCES - help - Enables support for the preallocated Memory resource. - -config MIN_RUNTIME_TFTP - bool "Support for minimum TFTP resource" - default y - depends on MIN_RUNTIME_RESOURCES - help - Enables support for the preallocated TFTP resource. diff --git a/trunk/arch/mips/powertv/asic/Makefile b/trunk/arch/mips/powertv/asic/Makefile deleted file mode 100644 index bebfdcff0443..000000000000 --- a/trunk/arch/mips/powertv/asic/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (C) 2009 Scientific-Atlanta, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -obj-y += asic-calliope.o asic-cronus.o asic-zeus.o asic_devices.o asic_int.o \ - irq_asic.o prealloc-calliope.o prealloc-cronus.o \ - prealloc-cronuslite.o prealloc-zeus.o - -EXTRA_CFLAGS += -Wall -Werror diff --git a/trunk/arch/mips/powertv/asic/asic-calliope.c b/trunk/arch/mips/powertv/asic/asic-calliope.c deleted file mode 100644 index 03d3884c6270..000000000000 --- a/trunk/arch/mips/powertv/asic/asic-calliope.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Locations of devices in the Calliope ASIC. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef - * - * Description: Defines the platform resources for the SA settop. - */ - -#include - -const struct register_map calliope_register_map = { - .eic_slow0_strt_add = 0x800000, - .eic_cfg_bits = 0x800038, - .eic_ready_status = 0x80004c, - - .chipver3 = 0xA00800, - .chipver2 = 0xA00804, - .chipver1 = 0xA00808, - .chipver0 = 0xA0080c, - - /* The registers of IRBlaster */ - .uart1_intstat = 0xA01800, - .uart1_inten = 0xA01804, - .uart1_config1 = 0xA01808, - .uart1_config2 = 0xA0180C, - .uart1_divisorhi = 0xA01810, - .uart1_divisorlo = 0xA01814, - .uart1_data = 0xA01818, - .uart1_status = 0xA0181C, - - .int_stat_3 = 0xA02800, - .int_stat_2 = 0xA02804, - .int_stat_1 = 0xA02808, - .int_stat_0 = 0xA0280c, - .int_config = 0xA02810, - .int_int_scan = 0xA02818, - .ien_int_3 = 0xA02830, - .ien_int_2 = 0xA02834, - .ien_int_1 = 0xA02838, - .ien_int_0 = 0xA0283c, - .int_level_3_3 = 0xA02880, - .int_level_3_2 = 0xA02884, - .int_level_3_1 = 0xA02888, - .int_level_3_0 = 0xA0288c, - .int_level_2_3 = 0xA02890, - .int_level_2_2 = 0xA02894, - .int_level_2_1 = 0xA02898, - .int_level_2_0 = 0xA0289c, - .int_level_1_3 = 0xA028a0, - .int_level_1_2 = 0xA028a4, - .int_level_1_1 = 0xA028a8, - .int_level_1_0 = 0xA028ac, - .int_level_0_3 = 0xA028b0, - .int_level_0_2 = 0xA028b4, - .int_level_0_1 = 0xA028b8, - .int_level_0_0 = 0xA028bc, - .int_docsis_en = 0xA028F4, - - .mips_pll_setup = 0x980000, - .usb_fs = 0x980030, /* -default 72800028- */ - .test_bus = 0x9800CC, - .crt_spare = 0x9800d4, - .usb2_ohci_int_mask = 0x9A000c, - .usb2_strap = 0x9A0014, - .ehci_hcapbase = 0x9BFE00, - .ohci_hc_revision = 0x9BFC00, - .bcm1_bs_lmi_steer = 0x9E0004, - .usb2_control = 0x9E0054, - .usb2_stbus_obc = 0x9BFF00, - .usb2_stbus_mess_size = 0x9BFF04, - .usb2_stbus_chunk_size = 0x9BFF08, - - .pcie_regs = 0x000000, /* -doesn't exist- */ - .tim_ch = 0xA02C10, - .tim_cl = 0xA02C14, - .gpio_dout = 0xA02c20, - .gpio_din = 0xA02c24, - .gpio_dir = 0xA02c2C, - .watchdog = 0xA02c30, - .front_panel = 0x000000, /* -not used- */ -}; diff --git a/trunk/arch/mips/powertv/asic/asic-cronus.c b/trunk/arch/mips/powertv/asic/asic-cronus.c deleted file mode 100644 index 5f4589c9f83d..000000000000 --- a/trunk/arch/mips/powertv/asic/asic-cronus.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Locations of devices in the Cronus ASIC - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef - * - * Description: Defines the platform resources for the SA settop. - */ - -#include - -const struct register_map cronus_register_map = { - .eic_slow0_strt_add = 0x000000, - .eic_cfg_bits = 0x000038, - .eic_ready_status = 0x00004C, - - .chipver3 = 0x2A0800, - .chipver2 = 0x2A0804, - .chipver1 = 0x2A0808, - .chipver0 = 0x2A080C, - - /* The registers of IRBlaster */ - .uart1_intstat = 0x2A1800, - .uart1_inten = 0x2A1804, - .uart1_config1 = 0x2A1808, - .uart1_config2 = 0x2A180C, - .uart1_divisorhi = 0x2A1810, - .uart1_divisorlo = 0x2A1814, - .uart1_data = 0x2A1818, - .uart1_status = 0x2A181C, - - .int_stat_3 = 0x2A2800, - .int_stat_2 = 0x2A2804, - .int_stat_1 = 0x2A2808, - .int_stat_0 = 0x2A280C, - .int_config = 0x2A2810, - .int_int_scan = 0x2A2818, - .ien_int_3 = 0x2A2830, - .ien_int_2 = 0x2A2834, - .ien_int_1 = 0x2A2838, - .ien_int_0 = 0x2A283C, - .int_level_3_3 = 0x2A2880, - .int_level_3_2 = 0x2A2884, - .int_level_3_1 = 0x2A2888, - .int_level_3_0 = 0x2A288C, - .int_level_2_3 = 0x2A2890, - .int_level_2_2 = 0x2A2894, - .int_level_2_1 = 0x2A2898, - .int_level_2_0 = 0x2A289C, - .int_level_1_3 = 0x2A28A0, - .int_level_1_2 = 0x2A28A4, - .int_level_1_1 = 0x2A28A8, - .int_level_1_0 = 0x2A28AC, - .int_level_0_3 = 0x2A28B0, - .int_level_0_2 = 0x2A28B4, - .int_level_0_1 = 0x2A28B8, - .int_level_0_0 = 0x2A28BC, - .int_docsis_en = 0x2A28F4, - - .mips_pll_setup = 0x1C0000, - .usb_fs = 0x1C0018, - .test_bus = 0x1C00CC, - .crt_spare = 0x1c00d4, - .usb2_ohci_int_mask = 0x20000C, - .usb2_strap = 0x200014, - .ehci_hcapbase = 0x21FE00, - .ohci_hc_revision = 0x1E0000, - .bcm1_bs_lmi_steer = 0x2E0008, - .usb2_control = 0x2E004C, - .usb2_stbus_obc = 0x21FF00, - .usb2_stbus_mess_size = 0x21FF04, - .usb2_stbus_chunk_size = 0x21FF08, - - .pcie_regs = 0x220000, - .tim_ch = 0x2A2C10, - .tim_cl = 0x2A2C14, - .gpio_dout = 0x2A2C20, - .gpio_din = 0x2A2C24, - .gpio_dir = 0x2A2C2C, - .watchdog = 0x2A2C30, - .front_panel = 0x2A3800, -}; diff --git a/trunk/arch/mips/powertv/asic/asic-zeus.c b/trunk/arch/mips/powertv/asic/asic-zeus.c deleted file mode 100644 index 1469daab920e..000000000000 --- a/trunk/arch/mips/powertv/asic/asic-zeus.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Locations of devices in the Zeus ASIC - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef - * - * Description: Defines the platform resources for the SA settop. - */ - -#include - -const struct register_map zeus_register_map = { - .eic_slow0_strt_add = 0x000000, - .eic_cfg_bits = 0x000038, - .eic_ready_status = 0x00004c, - - .chipver3 = 0x280800, - .chipver2 = 0x280804, - .chipver1 = 0x280808, - .chipver0 = 0x28080c, - - /* The registers of IRBlaster */ - .uart1_intstat = 0x281800, - .uart1_inten = 0x281804, - .uart1_config1 = 0x281808, - .uart1_config2 = 0x28180C, - .uart1_divisorhi = 0x281810, - .uart1_divisorlo = 0x281814, - .uart1_data = 0x281818, - .uart1_status = 0x28181C, - - .int_stat_3 = 0x282800, - .int_stat_2 = 0x282804, - .int_stat_1 = 0x282808, - .int_stat_0 = 0x28280c, - .int_config = 0x282810, - .int_int_scan = 0x282818, - .ien_int_3 = 0x282830, - .ien_int_2 = 0x282834, - .ien_int_1 = 0x282838, - .ien_int_0 = 0x28283c, - .int_level_3_3 = 0x282880, - .int_level_3_2 = 0x282884, - .int_level_3_1 = 0x282888, - .int_level_3_0 = 0x28288c, - .int_level_2_3 = 0x282890, - .int_level_2_2 = 0x282894, - .int_level_2_1 = 0x282898, - .int_level_2_0 = 0x28289c, - .int_level_1_3 = 0x2828a0, - .int_level_1_2 = 0x2828a4, - .int_level_1_1 = 0x2828a8, - .int_level_1_0 = 0x2828ac, - .int_level_0_3 = 0x2828b0, - .int_level_0_2 = 0x2828b4, - .int_level_0_1 = 0x2828b8, - .int_level_0_0 = 0x2828bc, - .int_docsis_en = 0x2828F4, - - .mips_pll_setup = 0x1a0000, - .usb_fs = 0x1a0018, - .test_bus = 0x1a0238, - .crt_spare = 0x1a0090, - .usb2_ohci_int_mask = 0x1e000c, - .usb2_strap = 0x1e0014, - .ehci_hcapbase = 0x1FFE00, - .ohci_hc_revision = 0x1FFC00, - .bcm1_bs_lmi_steer = 0x2C0008, - .usb2_control = 0x2c01a0, - .usb2_stbus_obc = 0x1FFF00, - .usb2_stbus_mess_size = 0x1FFF04, - .usb2_stbus_chunk_size = 0x1FFF08, - - .pcie_regs = 0x200000, - .tim_ch = 0x282C10, - .tim_cl = 0x282C14, - .gpio_dout = 0x282c20, - .gpio_din = 0x282c24, - .gpio_dir = 0x282c2C, - .watchdog = 0x282c30, - .front_panel = 0x283800, -}; diff --git a/trunk/arch/mips/powertv/asic/asic_devices.c b/trunk/arch/mips/powertv/asic/asic_devices.c deleted file mode 100644 index bae82880b6b5..000000000000 --- a/trunk/arch/mips/powertv/asic/asic_devices.c +++ /dev/null @@ -1,787 +0,0 @@ -/* - * ASIC Device List Intialization - * - * Description: Defines the platform resources for the SA settop. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef - * - * Description: Defines the platform resources for the SA settop. - * - * NOTE: The bootloader allocates persistent memory at an address which is - * 16 MiB below the end of the highest address in KSEG0. All fixed - * address memory reservations must avoid this region. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#ifdef CONFIG_BOOTLOADER_DRIVER -#include -#endif -#include - -#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) - -/* - * Forward Prototypes - */ -static void pmem_setup_resource(void); - -/* - * Global Variables - */ -enum asic_type asic; - -unsigned int platform_features; -unsigned int platform_family; -const struct register_map *register_map; -EXPORT_SYMBOL(register_map); /* Exported for testing */ -unsigned long asic_phy_base; -unsigned long asic_base; -EXPORT_SYMBOL(asic_base); /* Exported for testing */ -struct resource *gp_resources; -static bool usb_configured; - -/* - * Don't recommend to use it directly, it is usually used by kernel internally. - * Portable code should be using interfaces such as ioremp, dma_map_single, etc. - */ -unsigned long phys_to_bus_offset; -EXPORT_SYMBOL(phys_to_bus_offset); - -/* - * - * IO Resource Definition - * - */ - -struct resource asic_resource = { - .name = "ASIC Resource", - .start = 0, - .end = ASIC_IO_SIZE, - .flags = IORESOURCE_MEM, -}; - -/* - * - * USB Host Resource Definition - * - */ - -static struct resource ehci_resources[] = { - { - .parent = &asic_resource, - .start = 0, - .end = 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = irq_usbehci, - .end = irq_usbehci, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ehci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device ehci_device = { - .name = "powertv-ehci", - .id = 0, - .num_resources = 2, - .resource = ehci_resources, - .dev = { - .dma_mask = &ehci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct resource ohci_resources[] = { - { - .parent = &asic_resource, - .start = 0, - .end = 0xff, - .flags = IORESOURCE_MEM, - }, - { - .start = irq_usbohci, - .end = irq_usbohci, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 ohci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device ohci_device = { - .name = "powertv-ohci", - .id = 0, - .num_resources = 2, - .resource = ohci_resources, - .dev = { - .dma_mask = &ohci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -static struct platform_device *platform_devices[] = { - &ehci_device, - &ohci_device, -}; - -/* - * - * Platform Configuration and Device Initialization - * - */ -static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3) -{ - int en_prg, byp, pwr, nsb, val; - int sout; - - sout = 1; - en_prg = 1; - byp = 0; - nsb = 1; - pwr = 1; - - val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) | - (nsb<<1) | (disable_div_by_3<<5)); - - asic_write(val, usb_fs); - asic_write(val | (en_prg<<4), usb_fs); - asic_write(val | (en_prg<<4) | pwr, usb_fs); -} - -/* - * Allow override of bootloader-specified model - */ -static char __initdata cmdline[COMMAND_LINE_SIZE]; - -#define FORCEFAMILY_PARAM "forcefamily" - -static __init int check_forcefamily(unsigned char forced_family[2]) -{ - const char *p; - - forced_family[0] = '\0'; - forced_family[1] = '\0'; - - /* Check the command line for a forcefamily directive */ - strncpy(cmdline, arcs_cmdline, COMMAND_LINE_SIZE - 1); - p = strstr(cmdline, FORCEFAMILY_PARAM); - if (p && (p != cmdline) && (*(p - 1) != ' ')) - p = strstr(p, " " FORCEFAMILY_PARAM "="); - - if (p) { - p += strlen(FORCEFAMILY_PARAM "="); - - if (*p == '\0' || *(p + 1) == '\0' || - (*(p + 2) != '\0' && *(p + 2) != ' ')) - pr_err(FORCEFAMILY_PARAM " must be exactly two " - "characters long, ignoring value\n"); - - else { - forced_family[0] = *p; - forced_family[1] = *(p + 1); - } - } - - return 0; -} - -/* - * platform_set_family - determine major platform family type. - * - * Returns family type; -1 if none - * Returns the family type; -1 if none - * - */ -static __init noinline void platform_set_family(void) -{ -#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) - - unsigned char forced_family[2]; - unsigned short bootldr_family; - - check_forcefamily(forced_family); - - if (forced_family[0] != '\0' && forced_family[1] != '\0') - bootldr_family = BOOTLDRFAMILY(forced_family[0], - forced_family[1]); - else { - -#ifdef CONFIG_BOOTLOADER_DRIVER - bootldr_family = (unsigned short) kbldr_GetSWFamily(); -#else -#if defined(CONFIG_BOOTLOADER_FAMILY) - bootldr_family = (unsigned short) BOOTLDRFAMILY( - CONFIG_BOOTLOADER_FAMILY[0], - CONFIG_BOOTLOADER_FAMILY[1]); -#else -#error "Unknown Bootloader Family" -#endif -#endif - } - - pr_info("Bootloader Family = 0x%04X\n", bootldr_family); - - switch (bootldr_family) { - case BOOTLDRFAMILY('R', '1'): - platform_family = FAMILY_1500; - break; - case BOOTLDRFAMILY('4', '4'): - platform_family = FAMILY_4500; - break; - case BOOTLDRFAMILY('4', '6'): - platform_family = FAMILY_4600; - break; - case BOOTLDRFAMILY('A', '1'): - platform_family = FAMILY_4600VZA; - break; - case BOOTLDRFAMILY('8', '5'): - platform_family = FAMILY_8500; - break; - case BOOTLDRFAMILY('R', '2'): - platform_family = FAMILY_8500RNG; - break; - case BOOTLDRFAMILY('8', '6'): - platform_family = FAMILY_8600; - break; - case BOOTLDRFAMILY('B', '1'): - platform_family = FAMILY_8600VZB; - break; - case BOOTLDRFAMILY('E', '1'): - platform_family = FAMILY_1500VZE; - break; - case BOOTLDRFAMILY('F', '1'): - platform_family = FAMILY_1500VZF; - break; - default: - platform_family = -1; - } -} - -unsigned int platform_get_family(void) -{ - return platform_family; -} -EXPORT_SYMBOL(platform_get_family); - -/* - * \brief usb_eye_configure() for optimizing the USB eye on Calliope. - * - * \param unsigned int value saved to the register. - * - * \return none - * - */ -static void __init usb_eye_configure(unsigned int value) -{ - asic_write(asic_read(crt_spare) | value, crt_spare); -} - -/* - * platform_get_asic - determine the ASIC type. - * - * \param none - * - * \return ASIC type; ASIC_UNKNOWN if none - * - */ -enum asic_type platform_get_asic(void) -{ - return asic; -} -EXPORT_SYMBOL(platform_get_asic); - -/* - * platform_configure_usb - usb configuration based on platform type. - * @bcm1_usb2_ctl: value for the BCM1_USB2_CTL register, which is - * quirky - */ -static void __init platform_configure_usb(void) -{ - u32 bcm1_usb2_ctl; - - if (usb_configured) - return; - - switch (asic) { - case ASIC_ZEUS: - fs_update(0x0000, 0x11, 0x02, 0); - bcm1_usb2_ctl = 0x803; - break; - - case ASIC_CRONUS: - case ASIC_CRONUSLITE: - fs_update(0x0000, 0x11, 0x02, 0); - bcm1_usb2_ctl = 0x803; - break; - - case ASIC_CALLIOPE: - fs_update(0x0000, 0x11, 0x02, 1); - - switch (platform_family) { - case FAMILY_1500VZE: - break; - - case FAMILY_1500VZF: - usb_eye_configure(0x003c0000); - break; - - default: - usb_eye_configure(0x00300000); - break; - } - - bcm1_usb2_ctl = 0x803; - break; - - default: - pr_err("Unknown ASIC type: %d\n", asic); - break; - } - - /* turn on USB power */ - asic_write(0, usb2_strap); - /* Enable all OHCI interrupts */ - asic_write(bcm1_usb2_ctl, usb2_control); - /* USB2_STBUS_OBC store32/load32 */ - asic_write(3, usb2_stbus_obc); - /* USB2_STBUS_MESS_SIZE 2 packets */ - asic_write(1, usb2_stbus_mess_size); - /* USB2_STBUS_CHUNK_SIZE 2 packets */ - asic_write(1, usb2_stbus_chunk_size); - - usb_configured = true; -} - -/* - * Set up the USB EHCI interface - */ -void platform_configure_usb_ehci() -{ - platform_configure_usb(); -} - -/* - * Set up the USB OHCI interface - */ -void platform_configure_usb_ohci() -{ - platform_configure_usb(); -} - -/* - * Shut the USB EHCI interface down--currently a NOP - */ -void platform_unconfigure_usb_ehci() -{ -} - -/* - * Shut the USB OHCI interface down--currently a NOP - */ -void platform_unconfigure_usb_ohci() -{ -} - -/** - * configure_platform - configuration based on platform type. - */ -void __init configure_platform(void) -{ - platform_set_family(); - - switch (platform_family) { - case FAMILY_1500: - case FAMILY_1500VZE: - case FAMILY_1500VZF: - platform_features = FFS_CAPABLE; - asic = ASIC_CALLIOPE; - asic_phy_base = CALLIOPE_IO_BASE; - register_map = &calliope_register_map; - asic_base = (unsigned long)ioremap_nocache(asic_phy_base, - ASIC_IO_SIZE); - - if (platform_family == FAMILY_1500VZE) { - gp_resources = non_dvr_vze_calliope_resources; - pr_info("Platform: 1500/Vz Class E - " - "CALLIOPE, NON_DVR_CAPABLE\n"); - } else if (platform_family == FAMILY_1500VZF) { - gp_resources = non_dvr_vzf_calliope_resources; - pr_info("Platform: 1500/Vz Class F - " - "CALLIOPE, NON_DVR_CAPABLE\n"); - } else { - gp_resources = non_dvr_calliope_resources; - pr_info("Platform: 1500/RNG100 - CALLIOPE, " - "NON_DVR_CAPABLE\n"); - } - break; - - case FAMILY_4500: - platform_features = FFS_CAPABLE | PCIE_CAPABLE | - DISPLAY_CAPABLE; - asic = ASIC_ZEUS; - asic_phy_base = ZEUS_IO_BASE; - register_map = &zeus_register_map; - asic_base = (unsigned long)ioremap_nocache(asic_phy_base, - ASIC_IO_SIZE); - gp_resources = non_dvr_zeus_resources; - - pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n"); - break; - - case FAMILY_4600: - { - unsigned int chipversion = 0; - - /* The settop has PCIE but it isn't used, so don't advertise - * it*/ - platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; - asic_phy_base = CRONUS_IO_BASE; /* same as Cronus */ - register_map = &cronus_register_map; /* same as Cronus */ - asic_base = (unsigned long)ioremap_nocache(asic_phy_base, - ASIC_IO_SIZE); - gp_resources = non_dvr_cronuslite_resources; - - /* ASIC version will determine if this is a real CronusLite or - * Castrati(Cronus) */ - chipversion = asic_read(chipver3) << 24; - chipversion |= asic_read(chipver2) << 16; - chipversion |= asic_read(chipver1) << 8; - chipversion |= asic_read(chipver0); - - if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11)) - asic = ASIC_CRONUS; - else - asic = ASIC_CRONUSLITE; - - pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " - "chipversion=0x%08X\n", - (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE", - chipversion); - break; - } - case FAMILY_4600VZA: - platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; - asic = ASIC_CRONUS; - asic_phy_base = CRONUS_IO_BASE; - register_map = &cronus_register_map; - asic_base = (unsigned long)ioremap_nocache(asic_phy_base, - ASIC_IO_SIZE); - gp_resources = non_dvr_cronus_resources; - - pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n"); - break; - - case FAMILY_8500: - case FAMILY_8500RNG: - platform_features = DVR_CAPABLE | PCIE_CAPABLE | - DISPLAY_CAPABLE; - asic = ASIC_ZEUS; - asic_phy_base = ZEUS_IO_BASE; - register_map = &zeus_register_map; - asic_base = (unsigned long)ioremap_nocache(asic_phy_base, - ASIC_IO_SIZE); - gp_resources = dvr_zeus_resources; - - pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n"); - break; - - case FAMILY_8600: - case FAMILY_8600VZB: - platform_features = DVR_CAPABLE | PCIE_CAPABLE | - DISPLAY_CAPABLE; - asic = ASIC_CRONUS; - asic_phy_base = CRONUS_IO_BASE; - register_map = &cronus_register_map; - asic_base = (unsigned long)ioremap_nocache(asic_phy_base, - ASIC_IO_SIZE); - gp_resources = dvr_cronus_resources; - - pr_info("Platform: 8600/Vz Class B - CRONUS, " - "DVR_CAPABLE\n"); - break; - - default: - pr_crit("Platform: UNKNOWN PLATFORM\n"); - break; - } - - switch (asic) { - case ASIC_ZEUS: - phys_to_bus_offset = 0x30000000; - break; - case ASIC_CALLIOPE: - phys_to_bus_offset = 0x10000000; - break; - case ASIC_CRONUSLITE: - /* Fall through */ - case ASIC_CRONUS: - /* - * TODO: We suppose 0x10000000 aliases into 0x20000000- - * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000- - * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000. - */ - phys_to_bus_offset = 0x10000000; - break; - default: - phys_to_bus_offset = 0x00000000; - break; - } -} - -/** - * platform_devices_init - sets up USB device resourse. - */ -static int __init platform_devices_init(void) -{ - pr_notice("%s: ----- Initializing USB resources -----\n", __func__); - - asic_resource.start = asic_phy_base; - asic_resource.end += asic_resource.start; - - ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase); - ehci_resources[0].end += ehci_resources[0].start; - - ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision); - ohci_resources[0].end += ohci_resources[0].start; - - set_io_port_base(0); - - platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); - - return 0; -} - -arch_initcall(platform_devices_init); - -/* - * - * BOOTMEM ALLOCATION - * - */ -/* - * Allocates/reserves the Platform memory resources early in the boot process. - * This ignores any resources that are designated IORESOURCE_IO - */ -void __init platform_alloc_bootmem(void) -{ - int i; - int total = 0; - - /* Get persistent memory data from command line before allocating - * resources. This need to happen before normal command line parsing - * has been done */ - pmem_setup_resource(); - - /* Loop through looking for resources that want a particular address */ - for (i = 0; gp_resources[i].flags != 0; i++) { - int size = gp_resources[i].end - gp_resources[i].start + 1; - if ((gp_resources[i].start != 0) && - ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { - reserve_bootmem(bus_to_phys(gp_resources[i].start), - size, 0); - total += gp_resources[i].end - - gp_resources[i].start + 1; - pr_info("reserve resource %s at %08x (%u bytes)\n", - gp_resources[i].name, gp_resources[i].start, - gp_resources[i].end - - gp_resources[i].start + 1); - } - } - - /* Loop through assigning addresses for those that are left */ - for (i = 0; gp_resources[i].flags != 0; i++) { - int size = gp_resources[i].end - gp_resources[i].start + 1; - if ((gp_resources[i].start == 0) && - ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { - void *mem = alloc_bootmem_pages(size); - - if (mem == NULL) - pr_err("Unable to allocate bootmem pages " - "for %s\n", gp_resources[i].name); - - else { - gp_resources[i].start = - phys_to_bus(virt_to_phys(mem)); - gp_resources[i].end = - gp_resources[i].start + size - 1; - total += size; - pr_info("allocate resource %s at %08x " - "(%u bytes)\n", - gp_resources[i].name, - gp_resources[i].start, size); - } - } - } - - pr_info("Total Platform driver memory allocation: 0x%08x\n", total); - - /* indicate resources that are platform I/O related */ - for (i = 0; gp_resources[i].flags != 0; i++) { - if ((gp_resources[i].start != 0) && - ((gp_resources[i].flags & IORESOURCE_IO) != 0)) { - pr_info("reserved platform resource %s at %08x\n", - gp_resources[i].name, gp_resources[i].start); - } - } -} - -/* - * - * PERSISTENT MEMORY (PMEM) CONFIGURATION - * - */ -static unsigned long pmemaddr __initdata; - -static int __init early_param_pmemaddr(char *p) -{ - pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0); - return 0; -} -early_param("pmemaddr", early_param_pmemaddr); - -static long pmemlen __initdata; - -static int __init early_param_pmemlen(char *p) -{ -/* TODO: we can use this code when and if the bootloader ever changes this */ -#if 0 - pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); -#else - pmemlen = 0x20000; -#endif - return 0; -} -early_param("pmemlen", early_param_pmemlen); - -/* - * Set up persistent memory. If we were given values, we patch the array of - * resources. Otherwise, persistent memory may be allocated anywhere at all. - */ -static void __init pmem_setup_resource(void) -{ - struct resource *resource; - resource = asic_resource_get("DiagPersistentMemory"); - - if (resource && pmemaddr && pmemlen) { - /* The address provided by bootloader is in kseg0. Convert to - * a bus address. */ - resource->start = phys_to_bus(pmemaddr - 0x80000000); - resource->end = resource->start + pmemlen - 1; - - pr_info("persistent memory: start=0x%x end=0x%x\n", - resource->start, resource->end); - } -} - -/* - * - * RESOURCE ACCESS FUNCTIONS - * - */ - -/** - * asic_resource_get - retrieves parameters for a platform resource. - * @name: string to match resource - * - * Returns a pointer to a struct resource corresponding to the given name. - * - * CANNOT BE NAMED platform_resource_get, which would be the obvious choice, - * as this function name is already declared - */ -struct resource *asic_resource_get(const char *name) -{ - int i; - - for (i = 0; gp_resources[i].flags != 0; i++) { - if (strcmp(gp_resources[i].name, name) == 0) - return &gp_resources[i]; - } - - return NULL; -} -EXPORT_SYMBOL(asic_resource_get); - -/** - * platform_release_memory - release pre-allocated memory - * @ptr: pointer to memory to release - * @size: size of resource - * - * This must only be called for memory allocated or reserved via the boot - * memory allocator. - */ -void platform_release_memory(void *ptr, int size) -{ - unsigned long addr; - unsigned long end; - - addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK; - end = ((unsigned long)ptr + size) & PAGE_MASK; - - for (; addr < end; addr += PAGE_SIZE) { - ClearPageReserved(virt_to_page(__va(addr))); - init_page_count(virt_to_page(__va(addr))); - free_page((unsigned long)__va(addr)); - } -} -EXPORT_SYMBOL(platform_release_memory); - -/* - * - * FEATURE AVAILABILITY FUNCTIONS - * - */ -int platform_supports_dvr(void) -{ - return (platform_features & DVR_CAPABLE) != 0; -} - -int platform_supports_ffs(void) -{ - return (platform_features & FFS_CAPABLE) != 0; -} - -int platform_supports_pcie(void) -{ - return (platform_features & PCIE_CAPABLE) != 0; -} - -int platform_supports_display(void) -{ - return (platform_features & DISPLAY_CAPABLE) != 0; -} diff --git a/trunk/arch/mips/powertv/asic/asic_int.c b/trunk/arch/mips/powertv/asic/asic_int.c deleted file mode 100644 index 80b2eed21ac3..000000000000 --- a/trunk/arch/mips/powertv/asic/asic_int.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. - * Copyright (C) 2001 Ralf Baechle - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Routines for generic manipulation of the interrupts found on the PowerTV - * platform. - * - * The interrupt controller is located in the South Bridge a PIIX4 device - * with two internal 82C95 interrupt controllers. - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -static DEFINE_SPINLOCK(asic_irq_lock); - -static inline int get_int(void) -{ - unsigned long flags; - int irq; - - spin_lock_irqsave(&asic_irq_lock, flags); - - irq = (asic_read(int_int_scan) >> 4) - 1; - - if (irq == 0 || irq >= NR_IRQS) - irq = -1; - - spin_unlock_irqrestore(&asic_irq_lock, flags); - - return irq; -} - -static void asic_irqdispatch(void) -{ - int irq; - - irq = get_int(); - if (irq < 0) - return; /* interrupt has already been cleared */ - - do_IRQ(irq); -} - -static inline int clz(unsigned long x) -{ - __asm__( - " .set push \n" - " .set mips32 \n" - " clz %0, %1 \n" - " .set pop \n" - : "=r" (x) - : "r" (x)); - - return x; -} - -/* - * Version of ffs that only looks at bits 12..15. - */ -static inline unsigned int irq_ffs(unsigned int pending) -{ - return fls(pending) - 1 + CAUSEB_IP; -} - -/* - * TODO: check how it works under EIC mode. - */ -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - int irq; - - irq = irq_ffs(pending); - - if (irq == CAUSEF_IP3) - asic_irqdispatch(); - else if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); -} - -void __init arch_init_irq(void) -{ - int i; - - asic_irq_init(); - - /* - * Initialize interrupt exception vectors. - */ - if (cpu_has_veic || cpu_has_vint) { - int nvec = cpu_has_veic ? 64 : 8; - for (i = 0; i < nvec; i++) - set_vi_handler(i, asic_irqdispatch); - } -} diff --git a/trunk/arch/mips/powertv/asic/irq_asic.c b/trunk/arch/mips/powertv/asic/irq_asic.c deleted file mode 100644 index b54d24499b06..000000000000 --- a/trunk/arch/mips/powertv/asic/irq_asic.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Portions copyright (C) 2005-2009 Scientific Atlanta - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * Modified from arch/mips/kernel/irq-rm7000.c: - * Copyright (C) 2003 Ralf Baechle - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include - -#include -#include -#include - -#include - -static inline void unmask_asic_irq(unsigned int irq) -{ - unsigned long enable_bit; - - enable_bit = (1 << (irq & 0x1f)); - - switch (irq >> 5) { - case 0: - asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0); - break; - case 1: - asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1); - break; - case 2: - asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2); - break; - case 3: - asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3); - break; - default: - BUG(); - } -} - -static inline void mask_asic_irq(unsigned int irq) -{ - unsigned long disable_mask; - - disable_mask = ~(1 << (irq & 0x1f)); - - switch (irq >> 5) { - case 0: - asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0); - break; - case 1: - asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1); - break; - case 2: - asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2); - break; - case 3: - asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3); - break; - default: - BUG(); - } -} - -static struct irq_chip asic_irq_chip = { - .name = "ASIC Level", - .ack = mask_asic_irq, - .mask = mask_asic_irq, - .mask_ack = mask_asic_irq, - .unmask = unmask_asic_irq, - .eoi = unmask_asic_irq, -}; - -void __init asic_irq_init(void) -{ - int i; - - /* set priority to 0 */ - write_c0_status(read_c0_status() & ~(0x0000fc00)); - - asic_write(0, ien_int_0); - asic_write(0, ien_int_1); - asic_write(0, ien_int_2); - asic_write(0, ien_int_3); - - asic_write(0x0fffffff, int_level_3_3); - asic_write(0xffffffff, int_level_3_2); - asic_write(0xffffffff, int_level_3_1); - asic_write(0xffffffff, int_level_3_0); - asic_write(0xffffffff, int_level_2_3); - asic_write(0xffffffff, int_level_2_2); - asic_write(0xffffffff, int_level_2_1); - asic_write(0xffffffff, int_level_2_0); - asic_write(0xffffffff, int_level_1_3); - asic_write(0xffffffff, int_level_1_2); - asic_write(0xffffffff, int_level_1_1); - asic_write(0xffffffff, int_level_1_0); - asic_write(0xffffffff, int_level_0_3); - asic_write(0xffffffff, int_level_0_2); - asic_write(0xffffffff, int_level_0_1); - asic_write(0xffffffff, int_level_0_0); - - asic_write(0xf, int_int_scan); - - /* - * Initialize interrupt handlers. - */ - for (i = 0; i < NR_IRQS; i++) - set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq); -} diff --git a/trunk/arch/mips/powertv/asic/prealloc-calliope.c b/trunk/arch/mips/powertv/asic/prealloc-calliope.c deleted file mode 100644 index cd5b76a1c951..000000000000 --- a/trunk/arch/mips/powertv/asic/prealloc-calliope.c +++ /dev/null @@ -1,620 +0,0 @@ -/* - * Memory pre-allocations for Calliope boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef - */ - -#include -#include - -/* - * NON_DVR_CAPABLE CALLIOPE RESOURCES - */ -struct resource non_dvr_calliope_resources[] __initdata = -{ - /* - * VIDEO / LX1 - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x24200000 - 1, /*2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /*8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24202000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, - /* - * Sysaudio Driver - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * STAVEM driver/STAPI - */ - { - .name = "AVMEMPartition0", - .start = 0x00000000, - .end = 0x00600000 - 1, /* 6 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * DOCSIS Subsystem - */ - { - .name = "Docsis", - .start = 0x22000000, - .end = 0x22700000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * GHW HAL Driver - */ - { - .name = "GraphicsHeap", - .start = 0x22700000, - .end = 0x23500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * multi com buffer area - */ - { - .name = "MulticomSHM", - .start = 0x23700000, - .end = 0x23720000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * DMA Ring buffer (don't need recording buffers) - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Display bins buffer for unit0 - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * AVFS: player HAL memory - * - * - */ - { - .name = "AvfsDmaMem", - .start = 0x00000000, - .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_MEM, - }, - /* - * PMEM - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Smartcard - */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * NAND Flash - */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE + 0x400 - 1, - .flags = IORESOURCE_IO, - }, - /* - * Synopsys GMAC Memory Region - */ - { - .name = "GMAC", - .start = 0x00000000, - .end = 0x00010000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Add other resources here - * - */ - { }, -}; - -struct resource non_dvr_vz_calliope_resources[] __initdata = -{ - /* - * VIDEO / LX1 - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x24200000 - 1, /*2 Meg */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8k block ST231a monitor */ - .start = 0x24200000, - .end = 0x24202000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x22202000, - .end = 0x22C20B85 - 1, /* 10.12 Meg */ - .flags = IORESOURCE_MEM, - }, - /* - * Sysaudio Driver - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * STAVEM driver/STAPI - */ - { - .name = "AVMEMPartition0", - .start = 0x20300000, - .end = 0x20620000-1, /*3.125 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * GHW HAL Driver - */ - { - .name = "GraphicsHeap", - .start = 0x20100000, - .end = 0x20300000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * multi com buffer area - */ - { - .name = "MulticomSHM", - .start = 0x23900000, - .end = 0x23920000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * DMA Ring buffer - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Display bins buffer for unit0 - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, - .flags = IORESOURCE_MEM, - }, - /* - * PMEM - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Smartcard - */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * NAND Flash - */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE+0x400 - 1, - .flags = IORESOURCE_IO, - }, - /* - * Synopsys GMAC Memory Region - */ - { - .name = "GMAC", - .start = 0x00000000, - .end = 0x00010000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Add other resources here - */ - { }, -}; - -struct resource non_dvr_vze_calliope_resources[] __initdata = -{ - /* - * VIDEO / LX1 - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x22000000, - .end = 0x22200000 - 1, /*2 Meg */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8k block ST231a monitor */ - .start = 0x22200000, - .end = 0x22202000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x22202000, - .end = 0x22C20B85 - 1, /* 10.12 Meg */ - .flags = IORESOURCE_MEM, - }, - /* - * Sysaudio Driver - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * STAVEM driver/STAPI - */ - { - .name = "AVMEMPartition0", - .start = 0x20396000, - .end = 0x206B6000 - 1, /* 3.125 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * GHW HAL Driver - */ - { - .name = "GraphicsHeap", - .start = 0x20100000, - .end = 0x20396000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * multi com buffer area - */ - { - .name = "MulticomSHM", - .start = 0x206B6000, - .end = 0x206D6000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * DMA Ring buffer - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Display bins buffer for unit0 - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, - .flags = IORESOURCE_MEM, - }, - /* - * PMEM - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Smartcard - */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * NAND Flash - */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE+0x400 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Synopsys GMAC Memory Region - */ - { - .name = "GMAC", - .start = 0x00000000, - .end = 0x00010000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Add other resources here - */ - { }, -}; - -struct resource non_dvr_vzf_calliope_resources[] __initdata = -{ - /* - * VIDEO / LX1 - */ - { - .name = "ST231aImage", /*Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x24200000 - 1, /*2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /*8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24202000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */ - .end = 0x25580000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Sysaudio Driver - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * STAVEM driver/STAPI - */ - { - .name = "AVMEMPartition0", - .start = 0x00000000, - .end = 0x00480000 - 1, /* 4.5 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * GHW HAL Driver - */ - { - .name = "GraphicsHeap", - .start = 0x22700000, - .end = 0x23500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * multi com buffer area - */ - { - .name = "MulticomSHM", - .start = 0x23700000, - .end = 0x23720000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * DMA Ring buffer (don't need recording buffers) - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Display bins buffer for unit0 - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * Display bins buffer for unit1 - */ - { - .name = "DisplayBins1", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * AVFS: player HAL memory - * - * - */ - { - .name = "AvfsDmaMem", - .start = 0x00000000, - .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_MEM, - }, - /* - * PMEM - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Smartcard - */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * NAND Flash - */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE + 0x400 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Synopsys GMAC Memory Region - */ - { - .name = "GMAC", - .start = 0x00000000, - .end = 0x00010000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Add other resources here - */ - { }, -}; diff --git a/trunk/arch/mips/powertv/asic/prealloc-cronus.c b/trunk/arch/mips/powertv/asic/prealloc-cronus.c deleted file mode 100644 index 45a5c3ea718c..000000000000 --- a/trunk/arch/mips/powertv/asic/prealloc-cronus.c +++ /dev/null @@ -1,608 +0,0 @@ -/* - * Memory pre-allocations for Cronus boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef - */ - -#include -#include - -/* - * DVR_CAPABLE CRONUS RESOURCES - */ -struct resource dvr_cronus_resources[] __initdata = -{ - /* - * - * VIDEO1 / LX1 - * - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x241FFFFF, /* 2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24201FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, - /* - * - * VIDEO2 / LX2 - * - */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, - /* - * - * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * - * STAVEM driver/STAPI - * - * This driver requires: - * - * Arbitrary Based Buffers: - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - * - */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x64180000 - 1, /* 12 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * - */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x00280000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * - */ - { - .name = "DisplayBins1", - .start = 0x64AD4000, - .end = 0x64AD5000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * ITFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "ITFS", - .start = 0x64180000, - /* 815,104 bytes each for 2 ITFS partitions. */ - .end = 0x6430DFFF, - .flags = IORESOURCE_IO, - }, - /* - * - * AVFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "AvfsDmaMem", - .start = 0x6430E000, - /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ - .end = 0x64AD0000 - 1, - .flags = IORESOURCE_IO, - }, - { - .name = "AvfsFileSys", - .start = 0x64AD0000, - .end = 0x64AD1000 - 1, /* 4K */ - .flags = IORESOURCE_IO, - }, - /* - * - * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * - */ - { - .name = "SmartCardInfo", - .start = 0x64AD1000, - .end = 0x64AD3800 - 1, - .flags = IORESOURCE_IO, - }, - /* - * - * KAVNET - * NP Reset Vector - must be of the form xxCxxxxx - * NP Image - must be video bank 1 - * NP IPC - must be video bank 2 - */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, - /* - * Add other resources here - */ - { }, -}; - -/* - * NON_DVR_CAPABLE CRONUS RESOURCES - */ -struct resource non_dvr_cronus_resources[] __initdata = -{ - /* - * - * VIDEO1 / LX1 - * - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x24000000, - .end = 0x241FFFFF, /* 2MiB */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x24200000, - .end = 0x24201FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "MediaMemory1", - .start = 0x24202000, - .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_MEM, - }, - /* - * - * VIDEO2 / LX2 - * - */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, - /* - * - * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * - * STAVEM driver/STAPI - * - * This driver requires: - * - * Arbitrary Based Buffers: - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - * - */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x64180000 - 1, /* 12 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * - */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * - */ - { - .name = "DisplayBins1", - .start = 0x64AD4000, - .end = 0x64AD5000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * AVFS: player HAL memory - * - * - */ - { - .name = "AvfsDmaMem", - .start = 0x6430E000, - .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_IO, - }, - /* - * - * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * - */ - { - .name = "SmartCardInfo", - .start = 0x64AD1000, - .end = 0x64AD3800 - 1, - .flags = IORESOURCE_IO, - }, - /* - * - * KAVNET - * NP Reset Vector - must be of the form xxCxxxxx - * NP Image - must be video bank 1 - * NP IPC - must be video bank 2 - */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, - { }, -}; diff --git a/trunk/arch/mips/powertv/asic/prealloc-cronuslite.c b/trunk/arch/mips/powertv/asic/prealloc-cronuslite.c deleted file mode 100644 index 23a905613c04..000000000000 --- a/trunk/arch/mips/powertv/asic/prealloc-cronuslite.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Memory pre-allocations for Cronus Lite boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef - */ - -#include -#include - -/* - * NON_DVR_CAPABLE CRONUSLITE RESOURCES - */ -struct resource non_dvr_cronuslite_resources[] __initdata = -{ - /* - * - * VIDEO2 / LX2 - * - */ - { - .name = "ST231aImage", /* Delta-Mu 2 image and ram */ - .start = 0x60000000, - .end = 0x601FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231b monitor */ - .start = 0x60200000, - .end = 0x60201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory1", - .start = 0x60202000, - .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, - /* - * - * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * - * STAVEM driver/STAPI - * - * This driver requires: - * - * Arbitrary Based Buffers: - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - * - */ - { - .name = "AVMEMPartition0", - .start = 0x63580000, - .end = 0x63B80000 - 1, /* 6 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "Docsis", - .start = 0x62000000, - .end = 0x62700000 - 1, /* 7 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * - */ - { - .name = "GraphicsHeap", - .start = 0x62700000, - .end = 0x63500000 - 1, /* 14 MB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "MulticomSHM", - .start = 0x26000000, - .end = 0x26020000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x000AA000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * - */ - { - .name = "DisplayBins1", - .start = 0x63B83000, - .end = 0x63B84000 - 1, /* 4 KB total */ - .flags = IORESOURCE_IO, - }, - /* - * - * AVFS: player HAL memory - * - * - */ - { - .name = "AvfsDmaMem", - .start = 0x63B84000, - .end = 0x63E48C00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_IO, - }, - /* - * - * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * - */ - { - .name = "SmartCardInfo", - .start = 0x63B80000, - .end = 0x63B82800 - 1, - .flags = IORESOURCE_IO, - }, - /* - * - * KAVNET - * NP Reset Vector - must be of the form xxCxxxxx - * NP Image - must be video bank 1 - * NP IPC - must be video bank 2 - */ - { - .name = "NP_Reset_Vector", - .start = 0x27c00000, - .end = 0x27c01000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_Image", - .start = 0x27020000, - .end = 0x27060000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "NP_IPC", - .start = 0x63500000, - .end = 0x63580000 - 1, - .flags = IORESOURCE_IO, - }, - /* - * NAND Flash - */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE + 0x400 - 1, - .flags = IORESOURCE_IO, - }, - /* - * Add other resources here - */ - { }, -}; diff --git a/trunk/arch/mips/powertv/asic/prealloc-zeus.c b/trunk/arch/mips/powertv/asic/prealloc-zeus.c deleted file mode 100644 index 018d4514dbe3..000000000000 --- a/trunk/arch/mips/powertv/asic/prealloc-zeus.c +++ /dev/null @@ -1,459 +0,0 @@ -/* - * Memory pre-allocations for Zeus boxes. - * - * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: Ken Eppinett - * David Schleef - */ - -#include -#include - -/* - * DVR_CAPABLE RESOURCES - */ -struct resource dvr_zeus_resources[] __initdata = -{ - /* - * - * VIDEO1 / LX1 - * - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x20000000, - .end = 0x201FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x20200000, - .end = 0x20201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory1", - .start = 0x20202000, - .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, - /* - * - * VIDEO2 / LX2 - * - */ - { - .name = "ST231bImage", /* Delta-Mu 2 image and ram */ - .start = 0x30000000, - .end = 0x301FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ - .start = 0x30200000, - .end = 0x30201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory2", - .start = 0x30202000, - .end = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, - /* - * - * Sysaudio Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * DSP_Image_Buff - DSP code and data images (1MB) - * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) - * ADSC_AUX_Buff - ADSC AUX buffer (16KB) - * ADSC_Main_Buff - ADSC Main buffer (16KB) - * - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * - * STAVEM driver/STAPI - * - * This driver requires: - * - * Arbitrary Based Buffers: - * This memory area is used for allocating buffers for Video decoding - * purposes. Allocation/De-allocation within this buffer is managed - * by the STAVMEM driver of the STAPI. They could be Decimated - * Picture Buffers, Intermediate Buffers, as deemed necessary for - * video decoding purposes, for any video decoders on Zeus. - * - */ - { - .name = "AVMEMPartition0", - .start = 0x00000000, - .end = 0x00c00000 - 1, /* 12 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * DOCSIS Subsystem - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "Docsis", - .start = 0x40100000, - .end = 0x407fffff, - .flags = IORESOURCE_MEM, - }, - /* - * - * GHW HAL Driver - * - * This driver requires: - * - * Arbitrary Based Buffers: - * GraphicsHeap - PowerTV Graphics Heap - * - */ - { - .name = "GraphicsHeap", - .start = 0x46900000, - .end = 0x47700000 - 1, /* 14 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * multi com buffer area - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "MulticomSHM", - .start = 0x47900000, - .end = 0x47920000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * DMA Ring buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x00280000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer for unit0 - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit0 - * - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * Display bins buffer - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Display Bins for unit1 - * - */ - { - .name = "DisplayBins1", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * ITFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "ITFS", - .start = 0x00000000, - /* 815,104 bytes each for 2 ITFS partitions. */ - .end = 0x0018DFFF, - .flags = IORESOURCE_MEM, - }, - /* - * - * AVFS - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Docsis - - * - */ - { - .name = "AvfsDmaMem", - .start = 0x00000000, - /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ - .end = 0x007c2000 - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "AvfsFileSys", - .start = 0x00000000, - .end = 0x00001000 - 1, /* 4K */ - .flags = IORESOURCE_MEM, - }, - /* - * - * PMEM - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Persistent memory for diagnostics. - * - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * - * Smartcard - * - * This driver requires: - * - * Arbitrary Based Buffers: - * Read and write buffers for Internal/External cards - * - */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Add other resources here - */ - { }, -}; - -/* - * NON_DVR_CAPABLE ZEUS RESOURCES - */ -struct resource non_dvr_zeus_resources[] __initdata = -{ - /* - * VIDEO1 / LX1 - */ - { - .name = "ST231aImage", /* Delta-Mu 1 image and ram */ - .start = 0x20000000, - .end = 0x201FFFFF, /* 2MiB */ - .flags = IORESOURCE_IO, - }, - { - .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ - .start = 0x20200000, - .end = 0x20201FFF, - .flags = IORESOURCE_IO, - }, - { - .name = "MediaMemory1", - .start = 0x20202000, - .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ - .flags = IORESOURCE_IO, - }, - /* - * Sysaudio Driver - */ - { - .name = "DSP_Image_Buff", - .start = 0x00000000, - .end = 0x000FFFFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_CPU_PCM_Buff", - .start = 0x00000000, - .end = 0x00009FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_AUX_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - { - .name = "ADSC_Main_Buff", - .start = 0x00000000, - .end = 0x00003FFF, - .flags = IORESOURCE_MEM, - }, - /* - * STAVEM driver/STAPI - */ - { - .name = "AVMEMPartition0", - .start = 0x00000000, - .end = 0x00600000 - 1, /* 6 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * DOCSIS Subsystem - */ - { - .name = "Docsis", - .start = 0x40100000, - .end = 0x407fffff, - .flags = IORESOURCE_MEM, - }, - /* - * GHW HAL Driver - */ - { - .name = "GraphicsHeap", - .start = 0x46900000, - .end = 0x47700000 - 1, /* 14 MB total */ - .flags = IORESOURCE_MEM, - }, - /* - * multi com buffer area - */ - { - .name = "MulticomSHM", - .start = 0x47900000, - .end = 0x47920000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * DMA Ring buffer - */ - { - .name = "BMM_Buffer", - .start = 0x00000000, - .end = 0x00280000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Display bins buffer for unit0 - */ - { - .name = "DisplayBins0", - .start = 0x00000000, - .end = 0x00000FFF, /* 4 KB total */ - .flags = IORESOURCE_MEM, - }, - /* - * - * AVFS: player HAL memory - * - * - */ - { - .name = "AvfsDmaMem", - .start = 0x00000000, - .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ - .flags = IORESOURCE_MEM, - }, - /* - * PMEM - */ - { - .name = "DiagPersistentMemory", - .start = 0x00000000, - .end = 0x10000 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * Smartcard - */ - { - .name = "SmartCardInfo", - .start = 0x00000000, - .end = 0x2800 - 1, - .flags = IORESOURCE_MEM, - }, - /* - * NAND Flash - */ - { - .name = "NandFlash", - .start = NAND_FLASH_BASE, - .end = NAND_FLASH_BASE + 0x400 - 1, - .flags = IORESOURCE_IO, - }, - /* - * Add other resources here - */ - { }, -}; diff --git a/trunk/arch/mips/powertv/cmdline.c b/trunk/arch/mips/powertv/cmdline.c deleted file mode 100644 index 98d73cb0d452..000000000000 --- a/trunk/arch/mips/powertv/cmdline.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Kernel command line creation using the prom monitor (YAMON) argc/argv. - */ -#include -#include - -#include - -#include "init.h" - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension. - */ -#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) - -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - -void __init prom_init_cmdline(void) -{ - int len; - - if (prom_argc != 1) - return; - - len = strlen(arcs_cmdline); - - arcs_cmdline[len] = ' '; - - strlcpy(arcs_cmdline + len + 1, (char *)_prom_argv, - COMMAND_LINE_SIZE - len - 1); -} diff --git a/trunk/arch/mips/powertv/init.c b/trunk/arch/mips/powertv/init.c deleted file mode 100644 index 5f4e4c304e48..000000000000 --- a/trunk/arch/mips/powertv/init.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * PROM library initialisation code. - */ -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "init.h" - -int prom_argc; -int *_prom_argv, *_prom_envp; -unsigned long _prom_memsize; - -/* - * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. - * This macro take care of sign extension, if running in 64-bit mode. - */ -#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) - -char *prom_getenv(char *envname) -{ - char *result = NULL; - - if (_prom_envp != NULL) { - /* - * Return a pointer to the given environment variable. - * In 64-bit mode: we're using 64-bit pointers, but all pointers - * in the PROM structures are only 32-bit, so we need some - * workarounds, if we are running in 64-bit mode. - */ - int i, index = 0; - - i = strlen(envname); - - while (prom_envp(index)) { - if (strncmp(envname, prom_envp(index), i) == 0) { - result = prom_envp(index + 1); - break; - } - index += 2; - } - } - - return result; -} - -/* TODO: Verify on linux-mips mailing list that the following two */ -/* functions are correct */ -/* TODO: Copy NMI and EJTAG exception vectors to memory from the */ -/* BootROM exception vectors. Flush their cache entries. test it. */ - -static void __init mips_nmi_setup(void) -{ - void *base; -#if defined(CONFIG_CPU_MIPS32_R1) - base = cpu_has_veic ? - (void *)(CAC_BASE + 0xa80) : - (void *)(CAC_BASE + 0x380); -#elif defined(CONFIG_CPU_MIPS32_R2) - base = (void *)0xbfc00000; -#else -#error NMI exception handler address not defined -#endif -} - -static void __init mips_ejtag_setup(void) -{ - void *base; - -#if defined(CONFIG_CPU_MIPS32_R1) - base = cpu_has_veic ? - (void *)(CAC_BASE + 0xa00) : - (void *)(CAC_BASE + 0x300); -#elif defined(CONFIG_CPU_MIPS32_R2) - base = (void *)0xbfc00480; -#else -#error EJTAG exception handler address not defined -#endif -} - -void __init prom_init(void) -{ - prom_argc = fw_arg0; - _prom_argv = (int *) fw_arg1; - _prom_envp = (int *) fw_arg2; - _prom_memsize = (unsigned long) fw_arg3; - - board_nmi_handler_setup = mips_nmi_setup; - board_ejtag_handler_setup = mips_ejtag_setup; - - pr_info("\nLINUX started...\n"); - prom_init_cmdline(); - configure_platform(); - prom_meminit(); - -#ifndef CONFIG_BOOTLOADER_DRIVER - pr_info("\nBootloader driver isn't loaded...\n"); -#endif -} diff --git a/trunk/arch/mips/powertv/init.h b/trunk/arch/mips/powertv/init.h deleted file mode 100644 index 7af6bf25008c..000000000000 --- a/trunk/arch/mips/powertv/init.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Definitions from powertv init.c file - * - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn - */ - -#ifndef _POWERTV_INIT_H -#define _POWERTV_INIT_H -extern int prom_argc; -extern int *_prom_argv; -extern unsigned long _prom_memsize; -#endif diff --git a/trunk/arch/mips/powertv/memory.c b/trunk/arch/mips/powertv/memory.c deleted file mode 100644 index 28d06605fff6..000000000000 --- a/trunk/arch/mips/powertv/memory.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * Apparently originally from arch/mips/malta-memory.c. Modified to work - * with the PowerTV bootloader. - */ -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "init.h" - -/* Memory constants */ -#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ -#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ -#define DEFAULT_MEMSIZE MEBIBYTE(256) /* If no memsize provided */ -#define LOW_MEM_MAX MEBIBYTE(252) /* Max usable low mem */ -#define RES_BOOTLDR_MEMSIZE MEBIBYTE(1) /* Memory reserved for bldr */ -#define BOOT_MEM_SIZE KIBIBYTE(256) /* Memory reserved for bldr */ -#define PHYS_MEM_START 0x10000000 /* Start of physical memory */ - -unsigned long ptv_memsize; - -char __initdata cmdline[COMMAND_LINE_SIZE]; - -void __init prom_meminit(void) -{ - char *memsize_str; - unsigned long memsize = 0; - unsigned int physend; - char *ptr; - int low_mem; - int high_mem; - - /* Check the command line first for a memsize directive */ - strcpy(cmdline, arcs_cmdline); - ptr = strstr(cmdline, "memsize="); - if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) - ptr = strstr(ptr, " memsize="); - - if (ptr) { - memsize = memparse(ptr + 8, &ptr); - } else { - /* otherwise look in the environment */ - memsize_str = prom_getenv("memsize"); - - if (memsize_str != NULL) { - pr_info("prom memsize = %s\n", memsize_str); - memsize = simple_strtol(memsize_str, NULL, 0); - } - - if (memsize == 0) { - if (_prom_memsize != 0) { - memsize = _prom_memsize; - pr_info("_prom_memsize = 0x%lx\n", memsize); - /* add in memory that the bootloader doesn't - * report */ - memsize += BOOT_MEM_SIZE; - } else { - memsize = DEFAULT_MEMSIZE; - pr_info("Memsize not passed by bootloader, " - "defaulting to 0x%lx\n", memsize); - } - } - } - - /* Store memsize for diagnostic purposes */ - ptv_memsize = memsize; - - physend = PFN_ALIGN(&_end) - 0x80000000; - if (memsize > LOW_MEM_MAX) { - low_mem = LOW_MEM_MAX; - high_mem = memsize - low_mem; - } else { - low_mem = memsize; - high_mem = 0; - } - -/* - * TODO: We will use the hard code for memory configuration until - * the bootloader releases their device tree to us. - */ - /* - * Add the memory reserved for use by the bootloader to the - * memory map. - */ - add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE, - BOOT_MEM_RESERVED); -#ifdef CONFIG_HIGHMEM_256_128 - /* - * Add memory in low for general use by the kernel and its friends - * (like drivers, applications, etc). - */ - add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, - LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); - /* - * Add the memory reserved for reset vector. - */ - add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); - /* - * Add the memory reserved. - */ - add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED); - /* - * Add memory in high for general use by the kernel and its friends - * (like drivers, applications, etc). - * - * 75MB is reserved for devices which are using the memory in high. - */ - add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75), - BOOT_MEM_RAM); -#elif defined CONFIG_HIGHMEM_128_128 - /* - * Add memory in low for general use by the kernel and its friends - * (like drivers, applications, etc). - */ - add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, - MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); - /* - * Add the memory reserved. - */ - add_memory_region(PHYS_MEM_START + MEBIBYTE(128), - MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED); - /* - * Add memory in high for general use by the kernel and its friends - * (like drivers, applications, etc). - * - * 75MB is reserved for devices which are using the memory in high. - */ - add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75), - BOOT_MEM_RAM); -#else - /* Add low memory regions for either: - * - no-highmemory configuration case -OR- - * - highmemory "HIGHMEM_LOWBANK_ONLY" case - */ - /* - * Add memory for general use by the kernel and its friends - * (like drivers, applications, etc). - */ - add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, - low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); - /* - * Add the memory reserved for reset vector. - */ - add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); -#endif -} - -void __init prom_free_prom_memory(void) -{ - unsigned long addr; - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) - continue; - - addr = boot_mem_map.map[i].addr; - free_init_pages("prom memory", - addr, addr + boot_mem_map.map[i].size); - } -} diff --git a/trunk/arch/mips/powertv/pci/Makefile b/trunk/arch/mips/powertv/pci/Makefile deleted file mode 100644 index f5c62462fc9d..000000000000 --- a/trunk/arch/mips/powertv/pci/Makefile +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (C) 2009 Scientific-Atlanta, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# - -obj-$(CONFIG_PCI) += fixup-powertv.o - -EXTRA_CFLAGS += -Wall -Werror diff --git a/trunk/arch/mips/powertv/pci/fixup-powertv.c b/trunk/arch/mips/powertv/pci/fixup-powertv.c deleted file mode 100644 index 726bc2e824b3..000000000000 --- a/trunk/arch/mips/powertv/pci/fixup-powertv.c +++ /dev/null @@ -1,36 +0,0 @@ -#include -#include -#include -#include "powertv-pci.h" - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return asic_pcie_map_irq(dev, slot, pin); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -/* - * asic_pcie_map_irq - * - * Parameters: - * *dev - pointer to a pci_dev structure (not used) - * slot - slot number (not used) - * pin - pin number (not used) - * - * Return Value: - * Returns: IRQ number (always the PCI Express IRQ number) - * - * Description: - * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt. - * - */ -int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return irq_pciexp; -} -EXPORT_SYMBOL(asic_pcie_map_irq); diff --git a/trunk/arch/mips/powertv/pci/powertv-pci.h b/trunk/arch/mips/powertv/pci/powertv-pci.h deleted file mode 100644 index 1b5886bbd759..000000000000 --- a/trunk/arch/mips/powertv/pci/powertv-pci.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * powertv-pci.c - * - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -/* - * Local definitions for the powertv PCI code - */ - -#ifndef _POWERTV_PCI_POWERTV_PCI_H_ -#define _POWERTV_PCI_POWERTV_PCI_H_ -extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); -extern int asic_pcie_init(void); -extern int asic_pcie_init(void); - -extern int log_level; -#endif diff --git a/trunk/arch/mips/powertv/powertv-clock.h b/trunk/arch/mips/powertv/powertv-clock.h deleted file mode 100644 index d94c54311485..000000000000 --- a/trunk/arch/mips/powertv/powertv-clock.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn - */ - -#ifndef _POWERTV_POWERTV_CLOCK_H -#define _POWERTV_POWERTV_CLOCK_H -extern int powertv_clockevent_init(void); -extern void powertv_clocksource_init(void); -extern unsigned int mips_get_pll_freq(void); -#endif diff --git a/trunk/arch/mips/powertv/powertv_setup.c b/trunk/arch/mips/powertv/powertv_setup.c deleted file mode 100644 index bd8ebf128f29..000000000000 --- a/trunk/arch/mips/powertv/powertv_setup.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "reset.h" - -#define VAL(n) STR(n) - -/* - * Macros for loading addresses and storing registers: - * PTR_LA Load the address into a register - * LONG_S Store the full width of the given register. - * LONG_L Load the full width of the given register - * PTR_ADDIU Add a constant value to a register used as a pointer - * REG_SIZE Number of 8-bit bytes in a full width register - */ -#ifdef CONFIG_64BIT -#warning TODO: 64-bit code needs to be verified -#define PTR_LA "dla " -#define LONG_S "sd " -#define LONG_L "ld " -#define PTR_ADDIU "daddiu " -#define REG_SIZE "8" /* In bytes */ -#endif - -#ifdef CONFIG_32BIT -#define PTR_LA "la " -#define LONG_S "sw " -#define LONG_L "lw " -#define PTR_ADDIU "addiu " -#define REG_SIZE "4" /* In bytes */ -#endif - -static struct pt_regs die_regs; -static bool have_die_regs; - -static void register_panic_notifier(void); -static int panic_handler(struct notifier_block *notifier_block, - unsigned long event, void *cause_string); - -const char *get_system_type(void) -{ - return "PowerTV"; -} - -void __init plat_mem_setup(void) -{ - panic_on_oops = 1; - register_panic_notifier(); - -#if 0 - mips_pcibios_init(); -#endif - mips_reboot_setup(); -} - -/* - * Install a panic notifier for platform-specific diagnostics - */ -static void register_panic_notifier() -{ - static struct notifier_block panic_notifier = { - .notifier_call = panic_handler, - .next = NULL, - .priority = INT_MAX - }; - atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier); -} - -static int panic_handler(struct notifier_block *notifier_block, - unsigned long event, void *cause_string) -{ - struct pt_regs my_regs; - - /* Save all of the registers */ - { - unsigned long at, v0, v1; /* Must be on the stack */ - - /* Start by saving $at and v0 on the stack. We use $at - * ourselves, but it looks like the compiler may use v0 or v1 - * to load the address of the pt_regs structure. We'll come - * back later to store the registers in the pt_regs - * structure. */ - __asm__ __volatile__ ( - ".set noat\n" - LONG_S "$at, %[at]\n" - LONG_S "$2, %[v0]\n" - LONG_S "$3, %[v1]\n" - : - [at] "=m" (at), - [v0] "=m" (v0), - [v1] "=m" (v1) - : - : "at" - ); - - __asm__ __volatile__ ( - ".set noat\n" - "move $at, %[pt_regs]\n" - - /* Argument registers */ - LONG_S "$4, " VAL(PT_R4) "($at)\n" - LONG_S "$5, " VAL(PT_R5) "($at)\n" - LONG_S "$6, " VAL(PT_R6) "($at)\n" - LONG_S "$7, " VAL(PT_R7) "($at)\n" - - /* Temporary regs */ - LONG_S "$8, " VAL(PT_R8) "($at)\n" - LONG_S "$9, " VAL(PT_R9) "($at)\n" - LONG_S "$10, " VAL(PT_R10) "($at)\n" - LONG_S "$11, " VAL(PT_R11) "($at)\n" - LONG_S "$12, " VAL(PT_R12) "($at)\n" - LONG_S "$13, " VAL(PT_R13) "($at)\n" - LONG_S "$14, " VAL(PT_R14) "($at)\n" - LONG_S "$15, " VAL(PT_R15) "($at)\n" - - /* "Saved" registers */ - LONG_S "$16, " VAL(PT_R16) "($at)\n" - LONG_S "$17, " VAL(PT_R17) "($at)\n" - LONG_S "$18, " VAL(PT_R18) "($at)\n" - LONG_S "$19, " VAL(PT_R19) "($at)\n" - LONG_S "$20, " VAL(PT_R20) "($at)\n" - LONG_S "$21, " VAL(PT_R21) "($at)\n" - LONG_S "$22, " VAL(PT_R22) "($at)\n" - LONG_S "$23, " VAL(PT_R23) "($at)\n" - - /* Add'l temp regs */ - LONG_S "$24, " VAL(PT_R24) "($at)\n" - LONG_S "$25, " VAL(PT_R25) "($at)\n" - - /* Kernel temp regs */ - LONG_S "$26, " VAL(PT_R26) "($at)\n" - LONG_S "$27, " VAL(PT_R27) "($at)\n" - - /* Global pointer, stack pointer, frame pointer and - * return address */ - LONG_S "$gp, " VAL(PT_R28) "($at)\n" - LONG_S "$sp, " VAL(PT_R29) "($at)\n" - LONG_S "$fp, " VAL(PT_R30) "($at)\n" - LONG_S "$ra, " VAL(PT_R31) "($at)\n" - - /* Now we can get the $at and v0 registers back and - * store them */ - LONG_L "$8, %[at]\n" - LONG_S "$8, " VAL(PT_R1) "($at)\n" - LONG_L "$8, %[v0]\n" - LONG_S "$8, " VAL(PT_R2) "($at)\n" - LONG_L "$8, %[v1]\n" - LONG_S "$8, " VAL(PT_R3) "($at)\n" - : - : - [at] "m" (at), - [v0] "m" (v0), - [v1] "m" (v1), - [pt_regs] "r" (&my_regs) - : "at", "t0" - ); - - /* Set the current EPC value to be the current location in this - * function */ - __asm__ __volatile__ ( - ".set noat\n" - "1:\n" - PTR_LA "$at, 1b\n" - LONG_S "$at, %[cp0_epc]\n" - : - [cp0_epc] "=m" (my_regs.cp0_epc) - : - : "at" - ); - - my_regs.cp0_cause = read_c0_cause(); - my_regs.cp0_status = read_c0_status(); - } - -#ifdef CONFIG_DIAGNOSTICS - failure_report((char *) cause_string, - have_die_regs ? &die_regs : &my_regs); - have_die_regs = false; -#else - pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " - "zzzz... \n"); -#endif - - return NOTIFY_DONE; -} - -/** - * Platform-specific handling of oops - * @str: Pointer to the oops string - * @regs: Pointer to the oops registers - * All we do here is to save the registers for subsequent printing through - * the panic notifier. - */ -void platform_die(const char *str, const struct pt_regs *regs) -{ - /* If we already have saved registers, don't overwrite them as they - * they apply to the initial fault */ - - if (!have_die_regs) { - have_die_regs = true; - die_regs = *regs; - } -} - -/* Information about the RF MAC address, if one was supplied on the - * command line. */ -static bool have_rfmac; -static u8 rfmac[ETH_ALEN]; - -static int rfmac_param(char *p) -{ - u8 *q; - bool is_high_nibble; - int c; - - /* Skip a leading "0x", if present */ - if (*p == '0' && *(p+1) == 'x') - p += 2; - - q = rfmac; - is_high_nibble = true; - - for (c = (unsigned char) *p++; - isxdigit(c) && q - rfmac < ETH_ALEN; - c = (unsigned char) *p++) { - int nibble; - - nibble = (isdigit(c) ? (c - '0') : - (isupper(c) ? c - 'A' + 10 : c - 'a' + 10)); - - if (is_high_nibble) - *q = nibble << 4; - else - *q++ |= nibble; - - is_high_nibble = !is_high_nibble; - } - - /* If we parsed all the way to the end of the parameter value and - * parsed all ETH_ALEN bytes, we have a usable RF MAC address */ - have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN); - - return 0; -} - -early_param("rfmac", rfmac_param); - -/* - * Generate an Ethernet MAC address that has a good chance of being unique. - * @addr: Pointer to six-byte array containing the Ethernet address - * Generates an Ethernet MAC address that is highly likely to be unique for - * this particular system on a network with other systems of the same type. - * - * The problem we are solving is that, when random_ether_addr() is used to - * generate MAC addresses at startup, there isn't much entropy for the random - * number generator to use and the addresses it produces are fairly likely to - * be the same as those of other identical systems on the same local network. - * This is true even for relatively small numbers of systems (for the reason - * why, see the Wikipedia entry for "Birthday problem" at: - * http://en.wikipedia.org/wiki/Birthday_problem - * - * The good news is that we already have a MAC address known to be unique, the - * RF MAC address. The bad news is that this address is already in use on the - * RF interface. Worse, the obvious trick, taking the RF MAC address and - * turning on the locally managed bit, has already been used for other devices. - * Still, this does give us something to work with. - * - * The approach we take is: - * 1. If we can't get the RF MAC Address, just call random_ether_addr. - * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24 - * bits of the new address. This is very likely to be unique, except for - * the current box. - * 3. To avoid using addresses already on the current box, we set the top - * six bits of the address with a value different from any currently - * registered Scientific Atlanta organizationally unique identifyer - * (OUI). This avoids duplication with any addresses on the system that - * were generated from valid Scientific Atlanta-registered address by - * simply flipping the locally managed bit. - * 4. We aren't generating a multicast address, so we leave the multicast - * bit off. Since we aren't using a registered address, we have to set - * the locally managed bit. - * 5. We then randomly generate the remaining 16-bits. This does two - * things: - * a. It allows us to call this function for more than one device - * in this system - * b. It ensures that things will probably still work even if - * some device on the device network has a locally managed - * address that matches the top six bits from step 2. - */ -void platform_random_ether_addr(u8 addr[ETH_ALEN]) -{ - const int num_random_bytes = 2; - const unsigned char non_sciatl_oui_bits = 0xc0u; - const unsigned char mac_addr_locally_managed = (1 << 1); - - if (!have_rfmac) { - pr_warning("rfmac not available on command line; " - "generating random MAC address\n"); - random_ether_addr(addr); - } - - else { - int i; - - /* Set the first byte to something that won't match a Scientific - * Atlanta OUI, is locally managed, and isn't a multicast - * address */ - addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed; - - /* Get some bytes of random address information */ - get_random_bytes(&addr[1], num_random_bytes); - - /* Copy over the NIC-specific bits of the RF MAC address */ - for (i = 1 + num_random_bytes; i < ETH_ALEN; i++) - addr[i] = rfmac[i]; - } -} diff --git a/trunk/arch/mips/powertv/reset.c b/trunk/arch/mips/powertv/reset.c deleted file mode 100644 index 494c652c984b..000000000000 --- a/trunk/arch/mips/powertv/reset.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. - * Portions copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#include - -#include -#include /* Not included by linux/reboot.h */ - -#ifdef CONFIG_BOOTLOADER_DRIVER -#include -#endif - -#include -#include "reset.h" - -static void mips_machine_restart(char *command); -static void mips_machine_halt(void); - -static void mips_machine_restart(char *command) -{ -#ifdef CONFIG_BOOTLOADER_DRIVER - /* - * Call the bootloader's reset function to ensure - * that persistent data is flushed before hard reset - */ - kbldr_SetCauseAndReset(); -#else - writel(0x1, asic_reg_addr(watchdog)); -#endif -} - -static void mips_machine_halt(void) -{ -#ifdef CONFIG_BOOTLOADER_DRIVER - /* - * Call the bootloader's reset function to ensure - * that persistent data is flushed before hard reset - */ - kbldr_SetCauseAndReset(); -#else - writel(0x1, asic_reg_addr(watchdog)); -#endif -} - -void mips_reboot_setup(void) -{ - _machine_restart = mips_machine_restart; - _machine_halt = mips_machine_halt; - pm_power_off = mips_machine_halt; -} diff --git a/trunk/arch/mips/powertv/reset.h b/trunk/arch/mips/powertv/reset.h deleted file mode 100644 index 888fd09e2620..000000000000 --- a/trunk/arch/mips/powertv/reset.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Definitions from powertv reset.c file - * - * Copyright (C) 2009 Cisco Systems, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * Author: David VomLehn - */ - -#ifndef _POWERTV_POWERTV_RESET_H -#define _POWERTV_POWERTV_RESET_H -extern void mips_reboot_setup(void); -#endif diff --git a/trunk/arch/mips/rb532/prom.c b/trunk/arch/mips/rb532/prom.c index d7c26d00cfef..ad5bd1097974 100644 --- a/trunk/arch/mips/rb532/prom.c +++ b/trunk/arch/mips/rb532/prom.c @@ -69,7 +69,7 @@ static inline unsigned long tag2ul(char *arg, const char *tag) void __init prom_setup_cmdline(void) { - static char cmd_line[COMMAND_LINE_SIZE] __initdata; + static char cmd_line[CL_SIZE] __initdata; char *cp, *board; int prom_argc; char **prom_argv, **prom_envp; @@ -115,7 +115,7 @@ void __init prom_setup_cmdline(void) strcpy(cp, arcs_cmdline); cp += strlen(arcs_cmdline); } - cmd_line[COMMAND_LINE_SIZE - 1] = '\0'; + cmd_line[CL_SIZE-1] = '\0'; strcpy(arcs_cmdline, cmd_line); } diff --git a/trunk/arch/mips/sgi-ip22/ip22-eisa.c b/trunk/arch/mips/sgi-ip22/ip22-eisa.c index da44ccb20829..1617241d2737 100644 --- a/trunk/arch/mips/sgi-ip22/ip22-eisa.c +++ b/trunk/arch/mips/sgi-ip22/ip22-eisa.c @@ -50,9 +50,9 @@ static char __init *decode_eisa_sig(unsigned long addr) { - static char sig_str[EISA_SIG_LEN] __initdata; + static char sig_str[EISA_SIG_LEN]; u8 sig[4]; - u16 rev; + u16 rev; int i; for (i = 0; i < 4; i++) { diff --git a/trunk/arch/mips/sgi-ip22/ip22-int.c b/trunk/arch/mips/sgi-ip22/ip22-int.c index 383f11d7f442..0ecd5fe9486e 100644 --- a/trunk/arch/mips/sgi-ip22/ip22-int.c +++ b/trunk/arch/mips/sgi-ip22/ip22-int.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include @@ -151,7 +150,7 @@ static void indy_local1_irqdispatch(void) extern void ip22_be_interrupt(int irq); -static void __irq_entry indy_buserror_irq(void) +static void indy_buserror_irq(void) { int irq = SGI_BUSERR_IRQ; diff --git a/trunk/arch/mips/sgi-ip22/ip22-setup.c b/trunk/arch/mips/sgi-ip22/ip22-setup.c index 5deeb68b6c9c..b9a931358e23 100644 --- a/trunk/arch/mips/sgi-ip22/ip22-setup.c +++ b/trunk/arch/mips/sgi-ip22/ip22-setup.c @@ -67,7 +67,7 @@ void __init plat_mem_setup(void) cserial = ArcGetEnvironmentVariable("ConsoleOut"); if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) { - static char options[8] __initdata; + static char options[8]; char *baud = ArcGetEnvironmentVariable("dbaud"); if (baud) strcpy(options, baud); diff --git a/trunk/arch/mips/sgi-ip22/ip22-time.c b/trunk/arch/mips/sgi-ip22/ip22-time.c index 603fc91c1030..c8f7d2328b24 100644 --- a/trunk/arch/mips/sgi-ip22/ip22-time.c +++ b/trunk/arch/mips/sgi-ip22/ip22-time.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include @@ -116,7 +115,7 @@ __init void plat_time_init(void) } /* Generic SGI handler for (spurious) 8254 interrupts */ -void __irq_entry indy_8254timer_irq(void) +void indy_8254timer_irq(void) { int irq = SGI_8254_0_IRQ; ULONG cnt; diff --git a/trunk/arch/mips/sgi-ip32/ip32-setup.c b/trunk/arch/mips/sgi-ip32/ip32-setup.c index 3abd1465ec02..c5a5d4a31b4b 100644 --- a/trunk/arch/mips/sgi-ip32/ip32-setup.c +++ b/trunk/arch/mips/sgi-ip32/ip32-setup.c @@ -90,7 +90,7 @@ void __init plat_mem_setup(void) { char* con = ArcGetEnvironmentVariable("console"); if (con && *con == 'd') { - static char options[8] __initdata; + static char options[8]; char *baud = ArcGetEnvironmentVariable("dbaud"); if (baud) strcpy(options, baud); diff --git a/trunk/arch/mips/sibyte/common/cfe.c b/trunk/arch/mips/sibyte/common/cfe.c index 6343011e9902..eb5396cf81bb 100644 --- a/trunk/arch/mips/sibyte/common/cfe.c +++ b/trunk/arch/mips/sibyte/common/cfe.c @@ -287,7 +287,7 @@ void __init prom_init(void) * boot console */ cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); - if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, COMMAND_LINE_SIZE) < 0) { + if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) { if (argc >= 0) { /* The loader should have set the command line */ /* too early for panic to do any good */ @@ -318,7 +318,7 @@ void __init prom_init(void) #endif /* CONFIG_BLK_DEV_INITRD */ /* Not sure this is needed, but it's the safe way. */ - arcs_cmdline[COMMAND_LINE_SIZE-1] = 0; + arcs_cmdline[CL_SIZE-1] = 0; prom_meminit(); diff --git a/trunk/arch/mips/sni/a20r.c b/trunk/arch/mips/sni/a20r.c index e6980892834a..7dd76fb3b645 100644 --- a/trunk/arch/mips/sni/a20r.c +++ b/trunk/arch/mips/sni/a20r.c @@ -188,7 +188,7 @@ static void end_a20r_irq(unsigned int irq) } static struct irq_chip a20r_irq_type = { - .name = "A20R", + .typename = "A20R", .ack = mask_a20r_irq, .mask = mask_a20r_irq, .mask_ack = mask_a20r_irq, diff --git a/trunk/arch/mips/sni/pcimt.c b/trunk/arch/mips/sni/pcimt.c index 51e62bbaa23b..74e6c67982fb 100644 --- a/trunk/arch/mips/sni/pcimt.c +++ b/trunk/arch/mips/sni/pcimt.c @@ -214,7 +214,7 @@ static void end_pcimt_irq(unsigned int irq) } static struct irq_chip pcimt_irq_type = { - .name = "PCIMT", + .typename = "PCIMT", .ack = disable_pcimt_irq, .mask = disable_pcimt_irq, .mask_ack = disable_pcimt_irq, diff --git a/trunk/arch/mips/sni/pcit.c b/trunk/arch/mips/sni/pcit.c index f4699d35858b..071a9573ac7f 100644 --- a/trunk/arch/mips/sni/pcit.c +++ b/trunk/arch/mips/sni/pcit.c @@ -176,7 +176,7 @@ void end_pcit_irq(unsigned int irq) } static struct irq_chip pcit_irq_type = { - .name = "PCIT", + .typename = "PCIT", .ack = disable_pcit_irq, .mask = disable_pcit_irq, .mask_ack = disable_pcit_irq, diff --git a/trunk/arch/mips/sni/rm200.c b/trunk/arch/mips/sni/rm200.c index 46f00691f448..5e687819cbc2 100644 --- a/trunk/arch/mips/sni/rm200.c +++ b/trunk/arch/mips/sni/rm200.c @@ -449,7 +449,7 @@ void end_rm200_irq(unsigned int irq) } static struct irq_chip rm200_irq_type = { - .name = "RM200", + .typename = "RM200", .ack = disable_rm200_irq, .mask = disable_rm200_irq, .mask_ack = disable_rm200_irq, diff --git a/trunk/arch/mips/sni/setup.c b/trunk/arch/mips/sni/setup.c index d16b462154c3..a49272ce7ef5 100644 --- a/trunk/arch/mips/sni/setup.c +++ b/trunk/arch/mips/sni/setup.c @@ -60,7 +60,7 @@ static void __init sni_console_setup(void) char *cdev; char *baud; int port; - static char options[8] __initdata; + static char options[8]; cdev = prom_getenv("console_dev"); if (strncmp(cdev, "tty", 3) == 0) { diff --git a/trunk/arch/mips/txx9/generic/setup.c b/trunk/arch/mips/txx9/generic/setup.c index 06e801c7e258..d66802edebb2 100644 --- a/trunk/arch/mips/txx9/generic/setup.c +++ b/trunk/arch/mips/txx9/generic/setup.c @@ -160,7 +160,7 @@ static void __init prom_init_cmdline(void) int argc; int *argv32; int i; /* Always ignore the "-c" at argv[0] */ - static char builtin[COMMAND_LINE_SIZE] __initdata; + static char builtin[CL_SIZE] __initdata; if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { /* @@ -315,7 +315,7 @@ static inline void txx9_cache_fixup(void) static void __init preprocess_cmdline(void) { - static char cmdline[COMMAND_LINE_SIZE] __initdata; + static char cmdline[CL_SIZE] __initdata; char *s; strcpy(cmdline, arcs_cmdline); diff --git a/trunk/arch/mn10300/include/asm/asm-offsets.h b/trunk/arch/mn10300/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/mn10300/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/mn10300/include/asm/elf.h b/trunk/arch/mn10300/include/asm/elf.h index e5fa97cd9a14..75a70aa9fd6f 100644 --- a/trunk/arch/mn10300/include/asm/elf.h +++ b/trunk/arch/mn10300/include/asm/elf.h @@ -77,6 +77,7 @@ do { \ _ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \ } while (0) +#define USE_ELF_CORE_DUMP #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 diff --git a/trunk/arch/parisc/hpux/sys_hpux.c b/trunk/arch/parisc/hpux/sys_hpux.c index 92343bd35fa3..18072e03a019 100644 --- a/trunk/arch/parisc/hpux/sys_hpux.c +++ b/trunk/arch/parisc/hpux/sys_hpux.c @@ -445,7 +445,12 @@ int hpux_getdomainname(char __user *name, int len) int hpux_pipe(int *kstack_fildes) { - return do_pipe_flags(kstack_fildes, 0); + int error; + + lock_kernel(); + error = do_pipe_flags(kstack_fildes, 0); + unlock_kernel(); + return error; } /* lies - says it works, but it really didn't lock anything */ diff --git a/trunk/arch/parisc/include/asm/asm-offsets.h b/trunk/arch/parisc/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/parisc/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/parisc/include/asm/bug.h b/trunk/arch/parisc/include/asm/bug.h index 75e46c557a16..8cfc553fc837 100644 --- a/trunk/arch/parisc/include/asm/bug.h +++ b/trunk/arch/parisc/include/asm/bug.h @@ -32,14 +32,14 @@ "\t.popsection" \ : : "i" (__FILE__), "i" (__LINE__), \ "i" (0), "i" (sizeof(struct bug_entry)) ); \ - unreachable(); \ + for(;;) ; \ } while(0) #else #define BUG() \ do { \ asm volatile(PARISC_BUG_BREAK_ASM : : ); \ - unreachable(); \ + for(;;) ; \ } while(0) #endif diff --git a/trunk/arch/parisc/include/asm/elf.h b/trunk/arch/parisc/include/asm/elf.h index 19f6cb1a4a1c..9c802eb4be84 100644 --- a/trunk/arch/parisc/include/asm/elf.h +++ b/trunk/arch/parisc/include/asm/elf.h @@ -328,6 +328,7 @@ struct pt_regs; /* forward declaration... */ such function. */ #define ELF_PLAT_INIT(_r, load_addr) _r->gr[23] = 0 +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/parisc/include/asm/ftrace.h b/trunk/arch/parisc/include/asm/ftrace.h index 72c0fafaa039..2fa05dd6aeee 100644 --- a/trunk/arch/parisc/include/asm/ftrace.h +++ b/trunk/arch/parisc/include/asm/ftrace.h @@ -20,20 +20,6 @@ struct ftrace_ret_stack { * Defined in entry.S */ extern void return_to_handler(void); - - -extern unsigned long return_address(unsigned int); - -#define HAVE_ARCH_CALLER_ADDR - -#define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0)) -#define CALLER_ADDR1 return_address(1) -#define CALLER_ADDR2 return_address(2) -#define CALLER_ADDR3 return_address(3) -#define CALLER_ADDR4 return_address(4) -#define CALLER_ADDR5 return_address(5) -#define CALLER_ADDR6 return_address(6) - #endif /* __ASSEMBLY__ */ #endif /* _ASM_PARISC_FTRACE_H */ diff --git a/trunk/arch/parisc/kernel/asm-offsets.c b/trunk/arch/parisc/kernel/asm-offsets.c index ec787b411e9a..fcd3c707bf12 100644 --- a/trunk/arch/parisc/kernel/asm-offsets.c +++ b/trunk/arch/parisc/kernel/asm-offsets.c @@ -244,6 +244,9 @@ int main(void) DEFINE(THREAD_SZ, sizeof(struct thread_info)); DEFINE(THREAD_SZ_ALGN, align(sizeof(struct thread_info), 64)); BLANK(); + DEFINE(IRQSTAT_SIRQ_PEND, offsetof(irq_cpustat_t, __softirq_pending)); + DEFINE(IRQSTAT_SZ, sizeof(irq_cpustat_t)); + BLANK(); DEFINE(ICACHE_BASE, offsetof(struct pdc_cache_info, ic_base)); DEFINE(ICACHE_STRIDE, offsetof(struct pdc_cache_info, ic_stride)); DEFINE(ICACHE_COUNT, offsetof(struct pdc_cache_info, ic_count)); diff --git a/trunk/arch/parisc/kernel/irq.c b/trunk/arch/parisc/kernel/irq.c index efbcee5d2220..f47465e8d040 100644 --- a/trunk/arch/parisc/kernel/irq.c +++ b/trunk/arch/parisc/kernel/irq.c @@ -145,7 +145,7 @@ static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) #endif static struct irq_chip cpu_interrupt_type = { - .name = "CPU", + .typename = "CPU", .startup = cpu_startup_irq, .shutdown = cpu_disable_irq, .enable = cpu_enable_irq, @@ -192,7 +192,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, "%10u ", kstat_irqs(i)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", irq_desc[i].chip->typename); #ifndef PARISC_IRQ_CR16_COUNTS seq_printf(p, " %s", action->name); diff --git a/trunk/arch/parisc/kernel/signal.c b/trunk/arch/parisc/kernel/signal.c index fb37ac52e46c..e8467e4aa8d1 100644 --- a/trunk/arch/parisc/kernel/signal.c +++ b/trunk/arch/parisc/kernel/signal.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/parisc/kernel/smp.c b/trunk/arch/parisc/kernel/smp.c index 3f2fce8ce6b6..1fd0f0cec037 100644 --- a/trunk/arch/parisc/kernel/smp.c +++ b/trunk/arch/parisc/kernel/smp.c @@ -60,6 +60,8 @@ static int smp_debug_lvl = 0; #define smp_debug(lvl, ...) do { } while(0) #endif /* DEBUG_SMP */ +DEFINE_SPINLOCK(smp_lock); + volatile struct task_struct *smp_init_current_idle_task; /* track which CPU is booting */ @@ -67,7 +69,7 @@ static volatile int cpu_now_booting __cpuinitdata; static int parisc_max_cpus __cpuinitdata = 1; -static DEFINE_PER_CPU(spinlock_t, ipi_lock); +DEFINE_PER_CPU(spinlock_t, ipi_lock) = SPIN_LOCK_UNLOCKED; enum ipi_message_type { IPI_NOP=0, @@ -436,11 +438,6 @@ void __init smp_prepare_boot_cpu(void) */ void __init smp_prepare_cpus(unsigned int max_cpus) { - int cpu; - - for_each_possible_cpu(cpu) - spin_lock_init(&per_cpu(ipi_lock, cpu)); - init_cpu_present(cpumask_of(0)); parisc_max_cpus = max_cpus; diff --git a/trunk/arch/parisc/kernel/sys_parisc32.c b/trunk/arch/parisc/kernel/sys_parisc32.c index 9779ece2b070..76d23ec8dfaa 100644 --- a/trunk/arch/parisc/kernel/sys_parisc32.c +++ b/trunk/arch/parisc/kernel/sys_parisc32.c @@ -26,7 +26,13 @@ #include #include #include +#include #include +#include +#include +#include +#include +#include #include #include #include diff --git a/trunk/arch/parisc/kernel/unwind.c b/trunk/arch/parisc/kernel/unwind.c index d58eac1a8288..a36799e85693 100644 --- a/trunk/arch/parisc/kernel/unwind.c +++ b/trunk/arch/parisc/kernel/unwind.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include @@ -116,18 +115,24 @@ unwind_table_init(struct unwind_table *table, const char *name, } } -static int cmp_unwind_table_entry(const void *a, const void *b) -{ - return ((const struct unwind_table_entry *)a)->region_start - - ((const struct unwind_table_entry *)b)->region_start; -} - static void unwind_table_sort(struct unwind_table_entry *start, struct unwind_table_entry *finish) { - sort(start, finish - start, sizeof(struct unwind_table_entry), - cmp_unwind_table_entry, NULL); + struct unwind_table_entry el, *p, *q; + + for (p = start + 1; p < finish; ++p) { + if (p[0].region_start < p[-1].region_start) { + el = *p; + q = p; + do { + q[0] = q[-1]; + --q; + } while (q > start && + el.region_start < q[-1].region_start); + *q = el; + } + } } struct unwind_table * @@ -412,30 +417,3 @@ int unwind_to_user(struct unwind_frame_info *info) return ret; } - -unsigned long return_address(unsigned int level) -{ - struct unwind_frame_info info; - struct pt_regs r; - unsigned long sp; - - /* initialize unwind info */ - asm volatile ("copy %%r30, %0" : "=r"(sp)); - memset(&r, 0, sizeof(struct pt_regs)); - r.iaoq[0] = (unsigned long) current_text_addr(); - r.gr[2] = (unsigned long) __builtin_return_address(0); - r.gr[30] = sp; - unwind_frame_init(&info, current, &r); - - /* unwind stack */ - ++level; - do { - if (unwind_once(&info) < 0 || info.ip == 0) - return 0; - if (!__kernel_text_address(info.ip)) { - return 0; - } - } while (info.ip && level--); - - return info.ip; -} diff --git a/trunk/arch/powerpc/Kconfig b/trunk/arch/powerpc/Kconfig index ba3948c70072..0df57466e783 100644 --- a/trunk/arch/powerpc/Kconfig +++ b/trunk/arch/powerpc/Kconfig @@ -704,7 +704,7 @@ config PPC_PCI_CHOICE config PCI bool "PCI support" if PPC_PCI_CHOICE default y if !40x && !CPM2 && !8xx && !PPC_83xx \ - && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON + && !PPC_85xx && !PPC_86xx default PCI_PERMEDIA if !4xx && !CPM2 && !8xx default PCI_QSPAN if !4xx && !CPM2 && 8xx select ARCH_SUPPORTS_MSI diff --git a/trunk/arch/powerpc/Kconfig.debug b/trunk/arch/powerpc/Kconfig.debug index 5cdd7ed9a12e..bf3382f1904d 100644 --- a/trunk/arch/powerpc/Kconfig.debug +++ b/trunk/arch/powerpc/Kconfig.debug @@ -254,14 +254,6 @@ config PPC_EARLY_DEBUG_CPM using a CPM-based serial port. This assumes that the bootwrapper has run, and set up the CPM in a particular way. -config PPC_EARLY_DEBUG_USBGECKO - bool "Early debugging through the USB Gecko adapter" - depends on GAMECUBE_COMMON - select USBGECKO_UDBG - help - Select this to enable early debugging for Nintendo GameCube/Wii - consoles via an external USB Gecko adapter. - endchoice config PPC_EARLY_DEBUG_44x_PHYSLOW diff --git a/trunk/arch/powerpc/boot/Makefile b/trunk/arch/powerpc/boot/Makefile index bb2465bcb327..7bfc8ad87798 100644 --- a/trunk/arch/powerpc/boot/Makefile +++ b/trunk/arch/powerpc/boot/Makefile @@ -66,7 +66,7 @@ src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \ gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \ 4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \ cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \ - fsl-soc.c mpc8xx.c pq2.c ugecon.c + fsl-soc.c mpc8xx.c pq2.c src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \ cuboot-ebony.c cuboot-hotfoot.c treeboot-ebony.c prpmc2800.c \ ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \ @@ -76,8 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ - cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \ - gamecube-head.S gamecube.c wii-head.S wii.c + cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -255,8 +254,6 @@ image-$(CONFIG_KSI8560) += cuImage.ksi8560 image-$(CONFIG_STORCENTER) += cuImage.storcenter image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2 image-$(CONFIG_PPC_C2K) += cuImage.c2k -image-$(CONFIG_GAMECUBE) += dtbImage.gamecube -image-$(CONFIG_WII) += dtbImage.wii # Board port in arch/powerpc/platform/amigaone/Kconfig image-$(CONFIG_AMIGAONE) += cuImage.amigaone diff --git a/trunk/arch/powerpc/boot/dts/gamecube.dts b/trunk/arch/powerpc/boot/dts/gamecube.dts deleted file mode 100644 index ef3be0e58b02..000000000000 --- a/trunk/arch/powerpc/boot/dts/gamecube.dts +++ /dev/null @@ -1,114 +0,0 @@ -/* - * arch/powerpc/boot/dts/gamecube.dts - * - * Nintendo GameCube platform device tree source - * Copyright (C) 2007-2009 The GameCube Linux Team - * Copyright (C) 2007,2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -/dts-v1/; - -/ { - model = "nintendo,gamecube"; - compatible = "nintendo,gamecube"; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - bootargs = "root=/dev/gcnsda2 rootwait udbg-immortal"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x01800000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,gekko@0 { - device_type = "cpu"; - reg = <0>; - clock-frequency = <486000000>; /* 486MHz */ - bus-frequency = <162000000>; /* 162MHz core-to-bus 3x */ - timebase-frequency = <40500000>; /* 162MHz / 4 */ - i-cache-line-size = <32>; - d-cache-line-size = <32>; - i-cache-size = <32768>; - d-cache-size = <32768>; - }; - }; - - /* devices contained int the flipper chipset */ - flipper { - #address-cells = <1>; - #size-cells = <1>; - compatible = "nintendo,flipper"; - ranges = <0x0c000000 0x0c000000 0x00010000>; - interrupt-parent = <&PIC>; - - video@0c002000 { - compatible = "nintendo,flipper-vi"; - reg = <0x0c002000 0x100>; - interrupts = <8>; - }; - - processor-interface@0c003000 { - compatible = "nintendo,flipper-pi"; - reg = <0x0c003000 0x100>; - - PIC: pic { - #interrupt-cells = <1>; - compatible = "nintendo,flipper-pic"; - interrupt-controller; - }; - }; - - dsp@0c005000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "nintendo,flipper-dsp"; - reg = <0x0c005000 0x200>; - interrupts = <6>; - - memory@0 { - compatible = "nintendo,flipper-aram"; - reg = <0 0x1000000>; /* 16MB */ - }; - }; - - disk@0c006000 { - compatible = "nintendo,flipper-di"; - reg = <0x0c006000 0x40>; - interrupts = <2>; - }; - - audio@0c006c00 { - compatible = "nintendo,flipper-ai"; - reg = <0x0c006c00 0x20>; - interrupts = <6>; - }; - - gamepad-controller@0c006400 { - compatible = "nintendo,flipper-si"; - reg = <0x0c006400 0x100>; - interrupts = <3>; - }; - - /* External Interface bus */ - exi@0c006800 { - compatible = "nintendo,flipper-exi"; - reg = <0x0c006800 0x40>; - virtual-reg = <0x0c006800>; - interrupts = <4>; - }; - }; -}; - diff --git a/trunk/arch/powerpc/boot/dts/wii.dts b/trunk/arch/powerpc/boot/dts/wii.dts deleted file mode 100644 index 77528c9a8dbd..000000000000 --- a/trunk/arch/powerpc/boot/dts/wii.dts +++ /dev/null @@ -1,218 +0,0 @@ -/* - * arch/powerpc/boot/dts/wii.dts - * - * Nintendo Wii platform device tree source - * Copyright (C) 2008-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -/dts-v1/; - -/* - * This is commented-out for now. - * Until a later patch is merged, the kernel can use only the first - * contiguous RAM range and will BUG() if the memreserve is outside - * that range. - */ -/*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */ - -/ { - model = "nintendo,wii"; - compatible = "nintendo,wii"; - #address-cells = <1>; - #size-cells = <1>; - - chosen { - bootargs = "root=/dev/mmcblk0p2 rootwait udbg-immortal"; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */ - 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */ - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - PowerPC,broadway@0 { - device_type = "cpu"; - reg = <0>; - clock-frequency = <729000000>; /* 729MHz */ - bus-frequency = <243000000>; /* 243MHz core-to-bus 3x */ - timebase-frequency = <60750000>; /* 243MHz / 4 */ - i-cache-line-size = <32>; - d-cache-line-size = <32>; - i-cache-size = <32768>; - d-cache-size = <32768>; - }; - }; - - /* devices contained in the hollywood chipset */ - hollywood { - #address-cells = <1>; - #size-cells = <1>; - compatible = "nintendo,hollywood"; - ranges = <0x0c000000 0x0c000000 0x01000000 - 0x0d000000 0x0d000000 0x00800000 - 0x0d800000 0x0d800000 0x00800000>; - interrupt-parent = <&PIC0>; - - video@0c002000 { - compatible = "nintendo,hollywood-vi", - "nintendo,flipper-vi"; - reg = <0x0c002000 0x100>; - interrupts = <8>; - }; - - processor-interface@0c003000 { - compatible = "nintendo,hollywood-pi", - "nintendo,flipper-pi"; - reg = <0x0c003000 0x100>; - - PIC0: pic0 { - #interrupt-cells = <1>; - compatible = "nintendo,flipper-pic"; - interrupt-controller; - }; - }; - - dsp@0c005000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "nintendo,hollywood-dsp", - "nintendo,flipper-dsp"; - reg = <0x0c005000 0x200>; - interrupts = <6>; - }; - - gamepad-controller@0d006400 { - compatible = "nintendo,hollywood-si", - "nintendo,flipper-si"; - reg = <0x0d006400 0x100>; - interrupts = <3>; - }; - - audio@0c006c00 { - compatible = "nintendo,hollywood-ai", - "nintendo,flipper-ai"; - reg = <0x0d006c00 0x20>; - interrupts = <6>; - }; - - /* External Interface bus */ - exi@0d006800 { - compatible = "nintendo,hollywood-exi", - "nintendo,flipper-exi"; - reg = <0x0d006800 0x40>; - virtual-reg = <0x0d006800>; - interrupts = <4>; - }; - - usb@0d040000 { - compatible = "nintendo,hollywood-usb-ehci", - "usb-ehci"; - reg = <0x0d040000 0x100>; - interrupts = <4>; - interrupt-parent = <&PIC1>; - }; - - usb@0d050000 { - compatible = "nintendo,hollywood-usb-ohci", - "usb-ohci"; - reg = <0x0d050000 0x100>; - interrupts = <5>; - interrupt-parent = <&PIC1>; - }; - - usb@0d060000 { - compatible = "nintendo,hollywood-usb-ohci", - "usb-ohci"; - reg = <0x0d060000 0x100>; - interrupts = <6>; - interrupt-parent = <&PIC1>; - }; - - sd@0d070000 { - compatible = "nintendo,hollywood-sdhci", - "sdhci"; - reg = <0x0d070000 0x200>; - interrupts = <7>; - interrupt-parent = <&PIC1>; - }; - - sdio@0d080000 { - compatible = "nintendo,hollywood-sdhci", - "sdhci"; - reg = <0x0d080000 0x200>; - interrupts = <8>; - interrupt-parent = <&PIC1>; - }; - - ipc@0d000000 { - compatible = "nintendo,hollywood-ipc"; - reg = <0x0d000000 0x10>; - interrupts = <30>; - interrupt-parent = <&PIC1>; - }; - - PIC1: pic1@0d800030 { - #interrupt-cells = <1>; - compatible = "nintendo,hollywood-pic"; - reg = <0x0d800030 0x10>; - interrupt-controller; - interrupts = <14>; - }; - - GPIO: gpio@0d8000c0 { - #gpio-cells = <2>; - compatible = "nintendo,hollywood-gpio"; - reg = <0x0d8000c0 0x40>; - gpio-controller; - - /* - * This is commented out while a standard binding - * for i2c over gpio is defined. - */ - /* - i2c-video { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - - gpios = <&GPIO 15 0 - &GPIO 14 0>; - clock-frequency = <250000>; - no-clock-stretching; - scl-is-open-drain; - sda-is-open-drain; - sda-enforce-dir; - - AVE: audio-video-encoder@70 { - compatible = "nintendo,wii-audio-video-encoder"; - reg = <0x70>; - }; - }; - */ - }; - - control@0d800100 { - compatible = "nintendo,hollywood-control"; - reg = <0x0d800100 0x300>; - }; - - disk@0d806000 { - compatible = "nintendo,hollywood-di"; - reg = <0x0d806000 0x40>; - interrupts = <2>; - }; - }; -}; - diff --git a/trunk/arch/powerpc/boot/gamecube-head.S b/trunk/arch/powerpc/boot/gamecube-head.S deleted file mode 100644 index 65a9b2a3bf33..000000000000 --- a/trunk/arch/powerpc/boot/gamecube-head.S +++ /dev/null @@ -1,111 +0,0 @@ -/* - * arch/powerpc/boot/gamecube-head.S - * - * Nintendo GameCube bootwrapper entry. - * Copyright (C) 2004-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#include "ppc_asm.h" - -/* - * The entry code does no assumptions regarding: - * - if the data and instruction caches are enabled or not - * - if the MMU is enabled or not - * - * We enable the caches if not already enabled, enable the MMU with an - * identity mapping scheme and jump to the start code. - */ - - .text - - .globl _zimage_start -_zimage_start: - - /* turn the MMU off */ - mfmsr 9 - rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */ - bcl 20, 31, 1f -1: - mflr 8 - clrlwi 8, 8, 3 /* convert to a real address */ - addi 8, 8, _mmu_off - 1b - mtsrr0 8 - mtsrr1 9 - rfi -_mmu_off: - /* MMU disabled */ - - /* setup BATs */ - isync - li 8, 0 - mtspr 0x210, 8 /* IBAT0U */ - mtspr 0x212, 8 /* IBAT1U */ - mtspr 0x214, 8 /* IBAT2U */ - mtspr 0x216, 8 /* IBAT3U */ - mtspr 0x218, 8 /* DBAT0U */ - mtspr 0x21a, 8 /* DBAT1U */ - mtspr 0x21c, 8 /* DBAT2U */ - mtspr 0x21e, 8 /* DBAT3U */ - - li 8, 0x01ff /* first 16MiB */ - li 9, 0x0002 /* rw */ - mtspr 0x211, 9 /* IBAT0L */ - mtspr 0x210, 8 /* IBAT0U */ - mtspr 0x219, 9 /* DBAT0L */ - mtspr 0x218, 8 /* DBAT0U */ - - lis 8, 0x0c00 /* I/O mem */ - ori 8, 8, 0x3ff /* 32MiB */ - lis 9, 0x0c00 - ori 9, 9, 0x002a /* uncached, guarded, rw */ - mtspr 0x21b, 9 /* DBAT1L */ - mtspr 0x21a, 8 /* DBAT1U */ - - lis 8, 0x0100 /* next 8MiB */ - ori 8, 8, 0x00ff /* 8MiB */ - lis 9, 0x0100 - ori 9, 9, 0x0002 /* rw */ - mtspr 0x215, 9 /* IBAT2L */ - mtspr 0x214, 8 /* IBAT2U */ - mtspr 0x21d, 9 /* DBAT2L */ - mtspr 0x21c, 8 /* DBAT2U */ - - /* enable and invalidate the caches if not already enabled */ - mfspr 8, 0x3f0 /* HID0 */ - andi. 0, 8, (1<<15) /* HID0_ICE */ - bne 1f - ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/ -1: - andi. 0, 8, (1<<14) /* HID0_DCE */ - bne 1f - ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/ -1: - mtspr 0x3f0, 8 /* HID0 */ - isync - - /* initialize arguments */ - li 3, 0 - li 4, 0 - li 5, 0 - - /* turn the MMU on */ - bcl 20, 31, 1f -1: - mflr 8 - addi 8, 8, _mmu_on - 1b - mfmsr 9 - ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */ - mtsrr0 8 - mtsrr1 9 - sync - rfi -_mmu_on: - b _zimage_start_lib - diff --git a/trunk/arch/powerpc/boot/gamecube.c b/trunk/arch/powerpc/boot/gamecube.c deleted file mode 100644 index 28ae7057be5e..000000000000 --- a/trunk/arch/powerpc/boot/gamecube.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/powerpc/boot/gamecube.c - * - * Nintendo GameCube bootwrapper support - * Copyright (C) 2004-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#include -#include "stdio.h" -#include "types.h" -#include "io.h" -#include "ops.h" - -#include "ugecon.h" - -BSS_STACK(8192); - -void platform_init(unsigned long r3, unsigned long r4, unsigned long r5) -{ - u32 heapsize = 16*1024*1024 - (u32)_end; - - simple_alloc_init(_end, heapsize, 32, 64); - fdt_init(_dtb_start); - - if (ug_probe()) - console_ops.write = ug_console_write; -} - diff --git a/trunk/arch/powerpc/boot/ugecon.c b/trunk/arch/powerpc/boot/ugecon.c deleted file mode 100644 index 50609ea6ddf8..000000000000 --- a/trunk/arch/powerpc/boot/ugecon.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * arch/powerpc/boot/ugecon.c - * - * USB Gecko bootwrapper console. - * Copyright (C) 2008-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#include -#include "stdio.h" -#include "types.h" -#include "io.h" -#include "ops.h" - - -#define EXI_CLK_32MHZ 5 - -#define EXI_CSR 0x00 -#define EXI_CSR_CLKMASK (0x7<<4) -#define EXI_CSR_CLK_32MHZ (EXI_CLK_32MHZ<<4) -#define EXI_CSR_CSMASK (0x7<<7) -#define EXI_CSR_CS_0 (0x1<<7) /* Chip Select 001 */ - -#define EXI_CR 0x0c -#define EXI_CR_TSTART (1<<0) -#define EXI_CR_WRITE (1<<2) -#define EXI_CR_READ_WRITE (2<<2) -#define EXI_CR_TLEN(len) (((len)-1)<<4) - -#define EXI_DATA 0x10 - - -/* virtual address base for input/output, retrieved from device tree */ -static void *ug_io_base; - - -static u32 ug_io_transaction(u32 in) -{ - u32 *csr_reg = ug_io_base + EXI_CSR; - u32 *data_reg = ug_io_base + EXI_DATA; - u32 *cr_reg = ug_io_base + EXI_CR; - u32 csr, data, cr; - - /* select */ - csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0; - out_be32(csr_reg, csr); - - /* read/write */ - data = in; - out_be32(data_reg, data); - cr = EXI_CR_TLEN(2) | EXI_CR_READ_WRITE | EXI_CR_TSTART; - out_be32(cr_reg, cr); - - while (in_be32(cr_reg) & EXI_CR_TSTART) - barrier(); - - /* deselect */ - out_be32(csr_reg, 0); - - data = in_be32(data_reg); - return data; -} - -static int ug_is_txfifo_ready(void) -{ - return ug_io_transaction(0xc0000000) & 0x04000000; -} - -static void ug_raw_putc(char ch) -{ - ug_io_transaction(0xb0000000 | (ch << 20)); -} - -static void ug_putc(char ch) -{ - int count = 16; - - if (!ug_io_base) - return; - - while (!ug_is_txfifo_ready() && count--) - barrier(); - if (count) - ug_raw_putc(ch); -} - -void ug_console_write(const char *buf, int len) -{ - char *b = (char *)buf; - - while (len--) { - if (*b == '\n') - ug_putc('\r'); - ug_putc(*b++); - } -} - -static int ug_is_adapter_present(void) -{ - if (!ug_io_base) - return 0; - return ug_io_transaction(0x90000000) == 0x04700000; -} - -static void *ug_grab_exi_io_base(void) -{ - u32 v; - void *devp; - - devp = find_node_by_compatible(NULL, "nintendo,flipper-exi"); - if (devp == NULL) - goto err_out; - if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v)) - goto err_out; - - return (void *)v; - -err_out: - return NULL; -} - -void *ug_probe(void) -{ - void *exi_io_base; - int i; - - exi_io_base = ug_grab_exi_io_base(); - if (!exi_io_base) - return NULL; - - /* look for a usbgecko on memcard slots A and B */ - for (i = 0; i < 2; i++) { - ug_io_base = exi_io_base + 0x14 * i; - if (ug_is_adapter_present()) - break; - } - if (i == 2) - ug_io_base = NULL; - return ug_io_base; -} - diff --git a/trunk/arch/powerpc/boot/ugecon.h b/trunk/arch/powerpc/boot/ugecon.h deleted file mode 100644 index 43737539169b..000000000000 --- a/trunk/arch/powerpc/boot/ugecon.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * arch/powerpc/boot/ugecon.h - * - * USB Gecko early bootwrapper console. - * Copyright (C) 2008-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#ifndef __UGECON_H -#define __UGECON_H - -extern void *ug_probe(void); - -extern void ug_putc(char ch); -extern void ug_console_write(const char *buf, int len); - -#endif /* __UGECON_H */ - diff --git a/trunk/arch/powerpc/boot/wii-head.S b/trunk/arch/powerpc/boot/wii-head.S deleted file mode 100644 index edd79b836fcf..000000000000 --- a/trunk/arch/powerpc/boot/wii-head.S +++ /dev/null @@ -1,142 +0,0 @@ -/* - * arch/powerpc/boot/wii-head.S - * - * Nintendo Wii bootwrapper entry. - * Copyright (C) 2008-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#include "ppc_asm.h" - -/* - * The entry code does no assumptions regarding: - * - if the data and instruction caches are enabled or not - * - if the MMU is enabled or not - * - if the high BATs are enabled or not - * - * We enable the high BATs, enable the caches if not already enabled, - * enable the MMU with an identity mapping scheme and jump to the start code. - */ - - .text - - .globl _zimage_start -_zimage_start: - - /* turn the MMU off */ - mfmsr 9 - rlwinm 9, 9, 0, ~((1<<4)|(1<<5)) /* MSR_DR|MSR_IR */ - bcl 20, 31, 1f -1: - mflr 8 - clrlwi 8, 8, 3 /* convert to a real address */ - addi 8, 8, _mmu_off - 1b - mtsrr0 8 - mtsrr1 9 - rfi -_mmu_off: - /* MMU disabled */ - - /* setup BATs */ - isync - li 8, 0 - mtspr 0x210, 8 /* IBAT0U */ - mtspr 0x212, 8 /* IBAT1U */ - mtspr 0x214, 8 /* IBAT2U */ - mtspr 0x216, 8 /* IBAT3U */ - mtspr 0x218, 8 /* DBAT0U */ - mtspr 0x21a, 8 /* DBAT1U */ - mtspr 0x21c, 8 /* DBAT2U */ - mtspr 0x21e, 8 /* DBAT3U */ - - mtspr 0x230, 8 /* IBAT4U */ - mtspr 0x232, 8 /* IBAT5U */ - mtspr 0x234, 8 /* IBAT6U */ - mtspr 0x236, 8 /* IBAT7U */ - mtspr 0x238, 8 /* DBAT4U */ - mtspr 0x23a, 8 /* DBAT5U */ - mtspr 0x23c, 8 /* DBAT6U */ - mtspr 0x23e, 8 /* DBAT7U */ - - li 8, 0x01ff /* first 16MiB */ - li 9, 0x0002 /* rw */ - mtspr 0x211, 9 /* IBAT0L */ - mtspr 0x210, 8 /* IBAT0U */ - mtspr 0x219, 9 /* DBAT0L */ - mtspr 0x218, 8 /* DBAT0U */ - - lis 8, 0x0c00 /* I/O mem */ - ori 8, 8, 0x3ff /* 32MiB */ - lis 9, 0x0c00 - ori 9, 9, 0x002a /* uncached, guarded, rw */ - mtspr 0x21b, 9 /* DBAT1L */ - mtspr 0x21a, 8 /* DBAT1U */ - - lis 8, 0x0100 /* next 8MiB */ - ori 8, 8, 0x00ff /* 8MiB */ - lis 9, 0x0100 - ori 9, 9, 0x0002 /* rw */ - mtspr 0x215, 9 /* IBAT2L */ - mtspr 0x214, 8 /* IBAT2U */ - mtspr 0x21d, 9 /* DBAT2L */ - mtspr 0x21c, 8 /* DBAT2U */ - - lis 8, 0x1000 /* MEM2 */ - ori 8, 8, 0x07ff /* 64MiB */ - lis 9, 0x1000 - ori 9, 9, 0x0002 /* rw */ - mtspr 0x216, 8 /* IBAT3U */ - mtspr 0x217, 9 /* IBAT3L */ - mtspr 0x21e, 8 /* DBAT3U */ - mtspr 0x21f, 9 /* DBAT3L */ - - /* enable the high BATs */ - mfspr 8, 0x3f3 /* HID4 */ - oris 8, 8, 0x0200 - mtspr 0x3f3, 8 /* HID4 */ - - /* enable and invalidate the caches if not already enabled */ - mfspr 8, 0x3f0 /* HID0 */ - andi. 0, 8, (1<<15) /* HID0_ICE */ - bne 1f - ori 8, 8, (1<<15)|(1<<11) /* HID0_ICE|HID0_ICFI*/ -1: - andi. 0, 8, (1<<14) /* HID0_DCE */ - bne 1f - ori 8, 8, (1<<14)|(1<<10) /* HID0_DCE|HID0_DCFI*/ -1: - mtspr 0x3f0, 8 /* HID0 */ - isync - - /* initialize arguments */ - li 3, 0 - li 4, 0 - li 5, 0 - - /* turn the MMU on */ - bcl 20, 31, 1f -1: - mflr 8 - addi 8, 8, _mmu_on - 1b - mfmsr 9 - ori 9, 9, (1<<4)|(1<<5) /* MSR_DR|MSR_IR */ - mtsrr0 8 - mtsrr1 9 - sync - rfi -_mmu_on: - /* turn on the front blue led (aka: yay! we got here!) */ - lis 8, 0x0d00 - ori 8, 8, 0x00c0 - lwz 9, 0(8) - ori 9, 9, 0x20 - stw 9, 0(8) - - b _zimage_start_lib - diff --git a/trunk/arch/powerpc/boot/wii.c b/trunk/arch/powerpc/boot/wii.c deleted file mode 100644 index 2ebaec0344dd..000000000000 --- a/trunk/arch/powerpc/boot/wii.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * arch/powerpc/boot/wii.c - * - * Nintendo Wii bootwrapper support - * Copyright (C) 2008-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#include -#include "stdio.h" -#include "types.h" -#include "io.h" -#include "ops.h" - -#include "ugecon.h" - -BSS_STACK(8192); - -#define HW_REG(x) ((void *)(x)) - -#define EXI_CTRL HW_REG(0x0d800070) -#define EXI_CTRL_ENABLE (1<<0) - -#define MEM2_TOP (0x10000000 + 64*1024*1024) -#define FIRMWARE_DEFAULT_SIZE (12*1024*1024) - - -struct mipc_infohdr { - char magic[3]; - u8 version; - u32 mem2_boundary; - u32 ipc_in; - size_t ipc_in_size; - u32 ipc_out; - size_t ipc_out_size; -}; - -static int mipc_check_address(u32 pa) -{ - /* only MEM2 addresses */ - if (pa < 0x10000000 || pa > 0x14000000) - return -EINVAL; - return 0; -} - -static struct mipc_infohdr *mipc_get_infohdr(void) -{ - struct mipc_infohdr **hdrp, *hdr; - - /* 'mini' header pointer is the last word of MEM2 memory */ - hdrp = (struct mipc_infohdr **)0x13fffffc; - if (mipc_check_address((u32)hdrp)) { - printf("mini: invalid hdrp %08X\n", (u32)hdrp); - hdr = NULL; - goto out; - } - - hdr = *hdrp; - if (mipc_check_address((u32)hdr)) { - printf("mini: invalid hdr %08X\n", (u32)hdr); - hdr = NULL; - goto out; - } - if (memcmp(hdr->magic, "IPC", 3)) { - printf("mini: invalid magic\n"); - hdr = NULL; - goto out; - } - -out: - return hdr; -} - -static int mipc_get_mem2_boundary(u32 *mem2_boundary) -{ - struct mipc_infohdr *hdr; - int error; - - hdr = mipc_get_infohdr(); - if (!hdr) { - error = -1; - goto out; - } - - if (mipc_check_address(hdr->mem2_boundary)) { - printf("mini: invalid mem2_boundary %08X\n", - hdr->mem2_boundary); - error = -EINVAL; - goto out; - } - *mem2_boundary = hdr->mem2_boundary; - error = 0; -out: - return error; - -} - -static void platform_fixups(void) -{ - void *mem; - u32 reg[4]; - u32 mem2_boundary; - int len; - int error; - - mem = finddevice("/memory"); - if (!mem) - fatal("Can't find memory node\n"); - - /* two ranges of (address, size) words */ - len = getprop(mem, "reg", reg, sizeof(reg)); - if (len != sizeof(reg)) { - /* nothing to do */ - goto out; - } - - /* retrieve MEM2 boundary from 'mini' */ - error = mipc_get_mem2_boundary(&mem2_boundary); - if (error) { - /* if that fails use a sane value */ - mem2_boundary = MEM2_TOP - FIRMWARE_DEFAULT_SIZE; - } - - if (mem2_boundary > reg[2] && mem2_boundary < reg[2] + reg[3]) { - reg[3] = mem2_boundary - reg[2]; - printf("top of MEM2 @ %08X\n", reg[2] + reg[3]); - setprop(mem, "reg", reg, sizeof(reg)); - } - -out: - return; -} - -void platform_init(unsigned long r3, unsigned long r4, unsigned long r5) -{ - u32 heapsize = 24*1024*1024 - (u32)_end; - - simple_alloc_init(_end, heapsize, 32, 64); - fdt_init(_dtb_start); - - /* - * 'mini' boots the Broadway processor with EXI disabled. - * We need it enabled before probing for the USB Gecko. - */ - out_be32(EXI_CTRL, in_be32(EXI_CTRL) | EXI_CTRL_ENABLE); - - if (ug_probe()) - console_ops.write = ug_console_write; - - platform_ops.fixups = platform_fixups; -} - diff --git a/trunk/arch/powerpc/boot/wrapper b/trunk/arch/powerpc/boot/wrapper index 390512ae7f86..ac9e9a58b2b0 100755 --- a/trunk/arch/powerpc/boot/wrapper +++ b/trunk/arch/powerpc/boot/wrapper @@ -230,10 +230,6 @@ xpedite52*) link_address='0x1400000' platformo=$object/cuboot-85xx.o ;; -gamecube|wii) - link_address='0x600000' - platformo="$object/$platform-head.o $object/$platform.o" - ;; esac vmz="$tmpdir/`basename \"$kernel\"`.$ext" diff --git a/trunk/arch/powerpc/configs/gamecube_defconfig b/trunk/arch/powerpc/configs/gamecube_defconfig deleted file mode 100644 index 942e1193e9e4..000000000000 --- a/trunk/arch/powerpc/configs/gamecube_defconfig +++ /dev/null @@ -1,1061 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc8 -# Sun Nov 22 21:07:30 2009 -# -# CONFIG_PPC64 is not set - -# -# Processor support -# -CONFIG_PPC_BOOK3S_32=y -# CONFIG_PPC_85xx is not set -# CONFIG_PPC_8xx is not set -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_E200 is not set -CONFIG_PPC_BOOK3S=y -CONFIG_6xx=y -CONFIG_PPC_FPU=y -# CONFIG_ALTIVEC is not set -CONFIG_PPC_STD_MMU=y -CONFIG_PPC_STD_MMU_32=y -# CONFIG_PPC_MM_SLICES is not set -CONFIG_PPC_HAVE_PMU_SUPPORT=y -CONFIG_PPC_PERF_CTRS=y -# CONFIG_SMP is not set -CONFIG_NOT_COHERENT_CACHE=y -CONFIG_PPC32=y -CONFIG_WORD_SIZE=32 -# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set -CONFIG_MMU=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set -# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set -CONFIG_IRQ_PER_CPU=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_ARCH_HAS_ILOG2_U32=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -# CONFIG_ARCH_NO_VIRT_TO_BUS is not set -CONFIG_PPC=y -CONFIG_EARLY_PRINTK=y -CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_PPC_OF=y -CONFIG_OF=y -# CONFIG_PPC_UDBG_16550 is not set -# CONFIG_GENERIC_TBSYNC is not set -CONFIG_AUDIT_ARCH=y -CONFIG_GENERIC_BUG=y -CONFIG_DTC=y -# CONFIG_DEFAULT_UIMAGE is not set -# CONFIG_PPC_DCR_NATIVE is not set -# CONFIG_PPC_DCR_MMIO is not set -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="-gcn" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_HAVE_PERF_EVENTS=y - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -CONFIG_EVENT_PROFILE=y -CONFIG_PERF_COUNTERS=y -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -# CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_TRACEPOINTS=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_ATTRS=y -CONFIG_HAVE_DMA_API_DEBUG=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -CONFIG_LBDAF=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -# CONFIG_FREEZER is not set - -# -# Platform support -# -# CONFIG_PPC_CHRP is not set -# CONFIG_MPC5121_ADS is not set -# CONFIG_MPC5121_GENERIC is not set -# CONFIG_PPC_MPC52xx is not set -# CONFIG_PPC_PMAC is not set -# CONFIG_PPC_CELL is not set -# CONFIG_PPC_CELL_NATIVE is not set -# CONFIG_PPC_82xx is not set -# CONFIG_PQ2ADS is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set -CONFIG_EMBEDDED6xx=y -# CONFIG_LINKSTATION is not set -# CONFIG_STORCENTER is not set -# CONFIG_MPC7448HPC2 is not set -# CONFIG_PPC_HOLLY is not set -# CONFIG_PPC_PRPMC2800 is not set -# CONFIG_PPC_C2K is not set -CONFIG_GAMECUBE_COMMON=y -CONFIG_USBGECKO_UDBG=y -CONFIG_FLIPPER_PIC=y -CONFIG_GAMECUBE=y -# CONFIG_WII is not set -# CONFIG_AMIGAONE is not set -# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set -# CONFIG_IPIC is not set -# CONFIG_MPIC is not set -# CONFIG_MPIC_WEIRD is not set -# CONFIG_PPC_I8259 is not set -# CONFIG_PPC_RTAS is not set -# CONFIG_MMIO_NVRAM is not set -# CONFIG_PPC_MPC106 is not set -# CONFIG_PPC_970_NAP is not set -# CONFIG_PPC_INDIRECT_IO is not set -# CONFIG_GENERIC_IOMAP is not set -# CONFIG_CPU_FREQ is not set -# CONFIG_TAU is not set -# CONFIG_FSL_ULI1575 is not set -# CONFIG_SIMPLE_GPIO is not set - -# -# Kernel options -# -# CONFIG_HIGHMEM is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_BINFMT_ELF=y -# CONFIG_HAVE_AOUT is not set -CONFIG_BINFMT_MISC=m -# CONFIG_IOMMU_HELPER is not set -# CONFIG_SWIOTLB is not set -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_HAS_WALK_MEMORY=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y -CONFIG_KEXEC=y -# CONFIG_CRASH_DUMP is not set -CONFIG_MAX_ACTIVE_REGIONS=32 -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_MIGRATION is not set -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_PPC_4K_PAGES=y -# CONFIG_PPC_16K_PAGES is not set -# CONFIG_PPC_64K_PAGES is not set -# CONFIG_PPC_256K_PAGES is not set -CONFIG_FORCE_MAX_ZONEORDER=11 -CONFIG_PROC_DEVICETREE=y -# CONFIG_CMDLINE_BOOL is not set -CONFIG_EXTRA_TARGETS="" -# CONFIG_PM is not set -# CONFIG_SECCOMP is not set -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -CONFIG_ZONE_DMA=y -CONFIG_GENERIC_ISA_DMA=y -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set -# CONFIG_HAS_RAPIDIO is not set - -# -# Advanced setup -# -CONFIG_ADVANCED_OPTIONS=y -# CONFIG_LOWMEM_SIZE_BOOL is not set -CONFIG_LOWMEM_SIZE=0x30000000 -# CONFIG_PAGE_OFFSET_BOOL is not set -CONFIG_PAGE_OFFSET=0xc0000000 -# CONFIG_KERNEL_START_BOOL is not set -CONFIG_KERNEL_START=0xc0000000 -CONFIG_PHYSICAL_START=0x00000000 -# CONFIG_TASK_SIZE_BOOL is not set -CONFIG_TASK_SIZE=0xc0000000 -# CONFIG_CONSISTENT_SIZE_BOOL is not set -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set -# CONFIG_STANDALONE is not set -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -CONFIG_OF_DEVICE=y -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=2 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_MISC_DEVICES=y -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -# CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -# CONFIG_MACINTOSH_DRIVERS is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set -# CONFIG_ETHOC is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_XILINX_EMACLITE is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -# CONFIG_WLAN is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=m -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_JOYDEV=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -# CONFIG_JOYSTICK_ANALOG is not set -# CONFIG_JOYSTICK_A3D is not set -# CONFIG_JOYSTICK_ADI is not set -# CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_GF2K is not set -# CONFIG_JOYSTICK_GRIP is not set -# CONFIG_JOYSTICK_GRIP_MP is not set -# CONFIG_JOYSTICK_GUILLEMOT is not set -# CONFIG_JOYSTICK_INTERACT is not set -# CONFIG_JOYSTICK_SIDEWINDER is not set -# CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_IFORCE is not set -# CONFIG_JOYSTICK_WARRIOR is not set -# CONFIG_JOYSTICK_MAGELLAN is not set -# CONFIG_JOYSTICK_SPACEORB is not set -# CONFIG_JOYSTICK_SPACEBALL is not set -# CONFIG_JOYSTICK_STINGER is not set -# CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_ZHENHUA is not set -# CONFIG_JOYSTICK_JOYDUMP is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_XILINX_XPS_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_DEVKMEM is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=64 -# CONFIG_HVC_UDBG is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_NVRAM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_OF is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -# CONFIG_LOGO_LINUX_CLUT224 is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_SEQUENCER=y -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -CONFIG_SND_PPC=y -# CONFIG_SND_SOC is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set -# CONFIG_HID_PID is not set - -# -# Special HID drivers -# -# CONFIG_USB_SUPPORT is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_EDAC is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -CONFIG_RTC_DRV_GENERIC=y -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -# CONFIG_ZISOFS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -CONFIG_CIFS=y -# CONFIG_CIFS_STATS is not set -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_EXPERIMENTAL is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_HAVE_LMB=y -CONFIG_NLATTR=y -CONFIG_GENERIC_ATOMIC64=y - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -# CONFIG_DETECT_HUNG_TASK is not set -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -CONFIG_DEBUG_SPINLOCK_SLEEP=y -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -CONFIG_LATENCYTOP=y -CONFIG_SYSCTL_SYSCALL_CHECK=y -# CONFIG_DEBUG_PAGEALLOC is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_TRACER_MAX_TRACE=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_TRACING=y -CONFIG_GENERIC_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -CONFIG_SCHED_TRACER=y -CONFIG_BOOT_TRACER=y -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -CONFIG_DMA_API_DEBUG=y -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_PPC_DISABLE_WERROR is not set -CONFIG_PPC_WERROR=y -CONFIG_PRINT_STACK_DEPTH=64 -# CONFIG_DEBUG_STACKOVERFLOW is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_PPC_EMULATED_STATS is not set -# CONFIG_CODE_PATCHING_SELFTEST is not set -# CONFIG_FTR_FIXUP_SELFTEST is not set -# CONFIG_MSI_BITMAP_SELFTEST is not set -# CONFIG_XMON is not set -# CONFIG_IRQSTACKS is not set -# CONFIG_VIRQ_DEBUG is not set -# CONFIG_BDI_SWITCH is not set -# CONFIG_BOOTX_TEXT is not set -CONFIG_PPC_EARLY_DEBUG=y -# CONFIG_PPC_EARLY_DEBUG_LPAR is not set -# CONFIG_PPC_EARLY_DEBUG_G5 is not set -# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set -# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set -# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set -# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set -# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set -# CONFIG_PPC_EARLY_DEBUG_BEAT is not set -# CONFIG_PPC_EARLY_DEBUG_44x is not set -# CONFIG_PPC_EARLY_DEBUG_40x is not set -# CONFIG_PPC_EARLY_DEBUG_CPM is not set -CONFIG_PPC_EARLY_DEBUG_USBGECKO=y - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_CRYPTO is not set -# CONFIG_PPC_CLOCK is not set -# CONFIG_VIRTUALIZATION is not set diff --git a/trunk/arch/powerpc/configs/wii_defconfig b/trunk/arch/powerpc/configs/wii_defconfig deleted file mode 100644 index c386828c639a..000000000000 --- a/trunk/arch/powerpc/configs/wii_defconfig +++ /dev/null @@ -1,1406 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc8 -# Sun Nov 22 20:37:21 2009 -# -# CONFIG_PPC64 is not set - -# -# Processor support -# -CONFIG_PPC_BOOK3S_32=y -# CONFIG_PPC_85xx is not set -# CONFIG_PPC_8xx is not set -# CONFIG_40x is not set -# CONFIG_44x is not set -# CONFIG_E200 is not set -CONFIG_PPC_BOOK3S=y -CONFIG_6xx=y -CONFIG_PPC_FPU=y -# CONFIG_ALTIVEC is not set -CONFIG_PPC_STD_MMU=y -CONFIG_PPC_STD_MMU_32=y -# CONFIG_PPC_MM_SLICES is not set -CONFIG_PPC_HAVE_PMU_SUPPORT=y -CONFIG_PPC_PERF_CTRS=y -# CONFIG_SMP is not set -CONFIG_NOT_COHERENT_CACHE=y -CONFIG_PPC32=y -CONFIG_WORD_SIZE=32 -# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set -CONFIG_MMU=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set -# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set -CONFIG_IRQ_PER_CPU=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_HAVE_LATENCYTOP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_ARCH_HAS_ILOG2_U32=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_GPIO=y -# CONFIG_ARCH_NO_VIRT_TO_BUS is not set -CONFIG_PPC=y -CONFIG_EARLY_PRINTK=y -CONFIG_GENERIC_NVRAM=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_PPC_OF=y -CONFIG_OF=y -# CONFIG_PPC_UDBG_16550 is not set -# CONFIG_GENERIC_TBSYNC is not set -CONFIG_AUDIT_ARCH=y -CONFIG_GENERIC_BUG=y -CONFIG_DTC=y -# CONFIG_DEFAULT_UIMAGE is not set -# CONFIG_PPC_DCR_NATIVE is not set -# CONFIG_PPC_DCR_MMIO is not set -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="-wii" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set -# CONFIG_RCU_TRACE is not set -CONFIG_RCU_FANOUT=32 -# CONFIG_RCU_FANOUT_EXACT is not set -# CONFIG_TREE_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_GROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_RT_GROUP_SCHED is not set -CONFIG_USER_SCHED=y -# CONFIG_CGROUP_SCHED is not set -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_HAVE_PERF_EVENTS=y - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -CONFIG_EVENT_PROFILE=y -CONFIG_PERF_COUNTERS=y -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -# CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_PROFILING is not set -CONFIG_TRACEPOINTS=y -CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_ATTRS=y -CONFIG_HAVE_DMA_API_DEBUG=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_SLOW_WORK=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -CONFIG_LBDAF=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -# CONFIG_FREEZER is not set - -# -# Platform support -# -# CONFIG_PPC_CHRP is not set -# CONFIG_MPC5121_ADS is not set -# CONFIG_MPC5121_GENERIC is not set -# CONFIG_PPC_MPC52xx is not set -# CONFIG_PPC_PMAC is not set -# CONFIG_PPC_CELL is not set -# CONFIG_PPC_CELL_NATIVE is not set -# CONFIG_PPC_82xx is not set -# CONFIG_PQ2ADS is not set -# CONFIG_PPC_83xx is not set -# CONFIG_PPC_86xx is not set -CONFIG_EMBEDDED6xx=y -# CONFIG_LINKSTATION is not set -# CONFIG_STORCENTER is not set -# CONFIG_MPC7448HPC2 is not set -# CONFIG_PPC_HOLLY is not set -# CONFIG_PPC_PRPMC2800 is not set -# CONFIG_PPC_C2K is not set -CONFIG_GAMECUBE_COMMON=y -CONFIG_USBGECKO_UDBG=y -CONFIG_FLIPPER_PIC=y -# CONFIG_GAMECUBE is not set -CONFIG_HLWD_PIC=y -CONFIG_STARLET_MINI=y -CONFIG_WII=y -# CONFIG_AMIGAONE is not set -# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set -# CONFIG_IPIC is not set -# CONFIG_MPIC is not set -# CONFIG_MPIC_WEIRD is not set -# CONFIG_PPC_I8259 is not set -# CONFIG_PPC_RTAS is not set -# CONFIG_MMIO_NVRAM is not set -# CONFIG_PPC_MPC106 is not set -# CONFIG_PPC_970_NAP is not set -# CONFIG_PPC_INDIRECT_IO is not set -# CONFIG_GENERIC_IOMAP is not set -# CONFIG_CPU_FREQ is not set -# CONFIG_TAU is not set -# CONFIG_FSL_ULI1575 is not set -# CONFIG_SIMPLE_GPIO is not set - -# -# Kernel options -# -# CONFIG_HIGHMEM is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set -CONFIG_PREEMPT=y -CONFIG_BINFMT_ELF=y -# CONFIG_HAVE_AOUT is not set -CONFIG_BINFMT_MISC=m -# CONFIG_IOMMU_HELPER is not set -# CONFIG_SWIOTLB is not set -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_HAS_WALK_MEMORY=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y -CONFIG_KEXEC=y -# CONFIG_CRASH_DUMP is not set -CONFIG_MAX_ACTIVE_REGIONS=32 -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_MIGRATION is not set -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_BOUNCE=y -CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_PPC_4K_PAGES=y -# CONFIG_PPC_16K_PAGES is not set -# CONFIG_PPC_64K_PAGES is not set -# CONFIG_PPC_256K_PAGES is not set -CONFIG_FORCE_MAX_ZONEORDER=11 -CONFIG_PROC_DEVICETREE=y -# CONFIG_CMDLINE_BOOL is not set -CONFIG_EXTRA_TARGETS="" -# CONFIG_PM is not set -# CONFIG_SECCOMP is not set -CONFIG_ISA_DMA_API=y - -# -# Bus options -# -CONFIG_ZONE_DMA=y -CONFIG_GENERIC_ISA_DMA=y -# CONFIG_PCI is not set -# CONFIG_PCI_DOMAINS is not set -# CONFIG_PCI_SYSCALL is not set -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set -# CONFIG_HAS_RAPIDIO is not set - -# -# Advanced setup -# -CONFIG_ADVANCED_OPTIONS=y -# CONFIG_LOWMEM_SIZE_BOOL is not set -CONFIG_LOWMEM_SIZE=0x30000000 -# CONFIG_PAGE_OFFSET_BOOL is not set -CONFIG_PAGE_OFFSET=0xc0000000 -# CONFIG_KERNEL_START_BOOL is not set -CONFIG_KERNEL_START=0xc0000000 -CONFIG_PHYSICAL_START=0x00000000 -# CONFIG_TASK_SIZE_BOOL is not set -CONFIG_TASK_SIZE=0xc0000000 -# CONFIG_CONSISTENT_SIZE_BOOL is not set -CONFIG_CONSISTENT_SIZE=0x00200000 -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -CONFIG_BT=y -CONFIG_BT_L2CAP=y -# CONFIG_BT_SCO is not set -CONFIG_BT_RFCOMM=y -# CONFIG_BT_RFCOMM_TTY is not set -CONFIG_BT_BNEP=y -CONFIG_BT_BNEP_MC_FILTER=y -# CONFIG_BT_BNEP_PROTO_FILTER is not set -CONFIG_BT_HIDP=y - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTSDIO is not set -# CONFIG_BT_HCIUART is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -CONFIG_CFG80211=y -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_REG_DEBUG is not set -CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_DEFAULT_PS_VALUE=1 -# CONFIG_CFG80211_DEBUGFS is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -# CONFIG_LIB80211 is not set -CONFIG_MAC80211=y -# CONFIG_MAC80211_RC_PID is not set -CONFIG_MAC80211_RC_MINSTREL=y -# CONFIG_MAC80211_RC_DEFAULT_PID is not set -CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT="minstrel" -# CONFIG_MAC80211_MESH is not set -# CONFIG_MAC80211_LEDS is not set -# CONFIG_MAC80211_DEBUGFS is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -# CONFIG_DEVTMPFS is not set -# CONFIG_STANDALONE is not set -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -# CONFIG_FIRMWARE_IN_KERNEL is not set -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -CONFIG_OF_DEVICE=y -CONFIG_OF_GPIO=y -CONFIG_OF_I2C=y -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=2 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_MISC_DEVICES=y -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_ISL29003 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -# CONFIG_MACINTOSH_DRIVERS is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_PHYLIB is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_ETHOC is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_XILINX_EMACLITE is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set -CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -# CONFIG_LIBERTAS is not set -# CONFIG_LIBERTAS_THINFIRM is not set -# CONFIG_MAC80211_HWSIM is not set -# CONFIG_P54_COMMON is not set -# CONFIG_ATH_COMMON is not set -# CONFIG_HOSTAP is not set -CONFIG_B43=y -CONFIG_B43_SDIO=y -CONFIG_B43_PIO=y -# CONFIG_B43_PHY_LP is not set -CONFIG_B43_DEBUG=y -# CONFIG_B43_FORCE_PIO is not set -# CONFIG_B43LEGACY is not set -# CONFIG_RT2X00 is not set -# CONFIG_WL12XX is not set -# CONFIG_IWM is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=m -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 -CONFIG_INPUT_JOYDEV=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -# CONFIG_MOUSE_PS2 is not set -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -CONFIG_INPUT_JOYSTICK=y -# CONFIG_JOYSTICK_ANALOG is not set -# CONFIG_JOYSTICK_A3D is not set -# CONFIG_JOYSTICK_ADI is not set -# CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_GF2K is not set -# CONFIG_JOYSTICK_GRIP is not set -# CONFIG_JOYSTICK_GRIP_MP is not set -# CONFIG_JOYSTICK_GUILLEMOT is not set -# CONFIG_JOYSTICK_INTERACT is not set -# CONFIG_JOYSTICK_SIDEWINDER is not set -# CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_IFORCE is not set -# CONFIG_JOYSTICK_WARRIOR is not set -# CONFIG_JOYSTICK_MAGELLAN is not set -# CONFIG_JOYSTICK_SPACEORB is not set -# CONFIG_JOYSTICK_SPACEBALL is not set -# CONFIG_JOYSTICK_STINGER is not set -# CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_ZHENHUA is not set -# CONFIG_JOYSTICK_JOYDUMP is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -# CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_LIBPS2 is not set -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_XILINX_XPS_PS2 is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -# CONFIG_DEVKMEM is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=64 -# CONFIG_HVC_UDBG is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -CONFIG_NVRAM=y -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_ALGOBIT=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -CONFIG_I2C_GPIO=y -# CONFIG_I2C_MPC is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# -# CONFIG_GPIO_XILINX is not set - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# - -# -# AC97 GPIO expanders: -# -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -CONFIG_SSB=y -CONFIG_SSB_BLOCKIO=y -CONFIG_SSB_SDIOHOST_POSSIBLE=y -CONFIG_SSB_SDIOHOST=y -# CONFIG_SSB_SILENT is not set -CONFIG_SSB_DEBUG=y - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_OF is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -# CONFIG_LOGO is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SOUND_OSS_CORE_PRECLAIM=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_SEQUENCER=y -# CONFIG_SND_SEQ_DUMMY is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -# CONFIG_SND_VERBOSE_PROCFS is not set -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -CONFIG_SND_PPC=y -# CONFIG_SND_SOC is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HIDRAW is not set -# CONFIG_HID_PID is not set - -# -# Special HID drivers -# -CONFIG_HID_APPLE=m -CONFIG_HID_WACOM=m -CONFIG_USB_SUPPORT=y -# CONFIG_USB_ARCH_HAS_HCD is not set -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set - -# -# Enable Host or Gadget support to see Inventra options -# - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -# CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_OF is not set -# CONFIG_MMC_SDHCI_PLTFM is not set -# CONFIG_MMC_WBSD is not set -# CONFIG_MMC_AT91 is not set -# CONFIG_MMC_ATMELMCI is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_EDAC is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -CONFIG_RTC_DRV_GENERIC=y -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -# CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_EXT4_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -CONFIG_FUSE_FS=m -# CONFIG_CUSE is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -# CONFIG_ZISOFS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -CONFIG_CIFS=m -# CONFIG_CIFS_STATS is not set -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_EXPERIMENTAL is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_DECOMPRESS_GZIP=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_HAVE_LMB=y -CONFIG_NLATTR=y -CONFIG_GENERIC_ATOMIC64=y - -# -# Kernel hacking -# -CONFIG_PRINTK_TIME=y -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -CONFIG_MAGIC_SYSRQ=y -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_SHIRQ is not set -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -# CONFIG_DETECT_HUNG_TASK is not set -CONFIG_SCHED_DEBUG=y -CONFIG_SCHEDSTATS=y -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_KMEMLEAK is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -CONFIG_DEBUG_SPINLOCK_SLEEP=y -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_INFO is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# CONFIG_FAULT_INJECTION is not set -CONFIG_LATENCYTOP=y -CONFIG_SYSCTL_SYSCALL_CHECK=y -# CONFIG_DEBUG_PAGEALLOC is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_TRACER_MAX_TRACE=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_TRACING=y -CONFIG_GENERIC_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -CONFIG_SCHED_TRACER=y -CONFIG_BOOT_TRACER=y -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -CONFIG_BLK_DEV_IO_TRACE=y -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_DYNAMIC_DEBUG is not set -CONFIG_DMA_API_DEBUG=y -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_PPC_DISABLE_WERROR is not set -CONFIG_PPC_WERROR=y -CONFIG_PRINT_STACK_DEPTH=64 -# CONFIG_DEBUG_STACKOVERFLOW is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_PPC_EMULATED_STATS is not set -# CONFIG_CODE_PATCHING_SELFTEST is not set -# CONFIG_FTR_FIXUP_SELFTEST is not set -# CONFIG_MSI_BITMAP_SELFTEST is not set -# CONFIG_XMON is not set -# CONFIG_IRQSTACKS is not set -# CONFIG_VIRQ_DEBUG is not set -# CONFIG_BDI_SWITCH is not set -# CONFIG_BOOTX_TEXT is not set -CONFIG_PPC_EARLY_DEBUG=y -# CONFIG_PPC_EARLY_DEBUG_LPAR is not set -# CONFIG_PPC_EARLY_DEBUG_G5 is not set -# CONFIG_PPC_EARLY_DEBUG_RTAS_PANEL is not set -# CONFIG_PPC_EARLY_DEBUG_RTAS_CONSOLE is not set -# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set -# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set -# CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE is not set -# CONFIG_PPC_EARLY_DEBUG_BEAT is not set -# CONFIG_PPC_EARLY_DEBUG_44x is not set -# CONFIG_PPC_EARLY_DEBUG_40x is not set -# CONFIG_PPC_EARLY_DEBUG_CPM is not set -CONFIG_PPC_EARLY_DEBUG_USBGECKO=y - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_PCOMP=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -CONFIG_CRYPTO_WORKQUEUE=y -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_GHASH is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -# CONFIG_PPC_CLOCK is not set -# CONFIG_VIRTUALIZATION is not set diff --git a/trunk/arch/powerpc/include/asm/asm-offsets.h b/trunk/arch/powerpc/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/powerpc/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/powerpc/include/asm/async_tx.h b/trunk/arch/powerpc/include/asm/async_tx.h deleted file mode 100644 index 8b2dc55d01ab..000000000000 --- a/trunk/arch/powerpc/include/asm/async_tx.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2008-2009 DENX Software Engineering. - * - * Author: Yuri Tikhonov - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * The full GNU General Public License is included in this distribution in the - * file called COPYING. - */ -#ifndef _ASM_POWERPC_ASYNC_TX_H_ -#define _ASM_POWERPC_ASYNC_TX_H_ - -#if defined(CONFIG_440SPe) || defined(CONFIG_440SP) -extern struct dma_chan * -ppc440spe_async_tx_find_best_channel(enum dma_transaction_type cap, - struct page **dst_lst, int dst_cnt, struct page **src_lst, - int src_cnt, size_t src_sz); - -#define async_tx_find_channel(dep, cap, dst_lst, dst_cnt, src_lst, \ - src_cnt, src_sz) \ - ppc440spe_async_tx_find_best_channel(cap, dst_lst, dst_cnt, src_lst, \ - src_cnt, src_sz) -#else - -#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \ - __async_tx_find_channel(dep, type) - -struct dma_chan * -__async_tx_find_channel(struct async_submit_ctl *submit, - enum dma_transaction_type tx_type); - -#endif - -#endif diff --git a/trunk/arch/powerpc/include/asm/dcr-regs.h b/trunk/arch/powerpc/include/asm/dcr-regs.h index 380274de429f..828e3aa1f2fc 100644 --- a/trunk/arch/powerpc/include/asm/dcr-regs.h +++ b/trunk/arch/powerpc/include/asm/dcr-regs.h @@ -157,27 +157,4 @@ #define L2C_SNP_SSR_32G 0x0000f000 #define L2C_SNP_ESR 0x00000800 -/* - * DCR register offsets for 440SP/440SPe I2O/DMA controller. - * The base address is configured in the device tree. - */ -#define DCRN_I2O0_IBAL 0x006 -#define DCRN_I2O0_IBAH 0x007 -#define I2O_REG_ENABLE 0x00000001 /* Enable I2O/DMA access */ - -/* 440SP/440SPe Software Reset DCR */ -#define DCRN_SDR0_SRST 0x0200 -#define DCRN_SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */ - -/* 440SP/440SPe Memory Queue DCR offsets */ -#define DCRN_MQ0_XORBA 0x04 -#define DCRN_MQ0_CF2H 0x06 -#define DCRN_MQ0_CFBHL 0x0f -#define DCRN_MQ0_BAUH 0x10 - -/* HB/LL Paths Configuration Register */ -#define MQ0_CFBHL_TPLM 28 -#define MQ0_CFBHL_HBCL 23 -#define MQ0_CFBHL_POLY 15 - #endif /* __DCR_REGS_H__ */ diff --git a/trunk/arch/powerpc/include/asm/dma-mapping.h b/trunk/arch/powerpc/include/asm/dma-mapping.h index 80a973bb9e71..e281daebddca 100644 --- a/trunk/arch/powerpc/include/asm/dma-mapping.h +++ b/trunk/arch/powerpc/include/asm/dma-mapping.h @@ -197,7 +197,7 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) if (!dev->dma_mask) return 0; - return addr + size - 1 <= *dev->dma_mask; + return addr + size <= *dev->dma_mask; } static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) diff --git a/trunk/arch/powerpc/include/asm/elf.h b/trunk/arch/powerpc/include/asm/elf.h index 17828ad411eb..014a624f4c8e 100644 --- a/trunk/arch/powerpc/include/asm/elf.h +++ b/trunk/arch/powerpc/include/asm/elf.h @@ -170,6 +170,7 @@ typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG]; #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) #define compat_elf_check_arch(x) ((x)->e_machine == EM_PPC) +#define USE_ELF_CORE_DUMP #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE PAGE_SIZE diff --git a/trunk/arch/powerpc/include/asm/fixmap.h b/trunk/arch/powerpc/include/asm/fixmap.h index 5c2c0233175e..f1f4e23a84e9 100644 --- a/trunk/arch/powerpc/include/asm/fixmap.h +++ b/trunk/arch/powerpc/include/asm/fixmap.h @@ -44,9 +44,6 @@ */ enum fixed_addresses { FIX_HOLE, - /* reserve the top 128K for early debugging purposes */ - FIX_EARLY_DEBUG_TOP = FIX_HOLE, - FIX_EARLY_DEBUG_BASE = FIX_EARLY_DEBUG_TOP+((128*1024)/PAGE_SIZE)-1, #ifdef CONFIG_HIGHMEM FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, diff --git a/trunk/arch/powerpc/include/asm/module.h b/trunk/arch/powerpc/include/asm/module.h index 0192a4ee2bc2..08454880a2c0 100644 --- a/trunk/arch/powerpc/include/asm/module.h +++ b/trunk/arch/powerpc/include/asm/module.h @@ -87,10 +87,5 @@ struct exception_table_entry; void sort_ex_table(struct exception_table_entry *start, struct exception_table_entry *finish); -#ifdef CONFIG_MODVERSIONS -#define ARCH_RELOCATES_KCRCTAB - -extern const unsigned long reloc_start[]; -#endif #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_MODULE_H */ diff --git a/trunk/arch/powerpc/include/asm/ptrace.h b/trunk/arch/powerpc/include/asm/ptrace.h index cbd759e3cd78..8c341490cfc5 100644 --- a/trunk/arch/powerpc/include/asm/ptrace.h +++ b/trunk/arch/powerpc/include/asm/ptrace.h @@ -140,8 +140,6 @@ extern void user_enable_single_step(struct task_struct *); extern void user_enable_block_step(struct task_struct *); extern void user_disable_single_step(struct task_struct *); -#define ARCH_HAS_USER_SINGLE_STEP_INFO - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/trunk/arch/powerpc/include/asm/udbg.h b/trunk/arch/powerpc/include/asm/udbg.h index 11ae699135ba..cd21e5e6b04f 100644 --- a/trunk/arch/powerpc/include/asm/udbg.h +++ b/trunk/arch/powerpc/include/asm/udbg.h @@ -51,7 +51,6 @@ extern void __init udbg_init_btext(void); extern void __init udbg_init_44x_as1(void); extern void __init udbg_init_40x_realmode(void); extern void __init udbg_init_cpm(void); -extern void __init udbg_init_usbgecko(void); #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_UDBG_H */ diff --git a/trunk/arch/powerpc/kernel/cputable.c b/trunk/arch/powerpc/kernel/cputable.c index 2fc82bac3bbc..03c862b6a9c4 100644 --- a/trunk/arch/powerpc/kernel/cputable.c +++ b/trunk/arch/powerpc/kernel/cputable.c @@ -697,9 +697,9 @@ static struct cpu_spec __initdata cpu_specs[] = { .machine_check = machine_check_generic, .platform = "ppc750", }, - { /* 750CL (and "Broadway") */ - .pvr_mask = 0xfffff0e0, - .pvr_value = 0x00087000, + { /* 750CL */ + .pvr_mask = 0xfffff0f0, + .pvr_value = 0x00087010, .cpu_name = "750CL", .cpu_features = CPU_FTRS_750CL, .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, diff --git a/trunk/arch/powerpc/kernel/head_32.S b/trunk/arch/powerpc/kernel/head_32.S index e025e89fe93e..829c3fe7c5a2 100644 --- a/trunk/arch/powerpc/kernel/head_32.S +++ b/trunk/arch/powerpc/kernel/head_32.S @@ -164,9 +164,6 @@ __after_mmu_off: #ifdef CONFIG_PPC_EARLY_DEBUG_CPM bl setup_cpm_bat #endif -#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO - bl setup_usbgecko_bat -#endif /* * Call setup_cpu for CPU 0 and initialize 6xx Idle @@ -1206,28 +1203,6 @@ setup_cpm_bat: blr #endif -#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO -setup_usbgecko_bat: - /* prepare a BAT for early io */ -#if defined(CONFIG_GAMECUBE) - lis r8, 0x0c00 -#elif defined(CONFIG_WII) - lis r8, 0x0d00 -#else -#error Invalid platform for USB Gecko based early debugging. -#endif - /* - * The virtual address used must match the virtual address - * associated to the fixmap entry FIX_EARLY_DEBUG_BASE. - */ - lis r11, 0xfffe /* top 128K */ - ori r8, r8, 0x002a /* uncached, guarded ,rw */ - ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */ - mtspr SPRN_DBAT1L, r8 - mtspr SPRN_DBAT1U, r11 - blr -#endif - #ifdef CONFIG_8260 /* Jump into the system reset for the rom. * We first disable the MMU, and then jump to the ROM reset address. diff --git a/trunk/arch/powerpc/kernel/iommu.c b/trunk/arch/powerpc/kernel/iommu.c index 5547ae6e6b0b..fd51578e29dd 100644 --- a/trunk/arch/powerpc/kernel/iommu.c +++ b/trunk/arch/powerpc/kernel/iommu.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include @@ -251,7 +251,7 @@ static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, } ppc_md.tce_free(tbl, entry, npages); - bitmap_clear(tbl->it_map, free_entry, npages); + iommu_area_free(tbl->it_map, free_entry, npages); } static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, diff --git a/trunk/arch/powerpc/kernel/traps.c b/trunk/arch/powerpc/kernel/traps.c index d069ff8a7e03..804f0f30f227 100644 --- a/trunk/arch/powerpc/kernel/traps.c +++ b/trunk/arch/powerpc/kernel/traps.c @@ -174,15 +174,6 @@ int die(const char *str, struct pt_regs *regs, long err) return 0; } -void user_single_step_siginfo(struct task_struct *tsk, - struct pt_regs *regs, siginfo_t *info) -{ - memset(info, 0, sizeof(*info)); - info->si_signo = SIGTRAP; - info->si_code = TRAP_TRACE; - info->si_addr = (void __user *)regs->nip; -} - void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) { siginfo_t info; diff --git a/trunk/arch/powerpc/kernel/udbg.c b/trunk/arch/powerpc/kernel/udbg.c index e39cad83c884..fc9af47e2128 100644 --- a/trunk/arch/powerpc/kernel/udbg.c +++ b/trunk/arch/powerpc/kernel/udbg.c @@ -60,8 +60,6 @@ void __init udbg_early_init(void) udbg_init_40x_realmode(); #elif defined(CONFIG_PPC_EARLY_DEBUG_CPM) udbg_init_cpm(); -#elif defined(CONFIG_PPC_EARLY_DEBUG_USBGECKO) - udbg_init_usbgecko(); #endif #ifdef CONFIG_PPC_EARLY_DEBUG diff --git a/trunk/arch/powerpc/kernel/vmlinux.lds.S b/trunk/arch/powerpc/kernel/vmlinux.lds.S index dcd01c82e701..27735a7ac12b 100644 --- a/trunk/arch/powerpc/kernel/vmlinux.lds.S +++ b/trunk/arch/powerpc/kernel/vmlinux.lds.S @@ -38,9 +38,6 @@ jiffies = jiffies_64 + 4; #endif SECTIONS { - . = 0; - reloc_start = .; - . = KERNELBASE; /* diff --git a/trunk/arch/powerpc/mm/40x_mmu.c b/trunk/arch/powerpc/mm/40x_mmu.c index 08dfa8e6d86f..f5e7b9ce63dd 100644 --- a/trunk/arch/powerpc/mm/40x_mmu.c +++ b/trunk/arch/powerpc/mm/40x_mmu.c @@ -91,7 +91,7 @@ void __init MMU_init_hw(void) #define LARGE_PAGE_SIZE_16M (1<<24) #define LARGE_PAGE_SIZE_4M (1<<22) -unsigned long __init mmu_mapin_ram(unsigned long top) +unsigned long __init mmu_mapin_ram(void) { unsigned long v, s, mapped; phys_addr_t p; diff --git a/trunk/arch/powerpc/mm/44x_mmu.c b/trunk/arch/powerpc/mm/44x_mmu.c index 3986264b0993..98052ac96580 100644 --- a/trunk/arch/powerpc/mm/44x_mmu.c +++ b/trunk/arch/powerpc/mm/44x_mmu.c @@ -88,7 +88,7 @@ void __init MMU_init_hw(void) flush_instruction_cache(); } -unsigned long __init mmu_mapin_ram(unsigned long top) +unsigned long __init mmu_mapin_ram(void) { unsigned long addr; diff --git a/trunk/arch/powerpc/mm/fsl_booke_mmu.c b/trunk/arch/powerpc/mm/fsl_booke_mmu.c index c5394728bf2e..fcfcb6e976c7 100644 --- a/trunk/arch/powerpc/mm/fsl_booke_mmu.c +++ b/trunk/arch/powerpc/mm/fsl_booke_mmu.c @@ -207,7 +207,7 @@ unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx) return amount_mapped; } -unsigned long __init mmu_mapin_ram(unsigned long top) +unsigned long __init mmu_mapin_ram(void) { return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1; } diff --git a/trunk/arch/powerpc/mm/init_32.c b/trunk/arch/powerpc/mm/init_32.c index 4ec900af332f..9ddcfb4dc139 100644 --- a/trunk/arch/powerpc/mm/init_32.c +++ b/trunk/arch/powerpc/mm/init_32.c @@ -82,11 +82,6 @@ extern struct task_struct *current_set[NR_CPUS]; int __map_without_bats; int __map_without_ltlbs; -/* - * This tells the system to allow ioremapping memory marked as reserved. - */ -int __allow_ioremap_reserved; - /* max amount of low RAM to map in */ unsigned long __max_low_memory = MAX_LOW_MEM; @@ -136,13 +131,9 @@ void __init MMU_init(void) MMU_setup(); if (lmb.memory.cnt > 1) { -#ifndef CONFIG_WII lmb.memory.cnt = 1; lmb_analyze(); printk(KERN_WARNING "Only using first contiguous memory region"); -#else - wii_memory_fixups(); -#endif } total_lowmem = total_memory = lmb_end_of_DRAM() - memstart_addr; diff --git a/trunk/arch/powerpc/mm/mmu_decl.h b/trunk/arch/powerpc/mm/mmu_decl.h index d49a77503e19..e27a990af42d 100644 --- a/trunk/arch/powerpc/mm/mmu_decl.h +++ b/trunk/arch/powerpc/mm/mmu_decl.h @@ -104,7 +104,6 @@ extern void setbat(int index, unsigned long virt, phys_addr_t phys, unsigned int size, int flags); extern int __map_without_bats; -extern int __allow_ioremap_reserved; extern unsigned long ioremap_base; extern unsigned int rtas_data, rtas_size; @@ -126,32 +125,24 @@ extern phys_addr_t total_lowmem; extern phys_addr_t memstart_addr; extern phys_addr_t lowmem_end_addr; -#ifdef CONFIG_WII -extern unsigned long wii_hole_start; -extern unsigned long wii_hole_size; - -extern unsigned long wii_mmu_mapin_mem2(unsigned long top); -extern void wii_memory_fixups(void); -#endif - /* ...and now those things that may be slightly different between processor * architectures. -- Dan */ #if defined(CONFIG_8xx) #define MMU_init_hw() do { } while(0) -#define mmu_mapin_ram(top) (0UL) +#define mmu_mapin_ram() (0UL) #elif defined(CONFIG_4xx) extern void MMU_init_hw(void); -extern unsigned long mmu_mapin_ram(unsigned long top); +extern unsigned long mmu_mapin_ram(void); #elif defined(CONFIG_FSL_BOOKE) extern void MMU_init_hw(void); -extern unsigned long mmu_mapin_ram(unsigned long top); +extern unsigned long mmu_mapin_ram(void); extern void adjust_total_lowmem(void); #elif defined(CONFIG_PPC32) /* anything 32-bit except 4xx or 8xx */ extern void MMU_init_hw(void); -extern unsigned long mmu_mapin_ram(unsigned long top); +extern unsigned long mmu_mapin_ram(void); #endif diff --git a/trunk/arch/powerpc/mm/pgtable_32.c b/trunk/arch/powerpc/mm/pgtable_32.c index 177e4038b43c..cb96cb2e17cc 100644 --- a/trunk/arch/powerpc/mm/pgtable_32.c +++ b/trunk/arch/powerpc/mm/pgtable_32.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include @@ -192,8 +191,7 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags, * Don't allow anybody to remap normal RAM that we're using. * mem_init() sets high_memory so only do the check after that. */ - if (mem_init_done && (p < virt_to_phys(high_memory)) && - !(__allow_ioremap_reserved && lmb_is_region_reserved(p, size))) { + if (mem_init_done && (p < virt_to_phys(high_memory))) { printk("__ioremap(): phys addr 0x%llx is RAM lr %p\n", (unsigned long long)p, __builtin_return_address(0)); return NULL; @@ -285,18 +283,18 @@ int map_page(unsigned long va, phys_addr_t pa, int flags) } /* - * Map in a chunk of physical memory starting at start. + * Map in a big chunk of physical memory starting at PAGE_OFFSET. */ -void __init __mapin_ram_chunk(unsigned long offset, unsigned long top) +void __init mapin_ram(void) { unsigned long v, s, f; phys_addr_t p; int ktext; - s = offset; + s = mmu_mapin_ram(); v = PAGE_OFFSET + s; p = memstart_addr + s; - for (; s < top; s += PAGE_SIZE) { + for (; s < total_lowmem; s += PAGE_SIZE) { ktext = ((char *) v >= _stext && (char *) v < etext); f = ktext ? PAGE_KERNEL_TEXT : PAGE_KERNEL; map_page(v, p, f); @@ -309,30 +307,6 @@ void __init __mapin_ram_chunk(unsigned long offset, unsigned long top) } } -void __init mapin_ram(void) -{ - unsigned long s, top; - -#ifndef CONFIG_WII - top = total_lowmem; - s = mmu_mapin_ram(top); - __mapin_ram_chunk(s, top); -#else - if (!wii_hole_size) { - s = mmu_mapin_ram(total_lowmem); - __mapin_ram_chunk(s, total_lowmem); - } else { - top = wii_hole_start; - s = mmu_mapin_ram(top); - __mapin_ram_chunk(s, top); - - top = lmb_end_of_DRAM(); - s = wii_mmu_mapin_mem2(top); - __mapin_ram_chunk(s, top); - } -#endif -} - /* Scan the real Linux page tables and return a PTE pointer for * a virtual address in a context. * Returns true (1) if PTE was found, zero otherwise. The pointer to diff --git a/trunk/arch/powerpc/mm/ppc_mmu_32.c b/trunk/arch/powerpc/mm/ppc_mmu_32.c index f11c2cdcb0fe..2d2a87e10154 100644 --- a/trunk/arch/powerpc/mm/ppc_mmu_32.c +++ b/trunk/arch/powerpc/mm/ppc_mmu_32.c @@ -72,7 +72,7 @@ unsigned long p_mapped_by_bats(phys_addr_t pa) return 0; } -unsigned long __init mmu_mapin_ram(unsigned long top) +unsigned long __init mmu_mapin_ram(void) { unsigned long tot, bl, done; unsigned long max_size = (256<<20); @@ -86,7 +86,7 @@ unsigned long __init mmu_mapin_ram(unsigned long top) /* Make sure we don't map a block larger than the smallest alignment of the physical address. */ - tot = top; + tot = total_lowmem; for (bl = 128<<10; bl < max_size; bl <<= 1) { if (bl * 2 > tot) break; diff --git a/trunk/arch/powerpc/platforms/52xx/efika.c b/trunk/arch/powerpc/platforms/52xx/efika.c index 45c0cb9b67e6..bcc69e1f77c1 100644 --- a/trunk/arch/powerpc/platforms/52xx/efika.c +++ b/trunk/arch/powerpc/platforms/52xx/efika.c @@ -10,7 +10,7 @@ */ #include -#include +#include #include #include #include diff --git a/trunk/arch/powerpc/platforms/Kconfig.cputype b/trunk/arch/powerpc/platforms/Kconfig.cputype index fa0f690d3867..2eab27a94cc9 100644 --- a/trunk/arch/powerpc/platforms/Kconfig.cputype +++ b/trunk/arch/powerpc/platforms/Kconfig.cputype @@ -311,7 +311,7 @@ config NR_CPUS config NOT_COHERENT_CACHE bool - depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON + depends on 4xx || 8xx || E200 || PPC_MPC512x default y config CHECK_CACHE_COHERENCY diff --git a/trunk/arch/powerpc/platforms/amigaone/setup.c b/trunk/arch/powerpc/platforms/amigaone/setup.c index fb4eb0df054c..9290a7a442d0 100644 --- a/trunk/arch/powerpc/platforms/amigaone/setup.c +++ b/trunk/arch/powerpc/platforms/amigaone/setup.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include diff --git a/trunk/arch/powerpc/platforms/cell/spufs/Makefile b/trunk/arch/powerpc/platforms/cell/spufs/Makefile index b9d5d678aa44..b93f877ba504 100644 --- a/trunk/arch/powerpc/platforms/cell/spufs/Makefile +++ b/trunk/arch/powerpc/platforms/cell/spufs/Makefile @@ -13,8 +13,10 @@ SPU_CC := $(SPU_CROSS)gcc SPU_AS := $(SPU_CROSS)gcc SPU_LD := $(SPU_CROSS)ld SPU_OBJCOPY := $(SPU_CROSS)objcopy -SPU_CFLAGS := -O2 -Wall -I$(srctree)/include -D__KERNEL__ -SPU_AFLAGS := -c -D__ASSEMBLY__ -I$(srctree)/include -D__KERNEL__ +SPU_CFLAGS := -O2 -Wall -I$(srctree)/include \ + -I$(objtree)/include2 -D__KERNEL__ +SPU_AFLAGS := -c -D__ASSEMBLY__ -I$(srctree)/include \ + -I$(objtree)/include2 -D__KERNEL__ SPU_LDFLAGS := -N -Ttext=0x0 $(obj)/switch.o: $(obj)/spu_save_dump.h $(obj)/spu_restore_dump.h diff --git a/trunk/arch/powerpc/platforms/chrp/setup.c b/trunk/arch/powerpc/platforms/chrp/setup.c index 8f41685d8f42..52f3df3b4ca0 100644 --- a/trunk/arch/powerpc/platforms/chrp/setup.c +++ b/trunk/arch/powerpc/platforms/chrp/setup.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/trunk/arch/powerpc/platforms/embedded6xx/Kconfig b/trunk/arch/powerpc/platforms/embedded6xx/Kconfig index 524d971a1478..291ac9d8cbee 100644 --- a/trunk/arch/powerpc/platforms/embedded6xx/Kconfig +++ b/trunk/arch/powerpc/platforms/embedded6xx/Kconfig @@ -90,36 +90,3 @@ config MPC10X_OPENPIC config MPC10X_STORE_GATHERING bool "Enable MPC10x store gathering" depends on MPC10X_BRIDGE - -config GAMECUBE_COMMON - bool - -config USBGECKO_UDBG - bool "USB Gecko udbg console for the Nintendo GameCube/Wii" - depends on GAMECUBE_COMMON - help - If you say yes to this option, support will be included for the - USB Gecko adapter as an udbg console. - The USB Gecko is a EXI to USB Serial converter that can be plugged - into a memcard slot in the Nintendo GameCube/Wii. - - This driver bypasses the EXI layer completely. - - If in doubt, say N here. - -config GAMECUBE - bool "Nintendo-GameCube" - depends on EMBEDDED6xx - select GAMECUBE_COMMON - help - Select GAMECUBE if configuring for the Nintendo GameCube. - More information at: - -config WII - bool "Nintendo-Wii" - depends on EMBEDDED6xx - select GAMECUBE_COMMON - help - Select WII if configuring for the Nintendo Wii. - More information at: - diff --git a/trunk/arch/powerpc/platforms/embedded6xx/Makefile b/trunk/arch/powerpc/platforms/embedded6xx/Makefile index 66c23e423f40..0773c08bd444 100644 --- a/trunk/arch/powerpc/platforms/embedded6xx/Makefile +++ b/trunk/arch/powerpc/platforms/embedded6xx/Makefile @@ -7,7 +7,3 @@ obj-$(CONFIG_STORCENTER) += storcenter.o obj-$(CONFIG_PPC_HOLLY) += holly.o obj-$(CONFIG_PPC_PRPMC2800) += prpmc2800.o obj-$(CONFIG_PPC_C2K) += c2k.o -obj-$(CONFIG_USBGECKO_UDBG) += usbgecko_udbg.o -obj-$(CONFIG_GAMECUBE_COMMON) += flipper-pic.o -obj-$(CONFIG_GAMECUBE) += gamecube.o -obj-$(CONFIG_WII) += wii.o hlwd-pic.o diff --git a/trunk/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/trunk/arch/powerpc/platforms/embedded6xx/flipper-pic.c deleted file mode 100644 index d5963285e3be..000000000000 --- a/trunk/arch/powerpc/platforms/embedded6xx/flipper-pic.c +++ /dev/null @@ -1,263 +0,0 @@ -/* - * arch/powerpc/platforms/embedded6xx/flipper-pic.c - * - * Nintendo GameCube/Wii "Flipper" interrupt controller support. - * Copyright (C) 2004-2009 The GameCube Linux Team - * Copyright (C) 2007,2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ -#define DRV_MODULE_NAME "flipper-pic" -#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt - -#include -#include -#include -#include -#include - -#include "flipper-pic.h" - -#define FLIPPER_NR_IRQS 32 - -/* - * Each interrupt has a corresponding bit in both - * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers. - * - * Enabling/disabling an interrupt line involves setting/clearing - * the corresponding bit in IMR. - * Except for the RSW interrupt, all interrupts get deasserted automatically - * when the source deasserts the interrupt. - */ -#define FLIPPER_ICR 0x00 -#define FLIPPER_ICR_RSS (1<<16) /* reset switch state */ - -#define FLIPPER_IMR 0x04 - -#define FLIPPER_RESET 0x24 - - -/* - * IRQ chip hooks. - * - */ - -static void flipper_pic_mask_and_ack(unsigned int virq) -{ - int irq = virq_to_hw(virq); - void __iomem *io_base = get_irq_chip_data(virq); - u32 mask = 1 << irq; - - clrbits32(io_base + FLIPPER_IMR, mask); - /* this is at least needed for RSW */ - out_be32(io_base + FLIPPER_ICR, mask); -} - -static void flipper_pic_ack(unsigned int virq) -{ - int irq = virq_to_hw(virq); - void __iomem *io_base = get_irq_chip_data(virq); - - /* this is at least needed for RSW */ - out_be32(io_base + FLIPPER_ICR, 1 << irq); -} - -static void flipper_pic_mask(unsigned int virq) -{ - int irq = virq_to_hw(virq); - void __iomem *io_base = get_irq_chip_data(virq); - - clrbits32(io_base + FLIPPER_IMR, 1 << irq); -} - -static void flipper_pic_unmask(unsigned int virq) -{ - int irq = virq_to_hw(virq); - void __iomem *io_base = get_irq_chip_data(virq); - - setbits32(io_base + FLIPPER_IMR, 1 << irq); -} - - -static struct irq_chip flipper_pic = { - .name = "flipper-pic", - .ack = flipper_pic_ack, - .mask_ack = flipper_pic_mask_and_ack, - .mask = flipper_pic_mask, - .unmask = flipper_pic_unmask, -}; - -/* - * IRQ host hooks. - * - */ - -static struct irq_host *flipper_irq_host; - -static int flipper_pic_map(struct irq_host *h, unsigned int virq, - irq_hw_number_t hwirq) -{ - set_irq_chip_data(virq, h->host_data); - get_irq_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq); - return 0; -} - -static void flipper_pic_unmap(struct irq_host *h, unsigned int irq) -{ - set_irq_chip_data(irq, NULL); - set_irq_chip(irq, NULL); -} - -static int flipper_pic_match(struct irq_host *h, struct device_node *np) -{ - return 1; -} - - -static struct irq_host_ops flipper_irq_host_ops = { - .map = flipper_pic_map, - .unmap = flipper_pic_unmap, - .match = flipper_pic_match, -}; - -/* - * Platform hooks. - * - */ - -static void __flipper_quiesce(void __iomem *io_base) -{ - /* mask and ack all IRQs */ - out_be32(io_base + FLIPPER_IMR, 0x00000000); - out_be32(io_base + FLIPPER_ICR, 0xffffffff); -} - -struct irq_host * __init flipper_pic_init(struct device_node *np) -{ - struct device_node *pi; - struct irq_host *irq_host = NULL; - struct resource res; - void __iomem *io_base; - int retval; - - pi = of_get_parent(np); - if (!pi) { - pr_err("no parent found\n"); - goto out; - } - if (!of_device_is_compatible(pi, "nintendo,flipper-pi")) { - pr_err("unexpected parent compatible\n"); - goto out; - } - - retval = of_address_to_resource(pi, 0, &res); - if (retval) { - pr_err("no io memory range found\n"); - goto out; - } - io_base = ioremap(res.start, resource_size(&res)); - - pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); - - __flipper_quiesce(io_base); - - irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, FLIPPER_NR_IRQS, - &flipper_irq_host_ops, -1); - if (!irq_host) { - pr_err("failed to allocate irq_host\n"); - return NULL; - } - - irq_host->host_data = io_base; - -out: - return irq_host; -} - -unsigned int flipper_pic_get_irq(void) -{ - void __iomem *io_base = flipper_irq_host->host_data; - int irq; - u32 irq_status; - - irq_status = in_be32(io_base + FLIPPER_ICR) & - in_be32(io_base + FLIPPER_IMR); - if (irq_status == 0) - return NO_IRQ; /* no more IRQs pending */ - - irq = __ffs(irq_status); - return irq_linear_revmap(flipper_irq_host, irq); -} - -/* - * Probe function. - * - */ - -void __init flipper_pic_probe(void) -{ - struct device_node *np; - - np = of_find_compatible_node(NULL, NULL, "nintendo,flipper-pic"); - BUG_ON(!np); - - flipper_irq_host = flipper_pic_init(np); - BUG_ON(!flipper_irq_host); - - irq_set_default_host(flipper_irq_host); - - of_node_put(np); -} - -/* - * Misc functions related to the flipper chipset. - * - */ - -/** - * flipper_quiesce() - quiesce flipper irq controller - * - * Mask and ack all interrupt sources. - * - */ -void flipper_quiesce(void) -{ - void __iomem *io_base = flipper_irq_host->host_data; - - __flipper_quiesce(io_base); -} - -/* - * Resets the platform. - */ -void flipper_platform_reset(void) -{ - void __iomem *io_base; - - if (flipper_irq_host && flipper_irq_host->host_data) { - io_base = flipper_irq_host->host_data; - out_8(io_base + FLIPPER_RESET, 0x00); - } -} - -/* - * Returns non-zero if the reset button is pressed. - */ -int flipper_is_reset_button_pressed(void) -{ - void __iomem *io_base; - u32 icr; - - if (flipper_irq_host && flipper_irq_host->host_data) { - io_base = flipper_irq_host->host_data; - icr = in_be32(io_base + FLIPPER_ICR); - return !(icr & FLIPPER_ICR_RSS); - } - return 0; -} - diff --git a/trunk/arch/powerpc/platforms/embedded6xx/flipper-pic.h b/trunk/arch/powerpc/platforms/embedded6xx/flipper-pic.h deleted file mode 100644 index e339186b5663..000000000000 --- a/trunk/arch/powerpc/platforms/embedded6xx/flipper-pic.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * arch/powerpc/platforms/embedded6xx/flipper-pic.h - * - * Nintendo GameCube/Wii "Flipper" interrupt controller support. - * Copyright (C) 2004-2009 The GameCube Linux Team - * Copyright (C) 2007,2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#ifndef __FLIPPER_PIC_H -#define __FLIPPER_PIC_H - -unsigned int flipper_pic_get_irq(void); -void __init flipper_pic_probe(void); - -void flipper_quiesce(void); -void flipper_platform_reset(void); -int flipper_is_reset_button_pressed(void); - -#endif diff --git a/trunk/arch/powerpc/platforms/embedded6xx/gamecube.c b/trunk/arch/powerpc/platforms/embedded6xx/gamecube.c deleted file mode 100644 index 1106fd99627f..000000000000 --- a/trunk/arch/powerpc/platforms/embedded6xx/gamecube.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * arch/powerpc/platforms/embedded6xx/gamecube.c - * - * Nintendo GameCube board-specific support - * Copyright (C) 2004-2009 The GameCube Linux Team - * Copyright (C) 2007,2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "flipper-pic.h" -#include "usbgecko_udbg.h" - - -static void gamecube_spin(void) -{ - /* spin until power button pressed */ - for (;;) - cpu_relax(); -} - -static void gamecube_restart(char *cmd) -{ - local_irq_disable(); - flipper_platform_reset(); - gamecube_spin(); -} - -static void gamecube_power_off(void) -{ - local_irq_disable(); - gamecube_spin(); -} - -static void gamecube_halt(void) -{ - gamecube_restart(NULL); -} - -static void __init gamecube_init_early(void) -{ - ug_udbg_init(); -} - -static int __init gamecube_probe(void) -{ - unsigned long dt_root; - - dt_root = of_get_flat_dt_root(); - if (!of_flat_dt_is_compatible(dt_root, "nintendo,gamecube")) - return 0; - - return 1; -} - -static void gamecube_shutdown(void) -{ - flipper_quiesce(); -} - -#ifdef CONFIG_KEXEC -static int gamecube_kexec_prepare(struct kimage *image) -{ - return 0; -} -#endif /* CONFIG_KEXEC */ - - -define_machine(gamecube) { - .name = "gamecube", - .probe = gamecube_probe, - .init_early = gamecube_init_early, - .restart = gamecube_restart, - .power_off = gamecube_power_off, - .halt = gamecube_halt, - .init_IRQ = flipper_pic_probe, - .get_irq = flipper_pic_get_irq, - .calibrate_decr = generic_calibrate_decr, - .progress = udbg_progress, - .machine_shutdown = gamecube_shutdown, -#ifdef CONFIG_KEXEC - .machine_kexec_prepare = gamecube_kexec_prepare, -#endif -}; - - -static struct of_device_id gamecube_of_bus[] = { - { .compatible = "nintendo,flipper", }, - { }, -}; - -static int __init gamecube_device_probe(void) -{ - if (!machine_is(gamecube)) - return 0; - - of_platform_bus_probe(NULL, gamecube_of_bus, NULL); - return 0; -} -device_initcall(gamecube_device_probe); - diff --git a/trunk/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/trunk/arch/powerpc/platforms/embedded6xx/hlwd-pic.c deleted file mode 100644 index dd20bff33207..000000000000 --- a/trunk/arch/powerpc/platforms/embedded6xx/hlwd-pic.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * arch/powerpc/platforms/embedded6xx/hlwd-pic.c - * - * Nintendo Wii "Hollywood" interrupt controller support. - * Copyright (C) 2009 The GameCube Linux Team - * Copyright (C) 2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ -#define DRV_MODULE_NAME "hlwd-pic" -#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt - -#include -#include -#include -#include -#include - -#include "hlwd-pic.h" - -#define HLWD_NR_IRQS 32 - -/* - * Each interrupt has a corresponding bit in both - * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers. - * - * Enabling/disabling an interrupt line involves asserting/clearing - * the corresponding bit in IMR. ACK'ing a request simply involves - * asserting the corresponding bit in ICR. - */ -#define HW_BROADWAY_ICR 0x00 -#define HW_BROADWAY_IMR 0x04 - - -/* - * IRQ chip hooks. - * - */ - -static void hlwd_pic_mask_and_ack(unsigned int virq) -{ - int irq = virq_to_hw(virq); - void __iomem *io_base = get_irq_chip_data(virq); - u32 mask = 1 << irq; - - clrbits32(io_base + HW_BROADWAY_IMR, mask); - out_be32(io_base + HW_BROADWAY_ICR, mask); -} - -static void hlwd_pic_ack(unsigned int virq) -{ - int irq = virq_to_hw(virq); - void __iomem *io_base = get_irq_chip_data(virq); - - out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); -} - -static void hlwd_pic_mask(unsigned int virq) -{ - int irq = virq_to_hw(virq); - void __iomem *io_base = get_irq_chip_data(virq); - - clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); -} - -static void hlwd_pic_unmask(unsigned int virq) -{ - int irq = virq_to_hw(virq); - void __iomem *io_base = get_irq_chip_data(virq); - - setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); -} - - -static struct irq_chip hlwd_pic = { - .name = "hlwd-pic", - .ack = hlwd_pic_ack, - .mask_ack = hlwd_pic_mask_and_ack, - .mask = hlwd_pic_mask, - .unmask = hlwd_pic_unmask, -}; - -/* - * IRQ host hooks. - * - */ - -static struct irq_host *hlwd_irq_host; - -static int hlwd_pic_map(struct irq_host *h, unsigned int virq, - irq_hw_number_t hwirq) -{ - set_irq_chip_data(virq, h->host_data); - get_irq_desc(virq)->status |= IRQ_LEVEL; - set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq); - return 0; -} - -static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq) -{ - set_irq_chip_data(irq, NULL); - set_irq_chip(irq, NULL); -} - -static struct irq_host_ops hlwd_irq_host_ops = { - .map = hlwd_pic_map, - .unmap = hlwd_pic_unmap, -}; - -static unsigned int __hlwd_pic_get_irq(struct irq_host *h) -{ - void __iomem *io_base = h->host_data; - int irq; - u32 irq_status; - - irq_status = in_be32(io_base + HW_BROADWAY_ICR) & - in_be32(io_base + HW_BROADWAY_IMR); - if (irq_status == 0) - return NO_IRQ; /* no more IRQs pending */ - - irq = __ffs(irq_status); - return irq_linear_revmap(h, irq); -} - -static void hlwd_pic_irq_cascade(unsigned int cascade_virq, - struct irq_desc *desc) -{ - struct irq_host *irq_host = get_irq_data(cascade_virq); - unsigned int virq; - - spin_lock(&desc->lock); - desc->chip->mask(cascade_virq); /* IRQ_LEVEL */ - spin_unlock(&desc->lock); - - virq = __hlwd_pic_get_irq(irq_host); - if (virq != NO_IRQ) - generic_handle_irq(virq); - else - pr_err("spurious interrupt!\n"); - - spin_lock(&desc->lock); - desc->chip->ack(cascade_virq); /* IRQ_LEVEL */ - if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) - desc->chip->unmask(cascade_virq); - spin_unlock(&desc->lock); -} - -/* - * Platform hooks. - * - */ - -static void __hlwd_quiesce(void __iomem *io_base) -{ - /* mask and ack all IRQs */ - out_be32(io_base + HW_BROADWAY_IMR, 0); - out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff); -} - -struct irq_host *hlwd_pic_init(struct device_node *np) -{ - struct irq_host *irq_host; - struct resource res; - void __iomem *io_base; - int retval; - - retval = of_address_to_resource(np, 0, &res); - if (retval) { - pr_err("no io memory range found\n"); - return NULL; - } - io_base = ioremap(res.start, resource_size(&res)); - if (!io_base) { - pr_err("ioremap failed\n"); - return NULL; - } - - pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); - - __hlwd_quiesce(io_base); - - irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, HLWD_NR_IRQS, - &hlwd_irq_host_ops, -1); - if (!irq_host) { - pr_err("failed to allocate irq_host\n"); - return NULL; - } - irq_host->host_data = io_base; - - return irq_host; -} - -unsigned int hlwd_pic_get_irq(void) -{ - return __hlwd_pic_get_irq(hlwd_irq_host); -} - -/* - * Probe function. - * - */ - -void hlwd_pic_probe(void) -{ - struct irq_host *host; - struct device_node *np; - const u32 *interrupts; - int cascade_virq; - - for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") { - interrupts = of_get_property(np, "interrupts", NULL); - if (interrupts) { - host = hlwd_pic_init(np); - BUG_ON(!host); - cascade_virq = irq_of_parse_and_map(np, 0); - set_irq_data(cascade_virq, host); - set_irq_chained_handler(cascade_virq, - hlwd_pic_irq_cascade); - hlwd_irq_host = host; - break; - } - } -} - -/** - * hlwd_quiesce() - quiesce hollywood irq controller - * - * Mask and ack all interrupt sources. - * - */ -void hlwd_quiesce(void) -{ - void __iomem *io_base = hlwd_irq_host->host_data; - - __hlwd_quiesce(io_base); -} - diff --git a/trunk/arch/powerpc/platforms/embedded6xx/hlwd-pic.h b/trunk/arch/powerpc/platforms/embedded6xx/hlwd-pic.h deleted file mode 100644 index d2e5a092761e..000000000000 --- a/trunk/arch/powerpc/platforms/embedded6xx/hlwd-pic.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * arch/powerpc/platforms/embedded6xx/hlwd-pic.h - * - * Nintendo Wii "Hollywood" interrupt controller support. - * Copyright (C) 2009 The GameCube Linux Team - * Copyright (C) 2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#ifndef __HLWD_PIC_H -#define __HLWD_PIC_H - -extern unsigned int hlwd_pic_get_irq(void); -extern void hlwd_pic_probe(void); -extern void hlwd_quiesce(void); - -#endif diff --git a/trunk/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c b/trunk/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c deleted file mode 100644 index edc956cc8b13..000000000000 --- a/trunk/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - * arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c - * - * udbg serial input/output routines for the USB Gecko adapter. - * Copyright (C) 2008-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#include - -#include -#include -#include -#include - -#include "usbgecko_udbg.h" - - -#define EXI_CLK_32MHZ 5 - -#define EXI_CSR 0x00 -#define EXI_CSR_CLKMASK (0x7<<4) -#define EXI_CSR_CLK_32MHZ (EXI_CLK_32MHZ<<4) -#define EXI_CSR_CSMASK (0x7<<7) -#define EXI_CSR_CS_0 (0x1<<7) /* Chip Select 001 */ - -#define EXI_CR 0x0c -#define EXI_CR_TSTART (1<<0) -#define EXI_CR_WRITE (1<<2) -#define EXI_CR_READ_WRITE (2<<2) -#define EXI_CR_TLEN(len) (((len)-1)<<4) - -#define EXI_DATA 0x10 - -#define UG_READ_ATTEMPTS 100 -#define UG_WRITE_ATTEMPTS 100 - - -static void __iomem *ug_io_base; - -/* - * Performs one input/output transaction between the exi host and the usbgecko. - */ -static u32 ug_io_transaction(u32 in) -{ - u32 __iomem *csr_reg = ug_io_base + EXI_CSR; - u32 __iomem *data_reg = ug_io_base + EXI_DATA; - u32 __iomem *cr_reg = ug_io_base + EXI_CR; - u32 csr, data, cr; - - /* select */ - csr = EXI_CSR_CLK_32MHZ | EXI_CSR_CS_0; - out_be32(csr_reg, csr); - - /* read/write */ - data = in; - out_be32(data_reg, data); - cr = EXI_CR_TLEN(2) | EXI_CR_READ_WRITE | EXI_CR_TSTART; - out_be32(cr_reg, cr); - - while (in_be32(cr_reg) & EXI_CR_TSTART) - barrier(); - - /* deselect */ - out_be32(csr_reg, 0); - - /* result */ - data = in_be32(data_reg); - - return data; -} - -/* - * Returns true if an usbgecko adapter is found. - */ -static int ug_is_adapter_present(void) -{ - if (!ug_io_base) - return 0; - - return ug_io_transaction(0x90000000) == 0x04700000; -} - -/* - * Returns true if the TX fifo is ready for transmission. - */ -static int ug_is_txfifo_ready(void) -{ - return ug_io_transaction(0xc0000000) & 0x04000000; -} - -/* - * Tries to transmit a character. - * If the TX fifo is not ready the result is undefined. - */ -static void ug_raw_putc(char ch) -{ - ug_io_transaction(0xb0000000 | (ch << 20)); -} - -/* - * Transmits a character. - * It silently fails if the TX fifo is not ready after a number of retries. - */ -static void ug_putc(char ch) -{ - int count = UG_WRITE_ATTEMPTS; - - if (!ug_io_base) - return; - - if (ch == '\n') - ug_putc('\r'); - - while (!ug_is_txfifo_ready() && count--) - barrier(); - if (count) - ug_raw_putc(ch); -} - -/* - * Returns true if the RX fifo is ready for transmission. - */ -static int ug_is_rxfifo_ready(void) -{ - return ug_io_transaction(0xd0000000) & 0x04000000; -} - -/* - * Tries to receive a character. - * If a character is unavailable the function returns -1. - */ -static int ug_raw_getc(void) -{ - u32 data = ug_io_transaction(0xa0000000); - if (data & 0x08000000) - return (data >> 16) & 0xff; - else - return -1; -} - -/* - * Receives a character. - * It fails if the RX fifo is not ready after a number of retries. - */ -static int ug_getc(void) -{ - int count = UG_READ_ATTEMPTS; - - if (!ug_io_base) - return -1; - - while (!ug_is_rxfifo_ready() && count--) - barrier(); - return ug_raw_getc(); -} - -/* - * udbg functions. - * - */ - -/* - * Transmits a character. - */ -void ug_udbg_putc(char ch) -{ - ug_putc(ch); -} - -/* - * Receives a character. Waits until a character is available. - */ -static int ug_udbg_getc(void) -{ - int ch; - - while ((ch = ug_getc()) == -1) - barrier(); - return ch; -} - -/* - * Receives a character. If a character is not available, returns -1. - */ -static int ug_udbg_getc_poll(void) -{ - if (!ug_is_rxfifo_ready()) - return -1; - return ug_getc(); -} - -/* - * Retrieves and prepares the virtual address needed to access the hardware. - */ -static void __iomem *ug_udbg_setup_exi_io_base(struct device_node *np) -{ - void __iomem *exi_io_base = NULL; - phys_addr_t paddr; - const unsigned int *reg; - - reg = of_get_property(np, "reg", NULL); - if (reg) { - paddr = of_translate_address(np, reg); - if (paddr) - exi_io_base = ioremap(paddr, reg[1]); - } - return exi_io_base; -} - -/* - * Checks if a USB Gecko adapter is inserted in any memory card slot. - */ -static void __iomem *ug_udbg_probe(void __iomem *exi_io_base) -{ - int i; - - /* look for a usbgecko on memcard slots A and B */ - for (i = 0; i < 2; i++) { - ug_io_base = exi_io_base + 0x14 * i; - if (ug_is_adapter_present()) - break; - } - if (i == 2) - ug_io_base = NULL; - return ug_io_base; - -} - -/* - * USB Gecko udbg support initialization. - */ -void __init ug_udbg_init(void) -{ - struct device_node *np; - void __iomem *exi_io_base; - - if (ug_io_base) - udbg_printf("%s: early -> final\n", __func__); - - np = of_find_compatible_node(NULL, NULL, "nintendo,flipper-exi"); - if (!np) { - udbg_printf("%s: EXI node not found\n", __func__); - goto done; - } - - exi_io_base = ug_udbg_setup_exi_io_base(np); - if (!exi_io_base) { - udbg_printf("%s: failed to setup EXI io base\n", __func__); - goto done; - } - - if (!ug_udbg_probe(exi_io_base)) { - udbg_printf("usbgecko_udbg: not found\n"); - iounmap(exi_io_base); - } else { - udbg_putc = ug_udbg_putc; - udbg_getc = ug_udbg_getc; - udbg_getc_poll = ug_udbg_getc_poll; - udbg_printf("usbgecko_udbg: ready\n"); - } - -done: - if (np) - of_node_put(np); - return; -} - -#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO - -static phys_addr_t __init ug_early_grab_io_addr(void) -{ -#if defined(CONFIG_GAMECUBE) - return 0x0c000000; -#elif defined(CONFIG_WII) - return 0x0d000000; -#else -#error Invalid platform for USB Gecko based early debugging. -#endif -} - -/* - * USB Gecko early debug support initialization for udbg. - */ -void __init udbg_init_usbgecko(void) -{ - void __iomem *early_debug_area; - void __iomem *exi_io_base; - - /* - * At this point we have a BAT already setup that enables I/O - * to the EXI hardware. - * - * The BAT uses a virtual address range reserved at the fixmap. - * This must match the virtual address configured in - * head_32.S:setup_usbgecko_bat(). - */ - early_debug_area = (void __iomem *)__fix_to_virt(FIX_EARLY_DEBUG_BASE); - exi_io_base = early_debug_area + 0x00006800; - - /* try to detect a USB Gecko */ - if (!ug_udbg_probe(exi_io_base)) - return; - - /* we found a USB Gecko, load udbg hooks */ - udbg_putc = ug_udbg_putc; - udbg_getc = ug_udbg_getc; - udbg_getc_poll = ug_udbg_getc_poll; - - /* - * Prepare again the same BAT for MMU_init. - * This allows udbg I/O to continue working after the MMU is - * turned on for real. - * It is safe to continue using the same virtual address as it is - * a reserved fixmap area. - */ - setbat(1, (unsigned long)early_debug_area, - ug_early_grab_io_addr(), 128*1024, PAGE_KERNEL_NCG); -} - -#endif /* CONFIG_PPC_EARLY_DEBUG_USBGECKO */ - diff --git a/trunk/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h b/trunk/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h deleted file mode 100644 index bb6cde4ad764..000000000000 --- a/trunk/arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * arch/powerpc/platforms/embedded6xx/usbgecko_udbg.h - * - * udbg serial input/output routines for the USB Gecko adapter. - * Copyright (C) 2008-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ - -#ifndef __USBGECKO_UDBG_H -#define __USBGECKO_UDBG_H - -#ifdef CONFIG_USBGECKO_UDBG - -extern void __init ug_udbg_init(void); - -#else - -static inline void __init ug_udbg_init(void) -{ -} - -#endif /* CONFIG_USBGECKO_UDBG */ - -void __init udbg_init_usbgecko(void); - -#endif /* __USBGECKO_UDBG_H */ diff --git a/trunk/arch/powerpc/platforms/embedded6xx/wii.c b/trunk/arch/powerpc/platforms/embedded6xx/wii.c deleted file mode 100644 index 57e5b608fa1a..000000000000 --- a/trunk/arch/powerpc/platforms/embedded6xx/wii.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * arch/powerpc/platforms/embedded6xx/wii.c - * - * Nintendo Wii board-specific support - * Copyright (C) 2008-2009 The GameCube Linux Team - * Copyright (C) 2008,2009 Albert Herranz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - */ -#define DRV_MODULE_NAME "wii" -#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "flipper-pic.h" -#include "hlwd-pic.h" -#include "usbgecko_udbg.h" - -/* control block */ -#define HW_CTRL_COMPATIBLE "nintendo,hollywood-control" - -#define HW_CTRL_RESETS 0x94 -#define HW_CTRL_RESETS_SYS (1<<0) - -/* gpio */ -#define HW_GPIO_COMPATIBLE "nintendo,hollywood-gpio" - -#define HW_GPIO_BASE(idx) (idx * 0x20) -#define HW_GPIO_OUT(idx) (HW_GPIO_BASE(idx) + 0) -#define HW_GPIO_DIR(idx) (HW_GPIO_BASE(idx) + 4) - -#define HW_GPIO_SHUTDOWN (1<<1) -#define HW_GPIO_SLOT_LED (1<<5) -#define HW_GPIO_SENSOR_BAR (1<<8) - - -static void __iomem *hw_ctrl; -static void __iomem *hw_gpio; - -unsigned long wii_hole_start; -unsigned long wii_hole_size; - - -static int __init page_aligned(unsigned long x) -{ - return !(x & (PAGE_SIZE-1)); -} - -void __init wii_memory_fixups(void) -{ - struct lmb_property *p = lmb.memory.region; - - /* - * This is part of a workaround to allow the use of two - * discontiguous RAM ranges on the Wii, even if this is - * currently unsupported on 32-bit PowerPC Linux. - * - * We coealesce the two memory ranges of the Wii into a - * single range, then create a reservation for the "hole" - * between both ranges. - */ - - BUG_ON(lmb.memory.cnt != 2); - BUG_ON(!page_aligned(p[0].base) || !page_aligned(p[1].base)); - - p[0].size = _ALIGN_DOWN(p[0].size, PAGE_SIZE); - p[1].size = _ALIGN_DOWN(p[1].size, PAGE_SIZE); - - wii_hole_start = p[0].base + p[0].size; - wii_hole_size = p[1].base - wii_hole_start; - - pr_info("MEM1: <%08llx %08llx>\n", p[0].base, p[0].size); - pr_info("HOLE: <%08lx %08lx>\n", wii_hole_start, wii_hole_size); - pr_info("MEM2: <%08llx %08llx>\n", p[1].base, p[1].size); - - p[0].size += wii_hole_size + p[1].size; - - lmb.memory.cnt = 1; - lmb_analyze(); - - /* reserve the hole */ - lmb_reserve(wii_hole_start, wii_hole_size); - - /* allow ioremapping the address space in the hole */ - __allow_ioremap_reserved = 1; -} - -unsigned long __init wii_mmu_mapin_mem2(unsigned long top) -{ - unsigned long delta, size, bl; - unsigned long max_size = (256<<20); - - /* MEM2 64MB@0x10000000 */ - delta = wii_hole_start + wii_hole_size; - size = top - delta; - for (bl = 128<<10; bl < max_size; bl <<= 1) { - if (bl * 2 > size) - break; - } - setbat(4, PAGE_OFFSET+delta, delta, bl, PAGE_KERNEL_X); - return delta + bl; -} - -static void wii_spin(void) -{ - local_irq_disable(); - for (;;) - cpu_relax(); -} - -static void __iomem *wii_ioremap_hw_regs(char *name, char *compatible) -{ - void __iomem *hw_regs = NULL; - struct device_node *np; - struct resource res; - int error = -ENODEV; - - np = of_find_compatible_node(NULL, NULL, compatible); - if (!np) { - pr_err("no compatible node found for %s\n", compatible); - goto out; - } - error = of_address_to_resource(np, 0, &res); - if (error) { - pr_err("no valid reg found for %s\n", np->name); - goto out_put; - } - - hw_regs = ioremap(res.start, resource_size(&res)); - if (hw_regs) { - pr_info("%s at 0x%08x mapped to 0x%p\n", name, - res.start, hw_regs); - } - -out_put: - of_node_put(np); -out: - return hw_regs; -} - -static void __init wii_setup_arch(void) -{ - hw_ctrl = wii_ioremap_hw_regs("hw_ctrl", HW_CTRL_COMPATIBLE); - hw_gpio = wii_ioremap_hw_regs("hw_gpio", HW_GPIO_COMPATIBLE); - if (hw_gpio) { - /* turn off the front blue led and IR light */ - clrbits32(hw_gpio + HW_GPIO_OUT(0), - HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR); - } -} - -static void wii_restart(char *cmd) -{ - local_irq_disable(); - - if (hw_ctrl) { - /* clear the system reset pin to cause a reset */ - clrbits32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS); - } - wii_spin(); -} - -static void wii_power_off(void) -{ - local_irq_disable(); - - if (hw_gpio) { - /* make sure that the poweroff GPIO is configured as output */ - setbits32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN); - - /* drive the poweroff GPIO high */ - setbits32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN); - } - wii_spin(); -} - -static void wii_halt(void) -{ - if (ppc_md.restart) - ppc_md.restart(NULL); - wii_spin(); -} - -static void __init wii_init_early(void) -{ - ug_udbg_init(); -} - -static void __init wii_pic_probe(void) -{ - flipper_pic_probe(); - hlwd_pic_probe(); -} - -static int __init wii_probe(void) -{ - unsigned long dt_root; - - dt_root = of_get_flat_dt_root(); - if (!of_flat_dt_is_compatible(dt_root, "nintendo,wii")) - return 0; - - return 1; -} - -static void wii_shutdown(void) -{ - hlwd_quiesce(); - flipper_quiesce(); -} - -#ifdef CONFIG_KEXEC -static int wii_machine_kexec_prepare(struct kimage *image) -{ - return 0; -} -#endif /* CONFIG_KEXEC */ - -define_machine(wii) { - .name = "wii", - .probe = wii_probe, - .init_early = wii_init_early, - .setup_arch = wii_setup_arch, - .restart = wii_restart, - .power_off = wii_power_off, - .halt = wii_halt, - .init_IRQ = wii_pic_probe, - .get_irq = flipper_pic_get_irq, - .calibrate_decr = generic_calibrate_decr, - .progress = udbg_progress, - .machine_shutdown = wii_shutdown, -#ifdef CONFIG_KEXEC - .machine_kexec_prepare = wii_machine_kexec_prepare, -#endif -}; - -static struct of_device_id wii_of_bus[] = { - { .compatible = "nintendo,hollywood", }, - { }, -}; - -static int __init wii_device_probe(void) -{ - if (!machine_is(wii)) - return 0; - - of_platform_bus_probe(NULL, wii_of_bus, NULL); - return 0; -} -device_initcall(wii_device_probe); - diff --git a/trunk/arch/powerpc/platforms/powermac/bootx_init.c b/trunk/arch/powerpc/platforms/powermac/bootx_init.c index 9dd789a7370d..cf660916ae0b 100644 --- a/trunk/arch/powerpc/platforms/powermac/bootx_init.c +++ b/trunk/arch/powerpc/platforms/powermac/bootx_init.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/trunk/arch/s390/include/asm/asm-offsets.h b/trunk/arch/s390/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/s390/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/s390/include/asm/elf.h b/trunk/arch/s390/include/asm/elf.h index 354d42616c7e..e885442c1dfe 100644 --- a/trunk/arch/s390/include/asm/elf.h +++ b/trunk/arch/s390/include/asm/elf.h @@ -155,6 +155,7 @@ extern unsigned int vdso_enabled; } while (0) #define CORE_DUMP_USE_REGSET +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/score/include/asm/asm-offsets.h b/trunk/arch/score/include/asm/asm-offsets.h deleted file mode 100644 index d370ee36a182..000000000000 --- a/trunk/arch/score/include/asm/asm-offsets.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/trunk/arch/score/include/asm/cacheflush.h b/trunk/arch/score/include/asm/cacheflush.h index 1d545d0ce206..caaba24036e3 100644 --- a/trunk/arch/score/include/asm/cacheflush.h +++ b/trunk/arch/score/include/asm/cacheflush.h @@ -14,12 +14,10 @@ extern void flush_cache_sigtramp(unsigned long addr); extern void flush_icache_all(void); extern void flush_icache_range(unsigned long start, unsigned long end); extern void flush_dcache_range(unsigned long start, unsigned long end); -extern void flush_dcache_page(struct page *page); - -#define PG_dcache_dirty PG_arch_1 #define flush_cache_dup_mm(mm) do {} while (0) #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 +#define flush_dcache_page(page) do {} while (0) #define flush_dcache_mmap_lock(mapping) do {} while (0) #define flush_dcache_mmap_unlock(mapping) do {} while (0) #define flush_cache_vmap(start, end) do {} while (0) diff --git a/trunk/arch/score/include/asm/delay.h b/trunk/arch/score/include/asm/delay.h index 529e494712a5..6726ec199dc0 100644 --- a/trunk/arch/score/include/asm/delay.h +++ b/trunk/arch/score/include/asm/delay.h @@ -1,8 +1,6 @@ #ifndef _ASM_SCORE_DELAY_H #define _ASM_SCORE_DELAY_H -#include - static inline void __delay(unsigned long loops) { /* 3 cycles per loop. */ diff --git a/trunk/arch/score/include/asm/elf.h b/trunk/arch/score/include/asm/elf.h index f478ce94181f..43526d9fda93 100644 --- a/trunk/arch/score/include/asm/elf.h +++ b/trunk/arch/score/include/asm/elf.h @@ -61,6 +61,7 @@ struct task_struct; struct pt_regs; #define CORE_DUMP_USE_REGSET +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This yields a mask that user programs can use to figure out what diff --git a/trunk/arch/score/include/asm/page.h b/trunk/arch/score/include/asm/page.h index 1e9ade8e77e6..d92a5a2d36d4 100644 --- a/trunk/arch/score/include/asm/page.h +++ b/trunk/arch/score/include/asm/page.h @@ -74,7 +74,7 @@ extern unsigned long max_pfn; #define page_to_bus(page) (page_to_phys(page)) #define phys_to_page(paddr) (pfn_to_page(phys_to_pfn(paddr))) -#define pfn_valid(pfn) (((pfn) >= min_low_pfn) && ((pfn) < max_low_pfn)) +#define pfn_valid(pfn) ((pfn) >= min_low_pfn && (pfn) < max_mapnr) #define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) diff --git a/trunk/arch/score/kernel/setup.c b/trunk/arch/score/kernel/setup.c index 6f898c057878..6a2503c75c4e 100644 --- a/trunk/arch/score/kernel/setup.c +++ b/trunk/arch/score/kernel/setup.c @@ -49,7 +49,6 @@ static void __init bootmem_init(void) min_low_pfn = PFN_UP(MEMORY_START); max_low_pfn = PFN_UP(MEMORY_START + MEMORY_SIZE); - max_mapnr = max_low_pfn - min_low_pfn; /* Initialize the boot-time allocator with low memory only. */ bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn, diff --git a/trunk/arch/score/mm/cache.c b/trunk/arch/score/mm/cache.c index b25e95743600..dbac9d9dfddd 100644 --- a/trunk/arch/score/mm/cache.c +++ b/trunk/arch/score/mm/cache.c @@ -29,7 +29,6 @@ #include #include #include -#include #include @@ -52,27 +51,6 @@ static void flush_data_cache_page(unsigned long addr) } } -void flush_dcache_page(struct page *page) -{ - struct address_space *mapping = page_mapping(page); - unsigned long addr; - - if (PageHighMem(page)) - return; - if (mapping && !mapping_mapped(mapping)) { - set_bit(PG_dcache_dirty, &(page)->flags); - return; - } - - /* - * We could delay the flush for the !page_mapping case too. But that - * case is for exec env/arg pages and those are %99 certainly going to - * get faulted into the tlb (and thus flushed) anyways. - */ - addr = (unsigned long) page_address(page); - flush_data_cache_page(addr); -} - /* called by update_mmu_cache. */ void __update_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) @@ -85,11 +63,11 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address, if (unlikely(!pfn_valid(pfn))) return; page = pfn_to_page(pfn); - if (page_mapping(page) && test_bit(PG_dcache_dirty, &(page)->flags)) { + if (page_mapping(page) && test_bit(PG_arch_1, &page->flags)) { addr = (unsigned long) page_address(page); if (exec) flush_data_cache_page(addr); - clear_bit(PG_dcache_dirty, &(page)->flags); + clear_bit(PG_arch_1, &page->flags); } } diff --git a/trunk/arch/score/mm/init.c b/trunk/arch/score/mm/init.c index 8c15b2c85d5a..4e3dcd0c4716 100644 --- a/trunk/arch/score/mm/init.c +++ b/trunk/arch/score/mm/init.c @@ -83,6 +83,7 @@ void __init mem_init(void) unsigned long codesize, reservedpages, datasize, initsize; unsigned long tmp, ram = 0; + max_mapnr = max_low_pfn; high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT); totalram_pages += free_all_bootmem(); totalram_pages -= setup_zero_page(); /* Setup zeroed pages. */ @@ -100,6 +101,10 @@ void __init mem_init(void) datasize = (unsigned long) &_edata - (unsigned long) &_etext; initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; + kclist_add(&kcore_mem, __va(0), max_low_pfn << PAGE_SHIFT); + kclist_add(&kcore_vmalloc, (void *) VMALLOC_START, + VMALLOC_END - VMALLOC_START); + printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, " "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n", (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), diff --git a/trunk/arch/sh/Kconfig.debug b/trunk/arch/sh/Kconfig.debug index 12fec72fec5f..55907af1dc25 100644 --- a/trunk/arch/sh/Kconfig.debug +++ b/trunk/arch/sh/Kconfig.debug @@ -19,6 +19,50 @@ config SH_STANDARD_BIOS mask ROM and no flash (WindowsCE machines fall in this category). If unsure, say N. +config EARLY_SCIF_CONSOLE + bool "Use early SCIF console" + help + This enables an early console using a fixed SCIF port. This can + be used by platforms that are either not running the SH + standard BIOS, or do not wish to use the BIOS callbacks for the + serial I/O. + +config EARLY_SCIF_CONSOLE_PORT + hex + depends on EARLY_SCIF_CONSOLE + default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705 + default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721 + default "0xf8420000" if CPU_SUBTYPE_SH7619 + default "0xff804000" if CPU_SUBTYPE_MXG + default "0xffc30000" if CPU_SUBTYPE_SHX3 + default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \ + CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \ + CPU_SUBTYPE_SH7343 + default "0xfe4c0000" if CPU_SUBTYPE_SH7757 + default "0xffeb0000" if CPU_SUBTYPE_SH7785 + default "0xffeb0000" if CPU_SUBTYPE_SH7786 + default "0xfffe8000" if CPU_SUBTYPE_SH7203 + default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 + default "0xffe80000" if CPU_SH4 + default "0xa4000150" if CPU_SH3 + default "0x00000000" + +config EARLY_PRINTK + bool "Early printk support" + depends on SH_STANDARD_BIOS || EARLY_SCIF_CONSOLE + help + Say Y here to redirect kernel printk messages to the serial port + used by the SH-IPL bootloader, starting very early in the boot + process and ending when the kernel's serial console is initialised. + This option is only useful porting the kernel to a new machine, + when the kernel may crash or hang before the serial console is + initialised. If unsure, say N. + + On devices that are running SH-IPL and want to keep the port + initialization consistent while not using the BIOS callbacks, + select both the EARLY_SCIF_CONSOLE and SH_STANDARD_BIOS, using + the kernel command line option to toggle back and forth. + config STACK_DEBUG bool "Check for stack overflows" depends on DEBUG_KERNEL && SUPERH32 diff --git a/trunk/arch/sh/Makefile b/trunk/arch/sh/Makefile index db91925c79d1..ac17c5ac550e 100644 --- a/trunk/arch/sh/Makefile +++ b/trunk/arch/sh/Makefile @@ -205,7 +205,10 @@ libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y) BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.srec uImage.bin \ zImage vmlinux.srec romImage -PHONY += $(BOOT_TARGETS) +PHONY += maketools $(BOOT_TARGETS) FORCE + +maketools: include/linux/version.h FORCE + $(Q)$(MAKE) $(build)=arch/sh/tools include/asm-sh/machtypes.h all: $(KBUILD_IMAGE) @@ -214,8 +217,7 @@ $(BOOT_TARGETS): vmlinux compressed: zImage -archprepare: - $(Q)$(MAKE) $(build)=arch/sh/tools include/generated/machtypes.h +archprepare: maketools archclean: $(Q)$(MAKE) $(clean)=$(boot) @@ -232,3 +234,5 @@ define archhelp @echo ' uImage.bz2 - Kernel-only image for U-Boot (bzip2)' @echo ' uImage.lzma - Kernel-only image for U-Boot (lzma)' endef + +CLEAN_FILES += include/asm-sh/machtypes.h diff --git a/trunk/arch/sh/boards/mach-ap325rxa/setup.c b/trunk/arch/sh/boards/mach-ap325rxa/setup.c index 1f5fa5c44f6d..cf9dc12dfeb1 100644 --- a/trunk/arch/sh/boards/mach-ap325rxa/setup.c +++ b/trunk/arch/sh/boards/mach-ap325rxa/setup.c @@ -316,24 +316,20 @@ static struct soc_camera_platform_info camera_info = { .format_name = "UYVY", .format_depth = 16, .format = { - .code = V4L2_MBUS_FMT_YUYV8_2X8_BE, + .pixelformat = V4L2_PIX_FMT_UYVY, .colorspace = V4L2_COLORSPACE_SMPTE170M, - .field = V4L2_FIELD_NONE, .width = 640, .height = 480, }, .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | - SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | - SOCAM_DATA_ACTIVE_HIGH, + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, .set_capture = camera_set_capture, -}; - -struct soc_camera_link camera_link = { - .bus_id = 0, - .add_device = ap325rxa_camera_add, - .del_device = ap325rxa_camera_del, - .module_name = "soc_camera_platform", - .priv = &camera_info, + .link = { + .bus_id = 0, + .add_device = ap325rxa_camera_add, + .del_device = ap325rxa_camera_del, + .module_name = "soc_camera_platform", + }, }; static void dummy_release(struct device *dev) @@ -351,7 +347,7 @@ static struct platform_device camera_device = { static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev) { - if (icl != &camera_link || camera_probe() <= 0) + if (icl != &camera_info.link || camera_probe() <= 0) return -ENODEV; camera_info.dev = dev; @@ -361,7 +357,7 @@ static int ap325rxa_camera_add(struct soc_camera_link *icl, static void ap325rxa_camera_del(struct soc_camera_link *icl) { - if (icl != &camera_link) + if (icl != &camera_info.link) return; platform_device_unregister(&camera_device); @@ -474,15 +470,13 @@ static struct ov772x_camera_info ov7725_info = { .buswidth = SOCAM_DATAWIDTH_8, .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP, .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), -}; - -static struct soc_camera_link ov7725_link = { - .bus_id = 0, - .power = ov7725_power, - .board_info = &ap325rxa_i2c_camera[0], - .i2c_adapter_id = 0, - .module_name = "ov772x", - .priv = &ov7725_info, + .link = { + .bus_id = 0, + .power = ov7725_power, + .board_info = &ap325rxa_i2c_camera[0], + .i2c_adapter_id = 0, + .module_name = "ov772x", + }, }; static struct platform_device ap325rxa_camera[] = { @@ -490,13 +484,13 @@ static struct platform_device ap325rxa_camera[] = { .name = "soc-camera-pdrv", .id = 0, .dev = { - .platform_data = &ov7725_link, + .platform_data = &ov7725_info.link, }, }, { .name = "soc-camera-pdrv", .id = 1, .dev = { - .platform_data = &camera_link, + .platform_data = &camera_info.link, }, }, }; diff --git a/trunk/arch/sh/boards/mach-ecovec24/setup.c b/trunk/arch/sh/boards/mach-ecovec24/setup.c index 194aaca22d47..826e62326d51 100644 --- a/trunk/arch/sh/boards/mach-ecovec24/setup.c +++ b/trunk/arch/sh/boards/mach-ecovec24/setup.c @@ -19,18 +19,11 @@ #include #include #include -#include -#include -#include -#include #include #include #include #include