From c0e46359efaf56c8742f8194f3a19cbe426f8125 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 10 May 2012 17:23:58 +0900 Subject: [PATCH] --- yaml --- r: 305244 b: refs/heads/master c: c4f10e5cd79ce09ef94be0924395c62350bf262d h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index a1d52f29cf69..01d0de28c375 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bcb86e0adb6397013616567249d2d82f94b27891 +refs/heads/master: c4f10e5cd79ce09ef94be0924395c62350bf262d diff --git a/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c index 9f0109f6bfd3..f25127c46eca 100644 --- a/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c +++ b/trunk/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c @@ -1907,8 +1907,9 @@ static struct pinmux_gpio pinmux_gpios[] = { static struct pinmux_cfg_reg pinmux_config_regs[] = { /* "name" addr register_size Field_Width */ + /* where Field_Width is 1 for single mode registers or 4 for upto 16 - /* mode registers and modes are described in assending order [0..16] */ + mode registers and modes are described in assending order [0..16] */ { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 0, 0, 0, 0, 0, 0, 0, 0,