From c14b8f365ba2db0ba0b1dac3fea0dbb8d316af83 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 26 Nov 2007 23:40:01 +0100 Subject: [PATCH] --- yaml --- r: 78033 b: refs/heads/master c: e9c33572a92aa2ee565da5136745ea304ac23d9a h: refs/heads/master i: 78031: d9ca7e616d5f581b0a77b80e36321bd91069ee32 v: v3 --- [refs] | 2 +- trunk/arch/mips/mm/c-r4k.c | 4 ++-- trunk/include/asm-mips/r4kcache.h | 7 +++++++ 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 4ba5ca8774f3..6723cb1dbd17 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 87353d8ac39c52784da605ecbe965ecdfad609ad +refs/heads/master: e9c33572a92aa2ee565da5136745ea304ac23d9a diff --git a/trunk/arch/mips/mm/c-r4k.c b/trunk/arch/mips/mm/c-r4k.c index c91b59680695..06074948450d 100644 --- a/trunk/arch/mips/mm/c-r4k.c +++ b/trunk/arch/mips/mm/c-r4k.c @@ -589,7 +589,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) if (size >= scache_size) r4k_blast_scache(); else - blast_scache_range(addr, addr + size); + blast_inv_scache_range(addr, addr + size); return; } @@ -597,7 +597,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) r4k_blast_dcache(); } else { R4600_HIT_CACHEOP_WAR_IMPL; - blast_dcache_range(addr, addr + size); + blast_inv_dcache_range(addr, addr + size); } bc_inv(addr, size); diff --git a/trunk/include/asm-mips/r4kcache.h b/trunk/include/asm-mips/r4kcache.h index 2b8466ffd3ca..4c140db36786 100644 --- a/trunk/include/asm-mips/r4kcache.h +++ b/trunk/include/asm-mips/r4kcache.h @@ -403,6 +403,13 @@ __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16) +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32) +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16) +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32) +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64) +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128) + /* build blast_xxx_range, protected_blast_xxx_range */ #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \