From c18c37273d306731f642983a44789b8ac28e27d1 Mon Sep 17 00:00:00 2001 From: Russell King Date: Fri, 15 Jan 2010 18:19:56 +0000 Subject: [PATCH] --- yaml --- r: 191820 b: refs/heads/master c: 4ce1755275c13eb0de90fe23c950bce5e81e680f h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-versatile/timer-sp.c | 12 +++++------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index 1125cd879818..90874da0ab08 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fe8e1a57f0ccdaede41618ca9ced7d746b6298d3 +refs/heads/master: 4ce1755275c13eb0de90fe23c950bce5e81e680f diff --git a/trunk/arch/arm/plat-versatile/timer-sp.c b/trunk/arch/arm/plat-versatile/timer-sp.c index d1dbef5b17b1..fb0d1c299718 100644 --- a/trunk/arch/arm/plat-versatile/timer-sp.c +++ b/trunk/arch/arm/plat-versatile/timer-sp.c @@ -26,15 +26,13 @@ #include -#include - #include /* - * How long is the timer interval? + * These timers are currently always setup to be clocked at 1MHz. */ -#define TIMER_RELOAD (TICKS_PER_uSEC * mSEC_10) - +#define TIMER_FREQ_KHZ (1000) +#define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ) static void __iomem *clksrc_base; @@ -65,7 +63,7 @@ void __init sp804_clocksource_init(void __iomem *base) writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, clksrc_base + TIMER_CTRL); - cs->mult = clocksource_khz2mult(1000, cs->shift); + cs->mult = clocksource_khz2mult(TIMER_FREQ_KHZ, cs->shift); clocksource_register(cs); } @@ -149,7 +147,7 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq) clkevt_base = base; evt->irq = timer_irq; - evt->mult = div_sc(1000000, NSEC_PER_SEC, evt->shift); + evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift); evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt); evt->min_delta_ns = clockevent_delta2ns(0xf, evt);