From c1a6d1a61a44ae1608ded84205cc74a403fe524b Mon Sep 17 00:00:00 2001 From: Yong Shen Date: Tue, 4 Jan 2011 14:22:55 +0800 Subject: [PATCH] --- yaml --- r: 226167 b: refs/heads/master c: 644b1d586d6670262501057ae99d893fadb012de h: refs/heads/master i: 226165: 3f8354973d0888ad2b6c3aece1adde82f55fdd53 226163: a5eeb046c9647444b94f111f684b59ac76b78285 226159: 574023d8d7cda8afb8faacb4a393206a0d52dbbd v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-mx5/clock-mx51-mx53.c | 25 ++++++++++++++++++++++- trunk/arch/arm/mach-mx5/crm_regs.h | 4 ++++ 3 files changed, 29 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index e9f40c9dc307..40fc0b62aa12 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 96de6d447f40612acb93f81a561a834177cca685 +refs/heads/master: 644b1d586d6670262501057ae99d893fadb012de diff --git a/trunk/arch/arm/mach-mx5/clock-mx51-mx53.c b/trunk/arch/arm/mach-mx5/clock-mx51-mx53.c index ba9432c8f843..b21bc47d4827 100644 --- a/trunk/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/trunk/arch/arm/mach-mx5/clock-mx51-mx53.c @@ -127,7 +127,7 @@ static inline u32 _get_mux(struct clk *parent, struct clk *m0, return -EINVAL; } -static inline void __iomem *_get_pll_base(struct clk *pll) +static inline void __iomem *_mx51_get_pll_base(struct clk *pll) { if (pll == &pll1_main_clk) return MX51_DPLL1_BASE; @@ -135,6 +135,20 @@ static inline void __iomem *_get_pll_base(struct clk *pll) return MX51_DPLL2_BASE; else if (pll == &pll3_sw_clk) return MX51_DPLL3_BASE; + else + BUG(); + + return NULL; +} + +static inline void __iomem *_mx53_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) + return MX53_DPLL1_BASE; + else if (pll == &pll2_sw_clk) + return MX53_DPLL2_BASE; + else if (pll == &pll3_sw_clk) + return MX53_DPLL3_BASE; else if (pll == &mx53_pll4_sw_clk) return MX53_DPLL4_BASE; else @@ -143,6 +157,14 @@ static inline void __iomem *_get_pll_base(struct clk *pll) return NULL; } +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (cpu_is_mx51()) + return _mx51_get_pll_base(pll); + else + return _mx53_get_pll_base(pll); +} + static unsigned long clk_pll_get_rate(struct clk *clk) { long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; @@ -1341,6 +1363,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, clk_tree_init(); + clk_set_parent(&uart_root_clk, &pll3_sw_clk); clk_enable(&cpu_clk); clk_enable(&main_bus_clk); diff --git a/trunk/arch/arm/mach-mx5/crm_regs.h b/trunk/arch/arm/mach-mx5/crm_regs.h index 51ff9bb02379..b462c22f53d8 100644 --- a/trunk/arch/arm/mach-mx5/crm_regs.h +++ b/trunk/arch/arm/mach-mx5/crm_regs.h @@ -19,6 +19,10 @@ #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) /*MX53*/ +#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR) +#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) +#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) +#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) #define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) /* PLL Register Offsets */