From c2661258e34bb9e1a4026aac1b72b34865cc37f3 Mon Sep 17 00:00:00 2001
From: Hiroshi Doyu <hdoyu@nvidia.com>
Date: Fri, 11 Jan 2013 15:26:55 +0200
Subject: [PATCH] --- yaml --- r: 355579 b: refs/heads/master c:
 4dd2bd3736d1c40a9bcc12bd6d9a9fd30e99aa7a h: refs/heads/master i:   355577:
 3fcf44ec51db2686e64474f811ee4cdae0c27798   355575:
 7854534d664f6cd900ed3ca52a97571b825e67cf v: v3

---
 [refs]                               |  2 +-
 trunk/arch/arm/boot/dts/tegra20.dtsi | 17 +++++++++++++++++
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index bb3f5359236f..a4950b0a5fa5 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 5681f76576af872ced97e8c58ccab3c84a6627e6
+refs/heads/master: 4dd2bd3736d1c40a9bcc12bd6d9a9fd30e99aa7a
diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi
index b8effa1cbda7..3398df6b4d2f 100644
--- a/trunk/arch/arm/boot/dts/tegra20.dtsi
+++ b/trunk/arch/arm/boot/dts/tegra20.dtsi
@@ -410,6 +410,23 @@
 		status = "disabled";
 	};
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};
+
 	pmu {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <0 56 0x04