From c282992b6d5e800b68023dd80302b2979be80e92 Mon Sep 17 00:00:00 2001
From: Balaji T K <balajitk@ti.com>
Date: Mon, 9 Apr 2012 12:08:33 +0530
Subject: [PATCH] --- yaml --- r: 307937 b: refs/heads/master c:
 03b5d924b926dd994b16f30f7a13bfb71ee0f478 h: refs/heads/master i:   307935:
 e2949cd1d4fd07a70f3487154ee0d2b83438a9bf v: v3

---
 [refs]                              | 2 +-
 trunk/drivers/mmc/host/omap_hsmmc.c | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 53aa4cca84cc..786b16047857 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: dba3c29ea4a1d5d544f59b94fd8a41662135e071
+refs/heads/master: 03b5d924b926dd994b16f30f7a13bfb71ee0f478
diff --git a/trunk/drivers/mmc/host/omap_hsmmc.c b/trunk/drivers/mmc/host/omap_hsmmc.c
index dfa6f87b6cc2..dc41b9e4299e 100644
--- a/trunk/drivers/mmc/host/omap_hsmmc.c
+++ b/trunk/drivers/mmc/host/omap_hsmmc.c
@@ -92,6 +92,7 @@
 #define MSBS			(1 << 5)
 #define BCE			(1 << 1)
 #define FOUR_BIT		(1 << 1)
+#define DDR			(1 << 19)
 #define DW8			(1 << 5)
 #define CC			0x1
 #define TC			0x02
@@ -523,6 +524,10 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 	u32 con;
 
 	con = OMAP_HSMMC_READ(host->base, CON);
+	if (ios->timing == MMC_TIMING_UHS_DDR50)
+		con |= DDR;	/* configure in DDR mode */
+	else
+		con &= ~DDR;
 	switch (ios->bus_width) {
 	case MMC_BUS_WIDTH_8:
 		OMAP_HSMMC_WRITE(host->base, CON, con | DW8);