From c32f6e86f28cb0f066316bf135104109d1bb4d95 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Wed, 11 Apr 2012 20:42:42 +0200 Subject: [PATCH] --- yaml --- r: 307167 b: refs/heads/master c: 009be664ecc77d58d3c27fb22347b969745a329a h: refs/heads/master i: 307165: 077f5dba45629c2e702526f3df172c735cdfbc7b 307163: f76a2cb2d7a50f258839d396ef4c0693ad040cdd 307159: b27ddca051f2ff989f93b2ef44b7225562138716 307151: 55858c52a5a4528bd07274d40d3f063758ba085a 307135: 3bfc0f7d1cfc2ecfc952878cb996bb9f84f2283b v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 1 + trunk/drivers/gpu/drm/i915/intel_display.c | 4 ++++ 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 9da67ce1025a..d81c918c5ebf 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6 +refs/heads/master: 009be664ecc77d58d3c27fb22347b969745a329a diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index 6d9205436121..02124a51edad 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -639,6 +639,7 @@ #define CM0_MASK_SHIFT 16 #define CM0_IZ_OPT_DISABLE (1<<6) #define CM0_ZR_OPT_DISABLE (1<<5) +#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) #define CM0_DEPTH_EVICT_DISABLE (1<<4) #define CM0_COLOR_EVICT_DISABLE (1<<3) #define CM0_DEPTH_WRITE_DISABLE (1<<1) diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index 1a6bb6101491..7506a72ee882 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -8878,6 +8878,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); + /* clear masked bit */ + I915_WRITE(CACHE_MODE_0, + CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT); + I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | GEN6_BLBUNIT_CLOCK_GATE_DISABLE |