From c35205407cd9fbfcc06ad93c87202e2f6d810f31 Mon Sep 17 00:00:00 2001
From: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date: Thu, 29 Mar 2012 12:32:32 -0300
Subject: [PATCH] --- yaml --- r: 307039 b: refs/heads/master c:
 e93ea06aa0436f60a18962a195b95d8f36e9b7d6 h: refs/heads/master i:   307037:
 1c5b72f258e059b280f962ecc2f9705430d8e30a   307035:
 23578c94a92dcb4fe7d82a4948bf07de62e9ebcc   307031:
 65711ac9eba2ca4f259305a9a85ffe782d1d5f3d   307023:
 3e55175b1ac692bd6d917f01504dfe82f7521264   307007:
 19bf927d5e71999637e9141d70d29c0c546afcd9 v: v3

---
 [refs]                                | 2 +-
 trunk/drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index b4d0db9be2ac..fef330e029d0 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 52f025efa989318a6bc634103d70ca7a51a8b52d
+refs/heads/master: e93ea06aa0436f60a18962a195b95d8f36e9b7d6
diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h
index a9a47f6ef7d1..58046ffcf031 100644
--- a/trunk/drivers/gpu/drm/i915/i915_reg.h
+++ b/trunk/drivers/gpu/drm/i915/i915_reg.h
@@ -4134,4 +4134,12 @@
 #define  PIXCLK_GATE_UNGATE		1<<0
 #define  PIXCLK_GATE_GATE		0<<0
 
+/* SPLL */
+#define SPLL_CTL				0x46020
+#define  SPLL_PLL_ENABLE		(1<<31)
+#define  SPLL_PLL_SCC			(1<<28)
+#define  SPLL_PLL_NON_SCC		(2<<28)
+#define  SPLL_PLL_FREQ_810MHz	(0<<26)
+#define  SPLL_PLL_FREQ_1350MHz	(1<<26)
+
 #endif /* _I915_REG_H_ */