From c3d19e15dea50204599a9d4d9f2b7ba45750f5b1 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Fri, 20 Aug 2010 12:48:26 -0300 Subject: [PATCH] --- yaml --- r: 217386 b: refs/heads/master c: 6d37d240f2ff411c4d58bbbddefbda73a227d40c h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/edac/i7core_edac.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index f527f97504d9..572d1aff9862 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 21b6806a8cbda694eb1bed8d5b60bd7c322ad343 +refs/heads/master: 6d37d240f2ff411c4d58bbbddefbda73a227d40c diff --git a/trunk/drivers/edac/i7core_edac.c b/trunk/drivers/edac/i7core_edac.c index 4a12961c5ef6..915835339d7c 100644 --- a/trunk/drivers/edac/i7core_edac.c +++ b/trunk/drivers/edac/i7core_edac.c @@ -1968,6 +1968,10 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev) pvt = mci->pvt_info; memset(pvt, 0, sizeof(*pvt)); + /* Associates i7core_dev and mci for future usage */ + pvt->i7core_dev = i7core_dev; + i7core_dev->mci = mci; + /* * FIXME: how to handle RDDR3 at MCI level? It is possible to have * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different @@ -2033,10 +2037,6 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev) goto fail1; } - /* Associates i7core_dev and mci for future usage */ - pvt->i7core_dev = i7core_dev; - i7core_dev->mci = mci; - return 0; fail1: