From c4455cac6f052914a0e271ed4c083347d2292b7d Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Fri, 5 Jun 2009 15:38:41 +0800 Subject: [PATCH] --- yaml --- r: 148690 b: refs/heads/master c: 2cce0d8740f0d1454d012401257d96c513ce358f h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_gem_tiling.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index b15ce849b46f..571b13b38a66 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: e170b030dcd6aed11dde2d124c09991ec771f529 +refs/heads/master: 2cce0d8740f0d1454d012401257d96c513ce358f diff --git a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c index 540dd336e6ec..07d976bf4931 100644 --- a/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/trunk/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -170,6 +170,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) } } + /* FIXME: check with memory config on IGDNG */ + if (IS_IGDNG(dev)) { + DRM_ERROR("disable tiling on IGDNG...\n"); + swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; + swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; + } + dev_priv->mm.bit_6_swizzle_x = swizzle_x; dev_priv->mm.bit_6_swizzle_y = swizzle_y; }