From c4a795fdb101b5e07abe1826ac01c82e6cb84501 Mon Sep 17 00:00:00 2001 From: Matthew Wilcox Date: Fri, 25 Jul 2008 15:42:58 -0600 Subject: [PATCH] --- yaml --- r: 106951 b: refs/heads/master c: ce6fce4295ba727b36fdc73040e444bd1aae64cd h: refs/heads/master i: 106949: 26da13bfc975e581295f74270573fa7e8a033b72 106947: 406a9c94dfd9ecef782cb36e60f7c446a073b0b9 106943: 3f8448cee58a8343bda57c804dd3c25323a17cc5 v: v3 --- [refs] | 2 +- trunk/drivers/pci/msi.c | 15 ++++++++++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 7f9a7b04a37c..1cc3482df1b4 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 29111f579f4f3f2a07385f931854ab0527ae7ea5 +refs/heads/master: ce6fce4295ba727b36fdc73040e444bd1aae64cd diff --git a/trunk/drivers/pci/msi.c b/trunk/drivers/pci/msi.c index 15af618d36e2..18354817173c 100644 --- a/trunk/drivers/pci/msi.c +++ b/trunk/drivers/pci/msi.c @@ -126,7 +126,16 @@ static void msix_flush_writes(unsigned int irq) } } -static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag) +/* + * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to + * mask all MSI interrupts by clearing the MSI enable bit does not work + * reliably as devices without an INTx disable bit will then generate a + * level IRQ which will never be cleared. + * + * Returns 1 if it succeeded in masking the interrupt and 0 if the device + * doesn't support MSI masking. + */ +static int msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag) { struct msi_desc *entry; @@ -144,8 +153,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag) mask_bits |= flag & mask; pci_write_config_dword(entry->dev, pos, mask_bits); } else { - __msi_set_enable(entry->dev, entry->msi_attrib.pos, - !flag); + return 0; } break; case PCI_CAP_ID_MSIX: @@ -161,6 +169,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag) break; } entry->msi_attrib.masked = !!flag; + return 1; } void read_msi_msg(unsigned int irq, struct msi_msg *msg)