From c4d0536399d861f4c4389b1c6a8c568f9751a6a1 Mon Sep 17 00:00:00 2001 From: Jesse Barnes Date: Wed, 27 Jul 2011 11:51:40 -0700 Subject: [PATCH] --- yaml --- r: 262535 b: refs/heads/master c: 3bcf603f6d5d18bd9d076dc280de71f48add4101 h: refs/heads/master i: 262533: b2e37afac25a949a1ccdc086b45b74ba0408f045 262531: 1bd4a772bf65cb3d66257bc8d08d3a8d3027008b 262527: 16e13837db54cd59f81e22c0f03ee92c4f229de4 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 5 +++++ trunk/drivers/gpu/drm/i915/intel_display.c | 4 ++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index f0e33e821b0c..65804eee832b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 120eced9efe7fdb5123db4ea47e9adee9b66284e +refs/heads/master: 3bcf603f6d5d18bd9d076dc280de71f48add4101 diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index f7315653a842..00bd51070314 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -3072,6 +3072,11 @@ #define TRANS_6BPC (2<<5) #define TRANS_12BPC (3<<5) +#define _TRANSA_CHICKEN2 0xf0064 +#define _TRANSB_CHICKEN2 0xf1064 +#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2) +#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31) + #define SOUTH_CHICKEN2 0xc2004 #define DPLS_EDP_PPS_FIX_DIS (1<<0) diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index d9b8c15998d9..502efc37b074 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -7524,6 +7524,7 @@ static void ibx_init_clock_gating(struct drm_device *dev) static void cpt_init_clock_gating(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; + int pipe; /* * On Ibex Peak and Cougar Point, we need to disable clock @@ -7533,6 +7534,9 @@ static void cpt_init_clock_gating(struct drm_device *dev) I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | DPLS_EDP_PPS_FIX_DIS); + /* Without this, mode sets may fail silently on FDI */ + for_each_pipe(pipe) + I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); } static void ironlake_teardown_rc6(struct drm_device *dev)