From c557aa8b73c258dc62c033f436f213ca407e0f3b Mon Sep 17 00:00:00 2001
From: Murali Karicheri <m-karicheri2@ti.com>
Date: Wed, 3 Apr 2013 19:39:07 +0530
Subject: [PATCH] --- yaml --- r: 374127 b: refs/heads/master c:
 eed48556a789d2c7fd2dacbc0060e463ed72e449 h: refs/heads/master i:   374125:
 915aac97b37293dbca9894cdd3d1be13b506f049   374123:
 f48ea5943de813f1af2ef5112cf5fa440b11fe57   374119:
 944c769ff84d5a0c3dca2562cf1885da6df22d92   374111:
 86e28cfaa5f51f89271f33548a641e392c573b29 v: v3

---
 [refs]                                        |  2 +-
 .../devicetree/bindings/spi/spi-davinci.txt   | 51 +++++++++++++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)
 create mode 100644 trunk/Documentation/devicetree/bindings/spi/spi-davinci.txt

diff --git a/[refs] b/[refs]
index b2a75fb9b704..b9837096ee8c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 804413f2dd0bcef6d1aef7c8b3be749be9024eee
+refs/heads/master: eed48556a789d2c7fd2dacbc0060e463ed72e449
diff --git a/trunk/Documentation/devicetree/bindings/spi/spi-davinci.txt b/trunk/Documentation/devicetree/bindings/spi/spi-davinci.txt
new file mode 100644
index 000000000000..6d0ac8d0ad9b
--- /dev/null
+++ b/trunk/Documentation/devicetree/bindings/spi/spi-davinci.txt
@@ -0,0 +1,51 @@
+Davinci SPI controller device bindings
+
+Required properties:
+- #address-cells: number of cells required to define a chip select
+	address on the SPI bus. Should be set to 1.
+- #size-cells: should be zero.
+- compatible:
+	- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
+	- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
+- reg: Offset and length of SPI controller register space
+- num-cs: Number of chip selects
+- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
+	IP to the interrupt controller within the SoC. Possible values
+	are 0 and 1. Manual says one of the two possible interrupt
+	lines can be tied to the interrupt controller. Set this
+	based on a specifc SoC configuration.
+- interrupts: interrupt number mapped to CPU.
+- clocks: spi clk phandle
+
+Example of a NOR flash slave device (n25q032) connected to DaVinci
+SPI controller device over the SPI bus.
+
+spi0:spi@20BF0000 {
+	#address-cells			= <1>;
+	#size-cells			= <0>;
+	compatible			= "ti,dm6446-spi";
+	reg				= <0x20BF0000 0x1000>;
+	num-cs				= <4>;
+	ti,davinci-spi-intr-line	= <0>;
+	interrupts			= <338>;
+	clocks				= <&clkspi>;
+
+	flash: n25q032@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32";
+		spi-max-frequency = <25000000>;
+		reg = <0>;
+
+		partition@0 {
+			label = "u-boot-spl";
+			reg = <0x0 0x80000>;
+			read-only;
+		};
+
+		partition@1 {
+			label = "test";
+			reg = <0x80000 0x380000>;
+		};
+	};
+};