From c58655edc007032a9ab4b60f050bf1ecb1a7191f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 17 Jul 2007 18:49:48 +0100 Subject: [PATCH] --- yaml --- r: 62199 b: refs/heads/master c: 5a81299928f3d9abfaced60bedd85214cf9921a4 h: refs/heads/master i: 62197: 64a09559237c657364fb2972495e05a319e23565 62195: 61b59ac762120a5c3c786055abe48d35eb00f9da 62191: fab9718a2090723a15d36d87f73f3f136fbe829a v: v3 --- [refs] | 2 +- trunk/arch/mips/kernel/cpu-probe.c | 26 +++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 2e5c02f82213..34de8f34f8fc 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 17099b1142f6c0359fca60a3464dea8fb30badea +refs/heads/master: 5a81299928f3d9abfaced60bedd85214cf9921a4 diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c index c6b8b074a81a..06448a9656dc 100644 --- a/trunk/arch/mips/kernel/cpu-probe.c +++ b/trunk/arch/mips/kernel/cpu-probe.c @@ -75,6 +75,27 @@ static void r4k_wait_irqoff(void) local_irq_enable(); } +/* + * The RM7000 variant has to handle erratum 38. The workaround is to not + * have any pending stores when the WAIT instruction is executed. + */ +static void rm7k_wait_irqoff(void) +{ + local_irq_disable(); + if (!need_resched()) + __asm__( + " .set push \n" + " .set mips3 \n" + " .set noat \n" + " mfc0 $1, $12 \n" + " sync \n" + " mtc0 $1, $12 # stalls until W stage \n" + " wait \n" + " mtc0 $1, $12 # stalls until W stage \n" + " .set pop \n"); + local_irq_enable(); +} + /* The Au1xxx wait is available only if using 32khz counter or * external timer source, but specifically not CP0 Counter. */ int allow_au1k_wait; @@ -132,7 +153,6 @@ static inline void check_wait(void) case CPU_R4700: case CPU_R5000: case CPU_NEVADA: - case CPU_RM7000: case CPU_4KC: case CPU_4KEC: case CPU_4KSC: @@ -142,6 +162,10 @@ static inline void check_wait(void) cpu_wait = r4k_wait; break; + case CPU_RM7000: + cpu_wait = rm7k_wait_irqoff; + break; + case CPU_24K: case CPU_34K: cpu_wait = r4k_wait;