From c5974ca409757d3f69e6c5b1e44339f4b93d2169 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Thu, 24 Jan 2008 16:57:39 -0800 Subject: [PATCH] --- yaml --- r: 78079 b: refs/heads/master c: d10f2150eab62f633aeae36cf4612d1f648a817e h: refs/heads/master i: 78077: 8df174f9c4f7e0acdfe8a57076b024c45e6291d9 78075: 61ba8b195b036153d85106b352d74570db3660d4 78071: 304cabb5b55476a17234310c0a4863f361ccfcbf 78063: f8a2a2a8eb2bbcb37fa59109d5c09b7b9f091ab6 78047: c42d67d7de381806eaa8900bdcfe8c425ef69629 78015: 1ff3e58aa2435e31f81d822f7f7c5eeacf1cdb0a 77951: a1c44875a1905c09c82e285ba0293ff6d24cd234 77823: 6823498d406e27ca64bccfa471b34b2d50ea1fa5 v: v3 --- [refs] | 2 +- trunk/.gitignore | 1 - trunk/Documentation/filesystems/ext4.txt | 20 +- trunk/Documentation/filesystems/proc.txt | 39 - .../Documentation/kbuild/kconfig-language.txt | 111 +- trunk/Documentation/mips/00-INDEX | 2 + trunk/Documentation/mips/GT64120.README | 65 + trunk/Makefile | 28 +- trunk/arch/alpha/kernel/vmlinux.lds.S | 8 +- trunk/arch/alpha/lib/dec_and_lock.c | 3 +- trunk/arch/arm/kernel/vmlinux.lds.S | 10 +- trunk/arch/arm/mach-imx/Makefile | 3 + trunk/arch/arm/mach-netx/Makefile | 3 + trunk/arch/avr32/kernel/vmlinux.lds.S | 8 +- trunk/arch/blackfin/kernel/vmlinux.lds.S | 8 +- trunk/arch/cris/arch-v10/vmlinux.lds.S | 8 +- .../cris/arch-v32/boot/compressed/Makefile | 2 +- trunk/arch/cris/arch-v32/vmlinux.lds.S | 8 +- trunk/arch/frv/boot/Makefile | 8 +- trunk/arch/frv/kernel/gdb-stub.c | 2 +- trunk/arch/frv/kernel/vmlinux.lds.S | 14 +- trunk/arch/h8300/kernel/vmlinux.lds.S | 8 +- trunk/arch/ia64/kernel/vmlinux.lds.S | 8 +- trunk/arch/m32r/kernel/vmlinux.lds.S | 12 +- trunk/arch/m68k/kernel/vmlinux-std.lds | 8 +- trunk/arch/m68k/kernel/vmlinux-sun3.lds | 8 +- trunk/arch/m68knommu/kernel/vmlinux.lds.S | 8 +- trunk/arch/mips/Kconfig | 181 +- trunk/arch/mips/Makefile | 40 +- trunk/arch/mips/au1000/common/au1xxx_irqmap.c | 21 +- trunk/arch/mips/au1000/common/dbdma.c | 2 +- trunk/arch/mips/au1000/db1x00/init.c | 11 + trunk/arch/mips/au1000/mtx-1/init.c | 2 + trunk/arch/mips/au1000/mtx-1/platform.c | 27 +- trunk/arch/mips/au1000/pb1000/init.c | 2 + trunk/arch/mips/au1000/pb1100/init.c | 2 + trunk/arch/mips/au1000/pb1200/init.c | 2 + trunk/arch/mips/au1000/pb1500/init.c | 2 + trunk/arch/mips/au1000/pb1550/init.c | 2 + trunk/arch/mips/au1000/xxs1500/init.c | 2 + trunk/arch/mips/basler/excite/Kconfig | 9 - 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trunk/arch/mips/mips-boards/malta/malta_int.c | 129 +- .../arch/mips/mips-boards/malta/malta_setup.c | 210 +- .../arch/mips/mips-boards/malta/malta_smtc.c | 68 +- trunk/arch/mips/mips-boards/sead/sead_setup.c | 2 + trunk/arch/mips/mipssim/Makefile | 2 +- trunk/arch/mips/mipssim/sim_setup.c | 16 +- .../mips/mipssim/{sim_smtc.c => sim_smp.c} | 92 +- trunk/arch/mips/mm/c-r4k.c | 17 +- trunk/arch/mips/mm/dma-default.c | 2 +- trunk/arch/mips/mm/pg-r4k.c | 66 +- trunk/arch/mips/mm/tlbex.c | 252 +- trunk/arch/mips/oprofile/op_model_mipsxx.c | 2 +- trunk/arch/mips/pci/pci-bcm1480.c | 4 +- trunk/arch/mips/pci/pci-bcm1480ht.c | 4 +- .../arch/mips/philips/pnx8550/common/setup.c | 2 +- trunk/arch/mips/philips/pnx8550/common/time.c | 35 +- trunk/arch/mips/philips/pnx8550/jbs/init.c | 3 + .../mips/philips/pnx8550/stb810/prom_init.c | 2 + .../mips/pmc-sierra/yosemite/i2c-yosemite.h | 96 + trunk/arch/mips/pmc-sierra/yosemite/prom.c | 7 +- trunk/arch/mips/pmc-sierra/yosemite/smp.c | 149 +- trunk/arch/mips/qemu/Makefile | 10 + trunk/arch/mips/qemu/q-console.c | 26 + trunk/arch/mips/qemu/q-firmware.c | 24 + trunk/arch/mips/qemu/q-irq.c | 37 + trunk/arch/mips/qemu/q-mem.c | 5 + trunk/arch/mips/qemu/q-reset.c | 33 + trunk/arch/mips/qemu/q-setup.c | 22 + trunk/arch/mips/qemu/q-smp.c | 55 + trunk/arch/mips/sgi-ip22/Makefile | 8 +- trunk/arch/mips/sgi-ip22/ip22-mc.c | 4 - trunk/arch/mips/sgi-ip22/ip28-berr.c | 502 -- trunk/arch/mips/sgi-ip27/ip27-init.c | 1 + trunk/arch/mips/sgi-ip27/ip27-klnuma.c | 1 + trunk/arch/mips/sgi-ip27/ip27-smp.c | 109 +- trunk/arch/mips/sibyte/bcm1480/smp.c | 101 +- trunk/arch/mips/sibyte/cfe/Makefile | 1 + trunk/arch/mips/sibyte/cfe/setup.c | 14 +- trunk/arch/mips/sibyte/cfe/smp.c | 110 + trunk/arch/mips/sibyte/sb1250/smp.c | 100 +- trunk/arch/mips/sni/Makefile | 2 +- trunk/arch/mips/sni/a20r.c | 13 +- trunk/arch/mips/sni/eisa.c | 50 - trunk/arch/mips/sni/irq.c | 4 +- trunk/arch/mips/sni/pcit.c | 7 - trunk/arch/mips/sni/rm200.c | 326 +- trunk/arch/mips/sni/setup.c | 143 +- trunk/arch/mips/sni/sniprom.c | 251 + trunk/arch/mips/sni/time.c | 1 - trunk/arch/mips/tx4927/common/Makefile | 6 +- trunk/arch/mips/tx4927/common/tx4927_setup.c | 186 + .../toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 96 +- trunk/arch/mips/tx4938/common/Makefile | 6 +- trunk/arch/mips/tx4938/common/setup.c | 45 + .../mips/tx4938/toshiba_rbtx4938/Makefile | 4 + .../arch/mips/tx4938/toshiba_rbtx4938/prom.c | 1 + .../arch/mips/tx4938/toshiba_rbtx4938/setup.c | 31 +- trunk/arch/mips/vr41xx/common/init.c | 4 +- trunk/arch/mips/vr41xx/nec-cmbvr4133/setup.c | 4 +- trunk/arch/parisc/kernel/vmlinux.lds.S | 8 +- trunk/arch/powerpc/boot/Makefile | 2 +- trunk/arch/powerpc/kernel/sysfs.c | 2 +- trunk/arch/powerpc/kernel/vmlinux.lds.S | 10 +- trunk/arch/powerpc/oprofile/op_model_power4.c | 6 +- trunk/arch/ppc/kernel/vmlinux.lds.S | 8 +- trunk/arch/s390/kernel/vmlinux.lds.S | 8 +- trunk/arch/sh/kernel/vmlinux_32.lds.S | 8 +- trunk/arch/sh/kernel/vmlinux_64.lds.S | 8 +- trunk/arch/sparc/kernel/vmlinux.lds.S | 8 +- trunk/arch/sparc64/kernel/unaligned.c | 2 +- trunk/arch/sparc64/kernel/vmlinux.lds.S | 8 +- trunk/arch/um/include/init.h | 26 +- trunk/arch/um/kernel/dyn.lds.S | 4 +- trunk/arch/um/kernel/uml.lds.S | 4 +- trunk/arch/v850/kernel/vmlinux.lds.S | 10 +- trunk/arch/x86/kernel/vmlinux_32.lds.S | 14 +- trunk/arch/x86/kernel/vmlinux_64.lds.S | 19 +- trunk/arch/xtensa/kernel/vmlinux.lds.S | 9 +- trunk/arch/xtensa/mm/Makefile | 4 + trunk/arch/xtensa/platform-iss/Makefile | 5 + trunk/drivers/base/power/Makefile | 8 +- trunk/drivers/infiniband/hw/cxgb3/Makefile | 3 +- trunk/drivers/rapidio/rio.h | 4 +- trunk/fs/Kconfig | 1 - trunk/fs/afs/dir.c | 9 +- trunk/fs/afs/inode.c | 3 +- trunk/fs/buffer.c | 44 - trunk/fs/compat_ioctl.c | 2 +- trunk/fs/ext2/super.c | 32 +- trunk/fs/ext3/super.c | 32 +- trunk/fs/ext4/Makefile | 2 +- trunk/fs/ext4/balloc.c | 247 +- trunk/fs/ext4/dir.c | 14 +- trunk/fs/ext4/extents.c | 481 +- trunk/fs/ext4/file.c | 23 +- trunk/fs/ext4/group.h | 8 +- trunk/fs/ext4/ialloc.c | 141 +- trunk/fs/ext4/inode.c | 360 +- trunk/fs/ext4/ioctl.c | 7 +- trunk/fs/ext4/mballoc.c | 4552 ----------------- trunk/fs/ext4/migrate.c | 560 -- trunk/fs/ext4/namei.c | 135 +- trunk/fs/ext4/resize.c | 28 +- trunk/fs/ext4/super.c | 379 +- trunk/fs/ext4/xattr.c | 4 +- trunk/fs/inode.c | 5 - trunk/fs/jbd2/checkpoint.c | 22 +- trunk/fs/jbd2/commit.c | 255 +- trunk/fs/jbd2/journal.c | 368 +- trunk/fs/jbd2/recovery.c | 151 +- trunk/fs/jbd2/revoke.c | 6 +- trunk/fs/jbd2/transaction.c | 34 +- trunk/fs/ocfs2/cluster/sys.c | 2 +- trunk/fs/read_write.c | 1 - trunk/fs/smbfs/Makefile | 20 + trunk/include/asm-arm/bitops.h | 2 - trunk/include/asm-avr32/setup.h | 2 +- .../asm-generic/bitops/ext2-non-atomic.h | 2 - trunk/include/asm-generic/bitops/le.h | 4 - trunk/include/asm-generic/vmlinux.lds.h | 89 +- trunk/include/asm-ia64/gcc_intrin.h | 2 +- trunk/include/asm-m68k/bitops.h | 2 - trunk/include/asm-m68knommu/bitops.h | 2 - trunk/include/asm-mips/addrspace.h | 2 +- trunk/include/asm-mips/asm.h | 8 - trunk/include/asm-mips/bootinfo.h | 105 +- trunk/include/asm-mips/bugs.h | 25 - trunk/include/asm-mips/cpu-info.h | 5 +- trunk/include/asm-mips/cpu.h | 4 +- trunk/include/asm-mips/delay.h | 23 +- trunk/include/asm-mips/dma.h | 7 +- trunk/include/asm-mips/fixmap.h | 10 + trunk/include/asm-mips/fw/cfe/cfe_api.h | 87 +- trunk/include/asm-mips/fw/cfe/cfe_error.h | 19 +- trunk/include/asm-mips/mach-cobalt/cobalt.h | 15 +- .../mach-ip28/cpu-feature-overrides.h | 50 - trunk/include/asm-mips/mach-ip28/ds1286.h | 4 - trunk/include/asm-mips/mach-ip28/spaces.h | 22 - .../mach-qemu/cpu-feature-overrides.h | 32 + .../asm-mips/{mach-ip28 => mach-qemu}/war.h | 8 +- trunk/include/asm-mips/mips-boards/generic.h | 6 - trunk/include/asm-mips/mipsprom.h | 2 - .../asm-mips/pmc-sierra/msp71xx/msp_regs.h | 4 + trunk/include/asm-mips/r4kcache.h | 7 - trunk/include/asm-mips/sgi/ioc.h | 4 +- trunk/include/asm-mips/sibyte/board.h | 6 +- trunk/include/asm-mips/sibyte/sb1250.h | 2 + trunk/include/asm-mips/sibyte/swarm.h | 18 + trunk/include/asm-mips/smp-ops.h | 56 - trunk/include/asm-mips/smp.h | 64 +- trunk/include/asm-mips/sni.h | 159 +- trunk/include/asm-mips/stackframe.h | 9 - trunk/include/asm-mips/time.h | 9 +- trunk/include/asm-mips/topology.h | 16 - trunk/include/asm-mips/tx4927/tx4927_pci.h | 1 - trunk/include/asm-mips/uaccess.h | 13 +- trunk/include/asm-mips/war.h | 62 - trunk/include/asm-powerpc/bitops.h | 4 - trunk/include/asm-s390/bitops.h | 2 - trunk/include/asm-sh/machvec.h | 2 +- trunk/include/asm-sh/thread_info.h | 2 +- trunk/include/asm-x86/thread_info_32.h | 2 +- trunk/include/linux/Kbuild | 8 +- trunk/include/linux/buffer_head.h | 2 - trunk/include/linux/compiler-gcc3.h | 2 + trunk/include/linux/compiler-gcc4.h | 1 + trunk/include/linux/compiler.h | 9 +- trunk/include/linux/elfnote.h | 2 +- trunk/include/linux/ext4_fs.h | 198 +- trunk/include/linux/ext4_fs_extents.h | 25 +- trunk/include/linux/ext4_fs_i.h | 25 +- trunk/include/linux/ext4_fs_sb.h | 55 +- trunk/include/linux/fs.h | 19 +- trunk/include/linux/init.h | 130 +- trunk/include/linux/jbd2.h | 135 +- trunk/include/linux/module.h | 26 +- trunk/include/linux/moduleparam.h | 4 +- trunk/include/linux/pci.h | 2 +- trunk/init/Kconfig | 8 - trunk/kernel/extable.c | 3 +- trunk/kernel/kallsyms.c | 11 +- trunk/kernel/module.c | 102 +- trunk/kernel/params.c | 8 +- trunk/lib/Kconfig.debug | 32 - trunk/lib/find_next_bit.c | 43 - trunk/net/mac80211/rx.c | 13 + trunk/scripts/Makefile.build | 26 +- trunk/scripts/Makefile.lib | 6 - trunk/scripts/Makefile.modinst | 2 +- trunk/scripts/Makefile.modpost | 1 - trunk/scripts/basic/docproc.c | 44 +- trunk/scripts/decodecode | 17 +- trunk/scripts/gcc-version.sh | 5 +- trunk/scripts/genksyms/genksyms.c | 10 +- trunk/scripts/kconfig/Makefile | 39 +- trunk/scripts/kconfig/POTFILES.in | 7 - trunk/scripts/kconfig/conf.c | 69 +- trunk/scripts/kconfig/confdata.c | 24 +- trunk/scripts/kconfig/expr.c | 32 +- trunk/scripts/kconfig/expr.h | 16 +- trunk/scripts/kconfig/gconf.c | 16 +- trunk/scripts/kconfig/lex.zconf.c_shipped | 5 - trunk/scripts/kconfig/lkc.h | 5 - .../kconfig/lxdialog/check-lxdialog.sh | 16 +- trunk/scripts/kconfig/lxdialog/checklist.c | 4 +- trunk/scripts/kconfig/lxdialog/dialog.h | 11 +- trunk/scripts/kconfig/lxdialog/inputbox.c | 4 +- trunk/scripts/kconfig/lxdialog/menubox.c | 6 +- trunk/scripts/kconfig/lxdialog/textbox.c | 2 +- trunk/scripts/kconfig/lxdialog/util.c | 32 +- trunk/scripts/kconfig/lxdialog/yesno.c | 4 +- trunk/scripts/kconfig/mconf.c | 112 +- trunk/scripts/kconfig/menu.c | 49 +- trunk/scripts/kconfig/qconf.cc | 109 +- trunk/scripts/kconfig/symbol.c | 79 +- trunk/scripts/kconfig/util.c | 23 +- trunk/scripts/kconfig/zconf.gperf | 2 +- trunk/scripts/kconfig/zconf.hash.c_shipped | 19 +- trunk/scripts/kconfig/zconf.l | 5 - trunk/scripts/kernel-doc | 85 +- trunk/scripts/mkmakefile | 10 +- trunk/scripts/mod/modpost.c | 1210 ++--- trunk/scripts/mod/modpost.h | 2 - trunk/scripts/package/Makefile | 5 +- trunk/scripts/package/buildtar | 4 +- trunk/scripts/patch-kernel | 22 +- trunk/scripts/setlocalversion | 29 +- 359 files changed, 5065 insertions(+), 13336 deletions(-) create mode 100644 trunk/Documentation/mips/GT64120.README delete mode 100644 trunk/arch/mips/basler/excite/Kconfig delete mode 100644 trunk/arch/mips/fw/lib/Makefile delete mode 100644 trunk/arch/mips/fw/lib/call_o32.S delete mode 100644 trunk/arch/mips/fw/sni/Makefile delete mode 100644 trunk/arch/mips/fw/sni/sniprom.c create mode 100644 trunk/arch/mips/kernel/pcspeaker.c rename trunk/arch/mips/mipssim/{sim_smtc.c => sim_smp.c} (64%) create mode 100644 trunk/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h create mode 100644 trunk/arch/mips/qemu/Makefile create mode 100644 trunk/arch/mips/qemu/q-console.c create mode 100644 trunk/arch/mips/qemu/q-firmware.c create mode 100644 trunk/arch/mips/qemu/q-irq.c create mode 100644 trunk/arch/mips/qemu/q-mem.c create mode 100644 trunk/arch/mips/qemu/q-reset.c create mode 100644 trunk/arch/mips/qemu/q-setup.c create mode 100644 trunk/arch/mips/qemu/q-smp.c delete mode 100644 trunk/arch/mips/sgi-ip22/ip28-berr.c create mode 100644 trunk/arch/mips/sibyte/cfe/smp.c delete mode 100644 trunk/arch/mips/sni/eisa.c create mode 100644 trunk/arch/mips/sni/sniprom.c create mode 100644 trunk/arch/mips/tx4927/common/tx4927_setup.c create mode 100644 trunk/arch/mips/tx4938/common/setup.c delete mode 100644 trunk/fs/ext4/mballoc.c delete mode 100644 trunk/fs/ext4/migrate.c delete mode 100644 trunk/include/asm-mips/mach-ip28/cpu-feature-overrides.h delete mode 100644 trunk/include/asm-mips/mach-ip28/ds1286.h delete mode 100644 trunk/include/asm-mips/mach-ip28/spaces.h create mode 100644 trunk/include/asm-mips/mach-qemu/cpu-feature-overrides.h rename trunk/include/asm-mips/{mach-ip28 => mach-qemu}/war.h (82%) delete mode 100644 trunk/include/asm-mips/smp-ops.h diff --git a/[refs] b/[refs] index 8ffc4053e319..0d53b58b23b8 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 21af0297c7e56024a5ccc4d8ad2a590f9ec371ba +refs/heads/master: d10f2150eab62f633aeae36cf4612d1f648a817e diff --git a/trunk/.gitignore b/trunk/.gitignore index 8363e48cdcdc..8d14531846b9 100644 --- a/trunk/.gitignore +++ b/trunk/.gitignore @@ -17,7 +17,6 @@ *.i *.lst *.symtypes -*.order # # Top-level generic files diff --git a/trunk/Documentation/filesystems/ext4.txt b/trunk/Documentation/filesystems/ext4.txt index 560f88dc7090..6a4adcae9f9a 100644 --- a/trunk/Documentation/filesystems/ext4.txt +++ b/trunk/Documentation/filesystems/ext4.txt @@ -86,21 +86,9 @@ Alex is working on a new set of patches right now. When mounting an ext4 filesystem, the following option are accepted: (*) == default -extents (*) ext4 will use extents to address file data. The +extents ext4 will use extents to address file data. The file system will no longer be mountable by ext3. -noextents ext4 will not use extents for newly created files - -journal_checksum Enable checksumming of the journal transactions. - This will allow the recovery code in e2fsck and the - kernel to detect corruption in the kernel. It is a - compatible change and will be ignored by older kernels. - -journal_async_commit Commit block can be written to disk without waiting - for descriptor blocks. If enabled older kernels cannot - mount the device. This will enable 'journal_checksum' - internally. - journal=update Update the ext4 file system's journal to the current format. @@ -208,12 +196,6 @@ nobh (a) cache disk block mapping information "nobh" option tries to avoid associating buffer heads (supported only for "writeback" mode). -mballoc (*) Use the multiple block allocator for block allocation -nomballoc disabled multiple block allocator for block allocation. -stripe=n Number of filesystem blocks that mballoc will try - to use for allocation size and alignment. For RAID5/6 - systems this should be the number of data - disks * RAID chunk size in file system blocks. Data Mode --------- diff --git a/trunk/Documentation/filesystems/proc.txt b/trunk/Documentation/filesystems/proc.txt index 4413a2d4646f..dec99455321f 100644 --- a/trunk/Documentation/filesystems/proc.txt +++ b/trunk/Documentation/filesystems/proc.txt @@ -857,45 +857,6 @@ CPUs. The "procs_blocked" line gives the number of processes currently blocked, waiting for I/O to complete. -1.9 Ext4 file system parameters ------------------------------- -Ext4 file system have one directory per partition under /proc/fs/ext4/ -# ls /proc/fs/ext4/hdc/ -group_prealloc max_to_scan mb_groups mb_history min_to_scan order2_req -stats stream_req - -mb_groups: -This file gives the details of mutiblock allocator buddy cache of free blocks - -mb_history: -Multiblock allocation history. - -stats: -This file indicate whether the multiblock allocator should start collecting -statistics. The statistics are shown during unmount - -group_prealloc: -The multiblock allocator normalize the block allocation request to -group_prealloc filesystem blocks if we don't have strip value set. -The stripe value can be specified at mount time or during mke2fs. - -max_to_scan: -How long multiblock allocator can look for a best extent (in found extents) - -min_to_scan: -How long multiblock allocator must look for a best extent - -order2_req: -Multiblock allocator use 2^N search using buddies only for requests greater -than or equal to order2_req. The request size is specfied in file system -blocks. A value of 2 indicate only if the requests are greater than or equal -to 4 blocks. - -stream_req: -Files smaller than stream_req are served by the stream allocator, whose -purpose is to pack requests as close each to other as possible to -produce smooth I/O traffic. Avalue of 16 indicate that file smaller than 16 -filesystem block size will use group based preallocation. ------------------------------------------------------------------------------ Summary diff --git a/trunk/Documentation/kbuild/kconfig-language.txt b/trunk/Documentation/kbuild/kconfig-language.txt index 649cb8799890..616043a6da99 100644 --- a/trunk/Documentation/kbuild/kconfig-language.txt +++ b/trunk/Documentation/kbuild/kconfig-language.txt @@ -24,7 +24,7 @@ visible if its parent entry is also visible. Menu entries ------------ -Most entries define a config option; all other entries help to organize +Most entries define a config option, all other entries help to organize them. A single configuration option is defined like this: config MODVERSIONS @@ -50,7 +50,7 @@ applicable everywhere (see syntax). - type definition: "bool"/"tristate"/"string"/"hex"/"int" Every config option must have a type. There are only two basic types: - tristate and string; the other types are based on these two. The type + tristate and string, the other types are based on these two. The type definition optionally accepts an input prompt, so these two examples are equivalent: @@ -108,7 +108,7 @@ applicable everywhere (see syntax). equal to 'y' without visiting the dependencies. So abusing select you are able to select a symbol FOO even if FOO depends on BAR that is not set. In general use select only for - non-visible symbols (no prompts anywhere) and for symbols with + non-visible symbols (no promts anywhere) and for symbols with no dependencies. That will limit the usefulness but on the other hand avoid the illegal configurations all over. kconfig should one day warn about such things. @@ -127,27 +127,6 @@ applicable everywhere (see syntax). used to help visually separate configuration logic from help within the file as an aid to developers. -- misc options: "option" [=] - Various less common options can be defined via this option syntax, - which can modify the behaviour of the menu entry and its config - symbol. These options are currently possible: - - - "defconfig_list" - This declares a list of default entries which can be used when - looking for the default configuration (which is used when the main - .config doesn't exists yet.) - - - "modules" - This declares the symbol to be used as the MODULES symbol, which - enables the third modular state for all config symbols. - - - "env"= - This imports the environment variable into Kconfig. It behaves like - a default, except that the value comes from the environment, this - also means that the behaviour when mixing it with normal defaults is - undefined at this point. The symbol is currently not exported back - to the build environment (if this is desired, it can be done via - another symbol). Menu dependencies ----------------- @@ -183,9 +162,9 @@ An expression can have a value of 'n', 'm' or 'y' (or 0, 1, 2 respectively for calculations). A menu entry becomes visible when it's expression evaluates to 'm' or 'y'. -There are two types of symbols: constant and non-constant symbols. -Non-constant symbols are the most common ones and are defined with the -'config' statement. Non-constant symbols consist entirely of alphanumeric +There are two types of symbols: constant and nonconstant symbols. +Nonconstant symbols are the most common ones and are defined with the +'config' statement. Nonconstant symbols consist entirely of alphanumeric characters or underscores. Constant symbols are only part of expressions. Constant symbols are always surrounded by single or double quotes. Within the quote, any @@ -322,81 +301,3 @@ mainmenu: This sets the config program's title bar if the config program chooses to use it. - - -Kconfig hints -------------- -This is a collection of Kconfig tips, most of which aren't obvious at -first glance and most of which have become idioms in several Kconfig -files. - -Adding common features and make the usage configurable -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -It is a common idiom to implement a feature/functionality that are -relevant for some architectures but not all. -The recommended way to do so is to use a config variable named HAVE_* -that is defined in a common Kconfig file and selected by the relevant -architectures. -An example is the generic IOMAP functionality. - -We would in lib/Kconfig see: - -# Generic IOMAP is used to ... -config HAVE_GENERIC_IOMAP - -config GENERIC_IOMAP - depends on HAVE_GENERIC_IOMAP && FOO - -And in lib/Makefile we would see: -obj-$(CONFIG_GENERIC_IOMAP) += iomap.o - -For each architecture using the generic IOMAP functionality we would see: - -config X86 - select ... - select HAVE_GENERIC_IOMAP - select ... - -Note: we use the existing config option and avoid creating a new -config variable to select HAVE_GENERIC_IOMAP. - -Note: the use of the internal config variable HAVE_GENERIC_IOMAP, it is -introduced to overcome the limitation of select which will force a -config option to 'y' no matter the dependencies. -The dependencies are moved to the symbol GENERIC_IOMAP and we avoid the -situation where select forces a symbol equals to 'y'. - -Build as module only -~~~~~~~~~~~~~~~~~~~~ -To restrict a component build to module-only, qualify its config symbol -with "depends on m". E.g.: - -config FOO - depends on BAR && m - -limits FOO to module (=m) or disabled (=n). - - -Build limited by a third config symbol which may be =y or =m -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -A common idiom that we see (and sometimes have problems with) is this: - -When option C in B (module or subsystem) uses interfaces from A (module -or subsystem), and both A and B are tristate (could be =y or =m if they -were independent of each other, but they aren't), then we need to limit -C such that it cannot be built statically if A is built as a loadable -module. (C already depends on B, so there is no dependency issue to -take care of here.) - -If A is linked statically into the kernel image, C can be built -statically or as loadable module(s). However, if A is built as loadable -module(s), then C must be restricted to loadable module(s) also. This -can be expressed in kconfig language as: - -config C - depends on A = y || A = B - -or for real examples, use this command in a kernel tree: - -$ find . -name Kconfig\* | xargs grep -ns "depends on.*=.*||.*=" | grep -v orig - diff --git a/trunk/Documentation/mips/00-INDEX b/trunk/Documentation/mips/00-INDEX index 8ae9cffc2262..3f13bf8043d2 100644 --- a/trunk/Documentation/mips/00-INDEX +++ b/trunk/Documentation/mips/00-INDEX @@ -2,3 +2,5 @@ - this file. AU1xxx_IDE.README - README for MIPS AU1XXX IDE driver. +GT64120.README + - README for dir with info on MIPS boards using GT-64120 or GT-64120A. diff --git a/trunk/Documentation/mips/GT64120.README b/trunk/Documentation/mips/GT64120.README new file mode 100644 index 000000000000..2d0eec91dc59 --- /dev/null +++ b/trunk/Documentation/mips/GT64120.README @@ -0,0 +1,65 @@ +README for arch/mips/gt64120 directory and subdirectories + +Jun Sun, jsun@mvista.com or jsun@junsun.net +01/27, 2001 + +MOTIVATION +---------- + +Many MIPS boards share the same system controller (or CPU companian chip), +such as GT-64120. It is highly desirable to let these boards share +the same controller code instead of duplicating them. + +This directory is meant to hold all MIPS boards that use GT-64120 or GT-64120A. + + +HOW TO ADD A BOARD +------------------ + +. Create a subdirectory include/asm/gt64120/. + +. Create a file called gt64120_dep.h under that directory. + +. Modify include/asm/gt64120/gt64120.h file to include the new gt64120_dep.h + based on config options. The board-dep section is at the end of + include/asm/gt64120/gt64120.h file. There you can find all required + definitions include/asm/gt64120//gt64120_dep.h file must supply. + +. Create a subdirectory arch/mips/gt64120/ directory to hold + board specific routines. + +. The GT-64120 common code is supplied under arch/mips/gt64120/common directory. + It includes: + 1) arch/mips/gt64120/pci.c - + common PCI routine, include the top-level pcibios_init() + 2) arch/mips/gt64120/irq.c - + common IRQ routine, include the top-level do_IRQ() + [This part really belongs to arch/mips/kernel. jsun] + 3) arch/mips/gt64120/gt_irq.c - + common IRQ routines for GT-64120 chip. Currently it only handles + the timer interrupt. + +. Board-specific routines are supplied under arch/mips/gt64120/ dir. + 1) arch/mips/gt64120//pci.c - it provides bus fixup routine + 2) arch/mips/gt64120//irq.c - it provides enable/disable irqs + and board irq setup routine (irq_setup) + 3) arch/mips/gt64120//int-handler.S - + The first-level interrupt dispatching routine. + 4) a bunch of other "normal" stuff (setup, prom, dbg_io, reset, etc) + +. Follow other "normal" procedure to modify configuration files, etc. + + +TO-DO LIST +---------- + +. Expand arch/mips/gt64120/gt_irq.c to handle all GT-64120 interrupts. + We probably need to introduce GT_IRQ_BASE in board-dep header file, + which is used the starting irq_nr for all GT irqs. + + A function, gt64120_handle_irq(), will be added so that the first-level + irq dispatcher will call this function if it detects an interrupt + from GT-64120. + +. More support for GT-64120 PCI features (2nd PCI bus, perhaps) + diff --git a/trunk/Makefile b/trunk/Makefile index 0f84c742ed0e..6d419f67939c 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -520,11 +520,6 @@ KBUILD_CFLAGS += -g KBUILD_AFLAGS += -gdwarf-2 endif -# We trigger additional mismatches with less inlining -ifdef CONFIG_DEBUG_SECTION_MISMATCH -KBUILD_CFLAGS += $(call cc-option, -fno-inline-functions-called-once) -endif - # Force gcc to behave correct even for buggy distributions KBUILD_CFLAGS += $(call cc-option, -fno-stack-protector) @@ -798,7 +793,7 @@ define rule_vmlinux-modpost endef # vmlinux image - including updated kernel symbols -vmlinux: $(vmlinux-lds) $(vmlinux-init) $(vmlinux-main) vmlinux.o $(kallsyms.o) FORCE +vmlinux: $(vmlinux-lds) $(vmlinux-init) $(vmlinux-main) $(kallsyms.o) vmlinux.o FORCE ifdef CONFIG_HEADERS_CHECK $(Q)$(MAKE) -f $(srctree)/Makefile headers_check endif @@ -809,9 +804,7 @@ endif $(call if_changed_rule,vmlinux__) $(Q)rm -f .old_version -# build vmlinux.o first to catch section mismatch errors early -$(kallsyms.o): vmlinux.o -vmlinux.o: $(vmlinux-lds) $(vmlinux-init) $(vmlinux-main) FORCE +vmlinux.o: $(vmlinux-lds) $(vmlinux-init) $(vmlinux-main) $(kallsyms.o) FORCE $(call if_changed_rule,vmlinux-modpost) # The actual objects are generated when descending, @@ -1028,14 +1021,9 @@ ifdef CONFIG_MODULES all: modules # Build modules -# -# A module can be listed more than once in obj-m resulting in -# duplicate lines in modules.order files. Those are removed -# using awk while concatenating to the final file. PHONY += modules modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) - $(Q)$(AWK) '!x[$$0]++' $(vmlinux-dirs:%=$(objtree)/%/modules.order) > $(objtree)/modules.order @echo ' Building modules, stage 2.'; $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost @@ -1063,7 +1051,6 @@ _modinst_: rm -f $(MODLIB)/build ; \ ln -s $(objtree) $(MODLIB)/build ; \ fi - @cp -f $(objtree)/modules.order $(MODLIB)/ $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modinst # This depmod is only for convenience to give the initial @@ -1123,7 +1110,7 @@ clean: archclean $(clean-dirs) @find . $(RCS_FIND_IGNORE) \ \( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \ -o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \ - -o -name '*.symtypes' -o -name 'modules.order' \) \ + -o -name '*.symtypes' \) \ -type f -print | xargs rm -f # mrproper - Delete all generated files, including .config @@ -1188,7 +1175,7 @@ help: @echo ' dir/ - Build all files in dir and below' @echo ' dir/file.[ois] - Build specified target only' @echo ' dir/file.ko - Build module including final link' - @echo ' prepare - Set up for building external modules' + @echo ' rpm - Build a kernel as an RPM package' @echo ' tags/TAGS - Generate tags file for editors' @echo ' cscope - Generate cscope index' @echo ' kernelrelease - Output the release version string' @@ -1201,8 +1188,6 @@ help: @echo 'Static analysers' @echo ' checkstack - Generate a list of stack hogs' @echo ' namespacecheck - Name space analysis on compiled kernel' - @echo ' versioncheck - Sanity check on version.h usage' - @echo ' includecheck - Check for duplicate included header files' @echo ' export_report - List the usages of all exported symbols' @if [ -r $(srctree)/include/asm-$(SRCARCH)/Kbuild ]; then \ echo ' headers_check - Sanity check on exported headers'; \ @@ -1386,7 +1371,6 @@ define xtags if $1 --version 2>&1 | grep -iq exuberant; then \ $(all-sources) | xargs $1 -a \ -I __initdata,__exitdata,__acquires,__releases \ - -I __read_mostly,____cacheline_aligned,____cacheline_aligned_in_smp,____cacheline_internodealigned_in_smp \ -I EXPORT_SYMBOL,EXPORT_SYMBOL_GPL \ --extra=+f --c-kinds=+px \ --regex-asm='/^ENTRY\(([^)]*)\).*/\1/'; \ @@ -1444,12 +1428,12 @@ tags: FORCE includecheck: find * $(RCS_FIND_IGNORE) \ -name '*.[hcS]' -type f -print | sort \ - | xargs $(PERL) -w $(srctree)/scripts/checkincludes.pl + | xargs $(PERL) -w scripts/checkincludes.pl versioncheck: find * $(RCS_FIND_IGNORE) \ -name '*.[hcS]' -type f -print | sort \ - | xargs $(PERL) -w $(srctree)/scripts/checkversion.pl + | xargs $(PERL) -w scripts/checkversion.pl namespacecheck: $(PERL) $(srctree)/scripts/namespace.pl diff --git a/trunk/arch/alpha/kernel/vmlinux.lds.S b/trunk/arch/alpha/kernel/vmlinux.lds.S index f13249be17c5..55c05b511f4c 100644 --- a/trunk/arch/alpha/kernel/vmlinux.lds.S +++ b/trunk/arch/alpha/kernel/vmlinux.lds.S @@ -46,11 +46,11 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; } .init.data : { - INIT_DATA + *(.init.data) } . = ALIGN(16); @@ -136,8 +136,8 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) *(.exitcall.exit) } diff --git a/trunk/arch/alpha/lib/dec_and_lock.c b/trunk/arch/alpha/lib/dec_and_lock.c index 0f5520d2f45f..6ae2500a9d9e 100644 --- a/trunk/arch/alpha/lib/dec_and_lock.c +++ b/trunk/arch/alpha/lib/dec_and_lock.c @@ -30,7 +30,8 @@ _atomic_dec_and_lock: \n\ .previous \n\ .end _atomic_dec_and_lock"); -static int __used atomic_dec_and_lock_1(atomic_t *atomic, spinlock_t *lock) +static int __attribute_used__ +atomic_dec_and_lock_1(atomic_t *atomic, spinlock_t *lock) { /* Slow path */ spin_lock(lock); diff --git a/trunk/arch/arm/kernel/vmlinux.lds.S b/trunk/arch/arm/kernel/vmlinux.lds.S index 4898bdcfe7dd..30f732c7fdb5 100644 --- a/trunk/arch/arm/kernel/vmlinux.lds.S +++ b/trunk/arch/arm/kernel/vmlinux.lds.S @@ -30,7 +30,7 @@ SECTIONS } .init : { /* Init code and data */ - INIT_TEXT + *(.init.text) _einittext = .; __proc_info_begin = .; *(.proc.info.init) @@ -70,15 +70,15 @@ SECTIONS __per_cpu_end = .; #ifndef CONFIG_XIP_KERNEL __init_begin = _stext; - INIT_DATA + *(.init.data) . = ALIGN(4096); __init_end = .; #endif } /DISCARD/ : { /* Exit code and data */ - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) *(.exitcall.exit) #ifndef CONFIG_MMU *(.fixup) @@ -130,7 +130,7 @@ SECTIONS #ifdef CONFIG_XIP_KERNEL . = ALIGN(4096); __init_begin = .; - INIT_DATA + *(.init.data) . = ALIGN(4096); __init_end = .; #endif diff --git a/trunk/arch/arm/mach-imx/Makefile b/trunk/arch/arm/mach-imx/Makefile index 88d5e61a2e13..02272aa36e90 100644 --- a/trunk/arch/arm/mach-imx/Makefile +++ b/trunk/arch/arm/mach-imx/Makefile @@ -1,6 +1,9 @@ # # Makefile for the linux kernel. # +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). # Object file lists. diff --git a/trunk/arch/arm/mach-netx/Makefile b/trunk/arch/arm/mach-netx/Makefile index 7ce4ba9eb242..18785ff37657 100644 --- a/trunk/arch/arm/mach-netx/Makefile +++ b/trunk/arch/arm/mach-netx/Makefile @@ -1,6 +1,9 @@ # # Makefile for the linux kernel. # +# Note! Dependencies are done automagically by 'make dep', which also +# removes any old dependencies. DON'T put your own dependencies here +# unless it's something special (ie not a .c file). # Object file lists. diff --git a/trunk/arch/avr32/kernel/vmlinux.lds.S b/trunk/arch/avr32/kernel/vmlinux.lds.S index 481cfd40c053..11f08e35a2eb 100644 --- a/trunk/arch/avr32/kernel/vmlinux.lds.S +++ b/trunk/arch/avr32/kernel/vmlinux.lds.S @@ -27,19 +27,19 @@ SECTIONS __init_begin = .; _sinittext = .; *(.text.reset) - INIT_TEXT + *(.init.text) /* * .exit.text is discarded at runtime, not * link time, to deal with references from * __bug_table */ - EXIT_TEXT + *(.exit.text) _einittext = .; . = ALIGN(4); __tagtable_begin = .; *(.taglist.init) __tagtable_end = .; - INIT_DATA + *(.init.data) . = ALIGN(16); __setup_start = .; *(.init.setup) @@ -135,7 +135,7 @@ SECTIONS * thrown away, as cleanup code is never called unless it's a module. */ /DISCARD/ : { - EXIT_DATA + *(.exit.data) *(.exitcall.exit) } diff --git a/trunk/arch/blackfin/kernel/vmlinux.lds.S b/trunk/arch/blackfin/kernel/vmlinux.lds.S index 858722421b40..9b75bc83c71f 100644 --- a/trunk/arch/blackfin/kernel/vmlinux.lds.S +++ b/trunk/arch/blackfin/kernel/vmlinux.lds.S @@ -91,13 +91,13 @@ SECTIONS { . = ALIGN(PAGE_SIZE); __sinittext = .; - INIT_TEXT + *(.init.text) __einittext = .; } .init.data : { . = ALIGN(16); - INIT_DATA + *(.init.data) } .init.setup : { @@ -198,8 +198,8 @@ SECTIONS /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) *(.exitcall.exit) } } diff --git a/trunk/arch/cris/arch-v10/vmlinux.lds.S b/trunk/arch/cris/arch-v10/vmlinux.lds.S index 93c9f0ea286b..97a7876ed681 100644 --- a/trunk/arch/cris/arch-v10/vmlinux.lds.S +++ b/trunk/arch/cris/arch-v10/vmlinux.lds.S @@ -57,10 +57,10 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; } - .init.data : { INIT_DATA } + .init.data : { *(.init.data) } . = ALIGN(16); __setup_start = .; .init.setup : { *(.init.setup) } @@ -109,8 +109,8 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.text.exit) + *(.data.exit) *(.exitcall.exit) } diff --git a/trunk/arch/cris/arch-v32/boot/compressed/Makefile b/trunk/arch/cris/arch-v32/boot/compressed/Makefile index 609692f9d5eb..9f77eda914ba 100644 --- a/trunk/arch/cris/arch-v32/boot/compressed/Makefile +++ b/trunk/arch/cris/arch-v32/boot/compressed/Makefile @@ -7,7 +7,7 @@ target = $(target_compressed_dir) src = $(src_compressed_dir) -CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE) +CC = gcc-cris -mlinux -march=v32 -I $(TOPDIR)/include CFLAGS = -O2 LD = gcc-cris -mlinux -march=v32 -nostdlib OBJCOPY = objcopy-cris diff --git a/trunk/arch/cris/arch-v32/vmlinux.lds.S b/trunk/arch/cris/arch-v32/vmlinux.lds.S index fead8c59ea63..b076c134c0bb 100644 --- a/trunk/arch/cris/arch-v32/vmlinux.lds.S +++ b/trunk/arch/cris/arch-v32/vmlinux.lds.S @@ -61,10 +61,10 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; } - .init.data : { INIT_DATA } + .init.data : { *(.init.data) } . = ALIGN(16); __setup_start = .; .init.setup : { *(.init.setup) } @@ -124,8 +124,8 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.text.exit) + *(.data.exit) *(.exitcall.exit) } diff --git a/trunk/arch/frv/boot/Makefile b/trunk/arch/frv/boot/Makefile index 6ae3254da019..dc6f03824423 100644 --- a/trunk/arch/frv/boot/Makefile +++ b/trunk/arch/frv/boot/Makefile @@ -10,7 +10,7 @@ targets := Image zImage bootpImage -SYSTEM =$(LINUX) +SYSTEM =$(TOPDIR)/$(LINUX) ZTEXTADDR = 0x02080000 PARAMS_PHYS = 0x0207c000 @@ -45,7 +45,7 @@ zImage: $(CONFIGURE) compressed/$(LINUX) bootpImage: bootp/bootp $(OBJCOPY) -O binary -R .note -R .comment -S bootp/bootp $@ -compressed/$(LINUX): $(LINUX) dep +compressed/$(LINUX): $(TOPDIR)/$(LINUX) dep @$(MAKE) -C compressed $(LINUX) bootp/bootp: zImage initrd @@ -59,10 +59,10 @@ initrd: # installation # install: $(CONFIGURE) Image - sh ./install.sh $(KERNELRELEASE) Image System.map "$(INSTALL_PATH)" + sh ./install.sh $(KERNELRELEASE) Image $(TOPDIR)/System.map "$(INSTALL_PATH)" zinstall: $(CONFIGURE) zImage - sh ./install.sh $(KERNELRELEASE) zImage System.map "$(INSTALL_PATH)" + sh ./install.sh $(KERNELRELEASE) zImage $(TOPDIR)/System.map "$(INSTALL_PATH)" # # miscellany diff --git a/trunk/arch/frv/kernel/gdb-stub.c b/trunk/arch/frv/kernel/gdb-stub.c index 48a0393e7cee..e89cad1192a9 100644 --- a/trunk/arch/frv/kernel/gdb-stub.c +++ b/trunk/arch/frv/kernel/gdb-stub.c @@ -87,7 +87,7 @@ * Example: * $ cd ~/linux * $ make menuconfig - * $ make vmlinux + * $ make dep; make vmlinux * * Step 3: * Download the kernel to the remote target and start diff --git a/trunk/arch/frv/kernel/vmlinux.lds.S b/trunk/arch/frv/kernel/vmlinux.lds.S index f42b328b1dd0..a17a81d58bf6 100644 --- a/trunk/arch/frv/kernel/vmlinux.lds.S +++ b/trunk/arch/frv/kernel/vmlinux.lds.S @@ -28,14 +28,14 @@ SECTIONS .init.text : { *(.text.head) #ifndef CONFIG_DEBUG_INFO - INIT_TEXT - EXIT_TEXT - EXIT_DATA + *(.init.text) + *(.exit.text) + *(.exit.data) *(.exitcall.exit) #endif } _einittext = .; - .init.data : { INIT_DATA } + .init.data : { *(.init.data) } . = ALIGN(8); __setup_start = .; @@ -106,8 +106,8 @@ SECTIONS LOCK_TEXT #ifdef CONFIG_DEBUG_INFO *( - INIT_TEXT - EXIT_TEXT + .init.text + .exit.text .exitcall.exit ) #endif @@ -138,7 +138,7 @@ SECTIONS .data : { /* Data */ DATA_DATA *(.data.*) - EXIT_DATA + *(.exit.data) CONSTRUCTORS } diff --git a/trunk/arch/h8300/kernel/vmlinux.lds.S b/trunk/arch/h8300/kernel/vmlinux.lds.S index 43a87b9085b6..a2e72d495551 100644 --- a/trunk/arch/h8300/kernel/vmlinux.lds.S +++ b/trunk/arch/h8300/kernel/vmlinux.lds.S @@ -110,9 +110,9 @@ SECTIONS . = ALIGN(0x4) ; ___init_begin = .; __sinittext = .; - INIT_TEXT + *(.init.text) __einittext = .; - INIT_DATA + *(.init.data) . = ALIGN(0x4) ; ___setup_start = .; *(.init.setup) @@ -124,8 +124,8 @@ SECTIONS ___con_initcall_start = .; *(.con_initcall.init) ___con_initcall_end = .; - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) #if defined(CONFIG_BLK_DEV_INITRD) . = ALIGN(4); ___initramfs_start = .; diff --git a/trunk/arch/ia64/kernel/vmlinux.lds.S b/trunk/arch/ia64/kernel/vmlinux.lds.S index 80622acc95de..757e419ebcf8 100644 --- a/trunk/arch/ia64/kernel/vmlinux.lds.S +++ b/trunk/arch/ia64/kernel/vmlinux.lds.S @@ -27,8 +27,8 @@ SECTIONS { /* Sections to be discarded */ /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) *(.exitcall.exit) *(.IA_64.unwind.exit.text) *(.IA_64.unwind_info.exit.text) @@ -119,12 +119,12 @@ SECTIONS .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) { _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; } .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) - { INIT_DATA } + { *(.init.data) } #ifdef CONFIG_BLK_DEV_INITRD .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) diff --git a/trunk/arch/m32r/kernel/vmlinux.lds.S b/trunk/arch/m32r/kernel/vmlinux.lds.S index 41b07854fcc6..942a8c7a4417 100644 --- a/trunk/arch/m32r/kernel/vmlinux.lds.S +++ b/trunk/arch/m32r/kernel/vmlinux.lds.S @@ -76,10 +76,10 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; } - .init.data : { INIT_DATA } + .init.data : { *(.init.data) } . = ALIGN(16); __setup_start = .; .init.setup : { *(.init.setup) } @@ -100,8 +100,8 @@ SECTIONS .altinstr_replacement : { *(.altinstr_replacement) } /* .exit.text is discard at runtime, not link time, to deal with references from .altinstructions and .eh_frame */ - .exit.text : { EXIT_TEXT } - .exit.data : { EXIT_DATA } + .exit.text : { *(.exit.text) } + .exit.data : { *(.exit.data) } #ifdef CONFIG_BLK_DEV_INITRD . = ALIGN(4096); @@ -124,8 +124,8 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) *(.exitcall.exit) } diff --git a/trunk/arch/m68k/kernel/vmlinux-std.lds b/trunk/arch/m68k/kernel/vmlinux-std.lds index 7537cc5e6159..59fe285865ec 100644 --- a/trunk/arch/m68k/kernel/vmlinux-std.lds +++ b/trunk/arch/m68k/kernel/vmlinux-std.lds @@ -45,10 +45,10 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; } - .init.data : { INIT_DATA } + .init.data : { *(.init.data) } . = ALIGN(16); __setup_start = .; .init.setup : { *(.init.setup) } @@ -82,8 +82,8 @@ SECTIONS /* Sections to be discarded */ /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) *(.exitcall.exit) } diff --git a/trunk/arch/m68k/kernel/vmlinux-sun3.lds b/trunk/arch/m68k/kernel/vmlinux-sun3.lds index cdc313e7c299..4adffefb5c48 100644 --- a/trunk/arch/m68k/kernel/vmlinux-sun3.lds +++ b/trunk/arch/m68k/kernel/vmlinux-sun3.lds @@ -38,10 +38,10 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; } - .init.data : { INIT_DATA } + .init.data : { *(.init.data) } . = ALIGN(16); __setup_start = .; .init.setup : { *(.init.setup) } @@ -77,8 +77,8 @@ __init_begin = .; /* Sections to be discarded */ /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) *(.exitcall.exit) } diff --git a/trunk/arch/m68knommu/kernel/vmlinux.lds.S b/trunk/arch/m68knommu/kernel/vmlinux.lds.S index b44edb08e212..07a0055602f4 100644 --- a/trunk/arch/m68knommu/kernel/vmlinux.lds.S +++ b/trunk/arch/m68knommu/kernel/vmlinux.lds.S @@ -143,9 +143,9 @@ SECTIONS { . = ALIGN(4096); __init_begin = .; _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; - INIT_DATA + *(.init.data) . = ALIGN(16); __setup_start = .; *(.init.setup) @@ -170,8 +170,8 @@ SECTIONS { } > INIT /DISCARD/ : { - EXIT_TEXT - EXIT_DATA + *(.exit.text) + *(.exit.data) *(.exitcall.exit) } diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index 6b0f85f02c79..b22c043b6ef8 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -37,6 +37,16 @@ config BASLER_EXCITE The eXcite is a smart camera platform manufactured by Basler Vision Technologies AG. +config BASLER_EXCITE_PROTOTYPE + bool "Support for pre-release units" + depends on BASLER_EXCITE + default n + help + Pre-series (prototype) units are different from later ones in + some ways. Select this option if you have one of these. Please + note that a kernel built with this option selected will not be + able to run on normal units. + config BCM47XX bool "BCM47XX based boards" select CEVT_R4K @@ -72,7 +82,7 @@ config MIPS_COBALT select SYS_HAS_CPU_NEVADA select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL select SYS_SUPPORTS_LITTLE_ENDIAN select GENERIC_HARDIRQS_NO__DO_IRQ @@ -81,9 +91,6 @@ config MACH_DECSTATION select BOOT_ELF32 select CEVT_R4K select CSRC_R4K - select CPU_DADDI_WORKAROUNDS if 64BIT - select CPU_R4000_WORKAROUNDS if 64BIT - select CPU_R4400_WORKAROUNDS if 64BIT select DMA_NONCOHERENT select NO_IOPORT select IRQ_CPU @@ -117,12 +124,12 @@ config MACH_JAZZ select ARCH_MAY_HAVE_PC_FDC select CEVT_R4K select CSRC_R4K - select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN select GENERIC_ISA_DMA select IRQ_CPU select I8253 select I8259 select ISA + select PCSPEAKER select SYS_HAS_CPU_R4X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL @@ -180,7 +187,6 @@ config LEMOTE_FULONG config MIPS_ATLAS bool "MIPS Atlas board" select BOOT_ELF32 - select BOOT_RAW select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT @@ -213,7 +219,6 @@ config MIPS_MALTA bool "MIPS Malta board" select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 - select BOOT_RAW select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT @@ -359,6 +364,35 @@ config PMC_YOSEMITE Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra. +config QEMU + bool "Qemu" + select CEVT_R4K + select CSRC_R4K + select DMA_COHERENT + select GENERIC_ISA_DMA + select HAVE_STD_PC_SERIAL_PORT + select I8253 + select I8259 + select IRQ_CPU + select ISA + select PCSPEAKER + select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_HARDIRQS_NO__DO_IRQ + select NR_CPUS_DEFAULT_1 + select SYS_SUPPORTS_SMP + help + Qemu is a software emulator which among other architectures also + can simulate a MIPS32 4Kc system. This patch adds support for the + system architecture that currently is being simulated by Qemu. It + will eventually be removed again when Qemu has the capability to + simulate actual MIPS hardware platforms. More information on Qemu + can be found at http://www.linux-mips.org/wiki/Qemu. + config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select ARC @@ -366,7 +400,6 @@ config SGI_IP22 select BOOT_ELF32 select CEVT_R4K select CSRC_R4K - select DEFAULT_SGI_PARTITION select DMA_NONCOHERENT select HW_HAS_EISA select I8253 @@ -374,12 +407,6 @@ config SGI_IP22 select IP22_CPU_SCACHE select IRQ_CPU select GENERIC_ISA_DMA_SUPPORT_BROKEN - select SGI_HAS_DS1286 - select SGI_HAS_I8042 - select SGI_HAS_INDYDOG - select SGI_HAS_SEEQ - select SGI_HAS_WD93 - select SGI_HAS_ZILOG select SWAP_IO_SPACE select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 @@ -397,7 +424,6 @@ config SGI_IP27 select ARC select ARC64 select BOOT_ELF64 - select DEFAULT_SGI_PARTITION select DMA_IP27 select SYS_HAS_EARLY_PRINTK select HW_HAS_PCI @@ -414,36 +440,6 @@ config SGI_IP27 workstations. To compile a Linux kernel that runs on these, say Y here. -config SGI_IP28 - bool "SGI IP28 (Indigo2 R10k) (EXPERIMENTAL)" - depends on EXPERIMENTAL - select ARC - select ARC64 - select BOOT_ELF64 - select CEVT_R4K - select CSRC_R4K - select DEFAULT_SGI_PARTITION - select DMA_NONCOHERENT - select GENERIC_ISA_DMA_SUPPORT_BROKEN - select IRQ_CPU - select HW_HAS_EISA - select I8253 - select I8259 - select SGI_HAS_DS1286 - select SGI_HAS_I8042 - select SGI_HAS_INDYDOG - select SGI_HAS_SEEQ - select SGI_HAS_WD93 - select SGI_HAS_ZILOG - select SWAP_IO_SPACE - select SYS_HAS_CPU_R10000 - select SYS_HAS_EARLY_PRINTK - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_BIG_ENDIAN - help - This is the SGI Indigo2 with R10000 processor. To compile a Linux - kernel that runs on these, say Y here. - config SGI_IP32 bool "SGI IP32 (O2)" select ARC @@ -549,6 +545,19 @@ config SIBYTE_SENTOSA select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN +config SIBYTE_PTSWARM + bool "Sibyte BCM91250PT-PTSWARM" + depends on EXPERIMENTAL + select BOOT_ELF32 + select DMA_COHERENT + select NR_CPUS_DEFAULT_2 + select SIBYTE_SB1250 + select SWAP_IO_SPACE + select SYS_HAS_CPU_SB1 + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN + config SIBYTE_BIGSUR bool "Sibyte BCM91480B-BigSur" select BOOT_ELF32 @@ -566,12 +575,10 @@ config SNI_RM bool "SNI RM200/300/400" select ARC if CPU_LITTLE_ENDIAN select ARC32 if CPU_LITTLE_ENDIAN - select SNIPROM if CPU_BIG_ENDIAN select ARCH_MAY_HAVE_PC_FDC select BOOT_ELF32 select CEVT_R4K select CSRC_R4K - select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN select DMA_NONCOHERENT select GENERIC_ISA_DMA select HW_HAS_EISA @@ -580,6 +587,7 @@ config SNI_RM select I8253 select I8259 select ISA + select PCSPEAKER select SWAP_IO_SPACE if CPU_BIG_ENDIAN select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 @@ -682,7 +690,6 @@ config WR_PPMC endchoice source "arch/mips/au1000/Kconfig" -source "arch/mips/basler/excite/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" @@ -790,6 +797,10 @@ config DMA_COHERENT config DMA_IP27 bool +config DMA_IP32 + bool + select DMA_NEED_PCI_MAP_STATE + config DMA_NONCOHERENT bool select DMA_NEED_PCI_MAP_STATE @@ -945,40 +956,16 @@ config EMMA2RH config SERIAL_RM9000 bool -config SGI_HAS_DS1286 - bool - -config SGI_HAS_INDYDOG - bool - -config SGI_HAS_SEEQ - bool - -config SGI_HAS_WD93 - bool - -config SGI_HAS_ZILOG - bool - -config SGI_HAS_I8042 - bool - -config DEFAULT_SGI_PARTITION - bool - config ARC32 bool -config SNIPROM - bool - config BOOT_ELF32 bool config MIPS_L1_CACHE_SHIFT int default "4" if MACH_DECSTATION - default "7" if SGI_IP27 || SGI_IP28 || SNI_RM + default "7" if SGI_IP27 || SNI_RM default "4" if PMC_MSP4200_EVAL default "5" @@ -987,7 +974,7 @@ config HAVE_STD_PC_SERIAL_PORT config ARC_CONSOLE bool "ARC console support" - depends on SGI_IP22 || SGI_IP28 || (SNI_RM && CPU_LITTLE_ENDIAN) + depends on SGI_IP22 || (SNI_RM && CPU_LITTLE_ENDIAN) config ARC_MEMORY bool @@ -996,7 +983,7 @@ config ARC_MEMORY config ARC_PROMLIB bool - depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP28 || SGI_IP32 + depends on MACH_JAZZ || SNI_RM || SGI_IP22 || SGI_IP32 default y config ARC64 @@ -1456,9 +1443,7 @@ config MIPS_MT_SMP select MIPS_MT select NR_CPUS_DEFAULT_2 select SMP - select SYS_SUPPORTS_SCHED_SMT if SMP select SYS_SUPPORTS_SMP - select SMP_UP help This is a kernel model which is also known a VSMP or lately has been marketesed into SMVP. @@ -1475,7 +1460,6 @@ config MIPS_MT_SMTC select NR_CPUS_DEFAULT_8 select SMP select SYS_SUPPORTS_SMP - select SMP_UP help This is a kernel model which is known a SMTC or lately has been marketesed into SMVP. @@ -1485,19 +1469,6 @@ endchoice config MIPS_MT bool -config SCHED_SMT - bool "SMT (multithreading) scheduler support" - depends on SYS_SUPPORTS_SCHED_SMT - default n - help - SMT scheduler support improves the CPU scheduler's decision making - when dealing with MIPS MT enabled cores at a cost of slightly - increased overhead in some places. If unsure say N here. - -config SYS_SUPPORTS_SCHED_SMT - bool - - config SYS_SUPPORTS_MULTITHREADING bool @@ -1618,6 +1589,15 @@ config CPU_HAS_SMARTMIPS config CPU_HAS_WB bool +config 64BIT_CONTEXT + bool "Save 64bit integer registers" + depends on 32BIT && CPU_LOONGSON2 + help + Loongson2 CPU is 64bit , when used in 32BIT mode, its integer + registers can still be accessed as 64bit, mainly for multimedia + instructions. We must have all 64bit save/restored to make sure + those instructions to get correct result. + # # Vectored interrupt mode is an R2 feature # @@ -1638,19 +1618,6 @@ config CPU_HAS_SYNC config GENERIC_CLOCKEVENTS_BROADCAST bool -# -# CPU non-features -# -config CPU_DADDI_WORKAROUNDS - bool - -config CPU_R4000_WORKAROUNDS - bool - select CPU_R4400_WORKAROUNDS - -config CPU_R4400_WORKAROUNDS - bool - # # Use the generic interrupt handling code in kernel/irq/: # @@ -1754,9 +1721,6 @@ config SMP If you don't know what to do here, say N. -config SMP_UP - bool - config SYS_SUPPORTS_SMP bool @@ -2014,6 +1978,9 @@ config MMU config I8253 bool +config PCSPEAKER + bool + config ZONE_DMA32 bool diff --git a/trunk/arch/mips/Makefile b/trunk/arch/mips/Makefile index 3fb7f3065c92..a1f8d8b96b03 100644 --- a/trunk/arch/mips/Makefile +++ b/trunk/arch/mips/Makefile @@ -141,10 +141,6 @@ cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ -Wa,--trap -cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) -cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) -cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) - ifdef CONFIG_CPU_SB1 ifdef CONFIG_SB1_PASS_1_WORKAROUNDS MODFLAGS += -msb1-pass1-workarounds @@ -156,8 +152,6 @@ endif # libs-$(CONFIG_ARC) += arch/mips/fw/arc/ libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ -libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ -libs-y += arch/mips/fw/lib/ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ # @@ -314,7 +308,7 @@ core-$(CONFIG_MIPS_ATLAS) += arch/mips/mips-boards/atlas/ cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-atlas cflags-$(CONFIG_MIPS_ATLAS) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_ATLAS) += 0xffffffff80100000 -all-$(CONFIG_MIPS_ATLAS) := vmlinux.bin +all-$(CONFIG_MIPS_ATLAS) := vmlinux.srec # # MIPS Malta board @@ -322,7 +316,7 @@ all-$(CONFIG_MIPS_ATLAS) := vmlinux.bin core-$(CONFIG_MIPS_MALTA) += arch/mips/mips-boards/malta/ cflags-$(CONFIG_MIPS_MALTA) += -Iinclude/asm-mips/mach-mips load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 -all-$(CONFIG_MIPS_MALTA) := vmlinux.bin +all-$(CONFIG_MIPS_MALTA) := vmlinux.srec # # MIPS SEAD board @@ -354,6 +348,14 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 +# +# Qemu simulating MIPS32 4Kc +# +core-$(CONFIG_QEMU) += arch/mips/qemu/ +cflags-$(CONFIG_QEMU) += -Iinclude/asm-mips/mach-qemu +load-$(CONFIG_QEMU) += 0xffffffff80010000 +all-$(CONFIG_QEMU) := vmlinux.bin + # # Basler eXcite # @@ -472,20 +474,6 @@ OBJCOPYFLAGS := --change-addresses=0x57ffffff80000000 endif endif -# -# SGI IP28 (Indigo2 R10k) -# -# Set the load address to >= 0xa800000020080000 if you want to leave space for -# symmon, 0xa800000020004000 for production kernels ? Note that the value must -# be 16kb aligned or the handling of the current variable will break. -# Simplified: what IP22 does at 128MB+ in ksegN, IP28 does at 512MB+ in xkphys -# -#core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ arch/mips/arc/arc_con.o -core-$(CONFIG_SGI_IP28) += arch/mips/sgi-ip22/ -cflags-$(CONFIG_SGI_IP28) += -mr10k-cache-barrier=1 -Iinclude/asm-mips/mach-ip28 -#cflags-$(CONFIG_SGI_IP28) += -Iinclude/asm-mips/mach-ip28 -load-$(CONFIG_SGI_IP28) += 0xa800000020004000 - # # SGI-IP32 (O2) # @@ -614,11 +602,9 @@ ifdef CONFIG_64BIT endif endif - ifeq ($(KBUILD_SYM32)$(call cc-option-yn,-msym32), yy) - cflags-y += -msym32 -DKBUILD_64BIT_SYM32 - else - ifeq ($(CONFIG_CPU_DADDI_WORKAROUNDS), y) - $(error CONFIG_CPU_DADDI_WORKAROUNDS unsupported without -msym32) + ifeq ($(KBUILD_SYM32), y) + ifeq ($(call cc-option-yn,-msym32), y) + cflags-y += -msym32 -DKBUILD_64BIT_SYM32 endif endif endif diff --git a/trunk/arch/mips/au1000/common/au1xxx_irqmap.c b/trunk/arch/mips/au1000/common/au1xxx_irqmap.c index 37a10a01de9d..98a4e34b0248 100644 --- a/trunk/arch/mips/au1000/common/au1xxx_irqmap.c +++ b/trunk/arch/mips/au1000/common/au1xxx_irqmap.c @@ -25,10 +25,27 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#include #include -#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include -#include +#include +#include +#include +#include +#include /* The IC0 interrupt table. This is processor, rather than * board dependent, so no reason to keep this info in the board diff --git a/trunk/arch/mips/au1000/common/dbdma.c b/trunk/arch/mips/au1000/common/dbdma.c index 428ed275a0f6..edf91f41a786 100644 --- a/trunk/arch/mips/au1000/common/dbdma.c +++ b/trunk/arch/mips/au1000/common/dbdma.c @@ -179,7 +179,7 @@ static dbdev_tab_t dbdev_tab[] = { { 0, 0, 0, 0, 0, 0, 0 }, }; -#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) +#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t)) static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; diff --git a/trunk/arch/mips/au1000/db1x00/init.c b/trunk/arch/mips/au1000/db1x00/init.c index e822c123eab8..43298fd9459c 100644 --- a/trunk/arch/mips/au1000/db1x00/init.c +++ b/trunk/arch/mips/au1000/db1x00/init.c @@ -57,6 +57,17 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; + /* Set the platform # */ +#if defined(CONFIG_MIPS_DB1550) + mips_machtype = MACH_DB1550; +#elif defined(CONFIG_MIPS_DB1500) + mips_machtype = MACH_DB1500; +#elif defined(CONFIG_MIPS_DB1100) + mips_machtype = MACH_DB1100; +#else + mips_machtype = MACH_DB1000; +#endif + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/trunk/arch/mips/au1000/mtx-1/init.c b/trunk/arch/mips/au1000/mtx-1/init.c index e700fd312a24..cdeae3212a2d 100644 --- a/trunk/arch/mips/au1000/mtx-1/init.c +++ b/trunk/arch/mips/au1000/mtx-1/init.c @@ -54,6 +54,8 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; + mips_machtype = MACH_MTX1; /* set the platform # */ + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/trunk/arch/mips/au1000/mtx-1/platform.c b/trunk/arch/mips/au1000/mtx-1/platform.c index ce8637b3afa9..49c0fb409fea 100644 --- a/trunk/arch/mips/au1000/mtx-1/platform.c +++ b/trunk/arch/mips/au1000/mtx-1/platform.c @@ -22,32 +22,9 @@ #include #include #include -#include -#include #include -static struct gpio_keys_button mtx1_gpio_button[] = { - { - .gpio = 207, - .code = BTN_0, - .desc = "System button", - } -}; - -static struct gpio_keys_platform_data mtx1_buttons_data = { - .buttons = mtx1_gpio_button, - .nbuttons = ARRAY_SIZE(mtx1_gpio_button), -}; - -static struct platform_device mtx1_button = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &mtx1_buttons_data, - } -}; - static struct resource mtx1_wdt_res[] = { [0] = { .start = 15, @@ -89,13 +66,11 @@ static struct platform_device mtx1_gpio_leds = { static struct __initdata platform_device * mtx1_devs[] = { &mtx1_gpio_leds, - &mtx1_wdt, - &mtx1_button + &mtx1_wdt }; static int __init mtx1_register_devices(void) { - gpio_direction_input(207); return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); } diff --git a/trunk/arch/mips/au1000/pb1000/init.c b/trunk/arch/mips/au1000/pb1000/init.c index 2515b9fb24af..ddccaf6997d0 100644 --- a/trunk/arch/mips/au1000/pb1000/init.c +++ b/trunk/arch/mips/au1000/pb1000/init.c @@ -52,6 +52,8 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; + mips_machtype = MACH_PB1000; + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { diff --git a/trunk/arch/mips/au1000/pb1100/init.c b/trunk/arch/mips/au1000/pb1100/init.c index 490c3801c275..c93fd39b4aba 100644 --- a/trunk/arch/mips/au1000/pb1100/init.c +++ b/trunk/arch/mips/au1000/pb1100/init.c @@ -53,6 +53,8 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg3; + mips_machtype = MACH_PB1100; + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/trunk/arch/mips/au1000/pb1200/init.c b/trunk/arch/mips/au1000/pb1200/init.c index 069ed45f04f2..c251570749ee 100644 --- a/trunk/arch/mips/au1000/pb1200/init.c +++ b/trunk/arch/mips/au1000/pb1200/init.c @@ -53,6 +53,8 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; + mips_machtype = MACH_PB1200; + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { diff --git a/trunk/arch/mips/au1000/pb1500/init.c b/trunk/arch/mips/au1000/pb1500/init.c index db558c967048..507d4b204161 100644 --- a/trunk/arch/mips/au1000/pb1500/init.c +++ b/trunk/arch/mips/au1000/pb1500/init.c @@ -53,6 +53,8 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; + mips_machtype = MACH_PB1500; + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { diff --git a/trunk/arch/mips/au1000/pb1550/init.c b/trunk/arch/mips/au1000/pb1550/init.c index b716363ea564..b03eee601e36 100644 --- a/trunk/arch/mips/au1000/pb1550/init.c +++ b/trunk/arch/mips/au1000/pb1550/init.c @@ -53,6 +53,8 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; + mips_machtype = MACH_PB1550; + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); if (!memsize_str) { diff --git a/trunk/arch/mips/au1000/xxs1500/init.c b/trunk/arch/mips/au1000/xxs1500/init.c index 7e6878c1b0a5..6532939f377a 100644 --- a/trunk/arch/mips/au1000/xxs1500/init.c +++ b/trunk/arch/mips/au1000/xxs1500/init.c @@ -52,6 +52,8 @@ void __init prom_init(void) prom_argv = (char **) fw_arg1; prom_envp = (char **) fw_arg2; + mips_machtype = MACH_XXS1500; /* set the platform # */ + prom_init_cmdline(); memsize_str = prom_getenv("memsize"); diff --git a/trunk/arch/mips/basler/excite/Kconfig b/trunk/arch/mips/basler/excite/Kconfig deleted file mode 100644 index ba506075608b..000000000000 --- a/trunk/arch/mips/basler/excite/Kconfig +++ /dev/null @@ -1,9 +0,0 @@ -config BASLER_EXCITE_PROTOTYPE - bool "Support for pre-release units" - depends on BASLER_EXCITE - default n - help - Pre-series (prototype) units are different from later ones in - some ways. Select this option if you have one of these. Please - note that a kernel built with this option selected will not be - able to run on normal units. diff --git a/trunk/arch/mips/basler/excite/excite_iodev.c b/trunk/arch/mips/basler/excite/excite_iodev.c index 476d20e08d0e..6af0b21ebc32 100644 --- a/trunk/arch/mips/basler/excite/excite_iodev.c +++ b/trunk/arch/mips/basler/excite/excite_iodev.c @@ -48,7 +48,7 @@ static DECLARE_WAIT_QUEUE_HEAD(wq); -static const struct file_operations fops = +static struct file_operations fops = { .owner = THIS_MODULE, .open = iodev_open, diff --git a/trunk/arch/mips/basler/excite/excite_prom.c b/trunk/arch/mips/basler/excite/excite_prom.c index 68d8bc597e34..2d752c2f6e59 100644 --- a/trunk/arch/mips/basler/excite/excite_prom.c +++ b/trunk/arch/mips/basler/excite/excite_prom.c @@ -135,6 +135,8 @@ void __init prom_init(void) #ifdef CONFIG_64BIT # error 64 bit support not implemented #endif /* CONFIG_64BIT */ + + mips_machtype = MACH_TITAN_EXCITE; } /* This is called from free_initmem(), so we need to provide it */ diff --git a/trunk/arch/mips/cobalt/reset.c b/trunk/arch/mips/cobalt/reset.c index 516b4428df4e..71eb4ccc4bc1 100644 --- a/trunk/arch/mips/cobalt/reset.c +++ b/trunk/arch/mips/cobalt/reset.c @@ -10,10 +10,9 @@ */ #include #include +#include #include -#include - #include #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000)) @@ -30,15 +29,28 @@ device_initcall(ledtrig_power_off_init); void cobalt_machine_halt(void) { + int state, last, diff; + unsigned long mark; + /* * turn on power off LED on RaQ + * + * restart if ENTER and SELECT are pressed */ + + last = COBALT_KEY_PORT; + led_trigger_event(power_off_led_trigger, LED_FULL); - local_irq_disable(); - while (1) { - if (cpu_wait) - cpu_wait(); + for (state = 0;;) { + diff = COBALT_KEY_PORT ^ last; + last ^= diff; + + if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT))) + writeb(RESET, RESET_PORT); + + for (mark = jiffies; jiffies - mark < HZ;) + ; } } diff --git a/trunk/arch/mips/configs/atlas_defconfig b/trunk/arch/mips/configs/atlas_defconfig index 3443f6cd57bb..62bcc887f2ca 100644 --- a/trunk/arch/mips/configs/atlas_defconfig +++ b/trunk/arch/mips/configs/atlas_defconfig @@ -37,6 +37,7 @@ CONFIG_MIPS_ATLAS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_MIPS_ATLAS=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/bigsur_defconfig b/trunk/arch/mips/configs/bigsur_defconfig index abf70d74e9d7..3c70c9d16d01 100644 --- a/trunk/arch/mips/configs/bigsur_defconfig +++ b/trunk/arch/mips/configs/bigsur_defconfig @@ -37,6 +37,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_SIBYTE_BIGSUR=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/capcella_defconfig b/trunk/arch/mips/configs/capcella_defconfig index a94f14b5c8fa..8ecbbb226c76 100644 --- a/trunk/arch/mips/configs/capcella_defconfig +++ b/trunk/arch/mips/configs/capcella_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/cobalt_defconfig b/trunk/arch/mips/configs/cobalt_defconfig index b7295e988381..36c13039e237 100644 --- a/trunk/arch/mips/configs/cobalt_defconfig +++ b/trunk/arch/mips/configs/cobalt_defconfig @@ -24,6 +24,7 @@ CONFIG_MIPS_COBALT=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MIPS_COBALT=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/db1000_defconfig b/trunk/arch/mips/configs/db1000_defconfig index 36578968d386..5a8b7acb7dd7 100644 --- a/trunk/arch/mips/configs/db1000_defconfig +++ b/trunk/arch/mips/configs/db1000_defconfig @@ -38,6 +38,7 @@ CONFIG_MIPS_DB1000=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_MIPS_DB1000=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/db1100_defconfig b/trunk/arch/mips/configs/db1100_defconfig index 5a90740c363a..d4ed90bca269 100644 --- a/trunk/arch/mips/configs/db1100_defconfig +++ b/trunk/arch/mips/configs/db1100_defconfig @@ -38,6 +38,7 @@ CONFIG_MIPS_DB1100=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_MIPS_DB1100=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/db1200_defconfig b/trunk/arch/mips/configs/db1200_defconfig index 76f37a1159fe..a055657e6983 100644 --- a/trunk/arch/mips/configs/db1200_defconfig +++ b/trunk/arch/mips/configs/db1200_defconfig @@ -38,6 +38,7 @@ CONFIG_MIPS_DB1200=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_MIPS_DB1200=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/db1500_defconfig b/trunk/arch/mips/configs/db1500_defconfig index 508c91944f30..0ad08cf446ec 100644 --- a/trunk/arch/mips/configs/db1500_defconfig +++ b/trunk/arch/mips/configs/db1500_defconfig @@ -38,6 +38,7 @@ CONFIG_MIPS_DB1500=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_MIPS_DB1500=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/db1550_defconfig b/trunk/arch/mips/configs/db1550_defconfig index 0c2c70d21db9..057c7d429c80 100644 --- a/trunk/arch/mips/configs/db1550_defconfig +++ b/trunk/arch/mips/configs/db1550_defconfig @@ -38,6 +38,7 @@ CONFIG_MIPS_DB1550=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_MIPS_DB1550=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/decstation_defconfig b/trunk/arch/mips/configs/decstation_defconfig index 58c2cd68c3a7..2fb350432669 100644 --- a/trunk/arch/mips/configs/decstation_defconfig +++ b/trunk/arch/mips/configs/decstation_defconfig @@ -37,6 +37,7 @@ CONFIG_MACH_DECSTATION=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_MACH_DECSTATION=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/e55_defconfig b/trunk/arch/mips/configs/e55_defconfig index 90d81f5dcebc..d0d07faeb844 100644 --- a/trunk/arch/mips/configs/e55_defconfig +++ b/trunk/arch/mips/configs/e55_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/emma2rh_defconfig b/trunk/arch/mips/configs/emma2rh_defconfig index f9a003c2b3a1..d73d965f7615 100644 --- a/trunk/arch/mips/configs/emma2rh_defconfig +++ b/trunk/arch/mips/configs/emma2rh_defconfig @@ -37,6 +37,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set CONFIG_MARKEINS=y # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_MARKEINS=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/excite_defconfig b/trunk/arch/mips/configs/excite_defconfig index 15efacc75d73..17a866057fd4 100644 --- a/trunk/arch/mips/configs/excite_defconfig +++ b/trunk/arch/mips/configs/excite_defconfig @@ -38,6 +38,7 @@ CONFIG_BASLER_EXCITE=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_BASLER_EXCITE=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/fulong_defconfig b/trunk/arch/mips/configs/fulong_defconfig index 5887a1735fba..4ef39a0527cc 100644 --- a/trunk/arch/mips/configs/fulong_defconfig +++ b/trunk/arch/mips/configs/fulong_defconfig @@ -23,6 +23,7 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -32,6 +33,7 @@ CONFIG_LEMOTE_FULONG=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/ip22_defconfig b/trunk/arch/mips/configs/ip22_defconfig index 4f5e56c9335e..670039bb1a7c 100644 --- a/trunk/arch/mips/configs/ip22_defconfig +++ b/trunk/arch/mips/configs/ip22_defconfig @@ -25,6 +25,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set CONFIG_SGI_IP22=y # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,6 +36,7 @@ CONFIG_SGI_IP22=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/ip27_defconfig b/trunk/arch/mips/configs/ip27_defconfig index f40e437bd9e5..892d4c38fd0d 100644 --- a/trunk/arch/mips/configs/ip27_defconfig +++ b/trunk/arch/mips/configs/ip27_defconfig @@ -24,6 +24,7 @@ CONFIG_MIPS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_SGI_IP27=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/ip32_defconfig b/trunk/arch/mips/configs/ip32_defconfig index 2c5c624c5d42..47f49b60c5d6 100644 --- a/trunk/arch/mips/configs/ip32_defconfig +++ b/trunk/arch/mips/configs/ip32_defconfig @@ -37,6 +37,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_SGI_IP32=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/jazz_defconfig b/trunk/arch/mips/configs/jazz_defconfig index 56148745e8f2..fa655e247ecc 100644 --- a/trunk/arch/mips/configs/jazz_defconfig +++ b/trunk/arch/mips/configs/jazz_defconfig @@ -37,6 +37,7 @@ CONFIG_MACH_JAZZ=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_MACH_JAZZ=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/jmr3927_defconfig b/trunk/arch/mips/configs/jmr3927_defconfig index a7cd67753aac..eb96791c33ea 100644 --- a/trunk/arch/mips/configs/jmr3927_defconfig +++ b/trunk/arch/mips/configs/jmr3927_defconfig @@ -24,6 +24,7 @@ CONFIG_MIPS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set CONFIG_TOSHIBA_JMR3927=y @@ -462,6 +464,7 @@ CONFIG_SERIAL_TXX9_STDSERIAL=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set # CONFIG_R3964 is not set @@ -479,20 +482,6 @@ CONFIG_DEVPORT=y # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_TXX9_WDT=y - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set # # Multifunction device drivers diff --git a/trunk/arch/mips/configs/lasat_defconfig b/trunk/arch/mips/configs/lasat_defconfig index e6aef999854c..2c665fcef089 100644 --- a/trunk/arch/mips/configs/lasat_defconfig +++ b/trunk/arch/mips/configs/lasat_defconfig @@ -25,6 +25,7 @@ CONFIG_LASAT=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,6 +36,7 @@ CONFIG_LASAT=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/malta_defconfig b/trunk/arch/mips/configs/malta_defconfig index 3d0da952811c..4b7e43c9f69a 100644 --- a/trunk/arch/mips/configs/malta_defconfig +++ b/trunk/arch/mips/configs/malta_defconfig @@ -25,6 +25,7 @@ CONFIG_MIPS_MALTA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,6 +36,7 @@ CONFIG_MIPS_MALTA=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/mipssim_defconfig b/trunk/arch/mips/configs/mipssim_defconfig index 6db0bdaefb27..61b72f5a953e 100644 --- a/trunk/arch/mips/configs/mipssim_defconfig +++ b/trunk/arch/mips/configs/mipssim_defconfig @@ -26,6 +26,7 @@ CONFIG_MIPS_SIM=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -36,6 +37,7 @@ CONFIG_MIPS_SIM=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/mpc30x_defconfig b/trunk/arch/mips/configs/mpc30x_defconfig index 27e23fc9363a..8334350d7229 100644 --- a/trunk/arch/mips/configs/mpc30x_defconfig +++ b/trunk/arch/mips/configs/mpc30x_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/msp71xx_defconfig b/trunk/arch/mips/configs/msp71xx_defconfig index b12b73f6d74f..69278999c9a2 100644 --- a/trunk/arch/mips/configs/msp71xx_defconfig +++ b/trunk/arch/mips/configs/msp71xx_defconfig @@ -38,6 +38,7 @@ CONFIG_ZONE_DMA=y # CONFIG_MACH_VR41XX is not set CONFIG_PMC_MSP=y # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_PMC_MSP=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/mtx1_defconfig b/trunk/arch/mips/configs/mtx1_defconfig index fa3aa3919448..b536d7c63790 100644 --- a/trunk/arch/mips/configs/mtx1_defconfig +++ b/trunk/arch/mips/configs/mtx1_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MACH_ALCHEMY=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set @@ -1615,7 +1617,6 @@ CONFIG_INPUT_EVBUG=m # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=y -CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_SUNKBD=m CONFIG_KEYBOARD_LKKBD=m CONFIG_KEYBOARD_XTKBD=m diff --git a/trunk/arch/mips/configs/pb1100_defconfig b/trunk/arch/mips/configs/pb1100_defconfig index 1d0157d3a5bb..703d28db05b9 100644 --- a/trunk/arch/mips/configs/pb1100_defconfig +++ b/trunk/arch/mips/configs/pb1100_defconfig @@ -38,6 +38,7 @@ CONFIG_MIPS_PB1100=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_MIPS_PB1100=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/pb1500_defconfig b/trunk/arch/mips/configs/pb1500_defconfig index d0491a05ee58..82f0c5cee0dc 100644 --- a/trunk/arch/mips/configs/pb1500_defconfig +++ b/trunk/arch/mips/configs/pb1500_defconfig @@ -38,6 +38,7 @@ CONFIG_MIPS_PB1500=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_MIPS_PB1500=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/pb1550_defconfig b/trunk/arch/mips/configs/pb1550_defconfig index 16d78d3cd2aa..147a4fc7fdd8 100644 --- a/trunk/arch/mips/configs/pb1550_defconfig +++ b/trunk/arch/mips/configs/pb1550_defconfig @@ -38,6 +38,7 @@ CONFIG_MIPS_PB1550=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -47,6 +48,7 @@ CONFIG_MIPS_PB1550=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/pnx8550-jbs_defconfig b/trunk/arch/mips/configs/pnx8550-jbs_defconfig index 518a60892b78..f6906b069e04 100644 --- a/trunk/arch/mips/configs/pnx8550-jbs_defconfig +++ b/trunk/arch/mips/configs/pnx8550-jbs_defconfig @@ -37,6 +37,7 @@ CONFIG_PNX8550_JBS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_PNX8550_JBS=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/pnx8550-stb810_defconfig b/trunk/arch/mips/configs/pnx8550-stb810_defconfig index 68351eb81bc8..b741f81696fb 100644 --- a/trunk/arch/mips/configs/pnx8550-stb810_defconfig +++ b/trunk/arch/mips/configs/pnx8550-stb810_defconfig @@ -37,6 +37,7 @@ CONFIG_ZONE_DMA=y CONFIG_PNX8550_STB810=y # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_PNX8550_STB810=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/qemu_defconfig b/trunk/arch/mips/configs/qemu_defconfig index 72ca147f9422..b3caf5125c15 100644 --- a/trunk/arch/mips/configs/qemu_defconfig +++ b/trunk/arch/mips/configs/qemu_defconfig @@ -37,6 +37,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +CONFIG_QEMU=y # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_ZONE_DMA=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/rbhma4200_defconfig b/trunk/arch/mips/configs/rbhma4200_defconfig index 470f6f4d3ea2..9383a598094b 100644 --- a/trunk/arch/mips/configs/rbhma4200_defconfig +++ b/trunk/arch/mips/configs/rbhma4200_defconfig @@ -24,6 +24,7 @@ CONFIG_MIPS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set @@ -429,6 +431,7 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set # CONFIG_R3964 is not set @@ -446,20 +449,6 @@ CONFIG_DEVPORT=y # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_TXX9_WDT=m - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set # # Multifunction device drivers diff --git a/trunk/arch/mips/configs/rbhma4500_defconfig b/trunk/arch/mips/configs/rbhma4500_defconfig index 5a39f56b175e..d1b56cc0fd7c 100644 --- a/trunk/arch/mips/configs/rbhma4500_defconfig +++ b/trunk/arch/mips/configs/rbhma4500_defconfig @@ -24,6 +24,7 @@ CONFIG_MIPS=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MIPS=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set @@ -448,6 +450,7 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set # CONFIG_RTC is not set # CONFIG_R3964 is not set @@ -476,20 +479,6 @@ CONFIG_SPI_AT25=y # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_TXX9_WDT=m - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set # # Multifunction device drivers diff --git a/trunk/arch/mips/configs/rm200_defconfig b/trunk/arch/mips/configs/rm200_defconfig index 56371b860eb0..fc388118b114 100644 --- a/trunk/arch/mips/configs/rm200_defconfig +++ b/trunk/arch/mips/configs/rm200_defconfig @@ -37,6 +37,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_ZONE_DMA=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/sb1250-swarm_defconfig b/trunk/arch/mips/configs/sb1250-swarm_defconfig index 117470b60e34..c2798229cbfb 100644 --- a/trunk/arch/mips/configs/sb1250-swarm_defconfig +++ b/trunk/arch/mips/configs/sb1250-swarm_defconfig @@ -37,6 +37,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_SIBYTE_SWARM=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/sead_defconfig b/trunk/arch/mips/configs/sead_defconfig index 3ee75b15c0b0..2b6282d132a8 100644 --- a/trunk/arch/mips/configs/sead_defconfig +++ b/trunk/arch/mips/configs/sead_defconfig @@ -37,6 +37,7 @@ CONFIG_MIPS_SEAD=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_MIPS_SEAD=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/tb0219_defconfig b/trunk/arch/mips/configs/tb0219_defconfig index af82e1a1823c..326aa7aa40ea 100644 --- a/trunk/arch/mips/configs/tb0219_defconfig +++ b/trunk/arch/mips/configs/tb0219_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/tb0226_defconfig b/trunk/arch/mips/configs/tb0226_defconfig index a95385b24546..9fd0faeacf53 100644 --- a/trunk/arch/mips/configs/tb0226_defconfig +++ b/trunk/arch/mips/configs/tb0226_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/tb0287_defconfig b/trunk/arch/mips/configs/tb0287_defconfig index 40d4a40a970e..499b6bd7ee68 100644 --- a/trunk/arch/mips/configs/tb0287_defconfig +++ b/trunk/arch/mips/configs/tb0287_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/workpad_defconfig b/trunk/arch/mips/configs/workpad_defconfig index edf90b321fe6..b52256ca0b53 100644 --- a/trunk/arch/mips/configs/workpad_defconfig +++ b/trunk/arch/mips/configs/workpad_defconfig @@ -24,6 +24,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -34,6 +35,7 @@ CONFIG_MACH_VR41XX=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/configs/wrppmc_defconfig b/trunk/arch/mips/configs/wrppmc_defconfig index 2e3c683b2052..7e410e10fed7 100644 --- a/trunk/arch/mips/configs/wrppmc_defconfig +++ b/trunk/arch/mips/configs/wrppmc_defconfig @@ -37,6 +37,7 @@ CONFIG_WR_PPMC=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_WR_PPMC=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/configs/yosemite_defconfig b/trunk/arch/mips/configs/yosemite_defconfig index b6178ffbc523..acaf0e21bb00 100644 --- a/trunk/arch/mips/configs/yosemite_defconfig +++ b/trunk/arch/mips/configs/yosemite_defconfig @@ -37,6 +37,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_MACH_VR41XX is not set CONFIG_PMC_YOSEMITE=y +# CONFIG_QEMU is not set # CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set @@ -46,6 +47,7 @@ CONFIG_PMC_YOSEMITE=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CRHONE is not set diff --git a/trunk/arch/mips/dec/time.c b/trunk/arch/mips/dec/time.c index 60349062595a..820e5331205f 100644 --- a/trunk/arch/mips/dec/time.c +++ b/trunk/arch/mips/dec/time.c @@ -161,6 +161,7 @@ static cycle_t dec_ioasic_hpt_read(void) void __init plat_time_init(void) { + mips_timer_state = dec_timer_state; mips_timer_ack = dec_timer_ack; if (!cpu_has_counter && IOASIC) diff --git a/trunk/arch/mips/defconfig b/trunk/arch/mips/defconfig index 4f5e56c9335e..670039bb1a7c 100644 --- a/trunk/arch/mips/defconfig +++ b/trunk/arch/mips/defconfig @@ -25,6 +25,7 @@ CONFIG_ZONE_DMA=y # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set CONFIG_SGI_IP22=y # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP32 is not set @@ -35,6 +36,7 @@ CONFIG_SGI_IP22=y # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_PTSWARM is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_TOSHIBA_JMR3927 is not set diff --git a/trunk/arch/mips/fw/arc/cmdline.c b/trunk/arch/mips/fw/arc/cmdline.c index 4ca4eef934a5..fd604ef28823 100644 --- a/trunk/arch/mips/fw/arc/cmdline.c +++ b/trunk/arch/mips/fw/arc/cmdline.c @@ -52,7 +52,7 @@ static char * __init move_firmware_args(char* cp) strcat(cp, used_arc[i][1]); cp += strlen(used_arc[i][1]); /* ... and now the argument */ - s = strchr(prom_argv(actr), '='); + s = strstr(prom_argv(actr), "="); if (s) { s++; strcpy(cp, s); diff --git a/trunk/arch/mips/fw/arc/init.c b/trunk/arch/mips/fw/arc/init.c index 3ad8788b6eaa..e2f75b13312f 100644 --- a/trunk/arch/mips/fw/arc/init.c +++ b/trunk/arch/mips/fw/arc/init.c @@ -12,7 +12,6 @@ #include #include -#include #undef DEBUG_PROM_INIT @@ -49,11 +48,4 @@ void __init prom_init(void) ArcRead(0, &c, 1, &cnt); ArcEnterInteractiveMode(); #endif -#ifdef CONFIG_SGI_IP27 - { - extern struct plat_smp_ops ip27_smp_ops; - - register_smp_ops(&ip27_smp_ops); - } -#endif } diff --git a/trunk/arch/mips/fw/cfe/cfe_api.c b/trunk/arch/mips/fw/cfe/cfe_api.c index 717db74f7c6e..a9f69e4e40ac 100644 --- a/trunk/arch/mips/fw/cfe/cfe_api.c +++ b/trunk/arch/mips/fw/cfe/cfe_api.c @@ -16,16 +16,19 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* - * - * Broadcom Common Firmware Environment (CFE) - * - * This module contains device function stubs (small routines to - * call the standard "iocb" interface entry point to CFE). - * There should be one routine here per iocb function call. - * - * Authors: Mitch Lichtenberg, Chris Demetriou - */ +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device Function stubs File: cfe_api.c + * + * This module contains device function stubs (small routines to + * call the standard "iocb" interface entry point to CFE). + * There should be one routine here per iocb function call. + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ #include #include "cfe_api_int.h" @@ -34,8 +37,12 @@ #define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n)) #define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x)) -int cfe_iocb_dispatch(struct cfe_xiocb *xiocb); +#ifdef CFE_API_IMPL_NAMESPACE +#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a) +#endif +int cfe_iocb_dispatch(cfe_xiocb_t * xiocb); +#if defined(CFE_API_common) || defined(CFE_API_ALL) /* * Declare the dispatch function with args of "intptr_t". * This makes sure whatever model we're compiling in @@ -46,25 +53,27 @@ int cfe_iocb_dispatch(struct cfe_xiocb *xiocb); */ static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0; -static u64 cfe_handle = 0; +static cfe_xuint_t cfe_handle = 0; -int cfe_init(u64 handle, u64 ept) +int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept) { cfe_dispfunc = NATIVE_FROM_XPTR(ept); cfe_handle = handle; return 0; } -int cfe_iocb_dispatch(struct cfe_xiocb * xiocb) +int cfe_iocb_dispatch(cfe_xiocb_t * xiocb) { if (!cfe_dispfunc) return -1; return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb); } +#endif /* CFE_API_common || CFE_API_ALL */ +#if defined(CFE_API_close) || defined(CFE_API_ALL) int cfe_close(int handle) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE; xiocb.xiocb_status = 0; @@ -77,16 +86,18 @@ int cfe_close(int handle) return xiocb.xiocb_status; } +#endif /* CFE_API_close || CFE_API_ALL */ +#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL) int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl); + xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); xiocb.plist.xiocb_cpuctl.cpu_number = cpu; xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START; xiocb.plist.xiocb_cpuctl.gp_val = gp; @@ -98,16 +109,18 @@ int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1) return xiocb.xiocb_status; } +#endif /* CFE_API_cpu_start || CFE_API_ALL */ +#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL) int cfe_cpu_stop(int cpu) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl); + xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t); xiocb.plist.xiocb_cpuctl.cpu_number = cpu; xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP; @@ -115,16 +128,18 @@ int cfe_cpu_stop(int cpu) return xiocb.xiocb_status; } +#endif /* CFE_API_cpu_stop || CFE_API_ALL */ +#if defined(CFE_API_enumenv) || defined(CFE_API_ALL) int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_ENV_SET; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_envbuf); + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); xiocb.plist.xiocb_envbuf.enum_idx = idx; xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); xiocb.plist.xiocb_envbuf.name_length = namelen; @@ -135,17 +150,20 @@ int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen) return xiocb.xiocb_status; } +#endif /* CFE_API_enumenv || CFE_API_ALL */ +#if defined(CFE_API_enummem) || defined(CFE_API_ALL) int -cfe_enummem(int idx, int flags, u64 *start, u64 *length, u64 *type) +cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length, + cfe_xuint_t * type) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = flags; - xiocb.xiocb_psize = sizeof(struct xiocb_meminfo); + xiocb.xiocb_psize = sizeof(xiocb_meminfo_t); xiocb.plist.xiocb_meminfo.mi_idx = idx; cfe_iocb_dispatch(&xiocb); @@ -159,26 +177,30 @@ cfe_enummem(int idx, int flags, u64 *start, u64 *length, u64 *type) return 0; } +#endif /* CFE_API_enummem || CFE_API_ALL */ +#if defined(CFE_API_exit) || defined(CFE_API_ALL) int cfe_exit(int warm, int status) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_RESTART; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0; - xiocb.xiocb_psize = sizeof(struct xiocb_exitstat); + xiocb.xiocb_psize = sizeof(xiocb_exitstat_t); xiocb.plist.xiocb_exitstat.status = status; cfe_iocb_dispatch(&xiocb); return xiocb.xiocb_status; } +#endif /* CFE_API_exit || CFE_API_ALL */ +#if defined(CFE_API_flushcache) || defined(CFE_API_ALL) int cfe_flushcache(int flg) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE; xiocb.xiocb_status = 0; @@ -190,30 +212,34 @@ int cfe_flushcache(int flg) return xiocb.xiocb_status; } +#endif /* CFE_API_flushcache || CFE_API_ALL */ +#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL) int cfe_getdevinfo(char *name) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_buffer); + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); xiocb.plist.xiocb_buffer.buf_offset = 0; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_buffer.buf_length = strlen(name); + xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); cfe_iocb_dispatch(&xiocb); if (xiocb.xiocb_status < 0) return xiocb.xiocb_status; - return xiocb.plist.xiocb_buffer.buf_ioctlcmd; + return xiocb.plist.xiocb_buffer.buf_devflags; } +#endif /* CFE_API_getdevinfo || CFE_API_ALL */ +#if defined(CFE_API_getenv) || defined(CFE_API_ALL) int cfe_getenv(char *name, char *dest, int destlen) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; *dest = 0; @@ -221,10 +247,10 @@ int cfe_getenv(char *name, char *dest, int destlen) xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_envbuf); + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); xiocb.plist.xiocb_envbuf.enum_idx = 0; xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_envbuf.name_length = strlen(name); + xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest); xiocb.plist.xiocb_envbuf.val_length = destlen; @@ -232,16 +258,18 @@ int cfe_getenv(char *name, char *dest, int destlen) return xiocb.xiocb_status; } +#endif /* CFE_API_getenv || CFE_API_ALL */ +#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL) int cfe_getfwinfo(cfe_fwinfo_t * info) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_fwinfo); + xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t); cfe_iocb_dispatch(&xiocb); @@ -264,10 +292,12 @@ int cfe_getfwinfo(cfe_fwinfo_t * info) return 0; } +#endif /* CFE_API_getfwinfo || CFE_API_ALL */ +#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL) int cfe_getstdhandle(int flg) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE; xiocb.xiocb_status = 0; @@ -281,17 +311,23 @@ int cfe_getstdhandle(int flg) return xiocb.xiocb_status; return xiocb.xiocb_handle; } +#endif /* CFE_API_getstdhandle || CFE_API_ALL */ +#if defined(CFE_API_getticks) || defined(CFE_API_ALL) int64_t +#ifdef CFE_API_IMPL_NAMESPACE +__cfe_getticks(void) +#else cfe_getticks(void) +#endif { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_time); + xiocb.xiocb_psize = sizeof(xiocb_time_t); xiocb.plist.xiocb_time.ticks = 0; cfe_iocb_dispatch(&xiocb); @@ -299,16 +335,18 @@ cfe_getticks(void) return xiocb.plist.xiocb_time.ticks; } +#endif /* CFE_API_getticks || CFE_API_ALL */ +#if defined(CFE_API_inpstat) || defined(CFE_API_ALL) int cfe_inpstat(int handle) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT; xiocb.xiocb_status = 0; xiocb.xiocb_handle = handle; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_inpstat); + xiocb.xiocb_psize = sizeof(xiocb_inpstat_t); xiocb.plist.xiocb_inpstat.inp_status = 0; cfe_iocb_dispatch(&xiocb); @@ -317,18 +355,20 @@ int cfe_inpstat(int handle) return xiocb.xiocb_status; return xiocb.plist.xiocb_inpstat.inp_status; } +#endif /* CFE_API_inpstat || CFE_API_ALL */ +#if defined(CFE_API_ioctl) || defined(CFE_API_ALL) int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, - int length, int *retlen, u64 offset) + int length, int *retlen, cfe_xuint_t offset) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL; xiocb.xiocb_status = 0; xiocb.xiocb_handle = handle; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_buffer); + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); xiocb.plist.xiocb_buffer.buf_offset = offset; xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); @@ -340,19 +380,21 @@ cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer, *retlen = xiocb.plist.xiocb_buffer.buf_retlen; return xiocb.xiocb_status; } +#endif /* CFE_API_ioctl || CFE_API_ALL */ +#if defined(CFE_API_open) || defined(CFE_API_ALL) int cfe_open(char *name) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_buffer); + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); xiocb.plist.xiocb_buffer.buf_offset = 0; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_buffer.buf_length = strlen(name); + xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name); cfe_iocb_dispatch(&xiocb); @@ -360,21 +402,27 @@ int cfe_open(char *name) return xiocb.xiocb_status; return xiocb.xiocb_handle; } +#endif /* CFE_API_open || CFE_API_ALL */ +#if defined(CFE_API_read) || defined(CFE_API_ALL) int cfe_read(int handle, unsigned char *buffer, int length) { return cfe_readblk(handle, 0, buffer, length); } +#endif /* CFE_API_read || CFE_API_ALL */ -int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length) +#if defined(CFE_API_readblk) || defined(CFE_API_ALL) +int +cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer, + int length) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_READ; xiocb.xiocb_status = 0; xiocb.xiocb_handle = handle; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_buffer); + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); xiocb.plist.xiocb_buffer.buf_offset = offset; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); xiocb.plist.xiocb_buffer.buf_length = length; @@ -385,41 +433,62 @@ int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length) return xiocb.xiocb_status; return xiocb.plist.xiocb_buffer.buf_retlen; } +#endif /* CFE_API_readblk || CFE_API_ALL */ +#if defined(CFE_API_setenv) || defined(CFE_API_ALL) int cfe_setenv(char *name, char *val) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_ENV_SET; xiocb.xiocb_status = 0; xiocb.xiocb_handle = 0; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_envbuf); + xiocb.xiocb_psize = sizeof(xiocb_envbuf_t); xiocb.plist.xiocb_envbuf.enum_idx = 0; xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name); - xiocb.plist.xiocb_envbuf.name_length = strlen(name); + xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name); xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val); - xiocb.plist.xiocb_envbuf.val_length = strlen(val); + xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val); cfe_iocb_dispatch(&xiocb); return xiocb.xiocb_status; } +#endif /* CFE_API_setenv || CFE_API_ALL */ + +#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \ + && !defined(CFE_API_STRLEN_CUSTOM) +int cfe_strlen(char *name) +{ + int count = 0; + + while (*name++) + count++; + return count; +} +#endif /* CFE_API_strlen || CFE_API_ALL */ + +#if defined(CFE_API_write) || defined(CFE_API_ALL) int cfe_write(int handle, unsigned char *buffer, int length) { return cfe_writeblk(handle, 0, buffer, length); } +#endif /* CFE_API_write || CFE_API_ALL */ -int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) +#if defined(CFE_API_writeblk) || defined(CFE_API_ALL) +int +cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer, + int length) { - struct cfe_xiocb xiocb; + cfe_xiocb_t xiocb; xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE; xiocb.xiocb_status = 0; xiocb.xiocb_handle = handle; xiocb.xiocb_flags = 0; - xiocb.xiocb_psize = sizeof(struct xiocb_buffer); + xiocb.xiocb_psize = sizeof(xiocb_buffer_t); xiocb.plist.xiocb_buffer.buf_offset = offset; xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer); xiocb.plist.xiocb_buffer.buf_length = length; @@ -430,3 +499,4 @@ int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length) return xiocb.xiocb_status; return xiocb.plist.xiocb_buffer.buf_retlen; } +#endif /* CFE_API_writeblk || CFE_API_ALL */ diff --git a/trunk/arch/mips/fw/cfe/cfe_api_int.h b/trunk/arch/mips/fw/cfe/cfe_api_int.h index d9759e646956..f7e5a64b55f3 100644 --- a/trunk/arch/mips/fw/cfe/cfe_api_int.h +++ b/trunk/arch/mips/fw/cfe/cfe_api_int.h @@ -15,12 +15,28 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* ********************************************************************* + * + * Broadcom Common Firmware Environment (CFE) + * + * Device function prototypes File: cfe_api_int.h + * + * This header defines all internal types and macros for the + * library. This is stuff that's not exported to an app + * using the library. + * + * Authors: Mitch Lichtenberg, Chris Demetriou + * + ********************************************************************* */ + #ifndef CFE_API_INT_H #define CFE_API_INT_H -/* - * Constants. - */ +/* ********************************************************************* + * Constants + ********************************************************************* */ + #define CFE_CMD_FW_GETINFO 0 #define CFE_CMD_FW_RESTART 1 #define CFE_CMD_FW_BOOT 2 @@ -48,101 +64,89 @@ #define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */ -/* - * Structures. - */ +/* ********************************************************************* + * Structures + ********************************************************************* */ -/* eeek, signed "pointers" */ -typedef s64 cfe_xptr_t; +typedef uint64_t cfe_xuint_t; +typedef int64_t cfe_xint_t; +typedef int64_t cfe_xptr_t; -struct xiocb_buffer { - u64 buf_offset; /* offset on device (bytes) */ +typedef struct xiocb_buffer_s { + cfe_xuint_t buf_offset; /* offset on device (bytes) */ cfe_xptr_t buf_ptr; /* pointer to a buffer */ - u64 buf_length; /* length of this buffer */ - u64 buf_retlen; /* returned length (for read ops) */ - u64 buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */ -}; + cfe_xuint_t buf_length; /* length of this buffer */ + cfe_xuint_t buf_retlen; /* returned length (for read ops) */ + cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */ +} xiocb_buffer_t; + +#define buf_devflags buf_ioctlcmd /* returned device info flags */ -struct xiocb_inpstat { - u64 inp_status; /* 1 means input available */ -}; +typedef struct xiocb_inpstat_s { + cfe_xuint_t inp_status; /* 1 means input available */ +} xiocb_inpstat_t; -struct xiocb_envbuf { - s64 enum_idx; /* 0-based enumeration index */ +typedef struct xiocb_envbuf_s { + cfe_xint_t enum_idx; /* 0-based enumeration index */ cfe_xptr_t name_ptr; /* name string buffer */ - s64 name_length; /* size of name buffer */ + cfe_xint_t name_length; /* size of name buffer */ cfe_xptr_t val_ptr; /* value string buffer */ - s64 val_length; /* size of value string buffer */ -}; - -struct xiocb_cpuctl { - u64 cpu_number; /* cpu number to control */ - u64 cpu_command; /* command to issue to CPU */ - u64 start_addr; /* CPU start address */ - u64 gp_val; /* starting GP value */ - u64 sp_val; /* starting SP value */ - u64 a1_val; /* starting A1 value */ -}; - -struct xiocb_time { - s64 ticks; /* current time in ticks */ -}; - -struct xiocb_exitstat{ - s64 status; -}; - -struct xiocb_meminfo { - s64 mi_idx; /* 0-based enumeration index */ - s64 mi_type; /* type of memory block */ - u64 mi_addr; /* physical start address */ - u64 mi_size; /* block size */ -}; - -struct xiocb_fwinfo { - s64 fwi_version; /* major, minor, eco version */ - s64 fwi_totalmem; /* total installed mem */ - s64 fwi_flags; /* various flags */ - s64 fwi_boardid; /* board ID */ - s64 fwi_bootarea_va; /* VA of boot area */ - s64 fwi_bootarea_pa; /* PA of boot area */ - s64 fwi_bootarea_size; /* size of boot area */ - s64 fwi_reserved1; - s64 fwi_reserved2; - s64 fwi_reserved3; -}; - -struct cfe_xiocb { - u64 xiocb_fcode; /* IOCB function code */ - s64 xiocb_status; /* return status */ - s64 xiocb_handle; /* file/device handle */ - u64 xiocb_flags; /* flags for this IOCB */ - u64 xiocb_psize; /* size of parameter list */ + cfe_xint_t val_length; /* size of value string buffer */ +} xiocb_envbuf_t; + +typedef struct xiocb_cpuctl_s { + cfe_xuint_t cpu_number; /* cpu number to control */ + cfe_xuint_t cpu_command; /* command to issue to CPU */ + cfe_xuint_t start_addr; /* CPU start address */ + cfe_xuint_t gp_val; /* starting GP value */ + cfe_xuint_t sp_val; /* starting SP value */ + cfe_xuint_t a1_val; /* starting A1 value */ +} xiocb_cpuctl_t; + +typedef struct xiocb_time_s { + cfe_xint_t ticks; /* current time in ticks */ +} xiocb_time_t; + +typedef struct xiocb_exitstat_s { + cfe_xint_t status; +} xiocb_exitstat_t; + +typedef struct xiocb_meminfo_s { + cfe_xint_t mi_idx; /* 0-based enumeration index */ + cfe_xint_t mi_type; /* type of memory block */ + cfe_xuint_t mi_addr; /* physical start address */ + cfe_xuint_t mi_size; /* block size */ +} xiocb_meminfo_t; + +typedef struct xiocb_fwinfo_s { + cfe_xint_t fwi_version; /* major, minor, eco version */ + cfe_xint_t fwi_totalmem; /* total installed mem */ + cfe_xint_t fwi_flags; /* various flags */ + cfe_xint_t fwi_boardid; /* board ID */ + cfe_xint_t fwi_bootarea_va; /* VA of boot area */ + cfe_xint_t fwi_bootarea_pa; /* PA of boot area */ + cfe_xint_t fwi_bootarea_size; /* size of boot area */ + cfe_xint_t fwi_reserved1; + cfe_xint_t fwi_reserved2; + cfe_xint_t fwi_reserved3; +} xiocb_fwinfo_t; + +typedef struct cfe_xiocb_s { + cfe_xuint_t xiocb_fcode; /* IOCB function code */ + cfe_xint_t xiocb_status; /* return status */ + cfe_xint_t xiocb_handle; /* file/device handle */ + cfe_xuint_t xiocb_flags; /* flags for this IOCB */ + cfe_xuint_t xiocb_psize; /* size of parameter list */ union { - /* buffer parameters */ - struct xiocb_buffer xiocb_buffer; - - /* input status parameters */ - struct xiocb_inpstat xiocb_inpstat; - - /* environment function parameters */ - struct xiocb_envbuf xiocb_envbuf; - - /* CPU control parameters */ - struct xiocb_cpuctl xiocb_cpuctl; - - /* timer parameters */ - struct xiocb_time xiocb_time; - - /* memory arena info parameters */ - struct xiocb_meminfo xiocb_meminfo; - - /* firmware information */ - struct xiocb_fwinfo xiocb_fwinfo; - - /* Exit Status */ - struct xiocb_exitstat xiocb_exitstat; + xiocb_buffer_t xiocb_buffer; /* buffer parameters */ + xiocb_inpstat_t xiocb_inpstat; /* input status parameters */ + xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */ + xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */ + xiocb_time_t xiocb_time; /* timer parameters */ + xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */ + xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */ + xiocb_exitstat_t xiocb_exitstat; /* Exit Status */ } plist; -}; +} cfe_xiocb_t; -#endif /* CFE_API_INT_H */ +#endif /* CFE_API_INT_H */ diff --git a/trunk/arch/mips/fw/lib/Makefile b/trunk/arch/mips/fw/lib/Makefile deleted file mode 100644 index 84befc968fc4..000000000000 --- a/trunk/arch/mips/fw/lib/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for generic prom monitor library routines under Linux. -# - -lib-$(CONFIG_64BIT) += call_o32.o diff --git a/trunk/arch/mips/fw/lib/call_o32.S b/trunk/arch/mips/fw/lib/call_o32.S deleted file mode 100644 index bdf7d1d4081a..000000000000 --- a/trunk/arch/mips/fw/lib/call_o32.S +++ /dev/null @@ -1,97 +0,0 @@ -/* - * arch/mips/dec/prom/call_o32.S - * - * O32 interface for the 64 (or N32) ABI. - * - * Copyright (C) 2002 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include -#include - -/* Maximum number of arguments supported. Must be even! */ -#define O32_ARGC 32 -/* Number of static registers we save. */ -#define O32_STATC 11 -/* Frame size for static register */ -#define O32_FRAMESZ (SZREG * O32_STATC) -/* Frame size on new stack */ -#define O32_FRAMESZ_NEW (SZREG + 4 * O32_ARGC) - - .text - -/* - * O32 function call dispatcher, for interfacing 32-bit ROM routines. - * - * The standard 64 (N32) calling sequence is supported, with a0 - * holding a function pointer, a1 a new stack pointer, a2-a7 -- its - * first six arguments and the stack -- remaining ones (up to O32_ARGC, - * including a2-a7). Static registers, gp and fp are preserved, v0 holds - * a result. This code relies on the called o32 function for sp and ra - * restoration and this dispatcher has to be placed in a KSEGx (or KUSEG) - * address space. Any pointers passed have to point to addresses within - * one of these spaces as well. - */ -NESTED(call_o32, O32_FRAMESZ, ra) - REG_SUBU sp,O32_FRAMESZ - - REG_S ra,O32_FRAMESZ-1*SZREG(sp) - REG_S fp,O32_FRAMESZ-2*SZREG(sp) - REG_S gp,O32_FRAMESZ-3*SZREG(sp) - REG_S s7,O32_FRAMESZ-4*SZREG(sp) - REG_S s6,O32_FRAMESZ-5*SZREG(sp) - REG_S s5,O32_FRAMESZ-6*SZREG(sp) - REG_S s4,O32_FRAMESZ-7*SZREG(sp) - REG_S s3,O32_FRAMESZ-8*SZREG(sp) - REG_S s2,O32_FRAMESZ-9*SZREG(sp) - REG_S s1,O32_FRAMESZ-10*SZREG(sp) - REG_S s0,O32_FRAMESZ-11*SZREG(sp) - - move jp,a0 - REG_SUBU s0,a1,O32_FRAMESZ_NEW - REG_S sp,O32_FRAMESZ_NEW-1*SZREG(s0) - - sll a0,a2,zero - sll a1,a3,zero - sll a2,a4,zero - sll a3,a5,zero - sw a6,0x10(s0) - sw a7,0x14(s0) - - PTR_LA t0,O32_FRAMESZ(sp) - PTR_LA t1,0x18(s0) - li t2,O32_ARGC-6 -1: - lw t3,(t0) - REG_ADDU t0,SZREG - sw t3,(t1) - REG_SUBU t2,1 - REG_ADDU t1,4 - bnez t2,1b - - move sp,s0 - - jalr jp - - REG_L sp,O32_FRAMESZ_NEW-1*SZREG(sp) - - REG_L s0,O32_FRAMESZ-11*SZREG(sp) - REG_L s1,O32_FRAMESZ-10*SZREG(sp) - REG_L s2,O32_FRAMESZ-9*SZREG(sp) - REG_L s3,O32_FRAMESZ-8*SZREG(sp) - REG_L s4,O32_FRAMESZ-7*SZREG(sp) - REG_L s5,O32_FRAMESZ-6*SZREG(sp) - REG_L s6,O32_FRAMESZ-5*SZREG(sp) - REG_L s7,O32_FRAMESZ-4*SZREG(sp) - REG_L gp,O32_FRAMESZ-3*SZREG(sp) - REG_L fp,O32_FRAMESZ-2*SZREG(sp) - REG_L ra,O32_FRAMESZ-1*SZREG(sp) - - REG_ADDU sp,O32_FRAMESZ - jr ra -END(call_o32) diff --git a/trunk/arch/mips/fw/sni/Makefile b/trunk/arch/mips/fw/sni/Makefile deleted file mode 100644 index d9740a3788e2..000000000000 --- a/trunk/arch/mips/fw/sni/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for the SNI prom monitor routines under Linux. -# - -lib-$(CONFIG_SNIPROM) += sniprom.o diff --git a/trunk/arch/mips/fw/sni/sniprom.c b/trunk/arch/mips/fw/sni/sniprom.c deleted file mode 100644 index 96ba99202758..000000000000 --- a/trunk/arch/mips/fw/sni/sniprom.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Big Endian PROM code for SNI RM machines - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005-2006 Florian Lohoff (flo@rfc822.org) - * Copyright (C) 2005-2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* special SNI prom calls */ -/* - * This does not exist in all proms - SINIX compares - * the prom env variable "version" against "2.0008" - * or greater. If lesser it tries to probe interesting - * registers - */ -#define PROM_GET_MEMCONF 58 -#define PROM_GET_HWCONF 61 - -#define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000) -#define PROM_ENTRY(x) (PROM_VEC + (x)) - -#define ___prom_putchar ((int *(*)(int))PROM_ENTRY(PROM_PUTCHAR)) -#define ___prom_getenv ((char *(*)(char *))PROM_ENTRY(PROM_GETENV)) -#define ___prom_get_memconf ((void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF)) -#define ___prom_get_hwconf ((u32 (*)(void))PROM_ENTRY(PROM_GET_HWCONF)) - -#ifdef CONFIG_64BIT - -static u8 o32_stk[16384]; -#define O32_STK &o32_stk[sizeof(o32_stk)] - -#define __PROM_O32(fun, arg) fun arg __asm__(#fun); \ - __asm__(#fun " = call_o32") - -int __PROM_O32(__prom_putchar, (int *(*)(int), void *, int)); -char *__PROM_O32(__prom_getenv, (char *(*)(char *), void *, char *)); -void __PROM_O32(__prom_get_memconf, (void (*)(void *), void *, void *)); -u32 __PROM_O32(__prom_get_hwconf, (u32 (*)(void), void *)); - -#define _prom_putchar(x) __prom_putchar(___prom_putchar, O32_STK, x) -#define _prom_getenv(x) __prom_getenv(___prom_getenv, O32_STK, x) -#define _prom_get_memconf(x) __prom_get_memconf(___prom_get_memconf, O32_STK, x) -#define _prom_get_hwconf() __prom_get_hwconf(___prom_get_hwconf, O32_STK) - -#else -#define _prom_putchar(x) ___prom_putchar(x) -#define _prom_getenv(x) ___prom_getenv(x) -#define _prom_get_memconf(x) ___prom_get_memconf(x) -#define _prom_get_hwconf(x) ___prom_get_hwconf(x) -#endif - -void prom_putchar(char c) -{ - _prom_putchar(c); -} - - -char *prom_getenv(char *s) -{ - return _prom_getenv(s); -} - -void *prom_get_hwconf(void) -{ - u32 hwconf = _prom_get_hwconf(); - - if (hwconf == 0xffffffff) - return NULL; - - return (void *)CKSEG1ADDR(hwconf); -} - -void __init prom_free_prom_memory(void) -{ -} - -/* - * /proc/cpuinfo system type - * - */ -char *system_type = "Unknown"; -const char *get_system_type(void) -{ - return system_type; -} - -static void __init sni_mem_init(void) -{ - int i, memsize; - struct membank { - u32 size; - u32 base; - u32 size2; - u32 pad1; - u32 pad2; - } memconf[8]; - int brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE; - - - /* MemSIZE from prom in 16MByte chunks */ - memsize = *((unsigned char *) SNI_IDPROM_MEMSIZE) * 16; - - pr_debug("IDProm memsize: %u MByte\n", memsize); - - /* get memory bank layout from prom */ - _prom_get_memconf(&memconf); - - pr_debug("prom_get_mem_conf memory configuration:\n"); - for (i = 0; i < 8 && memconf[i].size; i++) { - if (brd_type == SNI_BRD_PCI_TOWER || - brd_type == SNI_BRD_PCI_TOWER_CPLUS) { - if (memconf[i].base >= 0x20000000 && - memconf[i].base < 0x30000000) - memconf[i].base -= 0x20000000; - } - pr_debug("Bank%d: %08x @ %08x\n", i, - memconf[i].size, memconf[i].base); - add_memory_region(memconf[i].base, memconf[i].size, - BOOT_MEM_RAM); - } -} - -void __init prom_init(void) -{ - int argc = fw_arg0; - u32 *argv = (u32 *)CKSEG0ADDR(fw_arg1); - int i; - - sni_mem_init(); - - /* copy prom cmdline parameters to kernel cmdline */ - for (i = 1; i < argc; i++) { - strcat(arcs_cmdline, (char *)CKSEG0ADDR(argv[i])); - if (i < (argc - 1)) - strcat(arcs_cmdline, " "); - } -} diff --git a/trunk/arch/mips/gt64120/wrppmc/setup.c b/trunk/arch/mips/gt64120/wrppmc/setup.c index 728ef6a80edd..51f6b7862460 100644 --- a/trunk/arch/mips/gt64120/wrppmc/setup.c +++ b/trunk/arch/mips/gt64120/wrppmc/setup.c @@ -121,6 +121,8 @@ const char *get_system_type(void) */ void __init prom_init(void) { + mips_machtype = MACH_WRPPMC; + add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); add_memory_region(WRPPMC_BOOTROM_BASE, WRPPMC_BOOTROM_SIZE, BOOT_MEM_ROM_DATA); diff --git a/trunk/arch/mips/jazz/setup.c b/trunk/arch/mips/jazz/setup.c index a7947199c99b..a7857973ca03 100644 --- a/trunk/arch/mips/jazz/setup.c +++ b/trunk/arch/mips/jazz/setup.c @@ -200,19 +200,12 @@ static struct platform_device jazz_cmos_pdev = { .resource = jazz_cmos_rsrc }; -static struct platform_device pcspeaker_pdev = { - .name = "pcspkr", - .id = -1, -}; - static int __init jazz_setup_devinit(void) { platform_device_register(&jazz_serial8250_device); platform_device_register(&jazz_esp_pdev); platform_device_register(&jazz_sonic_pdev); platform_device_register(&jazz_cmos_pdev); - platform_device_register(&pcspeaker_pdev); - return 0; } diff --git a/trunk/arch/mips/jmr3927/rbhma3100/init.c b/trunk/arch/mips/jmr3927/rbhma3100/init.c index 700b9cf8eb9d..b643f75ec9a5 100644 --- a/trunk/arch/mips/jmr3927/rbhma3100/init.c +++ b/trunk/arch/mips/jmr3927/rbhma3100/init.c @@ -52,6 +52,10 @@ void __init prom_init(void) puts("Warning: TX3927 TLB off\n"); #endif +#ifdef CONFIG_TOSHIBA_JMR3927 + mips_machtype = MACH_TOSHIBA_JMR3927; +#endif + prom_init_cmdline(); add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/jmr3927/rbhma3100/setup.c b/trunk/arch/mips/jmr3927/rbhma3100/setup.c index c886d804d303..06e01c8f4e3a 100644 --- a/trunk/arch/mips/jmr3927/rbhma3100/setup.c +++ b/trunk/arch/mips/jmr3927/rbhma3100/setup.c @@ -29,17 +29,21 @@ #include #include +#include #include #include +#include #include #include #include #include -#include #ifdef CONFIG_SERIAL_TXX9 +#include +#include #include #endif +#include #include #include #include @@ -234,8 +238,6 @@ static void __init tx3927_setup(void) tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW; /* Disable PCI snoop */ tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP; - /* do reset on watchdog */ - tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR; #ifdef DO_WRITE_THROUGH /* Enable PCI SNOOP - with write through only */ @@ -386,55 +388,3 @@ static int __init jmr3927_rtc_init(void) return IS_ERR(dev) ? PTR_ERR(dev) : 0; } device_initcall(jmr3927_rtc_init); - -/* Watchdog support */ - -static int __init txx9_wdt_init(unsigned long base) -{ - struct resource res = { - .start = base, - .end = base + 0x100 - 1, - .flags = IORESOURCE_MEM, - }; - struct platform_device *dev = - platform_device_register_simple("txx9wdt", -1, &res, 1); - return IS_ERR(dev) ? PTR_ERR(dev) : 0; -} - -static int __init jmr3927_wdt_init(void) -{ - return txx9_wdt_init(TX3927_TMR_REG(2)); -} -device_initcall(jmr3927_wdt_init); - -/* Minimum CLK support */ - -struct clk *clk_get(struct device *dev, const char *id) -{ - if (!strcmp(id, "imbus_clk")) - return (struct clk *)JMR3927_IMCLK; - return ERR_PTR(-ENOENT); -} -EXPORT_SYMBOL(clk_get); - -int clk_enable(struct clk *clk) -{ - return 0; -} -EXPORT_SYMBOL(clk_enable); - -void clk_disable(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_disable); - -unsigned long clk_get_rate(struct clk *clk) -{ - return (unsigned long)clk; -} -EXPORT_SYMBOL(clk_get_rate); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); diff --git a/trunk/arch/mips/kernel/cpu-bugs64.c b/trunk/arch/mips/kernel/cpu-bugs64.c index 417bb3e336ac..af78456d4138 100644 --- a/trunk/arch/mips/kernel/cpu-bugs64.c +++ b/trunk/arch/mips/kernel/cpu-bugs64.c @@ -18,15 +18,6 @@ #include #include -static char bug64hit[] __initdata = - "reliable operation impossible!\n%s"; -static char nowar[] __initdata = - "Please report to ."; -static char r4kwar[] __initdata = - "Enable CPU_R4000_WORKAROUNDS to rectify."; -static char daddiwar[] __initdata = - "Enable CPU_DADDI_WORKAROUNDS to rectify."; - static inline void align_mod(const int align, const int mod) { asm volatile( @@ -164,7 +155,13 @@ static inline void check_mult_sh(void) } printk("no.\n"); - panic(bug64hit, !R4000_WAR ? r4kwar : nowar); + panic("Reliable operation impossible!\n" +#ifndef CONFIG_CPU_R4000 + "Configure for R4000 to enable the workaround." +#else + "Please report to ." +#endif + ); } static volatile int daddi_ov __initdata = 0; @@ -236,11 +233,15 @@ static inline void check_daddi(void) } printk("no.\n"); - panic(bug64hit, !DADDI_WAR ? daddiwar : nowar); + panic("Reliable operation impossible!\n" +#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400) + "Configure for R4000 or R4400 to enable the workaround." +#else + "Please report to ." +#endif + ); } -int daddiu_bug __initdata = -1; - static inline void check_daddiu(void) { long v, w, tmp; @@ -280,9 +281,7 @@ static inline void check_daddiu(void) : "=&r" (v), "=&r" (w), "=&r" (tmp) : "I" (0xffffffffffffdb9aUL), "I" (0x1234)); - daddiu_bug = v != w; - - if (!daddiu_bug) { + if (v == w) { printk("no.\n"); return; } @@ -304,16 +303,18 @@ static inline void check_daddiu(void) } printk("no.\n"); - panic(bug64hit, !DADDI_WAR ? daddiwar : nowar); -} - -void __init check_bugs64_early(void) -{ - check_mult_sh(); - check_daddiu(); + panic("Reliable operation impossible!\n" +#if !defined(CONFIG_CPU_R4000) && !defined(CONFIG_CPU_R4400) + "Configure for R4000 or R4400 to enable the workaround." +#else + "Please report to ." +#endif + ); } void __init check_bugs64(void) { + check_mult_sh(); check_daddi(); + check_daddiu(); } diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c index 5861a432a52f..5c2794391bf5 100644 --- a/trunk/arch/mips/kernel/cpu-probe.c +++ b/trunk/arch/mips/kernel/cpu-probe.c @@ -188,8 +188,6 @@ static inline void check_wait(void) case CPU_AU1500: case CPU_AU1550: case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: if (allow_au1k_wait) cpu_wait = au1k_wait; break; @@ -735,11 +733,6 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) break; case 4: c->cputype = CPU_AU1200; - if (2 == (c->processor_id & 0xff)) - c->cputype = CPU_AU1250; - break; - case 5: - c->cputype = CPU_AU1210; break; default: panic("Unknown Au Core!"); @@ -865,8 +858,6 @@ static __init const char *cpu_to_name(struct cpuinfo_mips *c) case CPU_AU1100: name = "Au1100"; break; case CPU_AU1550: name = "Au1550"; break; case CPU_AU1200: name = "Au1200"; break; - case CPU_AU1210: name = "Au1210"; break; - case CPU_AU1250: name = "Au1250"; break; case CPU_4KEC: name = "MIPS 4KEc"; break; case CPU_4KSC: name = "MIPS 4KSc"; break; case CPU_VR41XX: name = "NEC Vr41xx"; break; diff --git a/trunk/arch/mips/kernel/genex.S b/trunk/arch/mips/kernel/genex.S index c6ada98ee042..e76a76bf0b3d 100644 --- a/trunk/arch/mips/kernel/genex.S +++ b/trunk/arch/mips/kernel/genex.S @@ -6,7 +6,7 @@ * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. - * Copyright (C) 2002, 2007 Maciej W. Rozycki + * Copyright (C) 2002 Maciej W. Rozycki */ #include @@ -471,13 +471,7 @@ NESTED(nmi_handler, PT_SIZE, sp) jr k0 rfe #else -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS LONG_ADDIU k0, 4 /* stall on $k0 */ -#else - .set at=v1 - LONG_ADDIU k0, 4 - .set noat -#endif MTC0 k0, CP0_EPC /* I hope three instructions between MTC0 and ERET are enough... */ ori k1, _THREAD_MASK diff --git a/trunk/arch/mips/kernel/kspd.c b/trunk/arch/mips/kernel/kspd.c index f6704ab16306..d2c2e00e5864 100644 --- a/trunk/arch/mips/kernel/kspd.c +++ b/trunk/arch/mips/kernel/kspd.c @@ -161,7 +161,8 @@ static unsigned int translate_open_flags(int flags) int i; unsigned int ret = 0; - for (i = 0; i < ARRAY_SIZE(open_flags_table); i++) { + for (i = 0; i < (sizeof(open_flags_table) / sizeof(struct apsp_table)); + i++) { if( (flags & open_flags_table[i].sp) ) { ret |= open_flags_table[i].ap; } diff --git a/trunk/arch/mips/kernel/linux32.c b/trunk/arch/mips/kernel/linux32.c index 65af3cc90abb..2b8ec1102e86 100644 --- a/trunk/arch/mips/kernel/linux32.c +++ b/trunk/arch/mips/kernel/linux32.c @@ -174,16 +174,36 @@ struct rlimit32 { int rlim_max; }; -asmlinkage long sys32_truncate64(const char __user * path, - unsigned long __dummy, int a2, int a3) +#ifdef __MIPSEB__ +asmlinkage long sys32_truncate64(const char __user * path, unsigned long __dummy, + int length_hi, int length_lo) +#endif +#ifdef __MIPSEL__ +asmlinkage long sys32_truncate64(const char __user * path, unsigned long __dummy, + int length_lo, int length_hi) +#endif { - return sys_truncate(path, merge_64(a2, a3)); + loff_t length; + + length = ((unsigned long) length_hi << 32) | (unsigned int) length_lo; + + return sys_truncate(path, length); } +#ifdef __MIPSEB__ asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy, - int a2, int a3) + int length_hi, int length_lo) +#endif +#ifdef __MIPSEL__ +asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy, + int length_lo, int length_hi) +#endif { - return sys_ftruncate(fd, merge_64(a2, a3)); + loff_t length; + + length = ((unsigned long) length_hi << 32) | (unsigned int) length_lo; + + return sys_ftruncate(fd, length); } static inline long diff --git a/trunk/arch/mips/kernel/mips-mt.c b/trunk/arch/mips/kernel/mips-mt.c index 640fb0cc6e39..3d6b1ec1f328 100644 --- a/trunk/arch/mips/kernel/mips-mt.c +++ b/trunk/arch/mips/kernel/mips-mt.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/mips/kernel/pcspeaker.c b/trunk/arch/mips/kernel/pcspeaker.c new file mode 100644 index 000000000000..475df6904219 --- /dev/null +++ b/trunk/arch/mips/kernel/pcspeaker.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2006 IBM Corporation + * + * Implements device information for i8253 timer chip + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation + */ + +#include + +static __init int add_pcspkr(void) +{ + struct platform_device *pd; + int ret; + + pd = platform_device_alloc("pcspkr", -1); + if (!pd) + return -ENOMEM; + + ret = platform_device_add(pd); + if (ret) + platform_device_put(pd); + + return ret; +} +device_initcall(add_pcspkr); diff --git a/trunk/arch/mips/kernel/proc.c b/trunk/arch/mips/kernel/proc.c index 36f065398243..6e6e947cce1e 100644 --- a/trunk/arch/mips/kernel/proc.c +++ b/trunk/arch/mips/kernel/proc.c @@ -62,7 +62,6 @@ static int show_cpuinfo(struct seq_file *m, void *v) ); seq_printf(m, "shadow register sets\t: %d\n", cpu_data[n].srsets); - seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", cpu_has_vce ? "%u" : "not available"); @@ -90,7 +89,7 @@ static void c_stop(struct seq_file *m, void *v) { } -const struct seq_operations cpuinfo_op = { +struct seq_operations cpuinfo_op = { .start = c_start, .next = c_next, .stop = c_stop, diff --git a/trunk/arch/mips/kernel/rtlx.c b/trunk/arch/mips/kernel/rtlx.c index 0233798f7155..1ba00c15505b 100644 --- a/trunk/arch/mips/kernel/rtlx.c +++ b/trunk/arch/mips/kernel/rtlx.c @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/mips/kernel/setup.c b/trunk/arch/mips/kernel/setup.c index 269c252d956f..f8a535afce39 100644 --- a/trunk/arch/mips/kernel/setup.c +++ b/trunk/arch/mips/kernel/setup.c @@ -8,7 +8,7 @@ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 Ralf Baechle * Copyright (C) 1996 Stoned Elipot * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki + * Copyright (C) 2000 2001, 2002 Maciej W. Rozycki */ #include #include @@ -24,12 +24,10 @@ #include #include -#include #include #include #include #include -#include #include struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; @@ -563,7 +561,6 @@ void __init setup_arch(char **cmdline_p) } #endif cpu_report(); - check_bugs_early(); #if defined(CONFIG_VT) #if defined(CONFIG_VGA_CONSOLE) @@ -576,7 +573,9 @@ void __init setup_arch(char **cmdline_p) arch_mem_init(cmdline_p); resource_init(); +#ifdef CONFIG_SMP plat_smp_setup(); +#endif } static int __init fpu_disable(char *s) diff --git a/trunk/arch/mips/kernel/smp-mt.c b/trunk/arch/mips/kernel/smp-mt.c index 89e6f6aa5166..94e210cc6cb6 100644 --- a/trunk/arch/mips/kernel/smp-mt.c +++ b/trunk/arch/mips/kernel/smp-mt.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include @@ -31,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -215,67 +215,68 @@ static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0) write_tc_c0_tchalt(TCHALT_H); } -static void vsmp_send_ipi_single(int cpu, unsigned int action) +/* + * Common setup before any secondaries are started + * Make sure all CPU's are in a sensible state before we boot any of the + * secondarys + */ +void __init plat_smp_setup(void) { - int i; - unsigned long flags; - int vpflags; - - local_irq_save(flags); + unsigned int mvpconf0, ntc, tc, ncpu = 0; - vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ +#ifdef CONFIG_MIPS_MT_FPAFF + /* If we have an FPU, enroll ourselves in the FPU-full mask */ + if (cpu_has_fpu) + cpu_set(0, mt_fpu_cpumask); +#endif /* CONFIG_MIPS_MT_FPAFF */ + if (!cpu_has_mipsmt) + return; - switch (action) { - case SMP_CALL_FUNCTION: - i = C_SW1; - break; + /* disable MT so we can configure */ + dvpe(); + dmt(); - case SMP_RESCHEDULE_YOURSELF: - default: - i = C_SW0; - break; - } + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); - /* 1:1 mapping of vpe and tc... */ - settc(cpu); - write_vpe_c0_cause(read_vpe_c0_cause() | i); - evpe(vpflags); + mvpconf0 = read_c0_mvpconf0(); + ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT; - local_irq_restore(flags); -} + /* we'll always have more TC's than VPE's, so loop setting everything + to a sensible state */ + for (tc = 0; tc <= ntc; tc++) { + settc(tc); -static void vsmp_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; + smp_tc_init(tc, mvpconf0); + ncpu = smp_vpe_init(tc, mvpconf0, ncpu); + } - for_each_cpu_mask(i, mask) - vsmp_send_ipi_single(i, action); -} + /* Release config state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); -static void __cpuinit vsmp_init_secondary(void) -{ - /* Enable per-cpu interrupts */ + /* We'll wait until starting the secondaries before starting MVPE */ - /* This is Malta specific: IPI,performance and timer inetrrupts */ - write_c0_status((read_c0_status() & ~ST0_IM ) | - (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7)); + printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu); } -static void __cpuinit vsmp_smp_finish(void) +void __init plat_prepare_cpus(unsigned int max_cpus) { - write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); + mips_mt_set_cpuoptions(); -#ifdef CONFIG_MIPS_MT_FPAFF - /* If we have an FPU, enroll ourselves in the FPU-full mask */ - if (cpu_has_fpu) - cpu_set(smp_processor_id(), mt_fpu_cpumask); -#endif /* CONFIG_MIPS_MT_FPAFF */ + /* set up ipi interrupts */ + if (cpu_has_vint) { + set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); + set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); + } - local_irq_enable(); -} + cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; + cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; -static void vsmp_cpus_done(void) -{ + setup_irq(cpu_ipi_resched_irq, &irq_resched); + setup_irq(cpu_ipi_call_irq, &irq_call); + + set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); + set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); } /* @@ -286,7 +287,7 @@ static void vsmp_cpus_done(void) * (unsigned long)idle->thread_info the gp * assumes a 1:1 mapping of TC => VPE */ -static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) +void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) { struct thread_info *gp = task_thread_info(idle); dvpe(); @@ -320,81 +321,57 @@ static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) evpe(EVPE_ENABLE); } -/* - * Common setup before any secondaries are started - * Make sure all CPU's are in a sensible state before we boot any of the - * secondarys - */ -static void __init vsmp_smp_setup(void) +void __cpuinit prom_init_secondary(void) { - unsigned int mvpconf0, ntc, tc, ncpu = 0; - unsigned int nvpe; + /* Enable per-cpu interrupts */ + + /* This is Malta specific: IPI,performance and timer inetrrupts */ + write_c0_status((read_c0_status() & ~ST0_IM ) | + (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP6 | STATUSF_IP7)); +} + +void __cpuinit prom_smp_finish(void) +{ + write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) - cpu_set(0, mt_fpu_cpumask); + cpu_set(smp_processor_id(), mt_fpu_cpumask); #endif /* CONFIG_MIPS_MT_FPAFF */ - if (!cpu_has_mipsmt) - return; - - /* disable MT so we can configure */ - dvpe(); - dmt(); - - /* Put MVPE's into 'configuration state' */ - set_c0_mvpcontrol(MVPCONTROL_VPC); - - mvpconf0 = read_c0_mvpconf0(); - ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT; - - nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; - smp_num_siblings = nvpe; - /* we'll always have more TC's than VPE's, so loop setting everything - to a sensible state */ - for (tc = 0; tc <= ntc; tc++) { - settc(tc); + local_irq_enable(); +} - smp_tc_init(tc, mvpconf0); - ncpu = smp_vpe_init(tc, mvpconf0, ncpu); - } +void prom_cpus_done(void) +{ +} - /* Release config state */ - clear_c0_mvpcontrol(MVPCONTROL_VPC); +void core_send_ipi(int cpu, unsigned int action) +{ + int i; + unsigned long flags; + int vpflags; - /* We'll wait until starting the secondaries before starting MVPE */ + local_irq_save(flags); - printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu); -} + vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ -static void __init vsmp_prepare_cpus(unsigned int max_cpus) -{ - mips_mt_set_cpuoptions(); + switch (action) { + case SMP_CALL_FUNCTION: + i = C_SW1; + break; - /* set up ipi interrupts */ - if (cpu_has_vint) { - set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); - set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); + case SMP_RESCHEDULE_YOURSELF: + default: + i = C_SW0; + break; } - cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; - cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; - - setup_irq(cpu_ipi_resched_irq, &irq_resched); - setup_irq(cpu_ipi_call_irq, &irq_call); + /* 1:1 mapping of vpe and tc... */ + settc(cpu); + write_vpe_c0_cause(read_vpe_c0_cause() | i); + evpe(vpflags); - set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); - set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); + local_irq_restore(flags); } - -struct plat_smp_ops vsmp_smp_ops = { - .send_ipi_single = vsmp_send_ipi_single, - .send_ipi_mask = vsmp_send_ipi_mask, - .init_secondary = vsmp_init_secondary, - .smp_finish = vsmp_smp_finish, - .cpus_done = vsmp_cpus_done, - .boot_secondary = vsmp_boot_secondary, - .smp_setup = vsmp_smp_setup, - .prepare_cpus = vsmp_prepare_cpus, -}; diff --git a/trunk/arch/mips/kernel/smp.c b/trunk/arch/mips/kernel/smp.c index 1e5dfc28294a..63989e9df4f9 100644 --- a/trunk/arch/mips/kernel/smp.c +++ b/trunk/arch/mips/kernel/smp.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #ifdef CONFIG_MIPS_MT_SMTC @@ -55,44 +56,6 @@ EXPORT_SYMBOL(cpu_online_map); extern void __init calibrate_delay(void); extern void cpu_idle(void); -/* Number of TCs (or siblings in Intel speak) per CPU core */ -int smp_num_siblings = 1; -EXPORT_SYMBOL(smp_num_siblings); - -/* representing the TCs (or siblings in Intel speak) of each logical CPU */ -cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly; -EXPORT_SYMBOL(cpu_sibling_map); - -/* representing cpus for which sibling maps can be computed */ -static cpumask_t cpu_sibling_setup_map; - -static inline void set_cpu_sibling_map(int cpu) -{ - int i; - - cpu_set(cpu, cpu_sibling_setup_map); - - if (smp_num_siblings > 1) { - for_each_cpu_mask(i, cpu_sibling_setup_map) { - if (cpu_data[cpu].core == cpu_data[i].core) { - cpu_set(i, cpu_sibling_map[cpu]); - cpu_set(cpu, cpu_sibling_map[i]); - } - } - } else - cpu_set(cpu, cpu_sibling_map[cpu]); -} - -struct plat_smp_ops *mp_ops; - -__cpuinit void register_smp_ops(struct plat_smp_ops *ops) -{ - if (ops) - printk(KERN_WARNING "Overriding previous set SMP ops\n"); - - mp_ops = ops; -} - /* * First C code run on the secondary CPUs after being started up by * the master. @@ -109,7 +72,7 @@ asmlinkage __cpuinit void start_secondary(void) cpu_report(); per_cpu_trap_init(); mips_clockevent_init(); - mp_ops->init_secondary(); + prom_init_secondary(); /* * XXX parity protection should be folded in here when it's converted @@ -121,8 +84,7 @@ asmlinkage __cpuinit void start_secondary(void) cpu = smp_processor_id(); cpu_data[cpu].udelay_val = loops_per_jiffy; - mp_ops->smp_finish(); - set_cpu_sibling_map(cpu); + prom_smp_finish(); cpu_set(cpu, cpu_callin_map); @@ -193,7 +155,7 @@ int smp_call_function_mask(cpumask_t mask, void (*func) (void *info), smp_mb(); /* Send a message to all other CPUs and wait for them to respond */ - mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); + core_send_ipi_mask(mask, SMP_CALL_FUNCTION); /* Wait for response */ /* FIXME: lock-up detection, backtrace on lock-up */ @@ -287,7 +249,7 @@ void smp_send_stop(void) void __init smp_cpus_done(unsigned int max_cpus) { - mp_ops->cpus_done(); + prom_cpus_done(); } /* called from main before smp_init() */ @@ -295,8 +257,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) { init_new_context(current, &init_mm); current_thread_info()->cpu = 0; - mp_ops->prepare_cpus(max_cpus); - set_cpu_sibling_map(0); + plat_prepare_cpus(max_cpus); #ifndef CONFIG_HOTPLUG_CPU cpu_present_map = cpu_possible_map; #endif @@ -334,7 +295,7 @@ int __cpuinit __cpu_up(unsigned int cpu) if (IS_ERR(idle)) panic(KERN_ERR "Fork failed for CPU %d", cpu); - mp_ops->boot_secondary(cpu, idle); + prom_boot_secondary(cpu, idle); /* * Trust is futile. We should really have timeouts ... diff --git a/trunk/arch/mips/kernel/smtc-proc.c b/trunk/arch/mips/kernel/smtc-proc.c index fe256559c997..6f3709996172 100644 --- a/trunk/arch/mips/kernel/smtc-proc.c +++ b/trunk/arch/mips/kernel/smtc-proc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/mips/kernel/smtc.c b/trunk/arch/mips/kernel/smtc.c index 85f700e58131..9c92d42996cb 100644 --- a/trunk/arch/mips/kernel/smtc.c +++ b/trunk/arch/mips/kernel/smtc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/mips/kernel/time.c b/trunk/arch/mips/kernel/time.c index 9f85d4cecc5b..2995be1ab3ca 100644 --- a/trunk/arch/mips/kernel/time.c +++ b/trunk/arch/mips/kernel/time.c @@ -50,6 +50,8 @@ int update_persistent_clock(struct timespec now) return rtc_mips_set_mmss(now.tv_sec); } +int (*mips_timer_state)(void); + int null_perf_irq(void) { return 0; diff --git a/trunk/arch/mips/kernel/vmlinux.lds.S b/trunk/arch/mips/kernel/vmlinux.lds.S index b5470ceb418b..5fc2398bdb76 100644 --- a/trunk/arch/mips/kernel/vmlinux.lds.S +++ b/trunk/arch/mips/kernel/vmlinux.lds.S @@ -114,11 +114,11 @@ SECTIONS __init_begin = .; .init.text : { _sinittext = .; - INIT_TEXT + *(.init.text) _einittext = .; } .init.data : { - INIT_DATA + *(.init.data) } . = ALIGN(16); .init.setup : { @@ -144,10 +144,10 @@ SECTIONS * references from .rodata */ .exit.text : { - EXIT_TEXT + *(.exit.text) } .exit.data : { - EXIT_DATA + *(.exit.data) } #if defined(CONFIG_BLK_DEV_INITRD) . = ALIGN(_PAGE_SIZE); diff --git a/trunk/arch/mips/kernel/vpe.c b/trunk/arch/mips/kernel/vpe.c index eed2dc4273e0..c06eb812a95e 100644 --- a/trunk/arch/mips/kernel/vpe.c +++ b/trunk/arch/mips/kernel/vpe.c @@ -53,6 +53,7 @@ #include #include #include +#include typedef void *vpe_handle; diff --git a/trunk/arch/mips/lasat/picvue.c b/trunk/arch/mips/lasat/picvue.c index d3d04c392e25..6471d0663fd8 100644 --- a/trunk/arch/mips/lasat/picvue.c +++ b/trunk/arch/mips/lasat/picvue.c @@ -22,6 +22,8 @@ struct pvc_defs *picvue; +DECLARE_MUTEX(pvc_sem); + static void pvc_reg_write(u32 val) { *picvue->reg = val; diff --git a/trunk/arch/mips/lasat/picvue.h b/trunk/arch/mips/lasat/picvue.h index 91df55371127..2a96bf971897 100644 --- a/trunk/arch/mips/lasat/picvue.h +++ b/trunk/arch/mips/lasat/picvue.h @@ -4,6 +4,8 @@ * Brian Murphy * */ +#include + struct pvc_defs { volatile u32 *reg; u32 data_shift; @@ -43,3 +45,4 @@ void pvc_move(u8 cmd); void pvc_clear(void); void pvc_home(void); +extern struct semaphore pvc_sem; diff --git a/trunk/arch/mips/lasat/picvue_proc.c b/trunk/arch/mips/lasat/picvue_proc.c index 0bb6037afba3..9947c1525822 100644 --- a/trunk/arch/mips/lasat/picvue_proc.c +++ b/trunk/arch/mips/lasat/picvue_proc.c @@ -13,11 +13,9 @@ #include #include -#include #include "picvue.h" -static DEFINE_MUTEX(pvc_mutex); static char pvc_lines[PVC_NLINES][PVC_LINELEN+1]; static int pvc_linedata[PVC_NLINES]; static struct proc_dir_entry *pvc_display_dir; @@ -50,9 +48,9 @@ static int pvc_proc_read_line(char *page, char **start, return 0; } - mutex_lock(&pvc_mutex); + down(&pvc_sem); page += sprintf(page, "%s\n", pvc_lines[lineno]); - mutex_unlock(&pvc_mutex); + up(&pvc_sem); return page - origpage; } @@ -75,10 +73,10 @@ static int pvc_proc_write_line(struct file *file, const char *buffer, if (buffer[count-1] == '\n') count--; - mutex_lock(&pvc_mutex); + down(&pvc_sem); strncpy(pvc_lines[lineno], buffer, count); pvc_lines[lineno][count] = '\0'; - mutex_unlock(&pvc_mutex); + up(&pvc_sem); tasklet_schedule(&pvc_display_tasklet); @@ -91,7 +89,7 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer, int origcount = count; int cmd = simple_strtol(buffer, NULL, 10); - mutex_lock(&pvc_mutex); + down(&pvc_sem); if (scroll_interval != 0) del_timer(&timer); @@ -108,7 +106,7 @@ static int pvc_proc_write_scroll(struct file *file, const char *buffer, } add_timer(&timer); } - mutex_unlock(&pvc_mutex); + up(&pvc_sem); return origcount; } @@ -119,9 +117,9 @@ static int pvc_proc_read_scroll(char *page, char **start, { char *origpage = page; - mutex_lock(&pvc_mutex); + down(&pvc_sem); page += sprintf(page, "%d\n", scroll_dir * scroll_interval); - mutex_unlock(&pvc_mutex); + up(&pvc_sem); return page - origpage; } diff --git a/trunk/arch/mips/lemote/lm2e/pci.c b/trunk/arch/mips/lemote/lm2e/pci.c index c1e41f15cc7e..1ade1cef3899 100644 --- a/trunk/arch/mips/lemote/lm2e/pci.c +++ b/trunk/arch/mips/lemote/lm2e/pci.c @@ -81,6 +81,9 @@ static void __init ict_pcimap(void) static int __init pcibios_init(void) { + extern int pci_probe_only; + pci_probe_only = 0; + ict_pcimap(); register_pci_controller(&loongson2e_pci_controller); diff --git a/trunk/arch/mips/lemote/lm2e/prom.c b/trunk/arch/mips/lemote/lm2e/prom.c index 7edc15dfed6c..824336812198 100644 --- a/trunk/arch/mips/lemote/lm2e/prom.c +++ b/trunk/arch/mips/lemote/lm2e/prom.c @@ -57,6 +57,8 @@ void __init prom_init(void) arg = (int *)fw_arg1; env = (int *)fw_arg2; + mips_machtype = MACH_LEMOTE_FULONG; + prom_init_cmdline(); if ((strstr(arcs_cmdline, "console=")) == NULL) diff --git a/trunk/arch/mips/lib/csum_partial.S b/trunk/arch/mips/lib/csum_partial.S index 8d7784122c14..c0a77fe038be 100644 --- a/trunk/arch/mips/lib/csum_partial.S +++ b/trunk/arch/mips/lib/csum_partial.S @@ -7,7 +7,6 @@ * * Copyright (C) 1998, 1999 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki */ #include #include @@ -53,12 +52,9 @@ #define UNIT(unit) ((unit)*NBYTES) #define ADDC(sum,reg) \ - .set push; \ - .set noat; \ ADD sum, reg; \ sltu v1, sum, reg; \ - ADD sum, v1; \ - .set pop + ADD sum, v1 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3) \ LOAD _t0, (offset + UNIT(0))(src); \ @@ -96,13 +92,13 @@ LEAF(csum_partial) move t7, zero sltiu t8, a1, 0x8 - bnez t8, .Lsmall_csumcpy /* < 8 bytes to copy */ + bnez t8, small_csumcpy /* < 8 bytes to copy */ move t2, a1 andi t7, src, 0x1 /* odd buffer? */ -.Lhword_align: - beqz t7, .Lword_align +hword_align: + beqz t7, word_align andi t8, src, 0x2 lbu t0, (src) @@ -114,8 +110,8 @@ LEAF(csum_partial) PTR_ADDU src, src, 0x1 andi t8, src, 0x2 -.Lword_align: - beqz t8, .Ldword_align +word_align: + beqz t8, dword_align sltiu t8, a1, 56 lhu t0, (src) @@ -124,12 +120,12 @@ LEAF(csum_partial) sltiu t8, a1, 56 PTR_ADDU src, src, 0x2 -.Ldword_align: - bnez t8, .Ldo_end_words +dword_align: + bnez t8, do_end_words move t8, a1 andi t8, src, 0x4 - beqz t8, .Lqword_align + beqz t8, qword_align andi t8, src, 0x8 lw t0, 0x00(src) @@ -138,8 +134,8 @@ LEAF(csum_partial) PTR_ADDU src, src, 0x4 andi t8, src, 0x8 -.Lqword_align: - beqz t8, .Loword_align +qword_align: + beqz t8, oword_align andi t8, src, 0x10 #ifdef USE_DOUBLE @@ -156,8 +152,8 @@ LEAF(csum_partial) PTR_ADDU src, src, 0x8 andi t8, src, 0x10 -.Loword_align: - beqz t8, .Lbegin_movement +oword_align: + beqz t8, begin_movement LONG_SRL t8, a1, 0x7 #ifdef USE_DOUBLE @@ -172,55 +168,51 @@ LEAF(csum_partial) PTR_ADDU src, src, 0x10 LONG_SRL t8, a1, 0x7 -.Lbegin_movement: +begin_movement: beqz t8, 1f andi t2, a1, 0x40 -.Lmove_128bytes: +move_128bytes: CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) CSUM_BIGCHUNK(src, 0x40, sum, t0, t1, t3, t4) CSUM_BIGCHUNK(src, 0x60, sum, t0, t1, t3, t4) LONG_SUBU t8, t8, 0x01 - .set reorder /* DADDI_WAR */ - PTR_ADDU src, src, 0x80 - bnez t8, .Lmove_128bytes - .set noreorder + bnez t8, move_128bytes + PTR_ADDU src, src, 0x80 1: beqz t2, 1f andi t2, a1, 0x20 -.Lmove_64bytes: +move_64bytes: CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) CSUM_BIGCHUNK(src, 0x20, sum, t0, t1, t3, t4) PTR_ADDU src, src, 0x40 1: - beqz t2, .Ldo_end_words + beqz t2, do_end_words andi t8, a1, 0x1c -.Lmove_32bytes: +move_32bytes: CSUM_BIGCHUNK(src, 0x00, sum, t0, t1, t3, t4) andi t8, a1, 0x1c PTR_ADDU src, src, 0x20 -.Ldo_end_words: - beqz t8, .Lsmall_csumcpy +do_end_words: + beqz t8, small_csumcpy andi t2, a1, 0x3 LONG_SRL t8, t8, 0x2 -.Lend_words: +end_words: lw t0, (src) LONG_SUBU t8, t8, 0x1 ADDC(sum, t0) - .set reorder /* DADDI_WAR */ - PTR_ADDU src, src, 0x4 - bnez t8, .Lend_words - .set noreorder + bnez t8, end_words + PTR_ADDU src, src, 0x4 /* unknown src alignment and < 8 bytes to go */ -.Lsmall_csumcpy: +small_csumcpy: move a1, t2 andi t0, a1, 4 @@ -254,8 +246,6 @@ LEAF(csum_partial) 1: ADDC(sum, t1) /* fold checksum */ - .set push - .set noat #ifdef USE_DOUBLE dsll32 v1, sum, 0 daddu sum, v1 @@ -276,7 +266,6 @@ LEAF(csum_partial) srl sum, sum, 8 or sum, v1 andi sum, 0xffff - .set pop 1: .set reorder /* Add the passed partial csum. */ @@ -384,11 +373,7 @@ LEAF(csum_partial) #define ADDRMASK (NBYTES-1) -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS .set noat -#else - .set at=v1 -#endif LEAF(__csum_partial_copy_user) PTR_ADDU AT, src, len /* See (1) above. */ @@ -413,101 +398,95 @@ FEXPORT(csum_partial_copy_nocheck) */ sltu t2, len, NBYTES and t1, dst, ADDRMASK - bnez t2, .Lcopy_bytes_checklen + bnez t2, copy_bytes_checklen and t0, src, ADDRMASK andi odd, dst, 0x1 /* odd buffer? */ - bnez t1, .Ldst_unaligned + bnez t1, dst_unaligned nop - bnez t0, .Lsrc_unaligned_dst_aligned + bnez t0, src_unaligned_dst_aligned /* * use delay slot for fall-through * src and dst are aligned; need to compute rem */ -.Lboth_aligned: +both_aligned: SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter - beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES + beqz t0, cleanup_both_aligned # len < 8*NBYTES nop SUB len, 8*NBYTES # subtract here for bgez loop .align 4 1: -EXC( LOAD t0, UNIT(0)(src), .Ll_exc) -EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) -EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) -EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) -EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy) -EXC( LOAD t5, UNIT(5)(src), .Ll_exc_copy) -EXC( LOAD t6, UNIT(6)(src), .Ll_exc_copy) -EXC( LOAD t7, UNIT(7)(src), .Ll_exc_copy) +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) +EXC( LOAD t4, UNIT(4)(src), l_exc_copy) +EXC( LOAD t5, UNIT(5)(src), l_exc_copy) +EXC( LOAD t6, UNIT(6)(src), l_exc_copy) +EXC( LOAD t7, UNIT(7)(src), l_exc_copy) SUB len, len, 8*NBYTES ADD src, src, 8*NBYTES -EXC( STORE t0, UNIT(0)(dst), .Ls_exc) +EXC( STORE t0, UNIT(0)(dst), s_exc) ADDC(sum, t0) -EXC( STORE t1, UNIT(1)(dst), .Ls_exc) +EXC( STORE t1, UNIT(1)(dst), s_exc) ADDC(sum, t1) -EXC( STORE t2, UNIT(2)(dst), .Ls_exc) +EXC( STORE t2, UNIT(2)(dst), s_exc) ADDC(sum, t2) -EXC( STORE t3, UNIT(3)(dst), .Ls_exc) +EXC( STORE t3, UNIT(3)(dst), s_exc) ADDC(sum, t3) -EXC( STORE t4, UNIT(4)(dst), .Ls_exc) +EXC( STORE t4, UNIT(4)(dst), s_exc) ADDC(sum, t4) -EXC( STORE t5, UNIT(5)(dst), .Ls_exc) +EXC( STORE t5, UNIT(5)(dst), s_exc) ADDC(sum, t5) -EXC( STORE t6, UNIT(6)(dst), .Ls_exc) +EXC( STORE t6, UNIT(6)(dst), s_exc) ADDC(sum, t6) -EXC( STORE t7, UNIT(7)(dst), .Ls_exc) +EXC( STORE t7, UNIT(7)(dst), s_exc) ADDC(sum, t7) - .set reorder /* DADDI_WAR */ - ADD dst, dst, 8*NBYTES bgez len, 1b - .set noreorder + ADD dst, dst, 8*NBYTES ADD len, 8*NBYTES # revert len (see above) /* * len == the number of bytes left to copy < 8*NBYTES */ -.Lcleanup_both_aligned: +cleanup_both_aligned: #define rem t7 - beqz len, .Ldone + beqz len, done sltu t0, len, 4*NBYTES - bnez t0, .Lless_than_4units + bnez t0, less_than_4units and rem, len, (NBYTES-1) # rem = len % NBYTES /* * len >= 4*NBYTES */ -EXC( LOAD t0, UNIT(0)(src), .Ll_exc) -EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) -EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) -EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) SUB len, len, 4*NBYTES ADD src, src, 4*NBYTES -EXC( STORE t0, UNIT(0)(dst), .Ls_exc) +EXC( STORE t0, UNIT(0)(dst), s_exc) ADDC(sum, t0) -EXC( STORE t1, UNIT(1)(dst), .Ls_exc) +EXC( STORE t1, UNIT(1)(dst), s_exc) ADDC(sum, t1) -EXC( STORE t2, UNIT(2)(dst), .Ls_exc) +EXC( STORE t2, UNIT(2)(dst), s_exc) ADDC(sum, t2) -EXC( STORE t3, UNIT(3)(dst), .Ls_exc) +EXC( STORE t3, UNIT(3)(dst), s_exc) ADDC(sum, t3) - .set reorder /* DADDI_WAR */ - ADD dst, dst, 4*NBYTES - beqz len, .Ldone - .set noreorder -.Lless_than_4units: + beqz len, done + ADD dst, dst, 4*NBYTES +less_than_4units: /* * rem = len % NBYTES */ - beq rem, len, .Lcopy_bytes + beq rem, len, copy_bytes nop 1: -EXC( LOAD t0, 0(src), .Ll_exc) +EXC( LOAD t0, 0(src), l_exc) ADD src, src, NBYTES SUB len, len, NBYTES -EXC( STORE t0, 0(dst), .Ls_exc) +EXC( STORE t0, 0(dst), s_exc) ADDC(sum, t0) - .set reorder /* DADDI_WAR */ - ADD dst, dst, NBYTES bne rem, len, 1b - .set noreorder + ADD dst, dst, NBYTES /* * src and dst are aligned, need to copy rem bytes (rem < NBYTES) @@ -521,20 +500,20 @@ EXC( STORE t0, 0(dst), .Ls_exc) * more instruction-level parallelism. */ #define bits t2 - beqz len, .Ldone + beqz len, done ADD t1, dst, len # t1 is just past last byte of dst li bits, 8*NBYTES SLL rem, len, 3 # rem = number of bits to keep -EXC( LOAD t0, 0(src), .Ll_exc) +EXC( LOAD t0, 0(src), l_exc) SUB bits, bits, rem # bits = number of bits to discard SHIFT_DISCARD t0, t0, bits -EXC( STREST t0, -1(t1), .Ls_exc) +EXC( STREST t0, -1(t1), s_exc) SHIFT_DISCARD_REVERT t0, t0, bits .set reorder ADDC(sum, t0) - b .Ldone + b done .set noreorder -.Ldst_unaligned: +dst_unaligned: /* * dst is unaligned * t0 = src & ADDRMASK @@ -545,25 +524,25 @@ EXC( STREST t0, -1(t1), .Ls_exc) * Set match = (src and dst have same alignment) */ #define match rem -EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc) +EXC( LDFIRST t3, FIRST(0)(src), l_exc) ADD t2, zero, NBYTES -EXC( LDREST t3, REST(0)(src), .Ll_exc_copy) +EXC( LDREST t3, REST(0)(src), l_exc_copy) SUB t2, t2, t1 # t2 = number of bytes copied xor match, t0, t1 -EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc) +EXC( STFIRST t3, FIRST(0)(dst), s_exc) SLL t4, t1, 3 # t4 = number of bits to discard SHIFT_DISCARD t3, t3, t4 /* no SHIFT_DISCARD_REVERT to handle odd buffer properly */ ADDC(sum, t3) - beq len, t2, .Ldone + beq len, t2, done SUB len, len, t2 ADD dst, dst, t2 - beqz match, .Lboth_aligned + beqz match, both_aligned ADD src, src, t2 -.Lsrc_unaligned_dst_aligned: +src_unaligned_dst_aligned: SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter - beqz t0, .Lcleanup_src_unaligned + beqz t0, cleanup_src_unaligned and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES 1: /* @@ -572,53 +551,49 @@ EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc) * It's OK to load FIRST(N+1) before REST(N) because the two addresses * are to the same unit (unless src is aligned, but it's not). */ -EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) -EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) SUB len, len, 4*NBYTES -EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) -EXC( LDREST t1, REST(1)(src), .Ll_exc_copy) -EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy) -EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy) -EXC( LDREST t2, REST(2)(src), .Ll_exc_copy) -EXC( LDREST t3, REST(3)(src), .Ll_exc_copy) +EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDREST t1, REST(1)(src), l_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) +EXC( LDREST t2, REST(2)(src), l_exc_copy) +EXC( LDREST t3, REST(3)(src), l_exc_copy) ADD src, src, 4*NBYTES #ifdef CONFIG_CPU_SB1 nop # improves slotting #endif -EXC( STORE t0, UNIT(0)(dst), .Ls_exc) +EXC( STORE t0, UNIT(0)(dst), s_exc) ADDC(sum, t0) -EXC( STORE t1, UNIT(1)(dst), .Ls_exc) +EXC( STORE t1, UNIT(1)(dst), s_exc) ADDC(sum, t1) -EXC( STORE t2, UNIT(2)(dst), .Ls_exc) +EXC( STORE t2, UNIT(2)(dst), s_exc) ADDC(sum, t2) -EXC( STORE t3, UNIT(3)(dst), .Ls_exc) +EXC( STORE t3, UNIT(3)(dst), s_exc) ADDC(sum, t3) - .set reorder /* DADDI_WAR */ - ADD dst, dst, 4*NBYTES bne len, rem, 1b - .set noreorder + ADD dst, dst, 4*NBYTES -.Lcleanup_src_unaligned: - beqz len, .Ldone +cleanup_src_unaligned: + beqz len, done and rem, len, NBYTES-1 # rem = len % NBYTES - beq rem, len, .Lcopy_bytes + beq rem, len, copy_bytes nop 1: -EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) -EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDREST t0, REST(0)(src), l_exc_copy) ADD src, src, NBYTES SUB len, len, NBYTES -EXC( STORE t0, 0(dst), .Ls_exc) +EXC( STORE t0, 0(dst), s_exc) ADDC(sum, t0) - .set reorder /* DADDI_WAR */ - ADD dst, dst, NBYTES bne len, rem, 1b - .set noreorder + ADD dst, dst, NBYTES -.Lcopy_bytes_checklen: - beqz len, .Ldone +copy_bytes_checklen: + beqz len, done nop -.Lcopy_bytes: +copy_bytes: /* 0 < len < NBYTES */ #ifdef CONFIG_CPU_LITTLE_ENDIAN #define SHIFT_START 0 @@ -629,14 +604,14 @@ EXC( STORE t0, 0(dst), .Ls_exc) #endif move t2, zero # partial word li t3, SHIFT_START # shift -/* use .Ll_exc_copy here to return correct sum on fault */ +/* use l_exc_copy here to return correct sum on fault */ #define COPY_BYTE(N) \ -EXC( lbu t0, N(src), .Ll_exc_copy); \ +EXC( lbu t0, N(src), l_exc_copy); \ SUB len, len, 1; \ -EXC( sb t0, N(dst), .Ls_exc); \ +EXC( sb t0, N(dst), s_exc); \ SLLV t0, t0, t3; \ addu t3, SHIFT_INC; \ - beqz len, .Lcopy_bytes_done; \ + beqz len, copy_bytes_done; \ or t2, t0 COPY_BYTE(0) @@ -647,17 +622,15 @@ EXC( sb t0, N(dst), .Ls_exc); \ COPY_BYTE(4) COPY_BYTE(5) #endif -EXC( lbu t0, NBYTES-2(src), .Ll_exc_copy) +EXC( lbu t0, NBYTES-2(src), l_exc_copy) SUB len, len, 1 -EXC( sb t0, NBYTES-2(dst), .Ls_exc) +EXC( sb t0, NBYTES-2(dst), s_exc) SLLV t0, t0, t3 or t2, t0 -.Lcopy_bytes_done: +copy_bytes_done: ADDC(sum, t2) -.Ldone: +done: /* fold checksum */ - .set push - .set noat #ifdef USE_DOUBLE dsll32 v1, sum, 0 daddu sum, v1 @@ -678,14 +651,13 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc) srl sum, sum, 8 or sum, v1 andi sum, 0xffff - .set pop 1: .set reorder ADDC(sum, psum) jr ra .set noreorder -.Ll_exc_copy: +l_exc_copy: /* * Copy bytes from src until faulting load address (or until a * lb faults) @@ -700,17 +672,15 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc) li t2, SHIFT_START LOAD t0, THREAD_BUADDR(t0) 1: -EXC( lbu t1, 0(src), .Ll_exc) +EXC( lbu t1, 0(src), l_exc) ADD src, src, 1 sb t1, 0(dst) # can't fault -- we're copy_from_user SLLV t1, t1, t2 addu t2, SHIFT_INC ADDC(sum, t1) - .set reorder /* DADDI_WAR */ - ADD dst, dst, 1 bne src, t0, 1b - .set noreorder -.Ll_exc: + ADD dst, dst, 1 +l_exc: LOAD t0, TI_TASK($28) nop LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address @@ -727,30 +697,19 @@ EXC( lbu t1, 0(src), .Ll_exc) * Clear len bytes starting at dst. Can't call __bzero because it * might modify len. An inefficient loop for these rare times... */ - .set reorder /* DADDI_WAR */ - SUB src, len, 1 - beqz len, .Ldone - .set noreorder + beqz len, done + SUB src, len, 1 1: sb zero, 0(dst) ADD dst, dst, 1 - .set push - .set noat -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS bnez src, 1b SUB src, src, 1 -#else - li v1, 1 - bnez src, 1b - SUB src, src, v1 -#endif li v1, -EFAULT - b .Ldone + b done sw v1, (errptr) -.Ls_exc: +s_exc: li v0, -1 /* invalid checksum */ li v1, -EFAULT jr ra sw v1, (errptr) - .set pop END(__csum_partial_copy_user) diff --git a/trunk/arch/mips/lib/memcpy-inatomic.S b/trunk/arch/mips/lib/memcpy-inatomic.S index 736d0fb56a94..3a534b2baa0f 100644 --- a/trunk/arch/mips/lib/memcpy-inatomic.S +++ b/trunk/arch/mips/lib/memcpy-inatomic.S @@ -9,7 +9,6 @@ * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. * Copyright (C) 2002 Broadcom, Inc. * memcpy/copy_user author: Mark Vandevoorde - * Copyright (C) 2007 Maciej W. Rozycki * * Mnemonic names for arguments to memcpy/__copy_user */ @@ -176,11 +175,7 @@ .text .set noreorder -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS .set noat -#else - .set at=v1 -#endif /* * A combined memcpy/__copy_user @@ -209,36 +204,36 @@ LEAF(__copy_user_inatomic) and t1, dst, ADDRMASK PREF( 0, 1*32(src) ) PREF( 1, 1*32(dst) ) - bnez t2, .Lcopy_bytes_checklen + bnez t2, copy_bytes_checklen and t0, src, ADDRMASK PREF( 0, 2*32(src) ) PREF( 1, 2*32(dst) ) - bnez t1, .Ldst_unaligned + bnez t1, dst_unaligned nop - bnez t0, .Lsrc_unaligned_dst_aligned + bnez t0, src_unaligned_dst_aligned /* * use delay slot for fall-through * src and dst are aligned; need to compute rem */ -.Lboth_aligned: - SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter - beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES - and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) +both_aligned: + SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter + beqz t0, cleanup_both_aligned # len < 8*NBYTES + and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) PREF( 0, 3*32(src) ) PREF( 1, 3*32(dst) ) .align 4 1: -EXC( LOAD t0, UNIT(0)(src), .Ll_exc) -EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) -EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) -EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) SUB len, len, 8*NBYTES -EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy) -EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy) +EXC( LOAD t4, UNIT(4)(src), l_exc_copy) +EXC( LOAD t7, UNIT(5)(src), l_exc_copy) STORE t0, UNIT(0)(dst) STORE t1, UNIT(1)(dst) -EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy) -EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy) +EXC( LOAD t0, UNIT(6)(src), l_exc_copy) +EXC( LOAD t1, UNIT(7)(src), l_exc_copy) ADD src, src, 8*NBYTES ADD dst, dst, 8*NBYTES STORE t2, UNIT(-6)(dst) @@ -255,43 +250,39 @@ EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy) /* * len == rem == the number of bytes left to copy < 8*NBYTES */ -.Lcleanup_both_aligned: - beqz len, .Ldone +cleanup_both_aligned: + beqz len, done sltu t0, len, 4*NBYTES - bnez t0, .Lless_than_4units + bnez t0, less_than_4units and rem, len, (NBYTES-1) # rem = len % NBYTES /* * len >= 4*NBYTES */ -EXC( LOAD t0, UNIT(0)(src), .Ll_exc) -EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) -EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) -EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) SUB len, len, 4*NBYTES ADD src, src, 4*NBYTES STORE t0, UNIT(0)(dst) STORE t1, UNIT(1)(dst) STORE t2, UNIT(2)(dst) STORE t3, UNIT(3)(dst) - .set reorder /* DADDI_WAR */ - ADD dst, dst, 4*NBYTES - beqz len, .Ldone - .set noreorder -.Lless_than_4units: + beqz len, done + ADD dst, dst, 4*NBYTES +less_than_4units: /* * rem = len % NBYTES */ - beq rem, len, .Lcopy_bytes + beq rem, len, copy_bytes nop 1: -EXC( LOAD t0, 0(src), .Ll_exc) +EXC( LOAD t0, 0(src), l_exc) ADD src, src, NBYTES SUB len, len, NBYTES STORE t0, 0(dst) - .set reorder /* DADDI_WAR */ - ADD dst, dst, NBYTES bne rem, len, 1b - .set noreorder + ADD dst, dst, NBYTES /* * src and dst are aligned, need to copy rem bytes (rem < NBYTES) @@ -305,17 +296,17 @@ EXC( LOAD t0, 0(src), .Ll_exc) * more instruction-level parallelism. */ #define bits t2 - beqz len, .Ldone + beqz len, done ADD t1, dst, len # t1 is just past last byte of dst li bits, 8*NBYTES SLL rem, len, 3 # rem = number of bits to keep -EXC( LOAD t0, 0(src), .Ll_exc) +EXC( LOAD t0, 0(src), l_exc) SUB bits, bits, rem # bits = number of bits to discard SHIFT_DISCARD t0, t0, bits STREST t0, -1(t1) jr ra move len, zero -.Ldst_unaligned: +dst_unaligned: /* * dst is unaligned * t0 = src & ADDRMASK @@ -326,22 +317,22 @@ EXC( LOAD t0, 0(src), .Ll_exc) * Set match = (src and dst have same alignment) */ #define match rem -EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc) +EXC( LDFIRST t3, FIRST(0)(src), l_exc) ADD t2, zero, NBYTES -EXC( LDREST t3, REST(0)(src), .Ll_exc_copy) +EXC( LDREST t3, REST(0)(src), l_exc_copy) SUB t2, t2, t1 # t2 = number of bytes copied xor match, t0, t1 STFIRST t3, FIRST(0)(dst) - beq len, t2, .Ldone + beq len, t2, done SUB len, len, t2 ADD dst, dst, t2 - beqz match, .Lboth_aligned + beqz match, both_aligned ADD src, src, t2 -.Lsrc_unaligned_dst_aligned: +src_unaligned_dst_aligned: SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter PREF( 0, 3*32(src) ) - beqz t0, .Lcleanup_src_unaligned + beqz t0, cleanup_src_unaligned and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES PREF( 1, 3*32(dst) ) 1: @@ -351,15 +342,15 @@ EXC( LDREST t3, REST(0)(src), .Ll_exc_copy) * It's OK to load FIRST(N+1) before REST(N) because the two addresses * are to the same unit (unless src is aligned, but it's not). */ -EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) -EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) SUB len, len, 4*NBYTES -EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) -EXC( LDREST t1, REST(1)(src), .Ll_exc_copy) -EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy) -EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy) -EXC( LDREST t2, REST(2)(src), .Ll_exc_copy) -EXC( LDREST t3, REST(3)(src), .Ll_exc_copy) +EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDREST t1, REST(1)(src), l_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) +EXC( LDREST t2, REST(2)(src), l_exc_copy) +EXC( LDREST t3, REST(3)(src), l_exc_copy) PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed) ADD src, src, 4*NBYTES #ifdef CONFIG_CPU_SB1 @@ -370,36 +361,32 @@ EXC( LDREST t3, REST(3)(src), .Ll_exc_copy) STORE t2, UNIT(2)(dst) STORE t3, UNIT(3)(dst) PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed) - .set reorder /* DADDI_WAR */ - ADD dst, dst, 4*NBYTES bne len, rem, 1b - .set noreorder + ADD dst, dst, 4*NBYTES -.Lcleanup_src_unaligned: - beqz len, .Ldone +cleanup_src_unaligned: + beqz len, done and rem, len, NBYTES-1 # rem = len % NBYTES - beq rem, len, .Lcopy_bytes + beq rem, len, copy_bytes nop 1: -EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) -EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDREST t0, REST(0)(src), l_exc_copy) ADD src, src, NBYTES SUB len, len, NBYTES STORE t0, 0(dst) - .set reorder /* DADDI_WAR */ - ADD dst, dst, NBYTES bne len, rem, 1b - .set noreorder + ADD dst, dst, NBYTES -.Lcopy_bytes_checklen: - beqz len, .Ldone +copy_bytes_checklen: + beqz len, done nop -.Lcopy_bytes: +copy_bytes: /* 0 < len < NBYTES */ #define COPY_BYTE(N) \ -EXC( lb t0, N(src), .Ll_exc); \ +EXC( lb t0, N(src), l_exc); \ SUB len, len, 1; \ - beqz len, .Ldone; \ + beqz len, done; \ sb t0, N(dst) COPY_BYTE(0) @@ -410,16 +397,16 @@ EXC( lb t0, N(src), .Ll_exc); \ COPY_BYTE(4) COPY_BYTE(5) #endif -EXC( lb t0, NBYTES-2(src), .Ll_exc) +EXC( lb t0, NBYTES-2(src), l_exc) SUB len, len, 1 jr ra sb t0, NBYTES-2(dst) -.Ldone: +done: jr ra nop END(__copy_user_inatomic) -.Ll_exc_copy: +l_exc_copy: /* * Copy bytes from src until faulting load address (or until a * lb faults) @@ -434,14 +421,12 @@ EXC( lb t0, NBYTES-2(src), .Ll_exc) nop LOAD t0, THREAD_BUADDR(t0) 1: -EXC( lb t1, 0(src), .Ll_exc) +EXC( lb t1, 0(src), l_exc) ADD src, src, 1 sb t1, 0(dst) # can't fault -- we're copy_from_user - .set reorder /* DADDI_WAR */ - ADD dst, dst, 1 bne src, t0, 1b - .set noreorder -.Ll_exc: + ADD dst, dst, 1 +l_exc: LOAD t0, TI_TASK($28) nop LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address diff --git a/trunk/arch/mips/lib/memcpy.S b/trunk/arch/mips/lib/memcpy.S index c06cccf60bec..a526c62cb76a 100644 --- a/trunk/arch/mips/lib/memcpy.S +++ b/trunk/arch/mips/lib/memcpy.S @@ -9,7 +9,6 @@ * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. * Copyright (C) 2002 Broadcom, Inc. * memcpy/copy_user author: Mark Vandevoorde - * Copyright (C) 2007 Maciej W. Rozycki * * Mnemonic names for arguments to memcpy/__copy_user */ @@ -176,11 +175,7 @@ .text .set noreorder -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS .set noat -#else - .set at=v1 -#endif /* * A combined memcpy/__copy_user @@ -191,7 +186,7 @@ .align 5 LEAF(memcpy) /* a0=dst a1=src a2=len */ move v0, dst /* return value */ -.L__memcpy: +__memcpy: FEXPORT(__copy_user) /* * Note: dst & src may be unaligned, len may be 0 @@ -199,7 +194,6 @@ FEXPORT(__copy_user) */ #define rem t8 - R10KCBARRIER(0(ra)) /* * The "issue break"s below are very approximate. * Issue delays for dcache fills will perturb the schedule, as will @@ -213,45 +207,44 @@ FEXPORT(__copy_user) and t1, dst, ADDRMASK PREF( 0, 1*32(src) ) PREF( 1, 1*32(dst) ) - bnez t2, .Lcopy_bytes_checklen + bnez t2, copy_bytes_checklen and t0, src, ADDRMASK PREF( 0, 2*32(src) ) PREF( 1, 2*32(dst) ) - bnez t1, .Ldst_unaligned + bnez t1, dst_unaligned nop - bnez t0, .Lsrc_unaligned_dst_aligned + bnez t0, src_unaligned_dst_aligned /* * use delay slot for fall-through * src and dst are aligned; need to compute rem */ -.Lboth_aligned: +both_aligned: SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter - beqz t0, .Lcleanup_both_aligned # len < 8*NBYTES + beqz t0, cleanup_both_aligned # len < 8*NBYTES and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES) PREF( 0, 3*32(src) ) PREF( 1, 3*32(dst) ) .align 4 1: - R10KCBARRIER(0(ra)) -EXC( LOAD t0, UNIT(0)(src), .Ll_exc) -EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) -EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) -EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) SUB len, len, 8*NBYTES -EXC( LOAD t4, UNIT(4)(src), .Ll_exc_copy) -EXC( LOAD t7, UNIT(5)(src), .Ll_exc_copy) -EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p8u) -EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p7u) -EXC( LOAD t0, UNIT(6)(src), .Ll_exc_copy) -EXC( LOAD t1, UNIT(7)(src), .Ll_exc_copy) +EXC( LOAD t4, UNIT(4)(src), l_exc_copy) +EXC( LOAD t7, UNIT(5)(src), l_exc_copy) +EXC( STORE t0, UNIT(0)(dst), s_exc_p8u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p7u) +EXC( LOAD t0, UNIT(6)(src), l_exc_copy) +EXC( LOAD t1, UNIT(7)(src), l_exc_copy) ADD src, src, 8*NBYTES ADD dst, dst, 8*NBYTES -EXC( STORE t2, UNIT(-6)(dst), .Ls_exc_p6u) -EXC( STORE t3, UNIT(-5)(dst), .Ls_exc_p5u) -EXC( STORE t4, UNIT(-4)(dst), .Ls_exc_p4u) -EXC( STORE t7, UNIT(-3)(dst), .Ls_exc_p3u) -EXC( STORE t0, UNIT(-2)(dst), .Ls_exc_p2u) -EXC( STORE t1, UNIT(-1)(dst), .Ls_exc_p1u) +EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) +EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) +EXC( STORE t4, UNIT(-4)(dst), s_exc_p4u) +EXC( STORE t7, UNIT(-3)(dst), s_exc_p3u) +EXC( STORE t0, UNIT(-2)(dst), s_exc_p2u) +EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u) PREF( 0, 8*32(src) ) PREF( 1, 8*32(dst) ) bne len, rem, 1b @@ -260,45 +253,39 @@ EXC( STORE t1, UNIT(-1)(dst), .Ls_exc_p1u) /* * len == rem == the number of bytes left to copy < 8*NBYTES */ -.Lcleanup_both_aligned: - beqz len, .Ldone +cleanup_both_aligned: + beqz len, done sltu t0, len, 4*NBYTES - bnez t0, .Lless_than_4units + bnez t0, less_than_4units and rem, len, (NBYTES-1) # rem = len % NBYTES /* * len >= 4*NBYTES */ -EXC( LOAD t0, UNIT(0)(src), .Ll_exc) -EXC( LOAD t1, UNIT(1)(src), .Ll_exc_copy) -EXC( LOAD t2, UNIT(2)(src), .Ll_exc_copy) -EXC( LOAD t3, UNIT(3)(src), .Ll_exc_copy) +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) SUB len, len, 4*NBYTES ADD src, src, 4*NBYTES - R10KCBARRIER(0(ra)) -EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p4u) -EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p3u) -EXC( STORE t2, UNIT(2)(dst), .Ls_exc_p2u) -EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u) - .set reorder /* DADDI_WAR */ - ADD dst, dst, 4*NBYTES - beqz len, .Ldone - .set noreorder -.Lless_than_4units: +EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) + beqz len, done + ADD dst, dst, 4*NBYTES +less_than_4units: /* * rem = len % NBYTES */ - beq rem, len, .Lcopy_bytes + beq rem, len, copy_bytes nop 1: - R10KCBARRIER(0(ra)) -EXC( LOAD t0, 0(src), .Ll_exc) +EXC( LOAD t0, 0(src), l_exc) ADD src, src, NBYTES SUB len, len, NBYTES -EXC( STORE t0, 0(dst), .Ls_exc_p1u) - .set reorder /* DADDI_WAR */ - ADD dst, dst, NBYTES +EXC( STORE t0, 0(dst), s_exc_p1u) bne rem, len, 1b - .set noreorder + ADD dst, dst, NBYTES /* * src and dst are aligned, need to copy rem bytes (rem < NBYTES) @@ -312,17 +299,17 @@ EXC( STORE t0, 0(dst), .Ls_exc_p1u) * more instruction-level parallelism. */ #define bits t2 - beqz len, .Ldone + beqz len, done ADD t1, dst, len # t1 is just past last byte of dst li bits, 8*NBYTES SLL rem, len, 3 # rem = number of bits to keep -EXC( LOAD t0, 0(src), .Ll_exc) +EXC( LOAD t0, 0(src), l_exc) SUB bits, bits, rem # bits = number of bits to discard SHIFT_DISCARD t0, t0, bits -EXC( STREST t0, -1(t1), .Ls_exc) +EXC( STREST t0, -1(t1), s_exc) jr ra move len, zero -.Ldst_unaligned: +dst_unaligned: /* * dst is unaligned * t0 = src & ADDRMASK @@ -333,23 +320,22 @@ EXC( STREST t0, -1(t1), .Ls_exc) * Set match = (src and dst have same alignment) */ #define match rem -EXC( LDFIRST t3, FIRST(0)(src), .Ll_exc) +EXC( LDFIRST t3, FIRST(0)(src), l_exc) ADD t2, zero, NBYTES -EXC( LDREST t3, REST(0)(src), .Ll_exc_copy) +EXC( LDREST t3, REST(0)(src), l_exc_copy) SUB t2, t2, t1 # t2 = number of bytes copied xor match, t0, t1 - R10KCBARRIER(0(ra)) -EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc) - beq len, t2, .Ldone +EXC( STFIRST t3, FIRST(0)(dst), s_exc) + beq len, t2, done SUB len, len, t2 ADD dst, dst, t2 - beqz match, .Lboth_aligned + beqz match, both_aligned ADD src, src, t2 -.Lsrc_unaligned_dst_aligned: +src_unaligned_dst_aligned: SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter PREF( 0, 3*32(src) ) - beqz t0, .Lcleanup_src_unaligned + beqz t0, cleanup_src_unaligned and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES PREF( 1, 3*32(dst) ) 1: @@ -359,59 +345,52 @@ EXC( STFIRST t3, FIRST(0)(dst), .Ls_exc) * It's OK to load FIRST(N+1) before REST(N) because the two addresses * are to the same unit (unless src is aligned, but it's not). */ - R10KCBARRIER(0(ra)) -EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) -EXC( LDFIRST t1, FIRST(1)(src), .Ll_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) SUB len, len, 4*NBYTES -EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) -EXC( LDREST t1, REST(1)(src), .Ll_exc_copy) -EXC( LDFIRST t2, FIRST(2)(src), .Ll_exc_copy) -EXC( LDFIRST t3, FIRST(3)(src), .Ll_exc_copy) -EXC( LDREST t2, REST(2)(src), .Ll_exc_copy) -EXC( LDREST t3, REST(3)(src), .Ll_exc_copy) +EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDREST t1, REST(1)(src), l_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) +EXC( LDREST t2, REST(2)(src), l_exc_copy) +EXC( LDREST t3, REST(3)(src), l_exc_copy) PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed) ADD src, src, 4*NBYTES #ifdef CONFIG_CPU_SB1 nop # improves slotting #endif -EXC( STORE t0, UNIT(0)(dst), .Ls_exc_p4u) -EXC( STORE t1, UNIT(1)(dst), .Ls_exc_p3u) -EXC( STORE t2, UNIT(2)(dst), .Ls_exc_p2u) -EXC( STORE t3, UNIT(3)(dst), .Ls_exc_p1u) +EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed) - .set reorder /* DADDI_WAR */ - ADD dst, dst, 4*NBYTES bne len, rem, 1b - .set noreorder + ADD dst, dst, 4*NBYTES -.Lcleanup_src_unaligned: - beqz len, .Ldone +cleanup_src_unaligned: + beqz len, done and rem, len, NBYTES-1 # rem = len % NBYTES - beq rem, len, .Lcopy_bytes + beq rem, len, copy_bytes nop 1: - R10KCBARRIER(0(ra)) -EXC( LDFIRST t0, FIRST(0)(src), .Ll_exc) -EXC( LDREST t0, REST(0)(src), .Ll_exc_copy) +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDREST t0, REST(0)(src), l_exc_copy) ADD src, src, NBYTES SUB len, len, NBYTES -EXC( STORE t0, 0(dst), .Ls_exc_p1u) - .set reorder /* DADDI_WAR */ - ADD dst, dst, NBYTES +EXC( STORE t0, 0(dst), s_exc_p1u) bne len, rem, 1b - .set noreorder + ADD dst, dst, NBYTES -.Lcopy_bytes_checklen: - beqz len, .Ldone +copy_bytes_checklen: + beqz len, done nop -.Lcopy_bytes: +copy_bytes: /* 0 < len < NBYTES */ - R10KCBARRIER(0(ra)) #define COPY_BYTE(N) \ -EXC( lb t0, N(src), .Ll_exc); \ +EXC( lb t0, N(src), l_exc); \ SUB len, len, 1; \ - beqz len, .Ldone; \ -EXC( sb t0, N(dst), .Ls_exc_p1) + beqz len, done; \ +EXC( sb t0, N(dst), s_exc_p1) COPY_BYTE(0) COPY_BYTE(1) @@ -421,16 +400,16 @@ EXC( sb t0, N(dst), .Ls_exc_p1) COPY_BYTE(4) COPY_BYTE(5) #endif -EXC( lb t0, NBYTES-2(src), .Ll_exc) +EXC( lb t0, NBYTES-2(src), l_exc) SUB len, len, 1 jr ra -EXC( sb t0, NBYTES-2(dst), .Ls_exc_p1) -.Ldone: +EXC( sb t0, NBYTES-2(dst), s_exc_p1) +done: jr ra nop END(memcpy) -.Ll_exc_copy: +l_exc_copy: /* * Copy bytes from src until faulting load address (or until a * lb faults) @@ -445,14 +424,12 @@ EXC( sb t0, NBYTES-2(dst), .Ls_exc_p1) nop LOAD t0, THREAD_BUADDR(t0) 1: -EXC( lb t1, 0(src), .Ll_exc) +EXC( lb t1, 0(src), l_exc) ADD src, src, 1 sb t1, 0(dst) # can't fault -- we're copy_from_user - .set reorder /* DADDI_WAR */ - ADD dst, dst, 1 bne src, t0, 1b - .set noreorder -.Ll_exc: + ADD dst, dst, 1 +l_exc: LOAD t0, TI_TASK($28) nop LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address @@ -469,33 +446,20 @@ EXC( lb t1, 0(src), .Ll_exc) * Clear len bytes starting at dst. Can't call __bzero because it * might modify len. An inefficient loop for these rare times... */ - .set reorder /* DADDI_WAR */ - SUB src, len, 1 - beqz len, .Ldone - .set noreorder + beqz len, done + SUB src, len, 1 1: sb zero, 0(dst) ADD dst, dst, 1 -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS bnez src, 1b SUB src, src, 1 -#else - .set push - .set noat - li v1, 1 - bnez src, 1b - SUB src, src, v1 - .set pop -#endif jr ra nop -#define SEXC(n) \ - .set reorder; /* DADDI_WAR */ \ -.Ls_exc_p ## n ## u: \ - ADD len, len, n*NBYTES; \ - jr ra; \ - .set noreorder +#define SEXC(n) \ +s_exc_p ## n ## u: \ + jr ra; \ + ADD len, len, n*NBYTES SEXC(8) SEXC(7) @@ -506,12 +470,10 @@ SEXC(3) SEXC(2) SEXC(1) -.Ls_exc_p1: - .set reorder /* DADDI_WAR */ - ADD len, len, 1 +s_exc_p1: jr ra - .set noreorder -.Ls_exc: + ADD len, len, 1 +s_exc: jr ra nop @@ -522,44 +484,38 @@ LEAF(memmove) sltu t0, a1, t0 # dst + len <= src -> memcpy sltu t1, a0, t1 # dst >= src + len -> memcpy and t0, t1 - beqz t0, .L__memcpy + beqz t0, __memcpy move v0, a0 /* return value */ - beqz a2, .Lr_out + beqz a2, r_out END(memmove) /* fall through to __rmemcpy */ LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ sltu t0, a1, a0 - beqz t0, .Lr_end_bytes_up # src >= dst + beqz t0, r_end_bytes_up # src >= dst nop ADD a0, a2 # dst = dst + len ADD a1, a2 # src = src + len -.Lr_end_bytes: - R10KCBARRIER(0(ra)) +r_end_bytes: lb t0, -1(a1) SUB a2, a2, 0x1 sb t0, -1(a0) SUB a1, a1, 0x1 - .set reorder /* DADDI_WAR */ - SUB a0, a0, 0x1 - bnez a2, .Lr_end_bytes - .set noreorder + bnez a2, r_end_bytes + SUB a0, a0, 0x1 -.Lr_out: +r_out: jr ra move a2, zero -.Lr_end_bytes_up: - R10KCBARRIER(0(ra)) +r_end_bytes_up: lb t0, (a1) SUB a2, a2, 0x1 sb t0, (a0) ADD a1, a1, 0x1 - .set reorder /* DADDI_WAR */ - ADD a0, a0, 0x1 - bnez a2, .Lr_end_bytes_up - .set noreorder + bnez a2, r_end_bytes_up + ADD a0, a0, 0x1 jr ra move a2, zero diff --git a/trunk/arch/mips/lib/memset.S b/trunk/arch/mips/lib/memset.S index 77dc3b20110a..3f8b8b3d0b23 100644 --- a/trunk/arch/mips/lib/memset.S +++ b/trunk/arch/mips/lib/memset.S @@ -5,7 +5,6 @@ * * Copyright (C) 1998, 1999, 2000 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki */ #include #include @@ -72,45 +71,34 @@ LEAF(memset) FEXPORT(__bzero) sltiu t0, a2, LONGSIZE /* very small region? */ - bnez t0, .Lsmall_memset + bnez t0, small_memset andi t0, a0, LONGMASK /* aligned? */ -#ifndef CONFIG_CPU_DADDI_WORKAROUNDS beqz t0, 1f PTR_SUBU t0, LONGSIZE /* alignment in bytes */ -#else - .set noat - li AT, LONGSIZE - beqz t0, 1f - PTR_SUBU t0, AT /* alignment in bytes */ - .set at -#endif - R10KCBARRIER(0(ra)) #ifdef __MIPSEB__ - EX(LONG_S_L, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */ + EX(LONG_S_L, a1, (a0), first_fixup) /* make word/dword aligned */ #endif #ifdef __MIPSEL__ - EX(LONG_S_R, a1, (a0), .Lfirst_fixup) /* make word/dword aligned */ + EX(LONG_S_R, a1, (a0), first_fixup) /* make word/dword aligned */ #endif PTR_SUBU a0, t0 /* long align ptr */ PTR_ADDU a2, t0 /* correct size */ 1: ori t1, a2, 0x3f /* # of full blocks */ xori t1, 0x3f - beqz t1, .Lmemset_partial /* no block to fill */ + beqz t1, memset_partial /* no block to fill */ andi t0, a2, 0x40-LONGSIZE PTR_ADDU t1, a0 /* end address */ .set reorder 1: PTR_ADDIU a0, 64 - R10KCBARRIER(0(ra)) - f_fill64 a0, -64, a1, .Lfwd_fixup + f_fill64 a0, -64, a1, fwd_fixup bne t1, a0, 1b .set noreorder -.Lmemset_partial: - R10KCBARRIER(0(ra)) +memset_partial: PTR_LA t1, 2f /* where to start */ #if LONGSIZE == 4 PTR_SUBU t1, t0 @@ -118,7 +106,7 @@ FEXPORT(__bzero) .set noat LONG_SRL AT, t0, 1 PTR_SUBU t1, AT - .set at + .set noat #endif jr t1 PTR_ADDU a0, t0 /* dest ptr */ @@ -126,28 +114,26 @@ FEXPORT(__bzero) .set push .set noreorder .set nomacro - f_fill64 a0, -64, a1, .Lpartial_fixup /* ... but first do longs ... */ + f_fill64 a0, -64, a1, partial_fixup /* ... but first do longs ... */ 2: .set pop andi a2, LONGMASK /* At most one long to go */ beqz a2, 1f PTR_ADDU a0, a2 /* What's left */ - R10KCBARRIER(0(ra)) #ifdef __MIPSEB__ - EX(LONG_S_R, a1, -1(a0), .Llast_fixup) + EX(LONG_S_R, a1, -1(a0), last_fixup) #endif #ifdef __MIPSEL__ - EX(LONG_S_L, a1, -1(a0), .Llast_fixup) + EX(LONG_S_L, a1, -1(a0), last_fixup) #endif 1: jr ra move a2, zero -.Lsmall_memset: +small_memset: beqz a2, 2f PTR_ADDU t1, a0, a2 1: PTR_ADDIU a0, 1 /* fill bytewise */ - R10KCBARRIER(0(ra)) bne t1, a0, 1b sb a1, -1(a0) @@ -155,11 +141,11 @@ FEXPORT(__bzero) move a2, zero END(memset) -.Lfirst_fixup: +first_fixup: jr ra nop -.Lfwd_fixup: +fwd_fixup: PTR_L t0, TI_TASK($28) LONG_L t0, THREAD_BUADDR(t0) andi a2, 0x3f @@ -167,7 +153,7 @@ FEXPORT(__bzero) jr ra LONG_SUBU a2, t0 -.Lpartial_fixup: +partial_fixup: PTR_L t0, TI_TASK($28) LONG_L t0, THREAD_BUADDR(t0) andi a2, LONGMASK @@ -175,6 +161,6 @@ FEXPORT(__bzero) jr ra LONG_SUBU a2, t0 -.Llast_fixup: +last_fixup: jr ra andi v1, a2, LONGMASK diff --git a/trunk/arch/mips/lib/strlen_user.S b/trunk/arch/mips/lib/strlen_user.S index fdbb970f670d..eca558d83a37 100644 --- a/trunk/arch/mips/lib/strlen_user.S +++ b/trunk/arch/mips/lib/strlen_user.S @@ -24,16 +24,16 @@ LEAF(__strlen_user_asm) LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a0 - bnez v0, .Lfault + bnez v0, fault FEXPORT(__strlen_user_nocheck_asm) move v0, a0 -1: EX(lb, t0, (v0), .Lfault) +1: EX(lb, t0, (v0), fault) PTR_ADDIU v0, 1 bnez t0, 1b PTR_SUBU v0, a0 jr ra END(__strlen_user_asm) -.Lfault: move v0, zero +fault: move v0, zero jr ra diff --git a/trunk/arch/mips/lib/strncpy_user.S b/trunk/arch/mips/lib/strncpy_user.S index 7201b2ff08c8..d16c76fbfac7 100644 --- a/trunk/arch/mips/lib/strncpy_user.S +++ b/trunk/arch/mips/lib/strncpy_user.S @@ -30,30 +30,29 @@ LEAF(__strncpy_from_user_asm) LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a1 - bnez v0, .Lfault + bnez v0, fault FEXPORT(__strncpy_from_user_nocheck_asm) move v0, zero move v1, a1 .set noreorder -1: EX(lbu, t0, (v1), .Lfault) +1: EX(lbu, t0, (v1), fault) PTR_ADDIU v1, 1 - R10KCBARRIER(0(ra)) beqz t0, 2f sb t0, (a0) PTR_ADDIU v0, 1 - .set reorder - PTR_ADDIU a0, 1 bne v0, a2, 1b + PTR_ADDIU a0, 1 + .set reorder 2: PTR_ADDU t0, a1, v0 xor t0, a1 - bltz t0, .Lfault + bltz t0, fault jr ra # return n END(__strncpy_from_user_asm) -.Lfault: li v0, -EFAULT +fault: li v0, -EFAULT jr ra .section __ex_table,"a" - PTR 1b, .Lfault + PTR 1b, fault .previous diff --git a/trunk/arch/mips/lib/strnlen_user.S b/trunk/arch/mips/lib/strnlen_user.S index c768e3000616..c0ea15194a0e 100644 --- a/trunk/arch/mips/lib/strnlen_user.S +++ b/trunk/arch/mips/lib/strnlen_user.S @@ -28,19 +28,18 @@ LEAF(__strnlen_user_asm) LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok? and v0, a0 - bnez v0, .Lfault + bnez v0, fault FEXPORT(__strnlen_user_nocheck_asm) move v0, a0 PTR_ADDU a1, a0 # stop pointer 1: beq v0, a1, 1f # limit reached? - EX(lb, t0, (v0), .Lfault) + EX(lb, t0, (v0), fault) PTR_ADDU v0, 1 bnez t0, 1b 1: PTR_SUBU v0, a0 jr ra END(__strnlen_user_asm) -.Lfault: - move v0, zero +fault: move v0, zero jr ra diff --git a/trunk/arch/mips/lib/uncached.c b/trunk/arch/mips/lib/uncached.c index 27b012d4341c..58d14f4d9349 100644 --- a/trunk/arch/mips/lib/uncached.c +++ b/trunk/arch/mips/lib/uncached.c @@ -46,9 +46,9 @@ unsigned long __init run_uncached(void *func) if (sp >= (long)CKSEG0 && sp < (long)CKSEG2) usp = CKSEG1ADDR(sp); #ifdef CONFIG_64BIT - else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0, 0) && - (long long)sp < (long long)PHYS_TO_XKPHYS(8, 0)) - usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED, + else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) && + (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0)) + usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED, XKPHYS_TO_PHYS((long long)sp)); #endif else { @@ -58,9 +58,9 @@ unsigned long __init run_uncached(void *func) if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2) ufunc = CKSEG1ADDR(lfunc); #ifdef CONFIG_64BIT - else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0, 0) && - (long long)lfunc < (long long)PHYS_TO_XKPHYS(8, 0)) - ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED, + else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0LL, 0) && + (long long)lfunc < (long long)PHYS_TO_XKPHYS(8LL, 0)) + ufunc = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED, XKPHYS_TO_PHYS((long long)lfunc)); #endif else { diff --git a/trunk/arch/mips/mips-boards/atlas/atlas_setup.c b/trunk/arch/mips/mips-boards/atlas/atlas_setup.c index 5c500802271e..e405d112a067 100644 --- a/trunk/arch/mips/mips-boards/atlas/atlas_setup.c +++ b/trunk/arch/mips/mips-boards/atlas/atlas_setup.c @@ -34,6 +34,12 @@ #include #include +extern void mips_reboot_setup(void); + +#ifdef CONFIG_KGDB +extern void kgdb_config(void); +#endif + static void __init serial_init(void); const char *get_system_type(void) diff --git a/trunk/arch/mips/mips-boards/generic/init.c b/trunk/arch/mips/mips-boards/generic/init.c index 1695dca5506b..30f1f54cb68b 100644 --- a/trunk/arch/mips/mips-boards/generic/init.c +++ b/trunk/arch/mips/mips-boards/generic/init.c @@ -250,8 +250,6 @@ void __init mips_ejtag_setup(void) flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); } -extern struct plat_smp_ops msmtc_smp_ops; - void __init prom_init(void) { prom_argc = fw_arg0; @@ -418,10 +416,4 @@ void __init prom_init(void) #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif -#ifdef CONFIG_MIPS_MT_SMP - register_smp_ops(&vsmp_smp_ops); -#endif -#ifdef CONFIG_MIPS_MT_SMTC - register_smp_ops(&msmtc_smp_ops); -#endif } diff --git a/trunk/arch/mips/mips-boards/malta/malta_int.c b/trunk/arch/mips/mips-boards/malta/malta_int.c index dbe60eb55e29..f010261b75d8 100644 --- a/trunk/arch/mips/mips-boards/malta/malta_int.c +++ b/trunk/arch/mips/mips-boards/malta/malta_int.c @@ -26,13 +26,13 @@ #include #include #include -#include #include #include #include #include #include +#include #include #include #include @@ -47,7 +47,7 @@ static DEFINE_SPINLOCK(mips_irq_lock); static inline int mips_pcibios_iack(void) { int irq; - u32 dummy; + u32 dummy; /* * Determine highest priority pending interrupt by performing @@ -58,7 +58,7 @@ static inline int mips_pcibios_iack(void) case MIPS_REVISION_SCON_ROCIT: case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: - MSC_READ(MSC01_PCI_IACK, irq); + MSC_READ(MSC01_PCI_IACK, irq); irq &= 0xff; break; case MIPS_REVISION_SCON_GT64120: @@ -83,7 +83,7 @@ static inline int mips_pcibios_iack(void) BONITO_PCIMAP_CFG = 0; break; default: - printk(KERN_WARNING "Unknown system controller.\n"); + printk("Unknown system controller.\n"); return -1; } return irq; @@ -114,8 +114,7 @@ static void malta_hw0_irqdispatch(void) irq = get_int(); if (irq < 0) { - /* interrupt has already been cleared */ - return; + return; /* interrupt has already been cleared */ } do_IRQ(MALTA_INT_BASE + irq); @@ -124,15 +123,15 @@ static void malta_hw0_irqdispatch(void) static void corehi_irqdispatch(void) { unsigned int intedge, intsteer, pcicmd, pcibadaddr; - unsigned int pcimstat, intisr, inten, intpol; + unsigned int pcimstat, intisr, inten, intpol; unsigned int intrcause, datalo, datahi; struct pt_regs *regs = get_irq_regs(); - printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); - printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" - "Cause : %08lx\nbadVaddr : %08lx\n", - regs->cp0_epc, regs->cp0_status, - regs->cp0_cause, regs->cp0_badvaddr); + printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); + printk("epc : %08lx\nStatus: %08lx\n" + "Cause : %08lx\nbadVaddr : %08lx\n", + regs->cp0_epc, regs->cp0_status, + regs->cp0_cause, regs->cp0_badvaddr); /* Read all the registers and then print them as there is a problem with interspersed printk's upsetting the Bonito controller. @@ -140,41 +139,41 @@ static void corehi_irqdispatch(void) */ switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: - ll_msc_irq(); - break; - case MIPS_REVISION_SCON_GT64120: - intrcause = GT_READ(GT_INTRCAUSE_OFS); - datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); - datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); - printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); - printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", - datahi, datalo); - break; - case MIPS_REVISION_SCON_BONITO: - pcibadaddr = BONITO_PCIBADADDR; - pcimstat = BONITO_PCIMSTAT; - intisr = BONITO_INTISR; - inten = BONITO_INTEN; - intpol = BONITO_INTPOL; - intedge = BONITO_INTEDGE; - intsteer = BONITO_INTSTEER; - pcicmd = BONITO_PCICMD; - printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); - printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); - printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); - printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); - printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); - printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); - printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); - printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); - break; - } - - die("CoreHi interrupt", regs); + ll_msc_irq(); + break; + case MIPS_REVISION_SCON_GT64120: + intrcause = GT_READ(GT_INTRCAUSE_OFS); + datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); + datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); + printk("GT_INTRCAUSE = %08x\n", intrcause); + printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo); + break; + case MIPS_REVISION_SCON_BONITO: + pcibadaddr = BONITO_PCIBADADDR; + pcimstat = BONITO_PCIMSTAT; + intisr = BONITO_INTISR; + inten = BONITO_INTEN; + intpol = BONITO_INTPOL; + intedge = BONITO_INTEDGE; + intsteer = BONITO_INTSTEER; + pcicmd = BONITO_PCICMD; + printk("BONITO_INTISR = %08x\n", intisr); + printk("BONITO_INTEN = %08x\n", inten); + printk("BONITO_INTPOL = %08x\n", intpol); + printk("BONITO_INTEDGE = %08x\n", intedge); + printk("BONITO_INTSTEER = %08x\n", intsteer); + printk("BONITO_PCICMD = %08x\n", pcicmd); + printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr); + printk("BONITO_PCIMSTAT = %08x\n", pcimstat); + break; + } + + /* We die here*/ + die("CoreHi interrupt", regs); } static inline int clz(unsigned long x) @@ -215,9 +214,9 @@ static inline unsigned int irq_ffs(unsigned int pending) t0 = pending & 0x8000; t0 = t0 < 1; - /* t0 = t0 << 2; */ + //t0 = t0 << 2; a0 = a0 - t0; - /* pending = pending << t0; */ + //pending = pending << t0; return a0; #endif @@ -300,29 +299,21 @@ void __init arch_init_irq(void) if (!cpu_has_veic) mips_cpu_irq_init(); - switch (mips_revision_sconid) { - case MIPS_REVISION_SCON_SOCIT: - case MIPS_REVISION_SCON_ROCIT: + switch(mips_revision_sconid) { + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: if (cpu_has_veic) - init_msc_irqs(MIPS_MSC01_IC_REG_BASE, - MSC01E_INT_BASE, msc_eicirqmap, - msc_nr_eicirqs); + init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else - init_msc_irqs(MIPS_MSC01_IC_REG_BASE, - MSC01C_INT_BASE, msc_irqmap, - msc_nr_irqs); + init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); break; - case MIPS_REVISION_SCON_SOCITSC: - case MIPS_REVISION_SCON_SOCITSCP: + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: if (cpu_has_veic) - init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, - MSC01E_INT_BASE, msc_eicirqmap, - msc_nr_eicirqs); + init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else - init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, - MSC01C_INT_BASE, msc_irqmap, - msc_nr_irqs); + init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); } if (cpu_has_veic) { @@ -330,7 +321,8 @@ void __init arch_init_irq(void) set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); - } else if (cpu_has_vint) { + } + else if (cpu_has_vint) { set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); #ifdef CONFIG_MIPS_MT_SMTC @@ -352,12 +344,11 @@ void __init arch_init_irq(void) } #else /* Not SMTC */ setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, - &corehi_irqaction); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); #endif /* CONFIG_MIPS_MT_SMTC */ - } else { + } + else { setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); - setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, - &corehi_irqaction); + setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); } } diff --git a/trunk/arch/mips/mips-boards/malta/malta_setup.c b/trunk/arch/mips/mips-boards/malta/malta_setup.c index 2cd8f5734b36..bc43a5c2224d 100644 --- a/trunk/arch/mips/mips-boards/malta/malta_setup.c +++ b/trunk/arch/mips/mips-boards/malta/malta_setup.c @@ -1,7 +1,6 @@ /* * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) Dmitri Vorobiev * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as @@ -16,57 +15,39 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. */ -#include #include #include #include -#include #include #include -#include +#include #include +#include #include #include #include #include #include +#include #include #ifdef CONFIG_VT #include #endif +extern void mips_reboot_setup(void); +extern unsigned long mips_rtc_get_time(void); + +#ifdef CONFIG_KGDB +extern void kgdb_config(void); +#endif + struct resource standard_io_resources[] = { - { - .name = "dma1", - .start = 0x00, - .end = 0x1f, - .flags = IORESOURCE_BUSY - }, - { - .name = "timer", - .start = 0x40, - .end = 0x5f, - .flags = IORESOURCE_BUSY - }, - { - .name = "keyboard", - .start = 0x60, - .end = 0x6f, - .flags = IORESOURCE_BUSY - }, - { - .name = "dma page reg", - .start = 0x80, - .end = 0x8f, - .flags = IORESOURCE_BUSY - }, - { - .name = "dma2", - .start = 0xc0, - .end = 0xdf, - .flags = IORESOURCE_BUSY - }, + { .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY }, + { .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY }, + { .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY }, + { .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY }, + { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY }, }; const char *get_system_type(void) @@ -81,7 +62,7 @@ const char display_string[] = " LINUX ON MALTA "; #endif /* CONFIG_MIPS_MT_SMTC */ #ifdef CONFIG_BLK_DEV_FD -static void __init fd_activate(void) +void __init fd_activate(void) { /* * Activate Floppy Controller in the SMSC FDC37M817 Super I/O @@ -102,85 +83,6 @@ static void __init fd_activate(void) } #endif -#ifdef CONFIG_BLK_DEV_IDE -static void __init pci_clock_check(void) -{ - unsigned int __iomem *jmpr_p = - (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); - int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; - static const int pciclocks[] __initdata = { - 33, 20, 25, 30, 12, 16, 37, 10 - }; - int pciclock = pciclocks[jmpr]; - char *argptr = prom_getcmdline(); - - if (pciclock != 33 && !strstr(argptr, "idebus=")) { - printk(KERN_WARNING "WARNING: PCI clock is %dMHz, " - "setting idebus\n", pciclock); - argptr += strlen(argptr); - sprintf(argptr, " idebus=%d", pciclock); - if (pciclock < 20 || pciclock > 66) - printk(KERN_WARNING "WARNING: IDE timing " - "calculations will be incorrect\n"); - } -} -#endif - -#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) -static void __init screen_info_setup(void) -{ - screen_info = (struct screen_info) { - .orig_x = 0, - .orig_y = 25, - .ext_mem_k = 0, - .orig_video_page = 0, - .orig_video_mode = 0, - .orig_video_cols = 80, - .unused2 = 0, - .orig_video_ega_bx = 0, - .unused3 = 0, - .orig_video_lines = 25, - .orig_video_isVGA = VIDEO_TYPE_VGAC, - .orig_video_points = 16 - }; -} -#endif - -static void __init bonito_quirks_setup(void) -{ - char *argptr; - - argptr = prom_getcmdline(); - if (strstr(argptr, "debug")) { - BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; - printk(KERN_INFO "Enabled Bonito debug mode\n"); - } else - BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; - -#ifdef CONFIG_DMA_COHERENT - if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { - BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; - printk(KERN_INFO "Enabled Bonito CPU coherency\n"); - - argptr = prom_getcmdline(); - if (strstr(argptr, "iobcuncached")) { - BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & - ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Disabled Bonito IOBC coherency\n"); - } else { - BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; - BONITO_PCIMEMBASECFG |= - (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | - BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); - printk(KERN_INFO "Enabled Bonito IOBC coherency\n"); - } - } else - panic("Hardware DMA cache coherency not supported"); -#endif -} - void __init plat_mem_setup(void) { unsigned int i; @@ -200,24 +102,86 @@ void __init plat_mem_setup(void) kgdb_config(); #endif + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + char *argptr; + + argptr = prom_getcmdline(); + if (strstr(argptr, "debug")) { + BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; + printk("Enabled Bonito debug mode\n"); + } + else + BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; + +#ifdef CONFIG_DMA_COHERENT + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + printk("Enabled Bonito CPU coherency\n"); + + argptr = prom_getcmdline(); + if (strstr(argptr, "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + printk("Disabled Bonito IOBC coherency\n"); + } + else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + printk("Enabled Bonito IOBC coherency\n"); + } + } + else + panic("Hardware DMA cache coherency not supported"); + +#endif + } #ifdef CONFIG_DMA_COHERENT - if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) + else { panic("Hardware DMA cache coherency not supported"); + } #endif - if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) - bonito_quirks_setup(); - #ifdef CONFIG_BLK_DEV_IDE - pci_clock_check(); + /* Check PCI clock */ + { + unsigned int __iomem *jmpr_p = (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); + int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; + static const int pciclocks[] __initdata = { + 33, 20, 25, 30, 12, 16, 37, 10 + }; + int pciclock = pciclocks[jmpr]; + char *argptr = prom_getcmdline(); + + if (pciclock != 33 && !strstr (argptr, "idebus=")) { + printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock); + argptr += strlen(argptr); + sprintf(argptr, " idebus=%d", pciclock); + if (pciclock < 20 || pciclock > 66) + printk("WARNING: IDE timing calculations will be incorrect\n"); + } + } #endif - #ifdef CONFIG_BLK_DEV_FD fd_activate(); #endif - -#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) - screen_info_setup(); +#ifdef CONFIG_VT +#if defined(CONFIG_VGA_CONSOLE) + screen_info = (struct screen_info) { + 0, 25, /* orig-x, orig-y */ + 0, /* unused */ + 0, /* orig-video-page */ + 0, /* orig-video-mode */ + 80, /* orig-video-cols */ + 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ + 25, /* orig-video-lines */ + VIDEO_TYPE_VGAC, /* orig-video-isVGA */ + 16 /* orig-video-points */ + }; +#endif #endif mips_reboot_setup(); } diff --git a/trunk/arch/mips/mips-boards/malta/malta_smtc.c b/trunk/arch/mips/mips-boards/malta/malta_smtc.c index 5ea705e49454..5c980f4a48fe 100644 --- a/trunk/arch/mips/mips-boards/malta/malta_smtc.c +++ b/trunk/arch/mips/mips-boards/malta/malta_smtc.c @@ -15,26 +15,28 @@ * Cause the specified action to be performed on a targeted "CPU" */ -static void msmtc_send_ipi_single(int cpu, unsigned int action) +void core_send_ipi(int cpu, unsigned int action) { /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ smtc_send_ipi(cpu, LINUX_SMP_IPI, action); } -static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; +/* + * Platform "CPU" startup hook + */ - for_each_cpu_mask(i, mask) - msmtc_send_ipi_single(i, action); +void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) +{ + smtc_boot_secondary(cpu, idle); } /* * Post-config but pre-boot cleanup entry point */ -static void __cpuinit msmtc_init_secondary(void) + +void __cpuinit prom_init_secondary(void) { - void smtc_init_secondary(void); + void smtc_init_secondary(void); int myvpe; /* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */ @@ -48,61 +50,45 @@ static void __cpuinit msmtc_init_secondary(void) set_c0_status(0x100 << cp0_perfcount_irq); } - smtc_init_secondary(); + smtc_init_secondary(); } /* - * Platform "CPU" startup hook + * Platform SMP pre-initialization + * + * As noted above, we can assume a single CPU for now + * but it may be multithreaded. */ -static void __cpuinit msmtc_boot_secondary(int cpu, struct task_struct *idle) + +void __cpuinit plat_smp_setup(void) { - smtc_boot_secondary(cpu, idle); + if (read_c0_config3() & (1<<2)) + mipsmt_build_cpu_map(0); } -/* - * SMP initialization finalization entry point - */ -static void __cpuinit msmtc_smp_finish(void) +void __init plat_prepare_cpus(unsigned int max_cpus) { - smtc_smp_finish(); + if (read_c0_config3() & (1<<2)) + mipsmt_prepare_cpus(); } /* - * Hook for after all CPUs are online + * SMP initialization finalization entry point */ -static void msmtc_cpus_done(void) +void __cpuinit prom_smp_finish(void) { + smtc_smp_finish(); } /* - * Platform SMP pre-initialization - * - * As noted above, we can assume a single CPU for now - * but it may be multithreaded. + * Hook for after all CPUs are online */ -static void __init msmtc_smp_setup(void) +void prom_cpus_done(void) { - mipsmt_build_cpu_map(0); } -static void __init msmtc_prepare_cpus(unsigned int max_cpus) -{ - mipsmt_prepare_cpus(); -} - -struct plat_smp_ops msmtc_smp_ops = { - .send_ipi_single = msmtc_send_ipi_single, - .send_ipi_mask = msmtc_send_ipi_mask, - .init_secondary = msmtc_init_secondary, - .smp_finish = msmtc_smp_finish, - .cpus_done = msmtc_cpus_done, - .boot_secondary = msmtc_boot_secondary, - .smp_setup = msmtc_smp_setup, - .prepare_cpus = msmtc_prepare_cpus, -}; - #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF /* * IRQ affinity hook diff --git a/trunk/arch/mips/mips-boards/sead/sead_setup.c b/trunk/arch/mips/mips-boards/sead/sead_setup.c index 8aa8e5b7b074..1fb61b852304 100644 --- a/trunk/arch/mips/mips-boards/sead/sead_setup.c +++ b/trunk/arch/mips/mips-boards/sead/sead_setup.c @@ -34,6 +34,8 @@ #include #include +extern void mips_reboot_setup(void); + static void __init serial_init(void); const char *get_system_type(void) diff --git a/trunk/arch/mips/mipssim/Makefile b/trunk/arch/mips/mipssim/Makefile index 57f43c1c7882..75568b584df4 100644 --- a/trunk/arch/mips/mipssim/Makefile +++ b/trunk/arch/mips/mipssim/Makefile @@ -21,6 +21,6 @@ obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o \ sim_cmdline.o obj-$(CONFIG_EARLY_PRINTK) += sim_console.o -obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o +obj-$(CONFIG_SMP) += sim_smp.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/mipssim/sim_setup.c b/trunk/arch/mips/mipssim/sim_setup.c index d49fe73426b7..452c129d02c1 100644 --- a/trunk/arch/mips/mipssim/sim_setup.c +++ b/trunk/arch/mips/mipssim/sim_setup.c @@ -60,8 +60,6 @@ void __init plat_mem_setup(void) #endif } -extern struct plat_smp_ops ssmtc_smp_ops; - void __init prom_init(void) { set_io_port_base(0xbfd00000); @@ -69,21 +67,9 @@ void __init prom_init(void) pr_info("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); - -#ifdef CONFIG_MIPS_MT_SMP - if (cpu_has_mipsmt) - register_smp_ops(&vsmp_smp_ops); - else - register_smp_ops(&up_smp_ops); -#endif -#ifdef CONFIG_MIPS_MT_SMTC - if (cpu_has_mipsmt) - register_smp_ops(&ssmtc_smp_ops); - else - register_smp_ops(&up_smp_ops); -#endif } + static void __init serial_init(void) { #ifdef CONFIG_SERIAL_8250 diff --git a/trunk/arch/mips/mipssim/sim_smtc.c b/trunk/arch/mips/mipssim/sim_smp.c similarity index 64% rename from trunk/arch/mips/mipssim/sim_smtc.c rename to trunk/arch/mips/mipssim/sim_smp.c index d6e4f656ad14..ccbbccac23ef 100644 --- a/trunk/arch/mips/mipssim/sim_smtc.c +++ b/trunk/arch/mips/mipssim/sim_smp.c @@ -16,7 +16,7 @@ * */ /* - * Simulator Platform-specific hooks for SMTC operation + * Simulator Platform-specific hooks for SMP operation */ #include #include @@ -29,72 +29,65 @@ #include #include #include +#ifdef CONFIG_MIPS_MT_SMTC #include +#endif /* CONFIG_MIPS_MT_SMTC */ /* VPE/SMP Prototype implements platform interfaces directly */ +#if !defined(CONFIG_MIPS_MT_SMP) /* * Cause the specified action to be performed on a targeted "CPU" */ -static void ssmtc_send_ipi_single(int cpu, unsigned int action) +void core_send_ipi(int cpu, unsigned int action) { +#ifdef CONFIG_MIPS_MT_SMTC smtc_send_ipi(cpu, LINUX_SMP_IPI, action); - /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ -} - -static inline void ssmtc_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; +#endif /* CONFIG_MIPS_MT_SMTC */ +/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ - for_each_cpu_mask(i, mask) - ssmtc_send_ipi_single(i, action); } /* - * Post-config but pre-boot cleanup entry point + * Platform "CPU" startup hook */ -static void __cpuinit ssmtc_init_secondary(void) -{ - void smtc_init_secondary(void); - smtc_init_secondary(); -} - -/* - * SMP initialization finalization entry point - */ -static void __cpuinit ssmtc_smp_finish(void) +void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) { - smtc_smp_finish(); +#ifdef CONFIG_MIPS_MT_SMTC + smtc_boot_secondary(cpu, idle); +#endif /* CONFIG_MIPS_MT_SMTC */ } /* - * Hook for after all CPUs are online + * Post-config but pre-boot cleanup entry point */ -static void ssmtc_cpus_done(void) -{ -} -/* - * Platform "CPU" startup hook - */ -static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle) +void __cpuinit prom_init_secondary(void) { - smtc_boot_secondary(cpu, idle); +#ifdef CONFIG_MIPS_MT_SMTC + void smtc_init_secondary(void); + + smtc_init_secondary(); +#endif /* CONFIG_MIPS_MT_SMTC */ } -static void __init ssmtc_smp_setup(void) +void plat_smp_setup(void) { +#ifdef CONFIG_MIPS_MT_SMTC if (read_c0_config3() & (1 << 2)) mipsmt_build_cpu_map(0); +#endif /* CONFIG_MIPS_MT_SMTC */ } /* * Platform SMP pre-initialization */ -static void ssmtc_prepare_cpus(unsigned int max_cpus) + +void plat_prepare_cpus(unsigned int max_cpus) { +#ifdef CONFIG_MIPS_MT_SMTC /* * As noted above, we can assume a single CPU for now * but it may be multithreaded. @@ -103,15 +96,28 @@ static void ssmtc_prepare_cpus(unsigned int max_cpus) if (read_c0_config3() & (1 << 2)) { mipsmt_prepare_cpus(); } +#endif /* CONFIG_MIPS_MT_SMTC */ } -struct plat_smp_ops ssmtc_smp_ops = { - .send_ipi_single = ssmtc_send_ipi_single, - .send_ipi_mask = ssmtc_send_ipi_mask, - .init_secondary = ssmtc_init_secondary, - .smp_finish = ssmtc_smp_finish, - .cpus_done = ssmtc_cpus_done, - .boot_secondary = ssmtc_boot_secondary, - .smp_setup = ssmtc_smp_setup, - .prepare_cpus = ssmtc_prepare_cpus, -}; +/* + * SMP initialization finalization entry point + */ + +void __cpuinit prom_smp_finish(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + smtc_smp_finish(); +#endif /* CONFIG_MIPS_MT_SMTC */ +} + +/* + * Hook for after all CPUs are online + */ + +void prom_cpus_done(void) +{ +#ifdef CONFIG_MIPS_MT_SMTC + +#endif /* CONFIG_MIPS_MT_SMTC */ +} +#endif /* CONFIG_MIPS32R2_MT_SMP */ diff --git a/trunk/arch/mips/mm/c-r4k.c b/trunk/arch/mips/mm/c-r4k.c index 02bd180f0e02..9355f1c9325f 100644 --- a/trunk/arch/mips/mm/c-r4k.c +++ b/trunk/arch/mips/mm/c-r4k.c @@ -449,7 +449,7 @@ static inline void local_r4k_flush_cache_page(void *args) * If the page isn't marked valid, the page cannot possibly be * in the cache. */ - if (!(pte_present(*ptep))) + if (!(pte_val(*ptep) & _PAGE_PRESENT)) return; if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) @@ -468,6 +468,8 @@ static inline void local_r4k_flush_cache_page(void *args) if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { r4k_blast_dcache_page(addr); + if (exec && !cpu_icache_snoops_remote_store) + r4k_blast_scache_page(addr); } if (exec) { if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { @@ -531,6 +533,13 @@ static inline void local_r4k_flush_icache_range(void *args) R4600_HIT_CACHEOP_WAR_IMPL; protected_blast_dcache_range(start, end); } + + if (!cpu_icache_snoops_remote_store && scache_size) { + if (end - start > scache_size) + r4k_blast_scache(); + else + protected_blast_scache_range(start, end); + } } if (end - start > icache_size) @@ -589,7 +598,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) if (size >= scache_size) r4k_blast_scache(); else - blast_inv_scache_range(addr, addr + size); + blast_scache_range(addr, addr + size); return; } @@ -597,7 +606,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) r4k_blast_dcache(); } else { R4600_HIT_CACHEOP_WAR_IMPL; - blast_inv_dcache_range(addr, addr + size); + blast_dcache_range(addr, addr + size); } bc_inv(addr, size); @@ -980,8 +989,6 @@ static void __init probe_pcache(void) case CPU_AU1100: case CPU_AU1550: case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } diff --git a/trunk/arch/mips/mm/dma-default.c b/trunk/arch/mips/mm/dma-default.c index ae39dd88b9aa..810535dd091b 100644 --- a/trunk/arch/mips/mm/dma-default.c +++ b/trunk/arch/mips/mm/dma-default.c @@ -383,7 +383,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size, BUG_ON(direction == DMA_NONE); if (!plat_device_is_coherent(dev)) - __dma_sync((unsigned long)vaddr, size, direction); + dma_cache_wback_inv((unsigned long)vaddr, size); } EXPORT_SYMBOL(dma_cache_sync); diff --git a/trunk/arch/mips/mm/pg-r4k.c b/trunk/arch/mips/mm/pg-r4k.c index 9185fbf37c0d..4f770ac885ce 100644 --- a/trunk/arch/mips/mm/pg-r4k.c +++ b/trunk/arch/mips/mm/pg-r4k.c @@ -4,7 +4,6 @@ * for more details. * * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) - * Copyright (C) 2007 Maciej W. Rozycki */ #include #include @@ -13,7 +12,6 @@ #include #include -#include #include #include #include @@ -257,58 +255,64 @@ static inline void build_store_reg(int reg) __build_store_reg(reg); } -static inline void build_addiu_rt_rs(unsigned int rt, unsigned int rs, - unsigned long offset) +static inline void build_addiu_a2_a0(unsigned long offset) { union mips_instruction mi; BUG_ON(offset > 0x7fff); - if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) { - mi.i_format.opcode = addiu_op; - mi.i_format.rs = 0; /* $zero */ - mi.i_format.rt = 25; /* $t9 */ - mi.i_format.simmediate = offset; - emit_instruction(mi); + mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; + mi.i_format.rs = 4; /* $a0 */ + mi.i_format.rt = 6; /* $a2 */ + mi.i_format.simmediate = offset; - mi.r_format.opcode = spec_op; - mi.r_format.rs = rs; - mi.r_format.rt = 25; /* $t9 */ - mi.r_format.rd = rt; - mi.r_format.re = 0; - mi.r_format.func = daddu_op; - } else { - mi.i_format.opcode = cpu_has_64bit_gp_regs ? - daddiu_op : addiu_op; - mi.i_format.rs = rs; - mi.i_format.rt = rt; - mi.i_format.simmediate = offset; - } emit_instruction(mi); } -static inline void build_addiu_a2_a0(unsigned long offset) -{ - build_addiu_rt_rs(6, 4, offset); /* $a2, $a0, offset */ -} - static inline void build_addiu_a2(unsigned long offset) { - build_addiu_rt_rs(6, 6, offset); /* $a2, $a2, offset */ + union mips_instruction mi; + + BUG_ON(offset > 0x7fff); + + mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; + mi.i_format.rs = 6; /* $a2 */ + mi.i_format.rt = 6; /* $a2 */ + mi.i_format.simmediate = offset; + + emit_instruction(mi); } static inline void build_addiu_a1(unsigned long offset) { - build_addiu_rt_rs(5, 5, offset); /* $a1, $a1, offset */ + union mips_instruction mi; + + BUG_ON(offset > 0x7fff); + + mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; + mi.i_format.rs = 5; /* $a1 */ + mi.i_format.rt = 5; /* $a1 */ + mi.i_format.simmediate = offset; load_offset -= offset; + + emit_instruction(mi); } static inline void build_addiu_a0(unsigned long offset) { - build_addiu_rt_rs(4, 4, offset); /* $a0, $a0, offset */ + union mips_instruction mi; + + BUG_ON(offset > 0x7fff); + + mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op; + mi.i_format.rs = 4; /* $a0 */ + mi.i_format.rt = 4; /* $a0 */ + mi.i_format.simmediate = offset; store_offset -= offset; + + emit_instruction(mi); } static inline void build_bne(unsigned int *dest) diff --git a/trunk/arch/mips/mm/tlbex.c b/trunk/arch/mips/mm/tlbex.c index d026302e0ecc..a61246d3533d 100644 --- a/trunk/arch/mips/mm/tlbex.c +++ b/trunk/arch/mips/mm/tlbex.c @@ -6,7 +6,7 @@ * Synthesize TLB refill handlers at runtime. * * Copyright (C) 2004,2005,2006 by Thiemo Seufer - * Copyright (C) 2005, 2007 Maciej W. Rozycki + * Copyright (C) 2005 Maciej W. Rozycki * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) * * ... and the days got worse and worse and now you see @@ -19,15 +19,20 @@ * (Condolences to Napoleon XIV) */ +#include + +#include #include #include #include #include -#include +#include +#include #include #include #include +#include #include static inline int r45k_bvahwbug(void) @@ -61,7 +66,7 @@ static inline int __maybe_unused r10000_llsc_war(void) * why; it's not an issue caused by the core RTL. * */ -static int __init m4kc_tlbp_war(void) +static __init int __attribute__((unused)) m4kc_tlbp_war(void) { return (current_cpu_data.processor_id & 0xffff00) == (PRID_COMP_MIPS | PRID_IMP_4KC); @@ -135,7 +140,7 @@ struct insn { | (e) << RE_SH \ | (f) << FUNC_SH) -static struct insn insn_table[] __initdata = { +static __initdata struct insn insn_table[] = { { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD }, { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD }, @@ -188,7 +193,7 @@ static struct insn insn_table[] __initdata = { #undef M -static u32 __init build_rs(u32 arg) +static __init u32 build_rs(u32 arg) { if (arg & ~RS_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -196,7 +201,7 @@ static u32 __init build_rs(u32 arg) return (arg & RS_MASK) << RS_SH; } -static u32 __init build_rt(u32 arg) +static __init u32 build_rt(u32 arg) { if (arg & ~RT_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -204,7 +209,7 @@ static u32 __init build_rt(u32 arg) return (arg & RT_MASK) << RT_SH; } -static u32 __init build_rd(u32 arg) +static __init u32 build_rd(u32 arg) { if (arg & ~RD_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -212,7 +217,7 @@ static u32 __init build_rd(u32 arg) return (arg & RD_MASK) << RD_SH; } -static u32 __init build_re(u32 arg) +static __init u32 build_re(u32 arg) { if (arg & ~RE_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -220,7 +225,7 @@ static u32 __init build_re(u32 arg) return (arg & RE_MASK) << RE_SH; } -static u32 __init build_simm(s32 arg) +static __init u32 build_simm(s32 arg) { if (arg > 0x7fff || arg < -0x8000) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -228,7 +233,7 @@ static u32 __init build_simm(s32 arg) return arg & 0xffff; } -static u32 __init build_uimm(u32 arg) +static __init u32 build_uimm(u32 arg) { if (arg & ~IMM_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -236,7 +241,7 @@ static u32 __init build_uimm(u32 arg) return arg & IMM_MASK; } -static u32 __init build_bimm(s32 arg) +static __init u32 build_bimm(s32 arg) { if (arg > 0x1ffff || arg < -0x20000) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -247,7 +252,7 @@ static u32 __init build_bimm(s32 arg) return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); } -static u32 __init build_jimm(u32 arg) +static __init u32 build_jimm(u32 arg) { if (arg & ~((JIMM_MASK) << 2)) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -255,7 +260,7 @@ static u32 __init build_jimm(u32 arg) return (arg >> 2) & JIMM_MASK; } -static u32 __init build_func(u32 arg) +static __init u32 build_func(u32 arg) { if (arg & ~FUNC_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -263,7 +268,7 @@ static u32 __init build_func(u32 arg) return arg & FUNC_MASK; } -static u32 __init build_set(u32 arg) +static __init u32 build_set(u32 arg) { if (arg & ~SET_MASK) printk(KERN_WARNING "TLB synthesizer field overflow\n"); @@ -288,7 +293,7 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...) break; } - if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) + if (!ip) panic("Unsupported TLB synthesizer instruction %d", opc); op = ip->match; @@ -310,69 +315,69 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...) } #define I_u1u2u3(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, a, b, c); \ } #define I_u2u1u3(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, b, a, c); \ } #define I_u3u1u2(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, unsigned int c) \ { \ build_insn(buf, insn##op, b, c, a); \ } #define I_u1u2s3(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, signed int c) \ { \ build_insn(buf, insn##op, a, b, c); \ } #define I_u2s3u1(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ signed int b, unsigned int c) \ { \ build_insn(buf, insn##op, c, a, b); \ } #define I_u2u1s3(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b, signed int c) \ { \ build_insn(buf, insn##op, b, a, c); \ } #define I_u1u2(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ unsigned int b) \ { \ build_insn(buf, insn##op, a, b); \ } #define I_u1s2(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a, \ + static inline void __init i##op(u32 **buf, unsigned int a, \ signed int b) \ { \ build_insn(buf, insn##op, a, b); \ } #define I_u1(op) \ - static void __init __maybe_unused i##op(u32 **buf, unsigned int a) \ + static inline void __init i##op(u32 **buf, unsigned int a) \ { \ build_insn(buf, insn##op, a); \ } #define I_0(op) \ - static void __init __maybe_unused i##op(u32 **buf) \ + static inline void __init i##op(u32 **buf) \ { \ build_insn(buf, insn##op); \ } @@ -452,7 +457,7 @@ struct label { enum label_id lab; }; -static void __init build_label(struct label **lab, u32 *addr, +static __init void build_label(struct label **lab, u32 *addr, enum label_id l) { (*lab)->addr = addr; @@ -461,7 +466,7 @@ static void __init build_label(struct label **lab, u32 *addr, } #define L_LA(lb) \ - static inline void __init l##lb(struct label **lab, u32 *addr) \ + static inline void l##lb(struct label **lab, u32 *addr) \ { \ build_label(lab, addr, label##lb); \ } @@ -520,46 +525,37 @@ L_LA(_r3000_write_probe_fail) #define i_ssnop(buf) i_sll(buf, 0, 0, 1) #define i_ehb(buf) i_sll(buf, 0, 0, 3) -static int __init __maybe_unused in_compat_space_p(long addr) +#ifdef CONFIG_64BIT +static __init int __maybe_unused in_compat_space_p(long addr) { /* Is this address in 32bit compat space? */ -#ifdef CONFIG_64BIT return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); -#else - return 1; -#endif } -static int __init __maybe_unused rel_highest(long val) +static __init int __maybe_unused rel_highest(long val) { -#ifdef CONFIG_64BIT return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; -#else - return 0; -#endif } -static int __init __maybe_unused rel_higher(long val) +static __init int __maybe_unused rel_higher(long val) { -#ifdef CONFIG_64BIT return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; -#else - return 0; -#endif } +#endif -static int __init rel_hi(long val) +static __init int rel_hi(long val) { return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; } -static int __init rel_lo(long val) +static __init int rel_lo(long val) { return ((val & 0xffff) ^ 0x8000) - 0x8000; } -static void __init i_LA_mostly(u32 **buf, unsigned int rs, long addr) +static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) { +#ifdef CONFIG_64BIT if (!in_compat_space_p(addr)) { i_lui(buf, rs, rel_highest(addr)); if (rel_higher(addr)) @@ -571,18 +567,16 @@ static void __init i_LA_mostly(u32 **buf, unsigned int rs, long addr) } else i_dsll32(buf, rs, rs, 0); } else +#endif i_lui(buf, rs, rel_hi(addr)); } -static void __init __maybe_unused i_LA(u32 **buf, unsigned int rs, long addr) +static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs, + long addr) { i_LA_mostly(buf, rs, addr); - if (rel_lo(addr)) { - if (!in_compat_space_p(addr)) - i_daddiu(buf, rs, rs, rel_lo(addr)); - else - i_addiu(buf, rs, rs, rel_lo(addr)); - } + if (rel_lo(addr)) + i_ADDIU(buf, rs, rs, rel_lo(addr)); } /* @@ -595,7 +589,7 @@ struct reloc { enum label_id lab; }; -static void __init r_mips_pc16(struct reloc **rel, u32 *addr, +static __init void r_mips_pc16(struct reloc **rel, u32 *addr, enum label_id l) { (*rel)->addr = addr; @@ -620,7 +614,7 @@ static inline void __resolve_relocs(struct reloc *rel, struct label *lab) } } -static void __init resolve_relocs(struct reloc *rel, struct label *lab) +static __init void resolve_relocs(struct reloc *rel, struct label *lab) { struct label *l; @@ -630,7 +624,7 @@ static void __init resolve_relocs(struct reloc *rel, struct label *lab) __resolve_relocs(rel, l); } -static void __init move_relocs(struct reloc *rel, u32 *first, u32 *end, +static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, long off) { for (; rel->lab != label_invalid; rel++) @@ -638,7 +632,7 @@ static void __init move_relocs(struct reloc *rel, u32 *first, u32 *end, rel->addr += off; } -static void __init move_labels(struct label *lab, u32 *first, u32 *end, +static __init void move_labels(struct label *lab, u32 *first, u32 *end, long off) { for (; lab->lab != label_invalid; lab++) @@ -646,7 +640,7 @@ static void __init move_labels(struct label *lab, u32 *first, u32 *end, lab->addr += off; } -static void __init copy_handler(struct reloc *rel, struct label *lab, +static __init void copy_handler(struct reloc *rel, struct label *lab, u32 *first, u32 *end, u32 *target) { long off = (long)(target - first); @@ -657,7 +651,7 @@ static void __init copy_handler(struct reloc *rel, struct label *lab, move_labels(lab, first, end, off); } -static int __init __maybe_unused insn_has_bdelay(struct reloc *rel, +static __init int __maybe_unused insn_has_bdelay(struct reloc *rel, u32 *addr) { for (; rel->lab != label_invalid; rel++) { @@ -720,22 +714,6 @@ il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l) i_bgez(p, reg, 0); } -/* - * For debug purposes. - */ -static inline void dump_handler(const u32 *handler, int count) -{ - int i; - - pr_debug("\t.set push\n"); - pr_debug("\t.set noreorder\n"); - - for (i = 0; i < count; i++) - pr_debug("\t%p\t.word 0x%08x\n", &handler[i], handler[i]); - - pr_debug("\t.set pop\n"); -} - /* The only general purpose registers allowed in TLB handlers. */ #define K0 26 #define K1 27 @@ -765,11 +743,11 @@ static inline void dump_handler(const u32 *handler, int count) * We deliberately chose a buffer size of 128, so we won't scribble * over anything important on overflow before we panic. */ -static u32 tlb_handler[128] __initdata; +static __initdata u32 tlb_handler[128]; /* simply assume worst case size for labels and relocs */ -static struct label labels[128] __initdata; -static struct reloc relocs[128] __initdata; +static __initdata struct label labels[128]; +static __initdata struct reloc relocs[128]; /* * The R3000 TLB handler is simple. @@ -778,6 +756,7 @@ static void __init build_r3000_tlb_refill_handler(void) { long pgdc = (long)pgd_current; u32 *p; + int i; memset(tlb_handler, 0, sizeof(tlb_handler)); p = tlb_handler; @@ -806,9 +785,13 @@ static void __init build_r3000_tlb_refill_handler(void) pr_info("Synthesized TLB refill handler (%u instructions).\n", (unsigned int)(p - tlb_handler)); - memcpy((void *)ebase, tlb_handler, 0x80); + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (p - tlb_handler); i++) + pr_debug("\t.word 0x%08x\n", tlb_handler[i]); + pr_debug("\t.set pop\n"); - dump_handler((u32 *)ebase, 32); + memcpy((void *)ebase, tlb_handler, 0x80); } /* @@ -818,7 +801,7 @@ static void __init build_r3000_tlb_refill_handler(void) * other one.To keep things simple, we first assume linear space, * then we relocate it to the final handler layout as needed. */ -static u32 final_handler[64] __initdata; +static __initdata u32 final_handler[64]; /* * Hazards @@ -842,7 +825,7 @@ static u32 final_handler[64] __initdata; * * As if we MIPS hackers wouldn't know how to nop pipelines happy ... */ -static void __init __maybe_unused build_tlb_probe_entry(u32 **p) +static __init void __maybe_unused build_tlb_probe_entry(u32 **p) { switch (current_cpu_type()) { /* Found by experiment: R4600 v2.0 needs this, too. */ @@ -866,7 +849,7 @@ static void __init __maybe_unused build_tlb_probe_entry(u32 **p) */ enum tlb_write_entry { tlb_random, tlb_indexed }; -static void __init build_tlb_write_entry(u32 **p, struct label **l, +static __init void build_tlb_write_entry(u32 **p, struct label **l, struct reloc **r, enum tlb_write_entry wmode) { @@ -877,12 +860,6 @@ static void __init build_tlb_write_entry(u32 **p, struct label **l, case tlb_indexed: tlbw = i_tlbwi; break; } - if (cpu_has_mips_r2) { - i_ehb(p); - tlbw(p); - return; - } - switch (current_cpu_type()) { case CPU_R4000PC: case CPU_R4000SC: @@ -917,8 +894,6 @@ static void __init build_tlb_write_entry(u32 **p, struct label **l, case CPU_AU1500: case CPU_AU1550: case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: case CPU_PR4450: i_nop(p); tlbw(p); @@ -960,6 +935,14 @@ static void __init build_tlb_write_entry(u32 **p, struct label **l, tlbw(p); break; + case CPU_4KEC: + case CPU_24K: + case CPU_34K: + case CPU_74K: + i_ehb(p); + tlbw(p); + break; + case CPU_RM9000: /* * When the JTLB is updated by tlbwi or tlbwr, a subsequent @@ -1010,7 +993,7 @@ static void __init build_tlb_write_entry(u32 **p, struct label **l, * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pmd entry. */ -static void __init +static __init void build_get_pmde64(u32 **p, struct label **l, struct reloc **r, unsigned int tmp, unsigned int ptr) { @@ -1071,7 +1054,7 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r, * BVADDR is the faulting address, PTR is scratch. * PTR will hold the pgd for vmalloc. */ -static void __init +static __init void build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, unsigned int bvaddr, unsigned int ptr) { @@ -1104,10 +1087,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, } else { i_LA_mostly(p, ptr, modd); il_b(p, r, label_vmalloc_done); - if (in_compat_space_p(modd)) - i_addiu(p, ptr, ptr, rel_lo(modd)); - else - i_daddiu(p, ptr, ptr, rel_lo(modd)); + i_daddiu(p, ptr, ptr, rel_lo(modd)); } l_vmalloc(l, *p); @@ -1128,10 +1108,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, } else { i_LA_mostly(p, ptr, swpd); il_b(p, r, label_vmalloc_done); - if (in_compat_space_p(swpd)) - i_addiu(p, ptr, ptr, rel_lo(swpd)); - else - i_daddiu(p, ptr, ptr, rel_lo(swpd)); + i_daddiu(p, ptr, ptr, rel_lo(swpd)); } } @@ -1141,7 +1118,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, * TMP and PTR are scratch. * TMP will be clobbered, PTR will hold the pgd entry. */ -static void __init __maybe_unused +static __init void __maybe_unused build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) { long pgdc = (long)pgd_current; @@ -1176,7 +1153,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) #endif /* !CONFIG_64BIT */ -static void __init build_adjust_context(u32 **p, unsigned int ctx) +static __init void build_adjust_context(u32 **p, unsigned int ctx) { unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); @@ -1202,7 +1179,7 @@ static void __init build_adjust_context(u32 **p, unsigned int ctx) i_andi(p, ctx, ctx, mask); } -static void __init build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) +static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) { /* * Bug workaround for the Nevada. It seems as if under certain @@ -1227,7 +1204,7 @@ static void __init build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) i_ADDU(p, ptr, ptr, tmp); /* add in offset */ } -static void __init build_update_entries(u32 **p, unsigned int tmp, +static __init void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) { /* @@ -1277,6 +1254,7 @@ static void __init build_r4000_tlb_refill_handler(void) struct reloc *r = relocs; u32 *f; unsigned int final_len; + int i; memset(tlb_handler, 0, sizeof(tlb_handler)); memset(labels, 0, sizeof(labels)); @@ -1378,9 +1356,20 @@ static void __init build_r4000_tlb_refill_handler(void) pr_info("Synthesized TLB refill handler (%u instructions).\n", final_len); - memcpy((void *)ebase, final_handler, 0x100); + f = final_handler; +#if defined(CONFIG_64BIT) && !defined(CONFIG_CPU_LOONGSON2) + if (final_len > 32) + final_len = 64; + else + f = final_handler + 32; +#endif /* CONFIG_64BIT */ + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < final_len; i++) + pr_debug("\t.word 0x%08x\n", f[i]); + pr_debug("\t.set pop\n"); - dump_handler((u32 *)ebase, 64); + memcpy((void *)ebase, final_handler, 0x100); } /* @@ -1392,15 +1381,18 @@ static void __init build_r4000_tlb_refill_handler(void) extern void tlb_do_page_fault_0(void); extern void tlb_do_page_fault_1(void); +#define __tlb_handler_align \ + __attribute__((__aligned__(1 << CONFIG_MIPS_L1_CACHE_SHIFT))) + /* * 128 instructions for the fastpath handler is generous and should * never be exceeded. */ #define FASTPATH_SIZE 128 -u32 handle_tlbl[FASTPATH_SIZE] __cacheline_aligned; -u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned; -u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; +u32 __tlb_handler_align handle_tlbl[FASTPATH_SIZE]; +u32 __tlb_handler_align handle_tlbs[FASTPATH_SIZE]; +u32 __tlb_handler_align handle_tlbm[FASTPATH_SIZE]; static void __init iPTE_LW(u32 **p, struct label **l, unsigned int pte, unsigned int ptr) @@ -1608,6 +1600,7 @@ static void __init build_r3000_tlb_load_handler(void) u32 *p = handle_tlbl; struct label *l = labels; struct reloc *r = relocs; + int i; memset(handle_tlbl, 0, sizeof(handle_tlbl)); memset(labels, 0, sizeof(labels)); @@ -1630,7 +1623,11 @@ static void __init build_r3000_tlb_load_handler(void) pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbl)); - dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (p - handle_tlbl); i++) + pr_debug("\t.word 0x%08x\n", handle_tlbl[i]); + pr_debug("\t.set pop\n"); } static void __init build_r3000_tlb_store_handler(void) @@ -1638,6 +1635,7 @@ static void __init build_r3000_tlb_store_handler(void) u32 *p = handle_tlbs; struct label *l = labels; struct reloc *r = relocs; + int i; memset(handle_tlbs, 0, sizeof(handle_tlbs)); memset(labels, 0, sizeof(labels)); @@ -1660,7 +1658,11 @@ static void __init build_r3000_tlb_store_handler(void) pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbs)); - dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (p - handle_tlbs); i++) + pr_debug("\t.word 0x%08x\n", handle_tlbs[i]); + pr_debug("\t.set pop\n"); } static void __init build_r3000_tlb_modify_handler(void) @@ -1668,6 +1670,7 @@ static void __init build_r3000_tlb_modify_handler(void) u32 *p = handle_tlbm; struct label *l = labels; struct reloc *r = relocs; + int i; memset(handle_tlbm, 0, sizeof(handle_tlbm)); memset(labels, 0, sizeof(labels)); @@ -1690,7 +1693,11 @@ static void __init build_r3000_tlb_modify_handler(void) pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbm)); - dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (p - handle_tlbm); i++) + pr_debug("\t.word 0x%08x\n", handle_tlbm[i]); + pr_debug("\t.set pop\n"); } /* @@ -1743,6 +1750,7 @@ static void __init build_r4000_tlb_load_handler(void) u32 *p = handle_tlbl; struct label *l = labels; struct reloc *r = relocs; + int i; memset(handle_tlbl, 0, sizeof(handle_tlbl)); memset(labels, 0, sizeof(labels)); @@ -1775,7 +1783,11 @@ static void __init build_r4000_tlb_load_handler(void) pr_info("Synthesized TLB load handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbl)); - dump_handler(handle_tlbl, ARRAY_SIZE(handle_tlbl)); + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (p - handle_tlbl); i++) + pr_debug("\t.word 0x%08x\n", handle_tlbl[i]); + pr_debug("\t.set pop\n"); } static void __init build_r4000_tlb_store_handler(void) @@ -1783,6 +1795,7 @@ static void __init build_r4000_tlb_store_handler(void) u32 *p = handle_tlbs; struct label *l = labels; struct reloc *r = relocs; + int i; memset(handle_tlbs, 0, sizeof(handle_tlbs)); memset(labels, 0, sizeof(labels)); @@ -1806,7 +1819,11 @@ static void __init build_r4000_tlb_store_handler(void) pr_info("Synthesized TLB store handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbs)); - dump_handler(handle_tlbs, ARRAY_SIZE(handle_tlbs)); + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (p - handle_tlbs); i++) + pr_debug("\t.word 0x%08x\n", handle_tlbs[i]); + pr_debug("\t.set pop\n"); } static void __init build_r4000_tlb_modify_handler(void) @@ -1814,6 +1831,7 @@ static void __init build_r4000_tlb_modify_handler(void) u32 *p = handle_tlbm; struct label *l = labels; struct reloc *r = relocs; + int i; memset(handle_tlbm, 0, sizeof(handle_tlbm)); memset(labels, 0, sizeof(labels)); @@ -1838,7 +1856,11 @@ static void __init build_r4000_tlb_modify_handler(void) pr_info("Synthesized TLB modify handler fastpath (%u instructions).\n", (unsigned int)(p - handle_tlbm)); - dump_handler(handle_tlbm, ARRAY_SIZE(handle_tlbm)); + pr_debug("\t.set push\n"); + pr_debug("\t.set noreorder\n"); + for (i = 0; i < (p - handle_tlbm); i++) + pr_debug("\t.word 0x%08x\n", handle_tlbm[i]); + pr_debug("\t.set pop\n"); } void __init build_tlb_refill_handler(void) diff --git a/trunk/arch/mips/oprofile/op_model_mipsxx.c b/trunk/arch/mips/oprofile/op_model_mipsxx.c index ccbea229a0e6..bdfa07aecd97 100644 --- a/trunk/arch/mips/oprofile/op_model_mipsxx.c +++ b/trunk/arch/mips/oprofile/op_model_mipsxx.c @@ -19,7 +19,7 @@ #define M_PERFCTL_SUPERVISOR (1UL << 2) #define M_PERFCTL_USER (1UL << 3) #define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) -#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) +#define M_PERFCTL_EVENT(event) (((event) & 0x3f) << 5) #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) #define M_PERFCTL_MT_EN(filter) ((filter) << 20) #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) diff --git a/trunk/arch/mips/pci/pci-bcm1480.c b/trunk/arch/mips/pci/pci-bcm1480.c index 30ed36125bcd..47f316c86ab1 100644 --- a/trunk/arch/mips/pci/pci-bcm1480.c +++ b/trunk/arch/mips/pci/pci-bcm1480.c @@ -178,8 +178,8 @@ struct pci_ops bcm1480_pci_ops = { static struct resource bcm1480_mem_resource = { .name = "BCM1480 PCI MEM", - .start = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, - .end = A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES + 0xfffffffUL, + .start = 0x30000000UL, + .end = 0x3fffffffUL, .flags = IORESOURCE_MEM, }; diff --git a/trunk/arch/mips/pci/pci-bcm1480ht.c b/trunk/arch/mips/pci/pci-bcm1480ht.c index 005e7fecab08..a63e3bd6b0ac 100644 --- a/trunk/arch/mips/pci/pci-bcm1480ht.c +++ b/trunk/arch/mips/pci/pci-bcm1480ht.c @@ -173,8 +173,8 @@ struct pci_ops bcm1480ht_pci_ops = { static struct resource bcm1480ht_mem_resource = { .name = "BCM1480 HT MEM", - .start = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES, - .end = A_BCM1480_PHYS_HT_MEM_MATCH_BYTES + 0x1fffffffUL, + .start = 0x40000000UL, + .end = 0x5fffffffUL, .flags = IORESOURCE_MEM, }; diff --git a/trunk/arch/mips/philips/pnx8550/common/setup.c b/trunk/arch/mips/philips/pnx8550/common/setup.c index 92d764c97701..2ce298f4d19a 100644 --- a/trunk/arch/mips/philips/pnx8550/common/setup.c +++ b/trunk/arch/mips/philips/pnx8550/common/setup.c @@ -74,7 +74,7 @@ struct resource standard_io_resources[] = { }, }; -#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources) +#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource)) extern struct resource pci_io_resource; extern struct resource pci_mem_resource; diff --git a/trunk/arch/mips/philips/pnx8550/common/time.c b/trunk/arch/mips/philips/pnx8550/common/time.c index 62f495b57f93..6d494e0de3d9 100644 --- a/trunk/arch/mips/philips/pnx8550/common/time.c +++ b/trunk/arch/mips/philips/pnx8550/common/time.c @@ -47,6 +47,11 @@ static struct clocksource pnx_clocksource = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +static void timer_ack(void) +{ + write_c0_compare(cpj); +} + static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *c = dev_id; @@ -89,22 +94,30 @@ static struct clock_event_device pnx8xxx_clockevent = { .set_next_event = pnx8xxx_set_next_event, }; -static inline void timer_ack(void) -{ - write_c0_compare(cpj); -} +/* + * plat_time_init() - it does the following things: + * + * 1) plat_time_init() - + * a) (optional) set up RTC routines, + * b) (optional) calibrate and set the mips_hpt_frequency + * (only needed if you intended to use cpu counter as timer interrupt + * source) + */ __init void plat_time_init(void) { - unsigned int configPR; - unsigned int n; - unsigned int m; - unsigned int p; - unsigned int pow2p; + unsigned int configPR; + unsigned int n; + unsigned int m; + unsigned int p; + unsigned int pow2p; clockevents_register_device(&pnx8xxx_clockevent); clocksource_register(&pnx_clocksource); + setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); + setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); + /* Timer 1 start */ configPR = read_c0_config7(); configPR &= ~0x00000008; @@ -145,6 +158,6 @@ __init void plat_time_init(void) write_c0_count2(0); write_c0_compare2(0xffffffff); - setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq); - setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction); } + + diff --git a/trunk/arch/mips/philips/pnx8550/jbs/init.c b/trunk/arch/mips/philips/pnx8550/jbs/init.c index 90b4d35f3ece..cfd90fa3d799 100644 --- a/trunk/arch/mips/philips/pnx8550/jbs/init.c +++ b/trunk/arch/mips/philips/pnx8550/jbs/init.c @@ -45,8 +45,11 @@ const char *get_system_type(void) void __init prom_init(void) { + unsigned long memsize; + mips_machtype = MACH_PHILIPS_JBS; + //memsize = 0x02800000; /* Trimedia uses memory above */ memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); diff --git a/trunk/arch/mips/philips/pnx8550/stb810/prom_init.c b/trunk/arch/mips/philips/pnx8550/stb810/prom_init.c index 832dd60b0a7a..fdb33ed089b9 100644 --- a/trunk/arch/mips/philips/pnx8550/stb810/prom_init.c +++ b/trunk/arch/mips/philips/pnx8550/stb810/prom_init.c @@ -41,6 +41,8 @@ void __init prom_init(void) prom_init_cmdline(); + mips_machtype = MACH_PHILIPS_STB810; + memsize = 0x08000000; /* Trimedia uses memory above */ add_memory_region(0, memsize, BOOT_MEM_RAM); } diff --git a/trunk/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h b/trunk/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h new file mode 100644 index 000000000000..31c5523276fa --- /dev/null +++ b/trunk/arch/mips/pmc-sierra/yosemite/i2c-yosemite.h @@ -0,0 +1,96 @@ +/* + * arch/mips/pmc-sierra/yosemite/i2c-yosemite.h + * + * Copyright (C) 2003 PMC-Sierra Inc. + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __I2C_YOSEMITE_H +#define __I2C_YOSEMITE_H + +/* Read and Write operations to the chip */ + +#define TITAN_I2C_BASE 0xbb000000 /* XXX Needs to change */ + +#define TITAN_I2C_WRITE(offset, data) \ + *(volatile unsigned long *)(TITAN_I2C_BASE + offset) = data + +#define TITAN_I2C_READ(offset) *(volatile unsigned long *)(TITAN_I2C_BASE + offset) + + +/* Local constansts*/ +#define TITAN_I2C_MAX_FILTER 15 +#define TITAN_I2C_MAX_CLK 1023 +#define TITAN_I2C_MAX_ARBF 15 +#define TITAN_I2C_MAX_NAK 15 +#define TITAN_I2C_MAX_MASTERCODE 7 +#define TITAN_I2C_MAX_WORDS_PER_RW 4 +#define TITAN_I2C_MAX_POLL 100 + +/* Registers used for I2C work */ +#define TITAN_I2C_SCMB_CONTROL 0x0180 /* SCMB Control */ +#define TITAN_I2C_SCMB_CLOCK_A 0x0184 /* SCMB Clock A */ +#define TITAN_I2C_SCMB_CLOCK_B 0x0188 /* SCMB Clock B */ +#define TITAN_I2C_CONFIG 0x01A0 /* I2C Config */ +#define TITAN_I2C_COMMAND 0x01A4 /* I2C Command */ +#define TITAN_I2C_SLAVE_ADDRESS 0x01A8 /* I2C Slave Address */ +#define TITAN_I2C_DATA 0x01AC /* I2C Data [15:0] */ +#define TITAN_I2C_INTERRUPTS 0x01BC /* I2C Interrupts */ + +/* Error */ +#define TITAN_I2C_ERR_ARB_LOST (-9220) +#define TITAN_I2C_ERR_NO_RESP (-9221) +#define TITAN_I2C_ERR_DATA_COLLISION (-9222) +#define TITAN_I2C_ERR_TIMEOUT (-9223) +#define TITAN_I2C_ERR_OK 0 + +/* I2C Command Type */ +typedef enum { + TITAN_I2C_CMD_WRITE = 0, + TITAN_I2C_CMD_READ = 1, + TITAN_I2C_CMD_READ_WRITE = 2 +} titan_i2c_cmd_type; + +/* I2C structures */ +typedef struct { + int filtera; /* Register 0x0184, bits 15 - 12 */ + int clka; /* Register 0x0184, bits 9 - 0 */ + int filterb; /* Register 0x0188, bits 15 - 12 */ + int clkb; /* Register 0x0188, bits 9 - 0 */ +} titan_i2c_config; + +/* I2C command type */ +typedef struct { + titan_i2c_cmd_type type; /* Type of command */ + int num_arb; /* Register 0x01a0, bits 15 - 12 */ + int num_nak; /* Register 0x01a0, bits 11 - 8 */ + int addr_size; /* Register 0x01a0, bit 7 */ + int mst_code; /* Register 0x01a0, bits 6 - 4 */ + int arb_en; /* Register 0x01a0, bit 1 */ + int speed; /* Register 0x01a0, bit 0 */ + int slave_addr; /* Register 0x01a8 */ + int write_size; /* Register 0x01a4, bits 10 - 8 */ + unsigned int *data; /* Register 0x01ac */ +} titan_i2c_command; + +#endif /* __I2C_YOSEMITE_H */ diff --git a/trunk/arch/mips/pmc-sierra/yosemite/prom.c b/trunk/arch/mips/pmc-sierra/yosemite/prom.c index 35dc435846a6..9b9936de6589 100644 --- a/trunk/arch/mips/pmc-sierra/yosemite/prom.c +++ b/trunk/arch/mips/pmc-sierra/yosemite/prom.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -79,8 +78,6 @@ static void prom_halt(void) __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0"); } -extern struct plat_smp_ops yos_smp_ops; - /* * Init routine which accepts the variables from PMON */ @@ -129,9 +126,9 @@ void __init prom_init(void) env++; } - prom_grab_secondary(); + mips_machtype = MACH_TITAN_YOSEMITE; - register_smp_ops(&yos_smp_ops); + prom_grab_secondary(); } void __init prom_free_prom_memory(void) diff --git a/trunk/arch/mips/pmc-sierra/yosemite/smp.c b/trunk/arch/mips/pmc-sierra/yosemite/smp.c index 653f3ec61cab..b0f12cd2968a 100644 --- a/trunk/arch/mips/pmc-sierra/yosemite/smp.c +++ b/trunk/arch/mips/pmc-sierra/yosemite/smp.c @@ -42,6 +42,70 @@ void __init prom_grab_secondary(void) launchstack + LAUNCHSTACK_SIZE, 0); } +/* + * Detect available CPUs, populate phys_cpu_present_map before smp_init + * + * We don't want to start the secondary CPU yet nor do we have a nice probing + * feature in PMON so we just assume presence of the secondary core. + */ +void __init plat_smp_setup(void) +{ + int i; + + cpus_clear(phys_cpu_present_map); + + for (i = 0; i < 2; i++) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = i; + __cpu_logical_map[i] = i; + } +} + +void __init plat_prepare_cpus(unsigned int max_cpus) +{ + /* + * Be paranoid. Enable the IPI only if we're really about to go SMP. + */ + if (cpus_weight(cpu_possible_map)) + set_c0_status(STATUSF_IP5); +} + +/* + * Firmware CPU startup hook + * Complicated by PMON's weird interface which tries to minimic the UNIX fork. + * It launches the next * available CPU and copies some information on the + * stack so the first thing we do is throw away that stuff and load useful + * values into the registers ... + */ +void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) +{ + unsigned long gp = (unsigned long) task_thread_info(idle); + unsigned long sp = __KSTK_TOS(idle); + + secondary_sp = sp; + secondary_gp = gp; + + spin_unlock(&launch_lock); +} + +/* Hook for after all CPUs are online */ +void prom_cpus_done(void) +{ +} + +/* + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +void __cpuinit prom_init_secondary(void) +{ + set_c0_status(ST0_CO | ST0_IE | ST0_IM); +} + +void __cpuinit prom_smp_finish(void) +{ +} + void titan_mailbox_irq(void) { int cpu = smp_processor_id(); @@ -69,7 +133,7 @@ void titan_mailbox_irq(void) /* * Send inter-processor interrupt */ -static void yos_send_ipi_single(int cpu, unsigned int action) +void core_send_ipi(int cpu, unsigned int action) { /* * Generate an INTMSG so that it can be sent over to the @@ -95,86 +159,3 @@ static void yos_send_ipi_single(int cpu, unsigned int action) break; } } - -static void yos_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; - - for_each_cpu_mask(i, mask) - yos_send_ipi_single(i, action); -} - -/* - * After we've done initial boot, this function is called to allow the - * board code to clean up state, if needed - */ -static void __cpuinit yos_init_secondary(void) -{ - set_c0_status(ST0_CO | ST0_IE | ST0_IM); -} - -static void __cpuinit yos_smp_finish(void) -{ -} - -/* Hook for after all CPUs are online */ -static void yos_cpus_done(void) -{ -} - -/* - * Firmware CPU startup hook - * Complicated by PMON's weird interface which tries to minimic the UNIX fork. - * It launches the next * available CPU and copies some information on the - * stack so the first thing we do is throw away that stuff and load useful - * values into the registers ... - */ -static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle) -{ - unsigned long gp = (unsigned long) task_thread_info(idle); - unsigned long sp = __KSTK_TOS(idle); - - secondary_sp = sp; - secondary_gp = gp; - - spin_unlock(&launch_lock); -} - -/* - * Detect available CPUs, populate phys_cpu_present_map before smp_init - * - * We don't want to start the secondary CPU yet nor do we have a nice probing - * feature in PMON so we just assume presence of the secondary core. - */ -static void __init yos_smp_setup(void) -{ - int i; - - cpus_clear(phys_cpu_present_map); - - for (i = 0; i < 2; i++) { - cpu_set(i, phys_cpu_present_map); - __cpu_number_map[i] = i; - __cpu_logical_map[i] = i; - } -} - -static void __init yos_prepare_cpus(unsigned int max_cpus) -{ - /* - * Be paranoid. Enable the IPI only if we're really about to go SMP. - */ - if (cpus_weight(cpu_possible_map)) - set_c0_status(STATUSF_IP5); -} - -struct plat_smp_ops yos_smp_ops = { - .send_ipi_single = yos_send_ipi_single, - .send_ipi_mask = yos_send_ipi_mask, - .init_secondary = yos_init_secondary, - .smp_finish = yos_smp_finish, - .cpus_done = yos_cpus_done, - .boot_secondary = yos_boot_secondary, - .smp_setup = yos_smp_setup, - .prepare_cpus = yos_prepare_cpus, -}; diff --git a/trunk/arch/mips/qemu/Makefile b/trunk/arch/mips/qemu/Makefile new file mode 100644 index 000000000000..2ba4ef34b4a7 --- /dev/null +++ b/trunk/arch/mips/qemu/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for Qemu specific kernel interface routines under Linux. +# + +obj-y = q-firmware.o q-irq.o q-mem.o q-setup.o q-reset.o + +obj-$(CONFIG_EARLY_PRINTK) += q-console.o +obj-$(CONFIG_SMP) += q-smp.o + +EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/qemu/q-console.c b/trunk/arch/mips/qemu/q-console.c new file mode 100644 index 000000000000..81101ae5017a --- /dev/null +++ b/trunk/arch/mips/qemu/q-console.c @@ -0,0 +1,26 @@ +#include +#include +#include +#include + +#define PORT(offset) (0x3f8 + (offset)) + +static inline unsigned int serial_in(int offset) +{ + return inb(PORT(offset)); +} + +static inline void serial_out(int offset, int value) +{ + outb(value, PORT(offset)); +} + +int prom_putchar(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c); + + return 1; +} diff --git a/trunk/arch/mips/qemu/q-firmware.c b/trunk/arch/mips/qemu/q-firmware.c new file mode 100644 index 000000000000..3ed43f416cd1 --- /dev/null +++ b/trunk/arch/mips/qemu/q-firmware.c @@ -0,0 +1,24 @@ +#include +#include +#include +#include +#include + +#define QEMU_PORT_BASE 0xb4000000 + +void __init prom_init(void) +{ + int *cmdline; + + cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260); + if (*cmdline == 0x12345678) { + if (*(char *)(cmdline + 1)) + strcpy(arcs_cmdline, (char *)(cmdline + 1)); + add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM); + } else { + add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); + } + + + set_io_port_base(QEMU_PORT_BASE); +} diff --git a/trunk/arch/mips/qemu/q-irq.c b/trunk/arch/mips/qemu/q-irq.c new file mode 100644 index 000000000000..7df36dbe65c7 --- /dev/null +++ b/trunk/arch/mips/qemu/q-irq.c @@ -0,0 +1,37 @@ +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & 0x8000) { + do_IRQ(Q_COUNT_COMPARE_IRQ); + return; + } + if (pending & 0x0400) { + int irq = i8259_irq(); + + if (likely(irq >= 0)) + do_IRQ(irq); + + return; + } +} + +void __init arch_init_irq(void) +{ + mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */ + + mips_cpu_irq_init(); + init_i8259_irqs(); + set_c0_status(0x400); +} diff --git a/trunk/arch/mips/qemu/q-mem.c b/trunk/arch/mips/qemu/q-mem.c new file mode 100644 index 000000000000..dae39b59de15 --- /dev/null +++ b/trunk/arch/mips/qemu/q-mem.c @@ -0,0 +1,5 @@ +#include + +void __init prom_free_prom_memory(void) +{ +} diff --git a/trunk/arch/mips/qemu/q-reset.c b/trunk/arch/mips/qemu/q-reset.c new file mode 100644 index 000000000000..dbbe44ad7e89 --- /dev/null +++ b/trunk/arch/mips/qemu/q-reset.c @@ -0,0 +1,33 @@ + +#include +#include +#include +#include + +static void qemu_machine_restart(char *command) +{ + volatile unsigned int *reg = (unsigned int *)QEMU_RESTART_REG; + + set_c0_status(ST0_BEV | ST0_ERL); + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + flush_cache_all(); + write_c0_wired(0); + *reg = 42; + while (1) + cpu_wait(); +} + +static void qemu_machine_halt(void) +{ + volatile unsigned int *reg = (unsigned int *)QEMU_HALT_REG; + + *reg = 42; + while (1) + cpu_wait(); +} + +void qemu_reboot_setup(void) +{ + _machine_restart = qemu_machine_restart; + _machine_halt = qemu_machine_halt; +} diff --git a/trunk/arch/mips/qemu/q-setup.c b/trunk/arch/mips/qemu/q-setup.c new file mode 100644 index 000000000000..969cedc8d8b9 --- /dev/null +++ b/trunk/arch/mips/qemu/q-setup.c @@ -0,0 +1,22 @@ +#include + +#include +#include +#include + +extern void qemu_reboot_setup(void); + +const char *get_system_type(void) +{ + return "Qemu"; +} + +void __init plat_time_init(void) +{ + setup_pit_timer(); +} + +void __init plat_mem_setup(void) +{ + qemu_reboot_setup(); +} diff --git a/trunk/arch/mips/qemu/q-smp.c b/trunk/arch/mips/qemu/q-smp.c new file mode 100644 index 000000000000..4b0178d0df0b --- /dev/null +++ b/trunk/arch/mips/qemu/q-smp.c @@ -0,0 +1,55 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org) + * + * Symmetric Uniprocessor (TM) Support + */ +#include +#include + +/* + * Send inter-processor interrupt + */ +void core_send_ipi(int cpu, unsigned int action) +{ + panic(KERN_ERR "%s called", __FUNCTION__); +} + +/* + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +void __cpuinit prom_init_secondary(void) +{ +} + +void __cpuinit prom_smp_finish(void) +{ +} + +/* Hook for after all CPUs are online */ +void prom_cpus_done(void) +{ +} + +void __init prom_prepare_cpus(unsigned int max_cpus) +{ + cpus_clear(phys_cpu_present_map); +} + +/* + * Firmware CPU startup hook + */ +void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) +{ +} + +void __init plat_smp_setup(void) +{ +} +void __init plat_prepare_cpus(unsigned int max_cpus) +{ +} diff --git a/trunk/arch/mips/sgi-ip22/Makefile b/trunk/arch/mips/sgi-ip22/Makefile index ef1564e40c8d..e3acb51b70b5 100644 --- a/trunk/arch/mips/sgi-ip22/Makefile +++ b/trunk/arch/mips/sgi-ip22/Makefile @@ -3,11 +3,9 @@ # under Linux. # -obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-time.o ip22-nvram.o \ - ip22-platform.o ip22-reset.o ip22-setup.o +obj-y += ip22-mc.o ip22-hpc.o ip22-int.o ip22-berr.o \ + ip22-time.o ip22-nvram.o ip22-platform.o ip22-reset.o ip22-setup.o -obj-$(CONFIG_SGI_IP22) += ip22-berr.o -obj-$(CONFIG_SGI_IP28) += ip28-berr.o obj-$(CONFIG_EISA) += ip22-eisa.o -# EXTRA_CFLAGS += -Werror +EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/sgi-ip22/ip22-mc.c b/trunk/arch/mips/sgi-ip22/ip22-mc.c index 3f35d6367bec..01a805dcc67c 100644 --- a/trunk/arch/mips/sgi-ip22/ip22-mc.c +++ b/trunk/arch/mips/sgi-ip22/ip22-mc.c @@ -4,7 +4,6 @@ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org) - * Copyright (C) 2004 Peter Fuerst (pf@net.alphadv.de) - IP28 */ #include @@ -138,12 +137,9 @@ void __init sgimc_init(void) /* Step 2: Enable all parity checking in cpu control register * zero. */ - /* don't touch parity settings for IP28 */ -#ifndef CONFIG_SGI_IP28 tmp = sgimc->cpuctrl0; tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM | SGIMC_CCTRL0_R4KNOCHKPARR); -#endif sgimc->cpuctrl0 = tmp; /* Step 3: Setup the MC write buffer depth, this is controlled diff --git a/trunk/arch/mips/sgi-ip22/ip28-berr.c b/trunk/arch/mips/sgi-ip22/ip28-berr.c deleted file mode 100644 index 30e12e2ec4b5..000000000000 --- a/trunk/arch/mips/sgi-ip22/ip28-berr.c +++ /dev/null @@ -1,502 +0,0 @@ -/* - * ip28-berr.c: Bus error handling. - * - * Copyright (C) 2002, 2003 Ladislav Michl (ladis@linux-mips.org) - * Copyright (C) 2005 Peter Fuerst (pf@net.alphadv.de) - IP28 - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static unsigned int count_be_is_fixup; -static unsigned int count_be_handler; -static unsigned int count_be_interrupt; -static int debug_be_interrupt; - -static unsigned int cpu_err_stat; /* Status reg for CPU */ -static unsigned int gio_err_stat; /* Status reg for GIO */ -static unsigned int cpu_err_addr; /* Error address reg for CPU */ -static unsigned int gio_err_addr; /* Error address reg for GIO */ -static unsigned int extio_stat; -static unsigned int hpc3_berr_stat; /* Bus error interrupt status */ - -struct hpc3_stat { - unsigned long addr; - unsigned int ctrl; - unsigned int cbp; - unsigned int ndptr; -}; - -static struct { - struct hpc3_stat pbdma[8]; - struct hpc3_stat scsi[2]; - struct hpc3_stat ethrx, ethtx; -} hpc3; - -static struct { - unsigned long err_addr; - struct { - u32 lo; - u32 hi; - } tags[1][2], tagd[4][2], tagi[4][2]; /* Way 0/1 */ -} cache_tags; - -static inline void save_cache_tags(unsigned busaddr) -{ - unsigned long addr = CAC_BASE | busaddr; - int i; - cache_tags.err_addr = addr; - - /* - * Starting with a bus-address, save secondary cache (indexed by - * PA[23..18:7..6]) tags first. - */ - addr &= ~1L; -#define tag cache_tags.tags[0] - cache_op(Index_Load_Tag_S, addr); - tag[0].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */ - tag[0].hi = read_c0_taghi(); /* PA[39:36] */ - cache_op(Index_Load_Tag_S, addr | 1L); - tag[1].lo = read_c0_taglo(); /* PA[35:18], VA[13:12] */ - tag[1].hi = read_c0_taghi(); /* PA[39:36] */ -#undef tag - - /* - * Save all primary data cache (indexed by VA[13:5]) tags which - * might fit to this bus-address, knowing that VA[11:0] == PA[11:0]. - * Saving all tags and evaluating them later is easier and safer - * than relying on VA[13:12] from the secondary cache tags to pick - * matching primary tags here already. - */ - addr &= (0xffL << 56) | ((1 << 12) - 1); -#define tag cache_tags.tagd[i] - for (i = 0; i < 4; ++i, addr += (1 << 12)) { - cache_op(Index_Load_Tag_D, addr); - tag[0].lo = read_c0_taglo(); /* PA[35:12] */ - tag[0].hi = read_c0_taghi(); /* PA[39:36] */ - cache_op(Index_Load_Tag_D, addr | 1L); - tag[1].lo = read_c0_taglo(); /* PA[35:12] */ - tag[1].hi = read_c0_taghi(); /* PA[39:36] */ - } -#undef tag - - /* - * Save primary instruction cache (indexed by VA[13:6]) tags - * the same way. - */ - addr &= (0xffL << 56) | ((1 << 12) - 1); -#define tag cache_tags.tagi[i] - for (i = 0; i < 4; ++i, addr += (1 << 12)) { - cache_op(Index_Load_Tag_I, addr); - tag[0].lo = read_c0_taglo(); /* PA[35:12] */ - tag[0].hi = read_c0_taghi(); /* PA[39:36] */ - cache_op(Index_Load_Tag_I, addr | 1L); - tag[1].lo = read_c0_taglo(); /* PA[35:12] */ - tag[1].hi = read_c0_taghi(); /* PA[39:36] */ - } -#undef tag -} - -#define GIO_ERRMASK 0xff00 -#define CPU_ERRMASK 0x3f00 - -static void save_and_clear_buserr(void) -{ - int i; - - /* save status registers */ - cpu_err_addr = sgimc->cerr; - cpu_err_stat = sgimc->cstat; - gio_err_addr = sgimc->gerr; - gio_err_stat = sgimc->gstat; - extio_stat = sgioc->extio; - hpc3_berr_stat = hpc3c0->bestat; - - hpc3.scsi[0].addr = (unsigned long)&hpc3c0->scsi_chan0; - hpc3.scsi[0].ctrl = hpc3c0->scsi_chan0.ctrl; /* HPC3_SCTRL_ACTIVE ? */ - hpc3.scsi[0].cbp = hpc3c0->scsi_chan0.cbptr; - hpc3.scsi[0].ndptr = hpc3c0->scsi_chan0.ndptr; - - hpc3.scsi[1].addr = (unsigned long)&hpc3c0->scsi_chan1; - hpc3.scsi[1].ctrl = hpc3c0->scsi_chan1.ctrl; /* HPC3_SCTRL_ACTIVE ? */ - hpc3.scsi[1].cbp = hpc3c0->scsi_chan1.cbptr; - hpc3.scsi[1].ndptr = hpc3c0->scsi_chan1.ndptr; - - hpc3.ethrx.addr = (unsigned long)&hpc3c0->ethregs.rx_cbptr; - hpc3.ethrx.ctrl = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */ - hpc3.ethrx.cbp = hpc3c0->ethregs.rx_cbptr; - hpc3.ethrx.ndptr = hpc3c0->ethregs.rx_ndptr; - - hpc3.ethtx.addr = (unsigned long)&hpc3c0->ethregs.tx_cbptr; - hpc3.ethtx.ctrl = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */ - hpc3.ethtx.cbp = hpc3c0->ethregs.tx_cbptr; - hpc3.ethtx.ndptr = hpc3c0->ethregs.tx_ndptr; - - for (i = 0; i < 8; ++i) { - /* HPC3_PDMACTRL_ISACT ? */ - hpc3.pbdma[i].addr = (unsigned long)&hpc3c0->pbdma[i]; - hpc3.pbdma[i].ctrl = hpc3c0->pbdma[i].pbdma_ctrl; - hpc3.pbdma[i].cbp = hpc3c0->pbdma[i].pbdma_bptr; - hpc3.pbdma[i].ndptr = hpc3c0->pbdma[i].pbdma_dptr; - } - i = 0; - if (gio_err_stat & CPU_ERRMASK) - i = gio_err_addr; - if (cpu_err_stat & CPU_ERRMASK) - i = cpu_err_addr; - save_cache_tags(i); - - sgimc->cstat = sgimc->gstat = 0; -} - -static void print_cache_tags(void) -{ - u32 scb, scw; - int i; - - printk(KERN_ERR "Cache tags @ %08x:\n", (unsigned)cache_tags.err_addr); - - /* PA[31:12] shifted to PTag0 (PA[35:12]) format */ - scw = (cache_tags.err_addr >> 4) & 0x0fffff00; - - scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 5) - 1); - for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */ - if ((cache_tags.tagd[i][0].lo & 0x0fffff00) != scw && - (cache_tags.tagd[i][1].lo & 0x0fffff00) != scw) - continue; - printk(KERN_ERR - "D: 0: %08x %08x, 1: %08x %08x (VA[13:5] %04x)\n", - cache_tags.tagd[i][0].hi, cache_tags.tagd[i][0].lo, - cache_tags.tagd[i][1].hi, cache_tags.tagd[i][1].lo, - scb | (1 << 12)*i); - } - scb = cache_tags.err_addr & ((1 << 12) - 1) & ~((1 << 6) - 1); - for (i = 0; i < 4; ++i) { /* for each possible VA[13:12] value */ - if ((cache_tags.tagi[i][0].lo & 0x0fffff00) != scw && - (cache_tags.tagi[i][1].lo & 0x0fffff00) != scw) - continue; - printk(KERN_ERR - "I: 0: %08x %08x, 1: %08x %08x (VA[13:6] %04x)\n", - cache_tags.tagi[i][0].hi, cache_tags.tagi[i][0].lo, - cache_tags.tagi[i][1].hi, cache_tags.tagi[i][1].lo, - scb | (1 << 12)*i); - } - i = read_c0_config(); - scb = i & (1 << 13) ? 7:6; /* scblksize = 2^[7..6] */ - scw = ((i >> 16) & 7) + 19 - 1; /* scwaysize = 2^[24..19] / 2 */ - - i = ((1 << scw) - 1) & ~((1 << scb) - 1); - printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x (PA[%u:%u] %05x)\n", - cache_tags.tags[0][0].hi, cache_tags.tags[0][0].lo, - cache_tags.tags[0][1].hi, cache_tags.tags[0][1].lo, - scw-1, scb, i & (unsigned)cache_tags.err_addr); -} - -static inline const char *cause_excode_text(int cause) -{ - static const char *txt[32] = - { "Interrupt", - "TLB modification", - "TLB (load or instruction fetch)", - "TLB (store)", - "Address error (load or instruction fetch)", - "Address error (store)", - "Bus error (instruction fetch)", - "Bus error (data: load or store)", - "Syscall", - "Breakpoint", - "Reserved instruction", - "Coprocessor unusable", - "Arithmetic Overflow", - "Trap", - "14", - "Floating-Point", - "16", "17", "18", "19", "20", "21", "22", - "Watch Hi/Lo", - "24", "25", "26", "27", "28", "29", "30", "31", - }; - return txt[(cause & 0x7c) >> 2]; -} - -static void print_buserr(const struct pt_regs *regs) -{ - const int field = 2 * sizeof(unsigned long); - int error = 0; - - if (extio_stat & EXTIO_MC_BUSERR) { - printk(KERN_ERR "MC Bus Error\n"); - error |= 1; - } - if (extio_stat & EXTIO_HPC3_BUSERR) { - printk(KERN_ERR "HPC3 Bus Error 0x%x:\n", - hpc3_berr_stat, - (hpc3_berr_stat & HPC3_BESTAT_PIDMASK) >> - HPC3_BESTAT_PIDSHIFT, - (hpc3_berr_stat & HPC3_BESTAT_CTYPE) ? "PIO" : "DMA", - hpc3_berr_stat & HPC3_BESTAT_BLMASK); - error |= 2; - } - if (extio_stat & EXTIO_EISA_BUSERR) { - printk(KERN_ERR "EISA Bus Error\n"); - error |= 4; - } - if (cpu_err_stat & CPU_ERRMASK) { - printk(KERN_ERR "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n", - cpu_err_stat, - cpu_err_stat & SGIMC_CSTAT_RD ? "RD " : "", - cpu_err_stat & SGIMC_CSTAT_PAR ? "PAR " : "", - cpu_err_stat & SGIMC_CSTAT_ADDR ? "ADDR " : "", - cpu_err_stat & SGIMC_CSTAT_SYSAD_PAR ? "SYSAD " : "", - cpu_err_stat & SGIMC_CSTAT_SYSCMD_PAR ? "SYSCMD " : "", - cpu_err_stat & SGIMC_CSTAT_BAD_DATA ? "BAD_DATA " : "", - cpu_err_addr); - error |= 8; - } - if (gio_err_stat & GIO_ERRMASK) { - printk(KERN_ERR "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x%08x\n", - gio_err_stat, - gio_err_stat & SGIMC_GSTAT_RD ? "RD " : "", - gio_err_stat & SGIMC_GSTAT_WR ? "WR " : "", - gio_err_stat & SGIMC_GSTAT_TIME ? "TIME " : "", - gio_err_stat & SGIMC_GSTAT_PROM ? "PROM " : "", - gio_err_stat & SGIMC_GSTAT_ADDR ? "ADDR " : "", - gio_err_stat & SGIMC_GSTAT_BC ? "BC " : "", - gio_err_stat & SGIMC_GSTAT_PIO_RD ? "PIO_RD " : "", - gio_err_stat & SGIMC_GSTAT_PIO_WR ? "PIO_WR " : "", - gio_err_addr); - error |= 16; - } - if (!error) - printk(KERN_ERR "MC: Hmm, didn't find any error condition.\n"); - else { - printk(KERN_ERR "CP0: config %08x, " - "MC: cpuctrl0/1: %08x/%05x, giopar: %04x\n" - "MC: cpu/gio_memacc: %08x/%05x, memcfg0/1: %08x/%08x\n", - read_c0_config(), - sgimc->cpuctrl0, sgimc->cpuctrl0, sgimc->giopar, - sgimc->cmacc, sgimc->gmacc, - sgimc->mconfig0, sgimc->mconfig1); - print_cache_tags(); - } - printk(KERN_ALERT "%s, epc == %0*lx, ra == %0*lx\n", - cause_excode_text(regs->cp0_cause), - field, regs->cp0_epc, field, regs->regs[31]); -} - -/* - * Check, whether MC's (virtual) DMA address caused the bus error. - * See "Virtual DMA Specification", Draft 1.5, Feb 13 1992, SGI - */ - -static int addr_is_ram(unsigned long addr, unsigned sz) -{ - int i; - - for (i = 0; i < boot_mem_map.nr_map; i++) { - unsigned long a = boot_mem_map.map[i].addr; - if (a <= addr && addr+sz <= a+boot_mem_map.map[i].size) - return 1; - } - return 0; -} - -static int check_microtlb(u32 hi, u32 lo, unsigned long vaddr) -{ - /* This is likely rather similar to correct code ;-) */ - - vaddr &= 0x7fffffff; /* Doc. states that top bit is ignored */ - - /* If tlb-entry is valid and VPN-high (bits [30:21] ?) matches... */ - if ((lo & 2) && (vaddr >> 21) == ((hi<<1) >> 22)) { - u32 ctl = sgimc->dma_ctrl; - if (ctl & 1) { - unsigned int pgsz = (ctl & 2) ? 14:12; /* 16k:4k */ - /* PTEIndex is VPN-low (bits [22:14]/[20:12] ?) */ - unsigned long pte = (lo >> 6) << 12; /* PTEBase */ - pte += 8*((vaddr >> pgsz) & 0x1ff); - if (addr_is_ram(pte, 8)) { - /* - * Note: Since DMA hardware does look up - * translation on its own, this PTE *must* - * match the TLB/EntryLo-register format ! - */ - unsigned long a = *(unsigned long *) - PHYS_TO_XKSEG_UNCACHED(pte); - a = (a & 0x3f) << 6; /* PFN */ - a += vaddr & ((1 << pgsz) - 1); - return (cpu_err_addr == a); - } - } - } - return 0; -} - -static int check_vdma_memaddr(void) -{ - if (cpu_err_stat & CPU_ERRMASK) { - u32 a = sgimc->maddronly; - - if (!(sgimc->dma_ctrl & 0x100)) /* Xlate-bit clear ? */ - return (cpu_err_addr == a); - - if (check_microtlb(sgimc->dtlb_hi0, sgimc->dtlb_lo0, a) || - check_microtlb(sgimc->dtlb_hi1, sgimc->dtlb_lo1, a) || - check_microtlb(sgimc->dtlb_hi2, sgimc->dtlb_lo2, a) || - check_microtlb(sgimc->dtlb_hi3, sgimc->dtlb_lo3, a)) - return 1; - } - return 0; -} - -static int check_vdma_gioaddr(void) -{ - if (gio_err_stat & GIO_ERRMASK) { - u32 a = sgimc->gio_dma_trans; - a = (sgimc->gmaddronly & ~a) | (sgimc->gio_dma_sbits & a); - return (gio_err_addr == a); - } - return 0; -} - -/* - * MC sends an interrupt whenever bus or parity errors occur. In addition, - * if the error happened during a CPU read, it also asserts the bus error - * pin on the R4K. Code in bus error handler save the MC bus error registers - * and then clear the interrupt when this happens. - */ - -static int ip28_be_interrupt(const struct pt_regs *regs) -{ - int i; - - save_and_clear_buserr(); - /* - * Try to find out, whether we got here by a mispredicted speculative - * load/store operation. If so, it's not fatal, we can go on. - */ - /* Any cause other than "Interrupt" (ExcCode 0) is fatal. */ - if (regs->cp0_cause & CAUSEF_EXCCODE) - goto mips_be_fatal; - - /* Any cause other than "Bus error interrupt" (IP6) is weird. */ - if ((regs->cp0_cause & CAUSEF_IP6) != CAUSEF_IP6) - goto mips_be_fatal; - - if (extio_stat & (EXTIO_HPC3_BUSERR | EXTIO_EISA_BUSERR)) - goto mips_be_fatal; - - /* Any state other than "Memory bus error" is fatal. */ - if (cpu_err_stat & CPU_ERRMASK & ~SGIMC_CSTAT_ADDR) - goto mips_be_fatal; - - /* GIO errors other than timeouts are fatal */ - if (gio_err_stat & GIO_ERRMASK & ~SGIMC_GSTAT_TIME) - goto mips_be_fatal; - - /* - * Now we have an asynchronous bus error, speculatively or DMA caused. - * Need to search all DMA descriptors for the error address. - */ - for (i = 0; i < sizeof(hpc3)/sizeof(struct hpc3_stat); ++i) { - struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i; - if ((cpu_err_stat & CPU_ERRMASK) && - (cpu_err_addr == hp->ndptr || cpu_err_addr == hp->cbp)) - break; - if ((gio_err_stat & GIO_ERRMASK) && - (gio_err_addr == hp->ndptr || gio_err_addr == hp->cbp)) - break; - } - if (i < sizeof(hpc3)/sizeof(struct hpc3_stat)) { - struct hpc3_stat *hp = (struct hpc3_stat *)&hpc3 + i; - printk(KERN_ERR "at DMA addresses: HPC3 @ %08lx:" - " ctl %08x, ndp %08x, cbp %08x\n", - CPHYSADDR(hp->addr), hp->ctrl, hp->ndptr, hp->cbp); - goto mips_be_fatal; - } - /* Check MC's virtual DMA stuff. */ - if (check_vdma_memaddr()) { - printk(KERN_ERR "at GIO DMA: mem address 0x%08x.\n", - sgimc->maddronly); - goto mips_be_fatal; - } - if (check_vdma_gioaddr()) { - printk(KERN_ERR "at GIO DMA: gio address 0x%08x.\n", - sgimc->gmaddronly); - goto mips_be_fatal; - } - /* A speculative bus error... */ - if (debug_be_interrupt) { - print_buserr(regs); - printk(KERN_ERR "discarded!\n"); - } - return MIPS_BE_DISCARD; - -mips_be_fatal: - print_buserr(regs); - return MIPS_BE_FATAL; -} - -void ip22_be_interrupt(int irq) -{ - const struct pt_regs *regs = get_irq_regs(); - - count_be_interrupt++; - - if (ip28_be_interrupt(regs) != MIPS_BE_DISCARD) { - /* Assume it would be too dangerous to continue ... */ - die_if_kernel("Oops", regs); - force_sig(SIGBUS, current); - } else if (debug_be_interrupt) - show_regs((struct pt_regs *)regs); -} - -static int ip28_be_handler(struct pt_regs *regs, int is_fixup) -{ - /* - * We arrive here only in the unusual case of do_be() invocation, - * i.e. by a bus error exception without a bus error interrupt. - */ - if (is_fixup) { - count_be_is_fixup++; - save_and_clear_buserr(); - return MIPS_BE_FIXUP; - } - count_be_handler++; - return ip28_be_interrupt(regs); -} - -void __init ip22_be_init(void) -{ - board_be_handler = ip28_be_handler; -} - -int ip28_show_be_info(struct seq_file *m) -{ - seq_printf(m, "IP28 be fixups\t\t: %u\n", count_be_is_fixup); - seq_printf(m, "IP28 be interrupts\t: %u\n", count_be_interrupt); - seq_printf(m, "IP28 be handler\t\t: %u\n", count_be_handler); - - return 0; -} - -static int __init debug_be_setup(char *str) -{ - debug_be_interrupt++; - return 1; -} -__setup("ip28_debug_be", debug_be_setup); diff --git a/trunk/arch/mips/sgi-ip27/ip27-init.c b/trunk/arch/mips/sgi-ip27/ip27-init.c index a49e7c85f724..3305fa9ae66d 100644 --- a/trunk/arch/mips/sgi-ip27/ip27-init.c +++ b/trunk/arch/mips/sgi-ip27/ip27-init.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/mips/sgi-ip27/ip27-klnuma.c b/trunk/arch/mips/sgi-ip27/ip27-klnuma.c index 48932ce1d730..f10d9839006d 100644 --- a/trunk/arch/mips/sgi-ip27/ip27-klnuma.c +++ b/trunk/arch/mips/sgi-ip27/ip27-klnuma.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include diff --git a/trunk/arch/mips/sgi-ip27/ip27-smp.c b/trunk/arch/mips/sgi-ip27/ip27-smp.c index f15fc93d6b35..a70656d42191 100644 --- a/trunk/arch/mips/sgi-ip27/ip27-smp.c +++ b/trunk/arch/mips/sgi-ip27/ip27-smp.c @@ -140,51 +140,30 @@ static __init void intr_clear_all(nasid_t nasid) REMOTE_HUB_CLR_INTR(nasid, i); } -static void ip27_send_ipi_single(int destid, unsigned int action) +void __init plat_smp_setup(void) { - int irq; + cnodeid_t cnode; - switch (action) { - case SMP_RESCHEDULE_YOURSELF: - irq = CPU_RESCHED_A_IRQ; - break; - case SMP_CALL_FUNCTION: - irq = CPU_CALL_A_IRQ; - break; - default: - panic("sendintr"); + for_each_online_node(cnode) { + if (cnode == 0) + continue; + intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); } - irq += cputoslice(destid); + replicate_kernel_text(); /* - * Convert the compact hub number to the NASID to get the correct - * part of the address space. Then set the interrupt bit associated - * with the CPU we want to send the interrupt to. + * Assumption to be fixed: we're always booted on logical / physical + * processor 0. While we're always running on logical processor 0 + * this still means this is physical processor zero; it might for + * example be disabled in the firwware. */ - REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cpu_to_node(destid)), irq); -} - -static void ip27_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; - - for_each_cpu_mask(i, mask) - ip27_send_ipi_single(i, action); -} - -static void __cpuinit ip27_init_secondary(void) -{ - per_cpu_init(); - local_irq_enable(); -} - -static void __cpuinit ip27_smp_finish(void) -{ + alloc_cpupda(0, 0); } -static void __init ip27_cpus_done(void) +void __init plat_prepare_cpus(unsigned int max_cpus) { + /* We already did everything necessary earlier */ } /* @@ -192,7 +171,7 @@ static void __init ip27_cpus_done(void) * set sp to the kernel stack of the newly created idle process, gp to the proc * struct so that current_thread_info() will work. */ -static void __cpuinit ip27_boot_secondary(int cpu, struct task_struct *idle) +void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) { unsigned long gp = (unsigned long)task_thread_info(idle); unsigned long sp = __KSTK_TOS(idle); @@ -202,39 +181,41 @@ static void __cpuinit ip27_boot_secondary(int cpu, struct task_struct *idle) 0, (void *) sp, (void *) gp); } -static void __init ip27_smp_setup(void) +void __cpuinit prom_init_secondary(void) { - cnodeid_t cnode; + per_cpu_init(); + local_irq_enable(); +} - for_each_online_node(cnode) { - if (cnode == 0) - continue; - intr_clear_all(COMPACT_TO_NASID_NODEID(cnode)); +void __init prom_cpus_done(void) +{ +} + +void __cpuinit prom_smp_finish(void) +{ +} + +void core_send_ipi(int destid, unsigned int action) +{ + int irq; + + switch (action) { + case SMP_RESCHEDULE_YOURSELF: + irq = CPU_RESCHED_A_IRQ; + break; + case SMP_CALL_FUNCTION: + irq = CPU_CALL_A_IRQ; + break; + default: + panic("sendintr"); } - replicate_kernel_text(); + irq += cputoslice(destid); /* - * Assumption to be fixed: we're always booted on logical / physical - * processor 0. While we're always running on logical processor 0 - * this still means this is physical processor zero; it might for - * example be disabled in the firwware. + * Convert the compact hub number to the NASID to get the correct + * part of the address space. Then set the interrupt bit associated + * with the CPU we want to send the interrupt to. */ - alloc_cpupda(0, 0); -} - -static void __init ip27_prepare_cpus(unsigned int max_cpus) -{ - /* We already did everything necessary earlier */ + REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cpu_to_node(destid)), irq); } - -struct plat_smp_ops ip27_smp_ops = { - .send_ipi_single = ip27_send_ipi_single, - .send_ipi_mask = ip27_send_ipi_mask, - .init_secondary = ip27_init_secondary, - .smp_finish = ip27_smp_finish, - .cpus_done = ip27_cpus_done, - .boot_secondary = ip27_boot_secondary, - .smp_setup = ip27_smp_setup, - .prepare_cpus = ip27_prepare_cpus, -}; diff --git a/trunk/arch/mips/sibyte/bcm1480/smp.c b/trunk/arch/mips/sibyte/bcm1480/smp.c index 183c460b9ca1..436ba78359ab 100644 --- a/trunk/arch/mips/sibyte/bcm1480/smp.c +++ b/trunk/arch/mips/sibyte/bcm1480/smp.c @@ -23,7 +23,6 @@ #include #include -#include #include #include #include @@ -68,114 +67,28 @@ void __cpuinit bcm1480_smp_init(void) change_c0_status(ST0_IM, imask); } -/* - * These are routines for dealing with the sb1250 smp capabilities - * independent of board/firmware - */ - -/* - * Simple enough; everything is set up, so just poke the appropriate mailbox - * register, and we should be set - */ -static void bcm1480_send_ipi_single(int cpu, unsigned int action) -{ - __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); -} - -static void bcm1480_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; - - for_each_cpu_mask(i, mask) - bcm1480_send_ipi_single(i, action); -} - -/* - * Code to run on secondary just after probing the CPU - */ -static void __cpuinit bcm1480_init_secondary(void) -{ - extern void bcm1480_smp_init(void); - - bcm1480_smp_init(); -} - -/* - * Do any tidying up before marking online and running the idle - * loop - */ -static void __cpuinit bcm1480_smp_finish(void) +void __cpuinit bcm1480_smp_finish(void) { extern void sb1480_clockevent_init(void); sb1480_clockevent_init(); local_irq_enable(); - bcm1480_smp_finish(); } /* - * Final cleanup after all secondaries booted - */ -static void bcm1480_cpus_done(void) -{ -} - -/* - * Setup the PC, SP, and GP of a secondary processor and start it - * running! + * These are routines for dealing with the sb1250 smp capabilities + * independent of board/firmware */ -static void __cpuinit bcm1480_boot_secondary(int cpu, struct task_struct *idle) -{ - int retval; - - retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, - __KSTK_TOS(idle), - (unsigned long)task_thread_info(idle), 0); - if (retval != 0) - printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); -} /* - * Use CFE to find out how many CPUs are available, setting up - * phys_cpu_present_map and the logical/physical mappings. - * XXXKW will the boot CPU ever not be physical 0? - * - * Common setup before any secondaries are started + * Simple enough; everything is set up, so just poke the appropriate mailbox + * register, and we should be set */ -static void __init bcm1480_smp_setup(void) -{ - int i, num; - - cpus_clear(phys_cpu_present_map); - cpu_set(0, phys_cpu_present_map); - __cpu_number_map[0] = 0; - __cpu_logical_map[0] = 0; - - for (i = 1, num = 0; i < NR_CPUS; i++) { - if (cfe_cpu_stop(i) == 0) { - cpu_set(i, phys_cpu_present_map); - __cpu_number_map[i] = ++num; - __cpu_logical_map[num] = i; - } - } - printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); -} - -static void __init bcm1480_prepare_cpus(unsigned int max_cpus) +void core_send_ipi(int cpu, unsigned int action) { + __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); } -struct plat_smp_ops bcm1480_smp_ops = { - .send_ipi_single = bcm1480_send_ipi_single, - .send_ipi_mask = bcm1480_send_ipi_mask, - .init_secondary = bcm1480_init_secondary, - .smp_finish = bcm1480_smp_finish, - .cpus_done = bcm1480_cpus_done, - .boot_secondary = bcm1480_boot_secondary, - .smp_setup = bcm1480_smp_setup, - .prepare_cpus = bcm1480_prepare_cpus, -}; - void bcm1480_mailbox_interrupt(void) { int cpu = smp_processor_id(); diff --git a/trunk/arch/mips/sibyte/cfe/Makefile b/trunk/arch/mips/sibyte/cfe/Makefile index 02b32e142adf..a1214937b705 100644 --- a/trunk/arch/mips/sibyte/cfe/Makefile +++ b/trunk/arch/mips/sibyte/cfe/Makefile @@ -1,2 +1,3 @@ lib-y = setup.o +lib-$(CONFIG_SMP) += smp.o lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o diff --git a/trunk/arch/mips/sibyte/cfe/setup.c b/trunk/arch/mips/sibyte/cfe/setup.c index 33fce826f8bf..dbd6e6fdd3f9 100644 --- a/trunk/arch/mips/sibyte/cfe/setup.c +++ b/trunk/arch/mips/sibyte/cfe/setup.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -233,9 +232,6 @@ static int __init initrd_setup(char *str) #endif -extern struct plat_smp_ops sb_smp_ops; -extern struct plat_smp_ops bcm1480_smp_ops; - /* * prom_init is called just after the cpu type is determined, from setup_arch() */ @@ -301,6 +297,9 @@ void __init prom_init(void) * command line */ strcpy(arcs_cmdline, "root=/dev/ram0 "); +#ifdef CONFIG_SIBYTE_PTSWARM + strcat(arcs_cmdline, "console=ttyS0,115200 "); +#endif } else { /* The loader should have set the command line */ /* too early for panic to do any good */ @@ -341,13 +340,6 @@ void __init prom_init(void) arcs_cmdline[CL_SIZE-1] = 0; prom_meminit(); - -#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) - register_smp_ops(&sb_smp_ops); -#endif -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) - register_smp_ops(&bcm1480_smp_ops); -#endif } void __init prom_free_prom_memory(void) diff --git a/trunk/arch/mips/sibyte/cfe/smp.c b/trunk/arch/mips/sibyte/cfe/smp.c new file mode 100644 index 000000000000..534a62912f21 --- /dev/null +++ b/trunk/arch/mips/sibyte/cfe/smp.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include + +#include +#include + +/* + * Use CFE to find out how many CPUs are available, setting up + * phys_cpu_present_map and the logical/physical mappings. + * XXXKW will the boot CPU ever not be physical 0? + * + * Common setup before any secondaries are started + */ +void __init plat_smp_setup(void) +{ + int i, num; + + cpus_clear(phys_cpu_present_map); + cpu_set(0, phys_cpu_present_map); + __cpu_number_map[0] = 0; + __cpu_logical_map[0] = 0; + + for (i = 1, num = 0; i < NR_CPUS; i++) { + if (cfe_cpu_stop(i) == 0) { + cpu_set(i, phys_cpu_present_map); + __cpu_number_map[i] = ++num; + __cpu_logical_map[num] = i; + } + } + printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); +} + +void __init plat_prepare_cpus(unsigned int max_cpus) +{ +} + +/* + * Setup the PC, SP, and GP of a secondary processor and start it + * running! + */ +void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle) +{ + int retval; + + retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, + __KSTK_TOS(idle), + (unsigned long)task_thread_info(idle), 0); + if (retval != 0) + printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); +} + +/* + * Code to run on secondary just after probing the CPU + */ +void __cpuinit prom_init_secondary(void) +{ +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + extern void bcm1480_smp_init(void); + bcm1480_smp_init(); +#elif defined(CONFIG_SIBYTE_SB1250) + extern void sb1250_smp_init(void); + sb1250_smp_init(); +#else +#error invalid SMP configuration +#endif +} + +/* + * Do any tidying up before marking online and running the idle + * loop + */ +void __cpuinit prom_smp_finish(void) +{ +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + extern void bcm1480_smp_finish(void); + bcm1480_smp_finish(); +#elif defined(CONFIG_SIBYTE_SB1250) + extern void sb1250_smp_finish(void); + sb1250_smp_finish(); +#else +#error invalid SMP configuration +#endif +} + +/* + * Final cleanup after all secondaries booted + */ +void prom_cpus_done(void) +{ +} diff --git a/trunk/arch/mips/sibyte/sb1250/smp.c b/trunk/arch/mips/sibyte/sb1250/smp.c index 0734b933e969..3f52c95a4eb8 100644 --- a/trunk/arch/mips/sibyte/sb1250/smp.c +++ b/trunk/arch/mips/sibyte/sb1250/smp.c @@ -24,7 +24,6 @@ #include #include -#include #include #include #include @@ -56,43 +55,7 @@ void __cpuinit sb1250_smp_init(void) change_c0_status(ST0_IM, imask); } -/* - * These are routines for dealing with the sb1250 smp capabilities - * independent of board/firmware - */ - -/* - * Simple enough; everything is set up, so just poke the appropriate mailbox - * register, and we should be set - */ -static void sb1250_send_ipi_single(int cpu, unsigned int action) -{ - __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); -} - -static inline void sb1250_send_ipi_mask(cpumask_t mask, unsigned int action) -{ - unsigned int i; - - for_each_cpu_mask(i, mask) - sb1250_send_ipi_single(i, action); -} - -/* - * Code to run on secondary just after probing the CPU - */ -static void __cpuinit sb1250_init_secondary(void) -{ - extern void sb1250_smp_init(void); - - sb1250_smp_init(); -} - -/* - * Do any tidying up before marking online and running the idle - * loop - */ -static void __cpuinit sb1250_smp_finish(void) +void __cpuinit sb1250_smp_finish(void) { extern void sb1250_clockevent_init(void); @@ -101,68 +64,19 @@ static void __cpuinit sb1250_smp_finish(void) } /* - * Final cleanup after all secondaries booted - */ -static void sb1250_cpus_done(void) -{ -} - -/* - * Setup the PC, SP, and GP of a secondary processor and start it - * running! + * These are routines for dealing with the sb1250 smp capabilities + * independent of board/firmware */ -static void __cpuinit sb1250_boot_secondary(int cpu, struct task_struct *idle) -{ - int retval; - - retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, - __KSTK_TOS(idle), - (unsigned long)task_thread_info(idle), 0); - if (retval != 0) - printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); -} /* - * Use CFE to find out how many CPUs are available, setting up - * phys_cpu_present_map and the logical/physical mappings. - * XXXKW will the boot CPU ever not be physical 0? - * - * Common setup before any secondaries are started + * Simple enough; everything is set up, so just poke the appropriate mailbox + * register, and we should be set */ -static void __init sb1250_smp_setup(void) -{ - int i, num; - - cpus_clear(phys_cpu_present_map); - cpu_set(0, phys_cpu_present_map); - __cpu_number_map[0] = 0; - __cpu_logical_map[0] = 0; - - for (i = 1, num = 0; i < NR_CPUS; i++) { - if (cfe_cpu_stop(i) == 0) { - cpu_set(i, phys_cpu_present_map); - __cpu_number_map[i] = ++num; - __cpu_logical_map[num] = i; - } - } - printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); -} - -static void __init sb1250_prepare_cpus(unsigned int max_cpus) +void core_send_ipi(int cpu, unsigned int action) { + __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); } -struct plat_smp_ops sb_smp_ops = { - .send_ipi_single = sb1250_send_ipi_single, - .send_ipi_mask = sb1250_send_ipi_mask, - .init_secondary = sb1250_init_secondary, - .smp_finish = sb1250_smp_finish, - .cpus_done = sb1250_cpus_done, - .boot_secondary = sb1250_boot_secondary, - .smp_setup = sb1250_smp_setup, - .prepare_cpus = sb1250_prepare_cpus, -}; - void sb1250_mailbox_interrupt(void) { int cpu = smp_processor_id(); diff --git a/trunk/arch/mips/sni/Makefile b/trunk/arch/mips/sni/Makefile index a7dbeebe7fe6..3a99cd62c0bd 100644 --- a/trunk/arch/mips/sni/Makefile +++ b/trunk/arch/mips/sni/Makefile @@ -3,6 +3,6 @@ # obj-y += irq.o reset.o setup.o a20r.o rm200.o pcimt.o pcit.o time.o -obj-$(CONFIG_EISA) += eisa.o +obj-$(CONFIG_CPU_BIG_ENDIAN) += sniprom.o EXTRA_CFLAGS += -Werror diff --git a/trunk/arch/mips/sni/a20r.c b/trunk/arch/mips/sni/a20r.c index 3f8cf5eb2f06..b74607599971 100644 --- a/trunk/arch/mips/sni/a20r.c +++ b/trunk/arch/mips/sni/a20r.c @@ -117,19 +117,10 @@ static struct resource sc26xx_rsrc[] = { } }; -static unsigned int sc26xx_data[2] = { - /* DTR | RTS | DSR | CTS | DCD | RI */ - (8 << 0) | (4 << 4) | (6 << 8) | (0 << 12) | (6 << 16) | (0 << 20), - (3 << 0) | (2 << 4) | (1 << 8) | (2 << 12) | (3 << 16) | (4 << 20) -}; - static struct platform_device sc26xx_pdev = { .name = "SC26xx", .num_resources = ARRAY_SIZE(sc26xx_rsrc), - .resource = sc26xx_rsrc, - .dev = { - .platform_data = sc26xx_data, - } + .resource = sc26xx_rsrc }; static u32 a20r_ack_hwint(void) @@ -240,9 +231,9 @@ static int __init snirm_a20r_setup_devinit(void) platform_device_register(&sc26xx_pdev); platform_device_register(&a20r_serial8250_device); platform_device_register(&a20r_ds1216_device); - sni_eisa_root_init(); break; } + return 0; } diff --git a/trunk/arch/mips/sni/eisa.c b/trunk/arch/mips/sni/eisa.c deleted file mode 100644 index 7396cd719900..000000000000 --- a/trunk/arch/mips/sni/eisa.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Virtual EISA root driver. - * Acts as a placeholder if we don't have a proper EISA bridge. - * - * (C) 2003 Marc Zyngier - * modified for SNI usage by Thomas Bogendoerfer - * - * This code is released under the GPL version 2. - */ - -#include -#include -#include -#include - -/* The default EISA device parent (virtual root device). - * Now use a platform device, since that's the obvious choice. */ - -static struct platform_device eisa_root_dev = { - .name = "eisa", - .id = 0, -}; - -static struct eisa_root_device eisa_bus_root = { - .dev = &eisa_root_dev.dev, - .bus_base_addr = 0, - .res = &ioport_resource, - .slots = EISA_MAX_SLOTS, - .dma_mask = 0xffffffff, - .force_probe = 1, -}; - -int __init sni_eisa_root_init(void) -{ - int r; - - r = platform_device_register(&eisa_root_dev); - if (!r) - return r; - - eisa_root_dev.dev.driver_data = &eisa_bus_root; - - if (eisa_root_register(&eisa_bus_root)) { - /* A real bridge may have been registered before - * us. So quietly unregister. */ - platform_device_unregister(&eisa_root_dev); - return -1; - } - return 0; -} diff --git a/trunk/arch/mips/sni/irq.c b/trunk/arch/mips/sni/irq.c index e8e72bb3a9af..9ccffdfb8289 100644 --- a/trunk/arch/mips/sni/irq.c +++ b/trunk/arch/mips/sni/irq.c @@ -35,14 +35,14 @@ static irqreturn_t sni_isa_irq_handler(int dummy, void *p) if (unlikely(irq < 0)) return IRQ_NONE; - generic_handle_irq(irq); + do_IRQ(irq); return IRQ_HANDLED; } struct irqaction sni_isa_irq = { .handler = sni_isa_irq_handler, .name = "ISA", - .flags = IRQF_SHARED | IRQF_DISABLED + .flags = IRQF_SHARED }; /* diff --git a/trunk/arch/mips/sni/pcit.c b/trunk/arch/mips/sni/pcit.c index e5f12cf96e8e..416f397c768b 100644 --- a/trunk/arch/mips/sni/pcit.c +++ b/trunk/arch/mips/sni/pcit.c @@ -76,11 +76,6 @@ static struct platform_device pcit_cmos_device = { .resource = pcit_cmos_rsrc }; -static struct platform_device pcit_pcspeaker_pdev = { - .name = "pcspkr", - .id = -1, -}; - static struct resource sni_io_resource = { .start = 0x00000000UL, .end = 0x03bfffffUL, @@ -282,13 +277,11 @@ static int __init snirm_pcit_setup_devinit(void) case SNI_BRD_PCI_TOWER: platform_device_register(&pcit_serial8250_device); platform_device_register(&pcit_cmos_device); - platform_device_register(&pcit_pcspeaker_pdev); break; case SNI_BRD_PCI_TOWER_CPLUS: platform_device_register(&pcit_cplus_serial8250_device); platform_device_register(&pcit_cmos_device); - platform_device_register(&pcit_pcspeaker_pdev); break; } return 0; diff --git a/trunk/arch/mips/sni/rm200.c b/trunk/arch/mips/sni/rm200.c index 5310aa75afa4..67b061eef6cd 100644 --- a/trunk/arch/mips/sni/rm200.c +++ b/trunk/arch/mips/sni/rm200.c @@ -5,36 +5,30 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2006,2007 Thomas Bogendoerfer (tsbogend@alpha.franken.de) - * - * i8259 parts ripped out of arch/mips/kernel/i8259.c + * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) */ -#include #include #include #include #include -#include #include #include #include -#define RM200_I8259A_IRQ_BASE 32 - -#define MEMPORT(_base,_irq) \ +#define PORT(_base,_irq) \ { \ - .mapbase = _base, \ + .iobase = _base, \ .irq = _irq, \ .uartclk = 1843200, \ - .iotype = UPIO_MEM, \ - .flags = UPF_BOOT_AUTOCONF|UPF_IOREMAP, \ + .iotype = UPIO_PORT, \ + .flags = UPF_BOOT_AUTOCONF, \ } static struct plat_serial8250_port rm200_data[] = { - MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4), - MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3), + PORT(0x3f8, 4), + PORT(0x2f8, 3), { }, }; @@ -118,311 +112,15 @@ static int __init snirm_setup_devinit(void) platform_device_register(&rm200_ds1216_device); platform_device_register(&snirm_82596_rm200_pdev); platform_device_register(&snirm_53c710_rm200_pdev); - sni_eisa_root_init(); } return 0; } device_initcall(snirm_setup_devinit); -/* - * RM200 has an ISA and an EISA bus. The iSA bus is only used - * for onboard devices and also has twi i8259 PICs. Since these - * PICs are no accessible via inb/outb the following code uses - * readb/writeb to access them - */ - -DEFINE_SPINLOCK(sni_rm200_i8259A_lock); -#define PIC_CMD 0x00 -#define PIC_IMR 0x01 -#define PIC_ISR PIC_CMD -#define PIC_POLL PIC_ISR -#define PIC_OCW3 PIC_ISR - -/* i8259A PIC related value */ -#define PIC_CASCADE_IR 2 -#define MASTER_ICW4_DEFAULT 0x01 -#define SLAVE_ICW4_DEFAULT 0x01 - -/* - * This contains the irq mask for both 8259A irq controllers, - */ -static unsigned int rm200_cached_irq_mask = 0xffff; -static __iomem u8 *rm200_pic_master; -static __iomem u8 *rm200_pic_slave; - -#define cached_master_mask (rm200_cached_irq_mask) -#define cached_slave_mask (rm200_cached_irq_mask >> 8) - -static void sni_rm200_disable_8259A_irq(unsigned int irq) -{ - unsigned int mask; - unsigned long flags; - - irq -= RM200_I8259A_IRQ_BASE; - mask = 1 << irq; - spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); - rm200_cached_irq_mask |= mask; - if (irq & 8) - writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); - else - writeb(cached_master_mask, rm200_pic_master + PIC_IMR); - spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); -} - -static void sni_rm200_enable_8259A_irq(unsigned int irq) -{ - unsigned int mask; - unsigned long flags; - - irq -= RM200_I8259A_IRQ_BASE; - mask = ~(1 << irq); - spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); - rm200_cached_irq_mask &= mask; - if (irq & 8) - writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); - else - writeb(cached_master_mask, rm200_pic_master + PIC_IMR); - spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); -} - -static inline int sni_rm200_i8259A_irq_real(unsigned int irq) -{ - int value; - int irqmask = 1 << irq; - - if (irq < 8) { - writeb(0x0B, rm200_pic_master + PIC_CMD); - value = readb(rm200_pic_master + PIC_CMD) & irqmask; - writeb(0x0A, rm200_pic_master + PIC_CMD); - return value; - } - writeb(0x0B, rm200_pic_slave + PIC_CMD); /* ISR register */ - value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8); - writeb(0x0A, rm200_pic_slave + PIC_CMD); - return value; -} - -/* - * Careful! The 8259A is a fragile beast, it pretty - * much _has_ to be done exactly like this (mask it - * first, _then_ send the EOI, and the order of EOI - * to the two 8259s is important! - */ -void sni_rm200_mask_and_ack_8259A(unsigned int irq) -{ - unsigned int irqmask; - unsigned long flags; - - irq -= RM200_I8259A_IRQ_BASE; - irqmask = 1 << irq; - spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); - /* - * Lightweight spurious IRQ detection. We do not want - * to overdo spurious IRQ handling - it's usually a sign - * of hardware problems, so we only do the checks we can - * do without slowing down good hardware unnecessarily. - * - * Note that IRQ7 and IRQ15 (the two spurious IRQs - * usually resulting from the 8259A-1|2 PICs) occur - * even if the IRQ is masked in the 8259A. Thus we - * can check spurious 8259A IRQs without doing the - * quite slow i8259A_irq_real() call for every IRQ. - * This does not cover 100% of spurious interrupts, - * but should be enough to warn the user that there - * is something bad going on ... - */ - if (rm200_cached_irq_mask & irqmask) - goto spurious_8259A_irq; - rm200_cached_irq_mask |= irqmask; - -handle_real_irq: - if (irq & 8) { - readb(rm200_pic_slave + PIC_IMR); - writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); - writeb(0x60+(irq & 7), rm200_pic_slave + PIC_CMD); - writeb(0x60+PIC_CASCADE_IR, rm200_pic_master + PIC_CMD); - } else { - readb(rm200_pic_master + PIC_IMR); - writeb(cached_master_mask, rm200_pic_master + PIC_IMR); - writeb(0x60+irq, rm200_pic_master + PIC_CMD); - } - spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); - return; - -spurious_8259A_irq: - /* - * this is the slow path - should happen rarely. - */ - if (sni_rm200_i8259A_irq_real(irq)) - /* - * oops, the IRQ _is_ in service according to the - * 8259A - not spurious, go handle it. - */ - goto handle_real_irq; - - { - static int spurious_irq_mask; - /* - * At this point we can be sure the IRQ is spurious, - * lets ACK and report it. [once per IRQ] - */ - if (!(spurious_irq_mask & irqmask)) { - printk(KERN_DEBUG - "spurious RM200 8259A interrupt: IRQ%d.\n", irq); - spurious_irq_mask |= irqmask; - } - atomic_inc(&irq_err_count); - /* - * Theoretically we do not have to handle this IRQ, - * but in Linux this does not cause problems and is - * simpler for us. - */ - goto handle_real_irq; - } -} - -static struct irq_chip sni_rm200_i8259A_chip = { - .name = "RM200-XT-PIC", - .mask = sni_rm200_disable_8259A_irq, - .unmask = sni_rm200_enable_8259A_irq, - .mask_ack = sni_rm200_mask_and_ack_8259A, -}; - -/* - * Do the traditional i8259 interrupt polling thing. This is for the few - * cases where no better interrupt acknowledge method is available and we - * absolutely must touch the i8259. - */ -static inline int sni_rm200_i8259_irq(void) -{ - int irq; - - spin_lock(&sni_rm200_i8259A_lock); - - /* Perform an interrupt acknowledge cycle on controller 1. */ - writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */ - irq = readb(rm200_pic_master + PIC_CMD) & 7; - if (irq == PIC_CASCADE_IR) { - /* - * Interrupt is cascaded so perform interrupt - * acknowledge on controller 2. - */ - writeb(0x0C, rm200_pic_slave + PIC_CMD); /* prepare for poll */ - irq = (readb(rm200_pic_slave + PIC_CMD) & 7) + 8; - } - - if (unlikely(irq == 7)) { - /* - * This may be a spurious interrupt. - * - * Read the interrupt status register (ISR). If the most - * significant bit is not set then there is no valid - * interrupt. - */ - writeb(0x0B, rm200_pic_master + PIC_ISR); /* ISR register */ - if (~readb(rm200_pic_master + PIC_ISR) & 0x80) - irq = -1; - } - - spin_unlock(&sni_rm200_i8259A_lock); - - return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq; -} - -void sni_rm200_init_8259A(void) -{ - unsigned long flags; - - spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); - - writeb(0xff, rm200_pic_master + PIC_IMR); - writeb(0xff, rm200_pic_slave + PIC_IMR); - - writeb(0x11, rm200_pic_master + PIC_CMD); - writeb(0, rm200_pic_master + PIC_IMR); - writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR); - writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR); - writeb(0x11, rm200_pic_slave + PIC_CMD); - writeb(8, rm200_pic_slave + PIC_IMR); - writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR); - writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR); - udelay(100); /* wait for 8259A to initialize */ - - writeb(cached_master_mask, rm200_pic_master + PIC_IMR); - writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); - - spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); -} - -/* - * IRQ2 is cascade interrupt to second interrupt controller - */ -static struct irqaction sni_rm200_irq2 = { - no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL -}; - -static struct resource sni_rm200_pic1_resource = { - .name = "onboard ISA pic1", - .start = 0x16000020, - .end = 0x16000023, - .flags = IORESOURCE_BUSY -}; - -static struct resource sni_rm200_pic2_resource = { - .name = "onboard ISA pic2", - .start = 0x160000a0, - .end = 0x160000a3, - .flags = IORESOURCE_BUSY -}; - -/* ISA irq handler */ -static irqreturn_t sni_rm200_i8259A_irq_handler(int dummy, void *p) -{ - int irq; - - irq = sni_rm200_i8259_irq(); - if (unlikely(irq < 0)) - return IRQ_NONE; - - do_IRQ(irq); - return IRQ_HANDLED; -} - -struct irqaction sni_rm200_i8259A_irq = { - .handler = sni_rm200_i8259A_irq_handler, - .name = "onboard ISA", - .flags = IRQF_SHARED -}; - -void __init sni_rm200_i8259_irqs(void) -{ - int i; - - rm200_pic_master = ioremap_nocache(0x16000020, 4); - if (!rm200_pic_master) - return; - rm200_pic_slave = ioremap_nocache(0x160000a0, 4); - if (!rm200_pic_master) { - iounmap(rm200_pic_master); - return; - } - - insert_resource(&iomem_resource, &sni_rm200_pic1_resource); - insert_resource(&iomem_resource, &sni_rm200_pic2_resource); - - sni_rm200_init_8259A(); - - for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++) - set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip, - handle_level_irq); - - setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2); -} - -#define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000) -#define SNI_RM200_INT_ENA_REG CKSEG1ADDR(0xbc080000) +#define SNI_RM200_INT_STAT_REG 0xbc000000 +#define SNI_RM200_INT_ENA_REG 0xbc080000 #define SNI_RM200_INT_START 24 #define SNI_RM200_INT_END 28 @@ -483,17 +181,17 @@ void __init sni_rm200_irq_init(void) * (volatile u8 *)SNI_RM200_INT_ENA_REG = 0x1f; - sni_rm200_i8259_irqs(); mips_cpu_irq_init(); /* Actually we've got more interrupts to handle ... */ for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) set_irq_chip(i, &rm200_irq_type); sni_hwint = sni_rm200_hwint; change_c0_status(ST0_IM, IE_IRQ0); - setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); - setup_irq(SNI_RM200_INT_START + 1, &sni_isa_irq); + setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq); } void __init sni_rm200_init(void) { + set_io_port_base(SNI_PORT_BASE + 0x02000000); + ioport_resource.end += 0x02000000; } diff --git a/trunk/arch/mips/sni/setup.c b/trunk/arch/mips/sni/setup.c index 5484e1c62054..e8b26bdee24c 100644 --- a/trunk/arch/mips/sni/setup.c +++ b/trunk/arch/mips/sni/setup.c @@ -19,17 +19,11 @@ #include #endif -#ifdef CONFIG_SNIPROM -#include -#endif - -#include #include #include #include unsigned int sni_brd_type; -EXPORT_SYMBOL(sni_brd_type); extern void sni_machine_restart(char *command); extern void sni_machine_power_off(void); @@ -53,152 +47,20 @@ static void __init sni_display_setup(void) #endif } -static void __init sni_console_setup(void) -{ -#ifndef CONFIG_ARC - char *ctype; - char *cdev; - char *baud; - int port; - static char options[8]; - - cdev = prom_getenv("console_dev"); - if (strncmp(cdev, "tty", 3) == 0) { - ctype = prom_getenv("console"); - switch (*ctype) { - default: - case 'l': - port = 0; - baud = prom_getenv("lbaud"); - break; - case 'r': - port = 1; - baud = prom_getenv("rbaud"); - break; - } - if (baud) - strcpy(options, baud); - if (strncmp(cdev, "tty552", 6) == 0) - add_preferred_console("ttyS", port, - baud ? options : NULL); - else - add_preferred_console("ttySC", port, - baud ? options : NULL); - } -#endif -} - -#ifdef DEBUG -static void __init sni_idprom_dump(void) -{ - int i; - - pr_debug("SNI IDProm dump:\n"); - for (i = 0; i < 256; i++) { - if (i%16 == 0) - pr_debug("%04x ", i); - - printk("%02x ", *(unsigned char *) (SNI_IDPROM_BASE + i)); - - if (i % 16 == 15) - printk("\n"); - } -} -#endif void __init plat_mem_setup(void) { - int cputype; - set_io_port_base(SNI_PORT_BASE); // ioport_resource.end = sni_io_resource.end; /* * Setup (E)ISA I/O memory access stuff */ - isa_slot_offset = CKSEG1ADDR(0xb0000000); + isa_slot_offset = 0xb0000000; #ifdef CONFIG_EISA EISA_bus = 1; #endif - sni_brd_type = *(unsigned char *)SNI_IDPROM_BRDTYPE; - cputype = *(unsigned char *)SNI_IDPROM_CPUTYPE; - switch (sni_brd_type) { - case SNI_BRD_TOWER_OASIC: - switch (cputype) { - case SNI_CPU_M8030: - system_type = "RM400-330"; - break; - case SNI_CPU_M8031: - system_type = "RM400-430"; - break; - case SNI_CPU_M8037: - system_type = "RM400-530"; - break; - case SNI_CPU_M8034: - system_type = "RM400-730"; - break; - default: - system_type = "RM400-xxx"; - break; - } - break; - case SNI_BRD_MINITOWER: - switch (cputype) { - case SNI_CPU_M8021: - case SNI_CPU_M8043: - system_type = "RM400-120"; - break; - case SNI_CPU_M8040: - system_type = "RM400-220"; - break; - case SNI_CPU_M8053: - system_type = "RM400-225"; - break; - case SNI_CPU_M8050: - system_type = "RM400-420"; - break; - default: - system_type = "RM400-xxx"; - break; - } - break; - case SNI_BRD_PCI_TOWER: - system_type = "RM400-Cxx"; - break; - case SNI_BRD_RM200: - system_type = "RM200-xxx"; - break; - case SNI_BRD_PCI_MTOWER: - system_type = "RM300-Cxx"; - break; - case SNI_BRD_PCI_DESKTOP: - switch (read_c0_prid() & 0xff00) { - case PRID_IMP_R4600: - case PRID_IMP_R4700: - system_type = "RM200-C20"; - break; - case PRID_IMP_R5000: - system_type = "RM200-C40"; - break; - default: - system_type = "RM200-Cxx"; - break; - } - break; - case SNI_BRD_PCI_TOWER_CPLUS: - system_type = "RM400-Exx"; - break; - case SNI_BRD_PCI_MTOWER_CPLUS: - system_type = "RM300-Exx"; - break; - } - pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, system_type); - -#ifdef DEBUG - sni_idprom_dump(); -#endif - switch (sni_brd_type) { case SNI_BRD_10: case SNI_BRD_10NEW: @@ -227,10 +89,9 @@ void __init plat_mem_setup(void) pm_power_off = sni_machine_power_off; sni_display_setup(); - sni_console_setup(); } -#ifdef CONFIG_PCI +#if CONFIG_PCI #include #include