From c5e0ee2fa0b7c67eeffe6dddd173b66d425bfe6f Mon Sep 17 00:00:00 2001
From: Florian Fainelli <florian@openwrt.org>
Date: Thu, 11 Jun 2009 13:21:24 +0100
Subject: [PATCH] --- yaml --- r: 146276 b: refs/heads/master c:
 08e0992f60ad44025a8a8b8a821838ca4a562686 h: refs/heads/master v: v3

---
 [refs]                            | 2 +-
 trunk/drivers/serial/8250.c       | 7 +++++++
 trunk/include/linux/serial_core.h | 3 ++-
 3 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 4610ca90a116..7bfd70ff4761 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 257a6e8cc7f9274f0af090494a3f1ee06548b5bd
+refs/heads/master: 08e0992f60ad44025a8a8b8a821838ca4a562686
diff --git a/trunk/drivers/serial/8250.c b/trunk/drivers/serial/8250.c
index a0127e93ade0..fb867a9f55e9 100644
--- a/trunk/drivers/serial/8250.c
+++ b/trunk/drivers/serial/8250.c
@@ -287,6 +287,13 @@ static const struct serial8250_config uart_config[] = {
 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 		.flags		= UART_CAP_FIFO,
 	},
+	[PORT_AR7] = {
+		.name		= "AR7",
+		.fifo_size	= 16,
+		.tx_loadsz	= 16,
+		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
+		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
+	},
 };
 
 #if defined (CONFIG_SERIAL_8250_AU1X00)
diff --git a/trunk/include/linux/serial_core.h b/trunk/include/linux/serial_core.h
index 57a97e52e58d..48766ea845cf 100644
--- a/trunk/include/linux/serial_core.h
+++ b/trunk/include/linux/serial_core.h
@@ -41,7 +41,8 @@
 #define PORT_XSCALE	15
 #define PORT_RM9000	16	/* PMC-Sierra RM9xxx internal UART */
 #define PORT_OCTEON	17	/* Cavium OCTEON internal UART */
-#define PORT_MAX_8250	17	/* max port ID */
+#define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
+#define PORT_MAX_8250	18	/* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed