From c6c9a89e516e446791304a6800ae9c340af6bb3c Mon Sep 17 00:00:00 2001 From: Al Viro Date: Wed, 16 Dec 2009 00:34:13 -0500 Subject: [PATCH] --- yaml --- r: 177381 b: refs/heads/master c: 853b3da10d617f08340e5fe569c99e7b54f2a568 h: refs/heads/master i: 177379: cc8486b95fc7874161c1bfad700a447ea284de79 v: v3 --- [refs] | 2 +- trunk/Documentation/Changes | 2 - trunk/Documentation/DocBook/Makefile | 38 +- .../Documentation/DocBook/media-entities.tmpl | 18 - .../Documentation/DocBook/media-indices.tmpl | 4 - trunk/Documentation/DocBook/procfs-guide.tmpl | 626 ++ trunk/Documentation/DocBook/procfs_example.c | 201 + trunk/Documentation/DocBook/v4l/common.xml | 35 - trunk/Documentation/DocBook/v4l/compat.xml | 16 +- trunk/Documentation/DocBook/v4l/v4l2.xml | 26 +- .../Documentation/DocBook/v4l/videodev2.h.xml | 116 +- .../DocBook/v4l/vidioc-enum-dv-presets.xml | 238 - .../DocBook/v4l/vidioc-enuminput.xml | 36 +- .../DocBook/v4l/vidioc-enumoutput.xml | 36 +- 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+- trunk/drivers/rtc/rtc-x1205.c | 53 +- trunk/drivers/serial/sh-sci.c | 54 +- trunk/drivers/sh/intc.c | 2 - trunk/drivers/sh/pfc.c | 2 +- .../staging/cx25821/cx25821-audups11.c | 33 +- trunk/drivers/staging/cx25821/cx25821-video.c | 6 +- .../drivers/staging/cx25821/cx25821-video0.c | 33 +- .../drivers/staging/cx25821/cx25821-video1.c | 33 +- .../drivers/staging/cx25821/cx25821-video2.c | 34 +- .../drivers/staging/cx25821/cx25821-video3.c | 34 +- .../drivers/staging/cx25821/cx25821-video4.c | 34 +- .../drivers/staging/cx25821/cx25821-video5.c | 34 +- .../drivers/staging/cx25821/cx25821-video6.c | 34 +- .../drivers/staging/cx25821/cx25821-video7.c | 34 +- .../staging/cx25821/cx25821-videoioctl.c | 32 +- .../staging/cx25821/cx25821-vidups10.c | 33 +- .../drivers/staging/cx25821/cx25821-vidups9.c | 33 +- trunk/drivers/staging/go7007/go7007-v4l2.c | 5 +- trunk/drivers/usb/host/isp1362-hcd.c | 26 +- trunk/drivers/video/Kconfig | 15 - trunk/drivers/video/Makefile | 1 - trunk/drivers/video/atafb.c | 3 - trunk/drivers/video/bfin-lq035q1-fb.c | 826 --- trunk/drivers/video/bfin-t350mcqb-fb.c | 32 +- trunk/drivers/video/clps711xfb.c | 50 +- trunk/drivers/video/da8xx-fb.c | 175 +- trunk/drivers/video/ep93xx-fb.c | 2 - trunk/drivers/video/geode/lxfb.h | 10 - trunk/drivers/video/i810/i810_dvt.c | 53 +- trunk/drivers/video/intelfb/intelfbdrv.c | 3 - trunk/drivers/video/intelfb/intelfbhw.c | 47 +- trunk/drivers/video/intelfb/intelfbhw.h | 1 - trunk/drivers/video/matrox/g450_pll.c | 3 +- trunk/drivers/video/maxinefb.c | 3 - trunk/drivers/video/mb862xx/Makefile | 2 +- trunk/drivers/video/mb862xx/mb862xxfb.c | 14 - trunk/drivers/video/mb862xx/mb862xxfb.h | 2 - trunk/drivers/video/mb862xx/mb862xxfb_accel.c | 331 -- trunk/drivers/video/mb862xx/mb862xxfb_accel.h | 203 - trunk/drivers/video/modedb.c | 24 +- trunk/drivers/video/pmag-ba-fb.c | 3 +- trunk/drivers/video/pmagb-b-fb.c | 3 +- trunk/drivers/video/pxafb.c | 5 +- trunk/drivers/video/sh_mobile_lcdcfb.c | 10 +- trunk/drivers/video/sis/sis_main.c | 2 +- trunk/drivers/video/sm501fb.c | 249 +- trunk/drivers/video/via/lcd.c | 40 +- trunk/drivers/video/via/viafbdev.c | 2 +- trunk/fs/aio.c | 40 +- trunk/fs/autofs4/autofs_i.h | 38 +- trunk/fs/autofs4/expire.c | 8 +- trunk/fs/autofs4/inode.c | 2 - trunk/fs/autofs4/root.c | 616 +- trunk/fs/binfmt_elf.c | 11 +- trunk/fs/binfmt_elf_fdpic.c | 8 +- trunk/fs/cifs/export.c | 2 +- trunk/fs/compat.c | 2 + trunk/fs/direct-io.c | 165 +- trunk/fs/exportfs/expfs.c | 2 +- trunk/fs/ext2/dir.c | 2 +- trunk/fs/ext2/ext2.h | 1 - trunk/fs/ext2/file.c | 21 +- trunk/fs/ext2/super.c | 22 - trunk/fs/fat/fat.h | 3 +- trunk/fs/fat/fatent.c | 25 +- trunk/fs/fat/inode.c | 8 +- trunk/fs/fat/misc.c | 57 +- trunk/fs/fscache/object-list.c | 2 +- trunk/fs/hpfs/super.c | 17 +- trunk/fs/isofs/export.c | 2 +- trunk/fs/jffs2/gc.c | 3 +- trunk/fs/jffs2/readinode.c | 2 +- trunk/fs/jffs2/summary.c | 2 +- trunk/fs/lockd/svc4proc.c | 4 + trunk/fs/lockd/svcproc.c | 4 + trunk/fs/nfs/Kconfig | 2 +- trunk/fs/nfs/nfs4_fs.h | 5 - trunk/fs/nfs/nfs4proc.c | 203 +- trunk/fs/nfs/nfs4state.c | 60 +- trunk/fs/nfsctl.c | 2 + trunk/fs/nfsd/auth.c | 12 +- trunk/fs/nfsd/export.c | 65 +- trunk/fs/nfsd/lockd.c | 10 +- trunk/fs/nfsd/nfs2acl.c | 27 +- trunk/fs/nfsd/nfs3acl.c | 15 +- trunk/fs/nfsd/nfs3proc.c | 20 +- trunk/fs/nfsd/nfs3xdr.c | 15 +- trunk/fs/nfsd/nfs4acl.c | 12 +- trunk/fs/nfsd/nfs4callback.c | 19 +- trunk/fs/nfsd/nfs4idmap.c | 17 +- trunk/fs/nfsd/nfs4proc.c | 19 +- trunk/fs/nfsd/nfs4recover.c | 16 +- trunk/fs/nfsd/nfs4state.c | 84 +- trunk/fs/nfsd/nfs4xdr.c | 26 +- trunk/fs/nfsd/nfscache.c | 14 +- trunk/fs/nfsd/nfsctl.c | 51 +- trunk/fs/nfsd/nfsfh.c | 102 +- trunk/fs/nfsd/nfsfh.h | 208 - trunk/fs/nfsd/nfsproc.c | 22 +- trunk/fs/nfsd/nfssvc.c | 22 +- trunk/fs/nfsd/nfsxdr.c | 12 +- trunk/fs/nfsd/stats.c | 11 +- trunk/fs/nfsd/vfs.c | 134 +- trunk/fs/nfsd/vfs.h | 101 - trunk/fs/ocfs2/aops.c | 34 +- trunk/fs/proc/base.c | 4 +- trunk/fs/proc/generic.c | 21 +- trunk/fs/proc/inode.c | 31 +- trunk/fs/proc/internal.h | 10 +- trunk/fs/qnx4/bitmap.c | 24 +- trunk/fs/qnx4/inode.c | 22 +- trunk/fs/reiserfs/Makefile | 6 +- trunk/fs/reiserfs/procfs.c | 65 + trunk/fs/reiserfs/super.c | 4 + trunk/fs/ufs/dir.c | 10 +- trunk/fs/ufs/namei.c | 8 +- trunk/fs/ufs/super.c | 52 - trunk/fs/ufs/ufs.h | 4 +- trunk/fs/xfs/linux-2.6/xfs_aops.c | 20 +- trunk/include/asm-generic/gpio.h | 6 - trunk/include/asm-generic/vmlinux.lds.h | 8 +- trunk/include/linux/aio.h | 4 + trunk/include/linux/bitmap.h | 11 - trunk/include/linux/can/dev.h | 9 - trunk/include/linux/dmaengine.h | 2 +- trunk/include/linux/exportfs.h | 2 +- trunk/include/linux/fs.h | 22 +- trunk/include/linux/ftrace_event.h | 4 +- trunk/include/linux/gpio.h | 6 - trunk/include/linux/i8042.h | 18 +- trunk/include/linux/init.h | 2 - trunk/include/linux/intel-iommu.h | 1 - trunk/include/linux/iommu-helper.h | 3 + trunk/include/linux/ioport.h | 4 +- trunk/include/linux/ipc_namespace.h | 2 +- trunk/include/linux/kernel.h | 3 - trunk/include/linux/kexec.h | 2 - trunk/include/linux/kmsg_dump.h | 60 - trunk/include/linux/ksm.h | 14 +- trunk/include/linux/memcontrol.h | 17 +- trunk/include/linux/mlx4/device.h | 1 - trunk/include/linux/module.h | 6 +- trunk/include/linux/mtd/bbm.h | 35 +- trunk/include/linux/mtd/cfi.h | 9 +- trunk/include/linux/mtd/flashchip.h | 9 - trunk/include/linux/mtd/nand.h | 97 +- trunk/include/linux/mtd/nand_ecc.h | 10 +- trunk/include/linux/mtd/onenand.h | 23 +- trunk/include/linux/mtd/onenand_regs.h | 2 - trunk/include/linux/nfs_xdr.h | 1 - trunk/include/linux/nfsacl.h | 1 - trunk/{fs => include/linux}/nfsd/cache.h | 5 +- trunk/include/linux/nfsd/export.h | 19 +- trunk/{fs => include/linux}/nfsd/nfsd.h | 98 +- trunk/include/linux/nfsd/nfsfh.h | 206 +- trunk/{fs => include/linux}/nfsd/state.h | 14 +- trunk/include/linux/nfsd/syscall.h | 8 +- trunk/{fs => include/linux}/nfsd/xdr.h | 10 +- trunk/{fs => include/linux}/nfsd/xdr3.h | 4 +- trunk/{fs => include/linux}/nfsd/xdr4.h | 5 +- trunk/include/linux/oom.h | 4 +- trunk/include/linux/page_cgroup.h | 7 +- trunk/include/linux/ptrace.h | 23 +- trunk/include/linux/reiserfs_fs.h | 35 +- trunk/include/linux/rtnetlink.h | 6 +- trunk/include/linux/sched.h | 14 +- trunk/include/linux/sem.h | 5 +- trunk/include/linux/sm501-regs.h | 2 - trunk/include/linux/sunrpc/debug.h | 3 + trunk/include/linux/sunrpc/rpc_rdma.h | 2 - trunk/include/linux/sunrpc/sched.h | 14 +- trunk/include/linux/sunrpc/svc.h | 7 + trunk/include/linux/syscalls.h | 6 +- trunk/include/linux/timb_gpio.h | 37 - trunk/include/linux/tracehook.h | 7 - trunk/include/linux/videodev2.h | 123 +- trunk/include/media/ir-common.h | 39 +- trunk/include/media/ir-core.h | 62 - trunk/include/media/mt9t112.h | 30 - trunk/include/media/ov772x.h | 4 +- trunk/include/media/rj54n1cb0c.h | 19 - trunk/include/media/saa7146_vv.h | 4 + trunk/include/media/sh_mobile_ceu.h | 2 - trunk/include/media/soc_camera.h | 30 +- trunk/include/media/soc_camera_platform.h | 3 +- trunk/include/media/soc_mediabus.h | 65 - trunk/include/media/tw9910.h | 1 + trunk/include/media/v4l2-chip-ident.h | 2 - trunk/include/media/v4l2-common.h | 2 +- trunk/include/media/v4l2-dev.h | 23 +- trunk/include/media/v4l2-ioctl.h | 15 - trunk/include/media/v4l2-mediabus.h | 61 - trunk/include/media/v4l2-subdev.h | 61 +- trunk/include/net/dst.h | 2 +- trunk/include/net/ip.h | 1 - trunk/include/net/ipv6.h | 8 - .../net/netfilter/ipv6/nf_conntrack_ipv6.h | 2 +- trunk/include/net/tcp.h | 3 +- trunk/include/rdma/ib_addr.h | 36 +- trunk/include/rdma/ib_sa.h | 6 - trunk/include/rdma/ib_user_sa.h | 16 - trunk/include/rdma/ib_verbs.h | 5 - trunk/include/rdma/rdma_user_cm.h | 6 +- trunk/include/trace/ftrace.h | 56 +- trunk/include/video/da8xx-fb.h | 1 - trunk/include/video/sh_mobile_lcdc.h | 2 - trunk/ipc/msg.c | 1 - trunk/ipc/sem.c | 214 +- trunk/ipc/shm.c | 1 - trunk/kernel/fork.c | 9 +- trunk/kernel/kexec.c | 59 - trunk/kernel/ksysfs.c | 21 - trunk/kernel/module.c | 28 +- trunk/kernel/panic.c | 3 - trunk/kernel/pid.c | 12 +- trunk/kernel/printk.c | 119 - trunk/kernel/relay.c | 2 +- trunk/kernel/signal.c | 38 +- trunk/kernel/time/timecompare.c | 2 +- trunk/kernel/trace/ftrace.c | 30 +- trunk/kernel/trace/power-traces.c | 2 + trunk/kernel/trace/ring_buffer.c | 29 +- trunk/kernel/trace/trace.c | 186 +- trunk/kernel/trace/trace.h | 23 +- trunk/kernel/trace/trace_event_profile.c | 6 +- trunk/kernel/trace/trace_events.c | 41 +- trunk/kernel/trace/trace_export.c | 4 + trunk/kernel/trace/trace_irqsoff.c | 2 - trunk/kernel/trace/trace_kprobe.c | 9 + trunk/kernel/trace/trace_ksym.c | 56 +- trunk/kernel/trace/trace_syscalls.c | 18 +- trunk/lib/bitmap.c | 81 - trunk/lib/genalloc.c | 33 +- trunk/lib/iommu-helper.c | 59 +- trunk/lib/swiotlb.c | 4 +- trunk/mm/memcontrol.c | 419 +- trunk/mm/memory.c | 2 - trunk/mm/oom_kill.c | 75 +- trunk/mm/page_alloc.c | 22 +- trunk/mm/rmap.c | 4 +- trunk/mm/truncate.c | 6 - trunk/net/core/dev.c | 11 - trunk/net/core/rtnetlink.c | 6 +- trunk/net/core/skbuff.c | 2 +- trunk/net/ipv4/Kconfig | 6 +- trunk/net/ipv4/ipconfig.c | 2 +- trunk/net/ipv4/netfilter/nf_defrag_ipv4.c | 21 +- trunk/net/ipv4/syncookies.c | 27 +- trunk/net/ipv4/tcp_input.c | 24 +- trunk/net/ipv4/tcp_ipv4.c | 21 +- trunk/net/ipv4/tcp_minisocks.c | 10 +- trunk/net/ipv4/tcp_output.c | 18 +- trunk/net/ipv4/udp.c | 7 +- .../netfilter/nf_conntrack_l3proto_ipv6.c | 19 +- trunk/net/ipv6/netfilter/nf_conntrack_reasm.c | 7 +- trunk/net/ipv6/reassembly.c | 5 +- trunk/net/ipv6/syncookies.c | 28 +- trunk/net/ipv6/tcp_ipv6.c | 3 +- trunk/net/netfilter/ipvs/ip_vs_core.c | 1 - trunk/net/netfilter/ipvs/ip_vs_ctl.c | 4 - trunk/net/packet/af_packet.c | 71 +- trunk/net/rds/ib.c | 4 +- trunk/net/rds/iw.c | 4 +- trunk/net/sunrpc/sched.c | 15 - trunk/net/sunrpc/svc_xprt.c | 31 +- trunk/net/sunrpc/svcauth_unix.c | 53 +- trunk/scripts/Makefile.lib | 5 - trunk/scripts/mod/Makefile | 2 +- trunk/scripts/mod/mk_elfconfig.c | 9 + trunk/scripts/mod/modpost.c | 177 +- trunk/scripts/mod/modpost.h | 3 + 1018 files changed, 28046 insertions(+), 43676 deletions(-) create mode 100644 trunk/Documentation/DocBook/procfs-guide.tmpl create mode 100644 trunk/Documentation/DocBook/procfs_example.c delete mode 100644 trunk/Documentation/DocBook/v4l/vidioc-enum-dv-presets.xml delete mode 100644 trunk/Documentation/DocBook/v4l/vidioc-g-dv-preset.xml delete mode 100644 trunk/Documentation/DocBook/v4l/vidioc-g-dv-timings.xml delete mode 100644 trunk/Documentation/DocBook/v4l/vidioc-query-dv-preset.xml delete mode 100644 trunk/Documentation/blackfin/Makefile create mode 100644 trunk/Documentation/blackfin/cache-lock.txt delete mode 100644 trunk/Documentation/blackfin/gptimers-example.c rename trunk/Documentation/filesystems/{nfs => }/Exporting (100%) rename trunk/Documentation/filesystems/{nfs => }/knfsd-stats.txt (100%) rename trunk/Documentation/filesystems/{nfs => }/nfs-rdma.txt (100%) rename trunk/Documentation/filesystems/{nfs => }/nfs.txt (100%) delete mode 100644 trunk/Documentation/filesystems/nfs/00-INDEX rename trunk/Documentation/filesystems/{nfs => }/nfs41-server.txt (96%) rename trunk/Documentation/filesystems/{nfs => }/nfsroot.txt (100%) rename trunk/Documentation/filesystems/{nfs => }/rpc-cache.txt (100%) delete mode 100644 trunk/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt delete mode 100644 trunk/Documentation/video4linux/sh_mobile_ceu_camera.txt delete mode 100644 trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h delete mode 100644 trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h delete mode 100644 trunk/arch/arm/mach-u300/include/mach/coh901318.h delete mode 100644 trunk/arch/blackfin/configs/BF561-ACVILON_defconfig delete mode 100644 trunk/arch/blackfin/include/asm/bfin-lq035q1.h create mode 100644 trunk/arch/blackfin/lib/checksum.c delete mode 100644 trunk/arch/blackfin/mach-bf538/ext-gpio.c delete mode 100644 trunk/arch/blackfin/mach-bf561/boards/acvilon.c delete mode 100644 trunk/arch/powerpc/include/asm/async_tx.h delete mode 100644 trunk/drivers/dma/coh901318.c delete mode 100644 trunk/drivers/dma/coh901318_lli.c delete mode 100644 trunk/drivers/dma/coh901318_lli.h delete mode 100644 trunk/drivers/dma/ppc4xx/Makefile delete mode 100644 trunk/drivers/dma/ppc4xx/adma.c delete mode 100644 trunk/drivers/dma/ppc4xx/adma.h delete mode 100644 trunk/drivers/dma/ppc4xx/dma.h delete mode 100644 trunk/drivers/dma/ppc4xx/xor.h delete mode 100644 trunk/drivers/gpio/timbgpio.c delete mode 100644 trunk/drivers/gpu/drm/radeon/r600_audio.c delete mode 100644 trunk/drivers/gpu/drm/radeon/r600_hdmi.c delete mode 100644 trunk/drivers/input/touchscreen/mc13783_ts.c delete mode 100644 trunk/drivers/media/IR/Kconfig delete mode 100644 trunk/drivers/media/IR/Makefile rename trunk/drivers/media/{IR => common}/ir-functions.c (92%) rename trunk/drivers/media/{IR => common}/ir-keymaps.c (97%) rename trunk/drivers/media/{IR => common}/ir-keytable.c (81%) delete mode 100644 trunk/drivers/media/dvb/frontends/dib0090.c delete mode 100644 trunk/drivers/media/dvb/frontends/dib0090.h delete mode 100644 trunk/drivers/media/video/mt9t112.c delete mode 100644 trunk/drivers/media/video/soc_mediabus.c create mode 100644 trunk/drivers/mtd/maps/ipaq-flash.c delete mode 100644 trunk/drivers/mtd/nand/bcm_umi_bch.c delete mode 100644 trunk/drivers/mtd/nand/bcm_umi_nand.c delete mode 100644 trunk/drivers/mtd/nand/nand_bcm_umi.c delete mode 100644 trunk/drivers/mtd/nand/nand_bcm_umi.h delete mode 100644 trunk/drivers/mtd/tests/mtd_nandecctest.c delete mode 100644 trunk/drivers/rtc/rtc-bq32k.c delete mode 100644 trunk/drivers/rtc/rtc-mc13783.c delete mode 100644 trunk/drivers/rtc/rtc-nuc900.c delete mode 100644 trunk/drivers/video/bfin-lq035q1-fb.c delete mode 100644 trunk/drivers/video/mb862xx/mb862xxfb_accel.c delete mode 100644 trunk/drivers/video/mb862xx/mb862xxfb_accel.h delete mode 100644 trunk/fs/nfsd/nfsfh.h delete mode 100644 trunk/fs/nfsd/vfs.h delete mode 100644 trunk/include/linux/kmsg_dump.h rename trunk/{fs => include/linux}/nfsd/cache.h (95%) rename trunk/{fs => include/linux}/nfsd/nfsd.h (79%) rename trunk/{fs => include/linux}/nfsd/state.h (98%) rename trunk/{fs => include/linux}/nfsd/xdr.h (96%) rename trunk/{fs => include/linux}/nfsd/xdr3.h (99%) rename trunk/{fs => include/linux}/nfsd/xdr4.h (99%) delete mode 100644 trunk/include/linux/timb_gpio.h delete mode 100644 trunk/include/media/ir-core.h delete mode 100644 trunk/include/media/mt9t112.h delete mode 100644 trunk/include/media/rj54n1cb0c.h delete mode 100644 trunk/include/media/soc_mediabus.h delete mode 100644 trunk/include/media/v4l2-mediabus.h diff --git a/[refs] b/[refs] index baebdf7d5e5e..4fb586a68ec5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 529e89430d6c0d64db8ac474cb95e68e2527c79a +refs/heads/master: 853b3da10d617f08340e5fe569c99e7b54f2a568 diff --git a/trunk/Documentation/Changes b/trunk/Documentation/Changes index f08b313cd235..6d0f1efc5bf6 100644 --- a/trunk/Documentation/Changes +++ b/trunk/Documentation/Changes @@ -49,8 +49,6 @@ o oprofile 0.9 # oprofiled --version o udev 081 # udevinfo -V o grub 0.93 # grub --version o mcelog 0.6 -o iptables 1.4.1 # iptables -V - Kernel compilation ================== diff --git a/trunk/Documentation/DocBook/Makefile b/trunk/Documentation/DocBook/Makefile index 325cfd1d6d99..ab8300f67182 100644 --- a/trunk/Documentation/DocBook/Makefile +++ b/trunk/Documentation/DocBook/Makefile @@ -8,7 +8,7 @@ DOCBOOKS := z8530book.xml mcabook.xml device-drivers.xml \ kernel-hacking.xml kernel-locking.xml deviceiobook.xml \ - writing_usb_driver.xml networking.xml \ + procfs-guide.xml writing_usb_driver.xml networking.xml \ kernel-api.xml filesystems.xml lsm.xml usb.xml kgdb.xml \ gadget.xml libata.xml mtdnand.xml librs.xml rapidio.xml \ genericirq.xml s390-drivers.xml uio-howto.xml scsi.xml \ @@ -32,10 +32,10 @@ PS_METHOD = $(prefer-db2x) ### # The targets that may be used. -PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs xmldoclinks +PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs media BOOKS := $(addprefix $(obj)/,$(DOCBOOKS)) -xmldocs: $(BOOKS) xmldoclinks +xmldocs: $(BOOKS) sgmldocs: xmldocs PS := $(patsubst %.xml, %.ps, $(BOOKS)) @@ -45,24 +45,15 @@ PDF := $(patsubst %.xml, %.pdf, $(BOOKS)) pdfdocs: $(PDF) HTML := $(sort $(patsubst %.xml, %.html, $(BOOKS))) -htmldocs: $(HTML) +htmldocs: media $(HTML) $(call build_main_index) - $(call build_images) MAN := $(patsubst %.xml, %.9, $(BOOKS)) mandocs: $(MAN) -build_images = mkdir -p $(objtree)/Documentation/DocBook/media/ && \ - cp $(srctree)/Documentation/DocBook/dvb/*.png $(srctree)/Documentation/DocBook/v4l/*.gif $(objtree)/Documentation/DocBook/media/ - -xmldoclinks: -ifneq ($(objtree),$(srctree)) - for dep in dvb media-entities.tmpl media-indices.tmpl v4l; do \ - rm -f $(objtree)/Documentation/DocBook/$$dep \ - && ln -s $(srctree)/Documentation/DocBook/$$dep $(objtree)/Documentation/DocBook/ \ - || exit; \ - done -endif +media: + mkdir -p $(srctree)/Documentation/DocBook/media/ + cp $(srctree)/Documentation/DocBook/dvb/*.png $(srctree)/Documentation/DocBook/v4l/*.gif $(srctree)/Documentation/DocBook/media/ installmandocs: mandocs mkdir -p /usr/local/man/man9/ @@ -74,7 +65,7 @@ KERNELDOC = $(srctree)/scripts/kernel-doc DOCPROC = $(objtree)/scripts/basic/docproc XMLTOFLAGS = -m $(srctree)/Documentation/DocBook/stylesheet.xsl -XMLTOFLAGS += --skip-validation +#XMLTOFLAGS += --skip-validation ### # DOCPROC is used for two purposes: @@ -110,6 +101,17 @@ endif # Changes in kernel-doc force a rebuild of all documentation $(BOOKS): $(KERNELDOC) +### +# procfs guide uses a .c file as example code. +# This requires an explicit dependency +C-procfs-example = procfs_example.xml +C-procfs-example2 = $(addprefix $(obj)/,$(C-procfs-example)) +$(obj)/procfs-guide.xml: $(C-procfs-example2) + +# List of programs to build +##oops, this is a kernel module::hostprogs-y := procfs_example +obj-m += procfs_example.o + # Tell kbuild to always build the programs always := $(hostprogs-y) @@ -236,7 +238,7 @@ clean-files := $(DOCBOOKS) \ $(patsubst %.xml, %.pdf, $(DOCBOOKS)) \ $(patsubst %.xml, %.html, $(DOCBOOKS)) \ $(patsubst %.xml, %.9, $(DOCBOOKS)) \ - $(index) + $(C-procfs-example) $(index) clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man diff --git a/trunk/Documentation/DocBook/media-entities.tmpl b/trunk/Documentation/DocBook/media-entities.tmpl index c725cb852c54..bb5ab741220e 100644 --- a/trunk/Documentation/DocBook/media-entities.tmpl +++ b/trunk/Documentation/DocBook/media-entities.tmpl @@ -23,7 +23,6 @@ VIDIOC_ENUMINPUT"> VIDIOC_ENUMOUTPUT"> VIDIOC_ENUMSTD"> -VIDIOC_ENUM_DV_PRESETS"> VIDIOC_ENUM_FMT"> VIDIOC_ENUM_FRAMEINTERVALS"> VIDIOC_ENUM_FRAMESIZES"> @@ -31,8 +30,6 @@ VIDIOC_G_AUDOUT"> VIDIOC_G_CROP"> VIDIOC_G_CTRL"> -VIDIOC_G_DV_PRESET"> -VIDIOC_G_DV_TIMINGS"> VIDIOC_G_ENC_INDEX"> VIDIOC_G_EXT_CTRLS"> VIDIOC_G_FBUF"> @@ -56,7 +53,6 @@ VIDIOC_QUERYCTRL"> VIDIOC_QUERYMENU"> VIDIOC_QUERYSTD"> -VIDIOC_QUERY_DV_PRESET"> VIDIOC_REQBUFS"> VIDIOC_STREAMOFF"> VIDIOC_STREAMON"> @@ -64,8 +60,6 @@ VIDIOC_S_AUDOUT"> VIDIOC_S_CROP"> VIDIOC_S_CTRL"> -VIDIOC_S_DV_PRESET"> -VIDIOC_S_DV_TIMINGS"> VIDIOC_S_EXT_CTRLS"> VIDIOC_S_FBUF"> VIDIOC_S_FMT"> @@ -124,7 +118,6 @@ v4l2_audio"> v4l2_audioout"> -v4l2_bt_timings"> v4l2_buffer"> v4l2_capability"> v4l2_captureparm"> @@ -135,9 +128,6 @@ v4l2_dbg_chip_ident"> v4l2_dbg_match"> v4l2_dbg_register"> -v4l2_dv_enum_preset"> -v4l2_dv_preset"> -v4l2_dv_timings"> v4l2_enc_idx"> v4l2_enc_idx_entry"> v4l2_encoder_cmd"> @@ -253,10 +243,6 @@ - - - - @@ -347,10 +333,6 @@ - - - - diff --git a/trunk/Documentation/DocBook/media-indices.tmpl b/trunk/Documentation/DocBook/media-indices.tmpl index 78d6031de001..9e30a236d74f 100644 --- a/trunk/Documentation/DocBook/media-indices.tmpl +++ b/trunk/Documentation/DocBook/media-indices.tmpl @@ -36,7 +36,6 @@ enum v4l2_preemphasis struct v4l2_audio struct v4l2_audioout -struct v4l2_bt_timings struct v4l2_buffer struct v4l2_capability struct v4l2_captureparm @@ -47,9 +46,6 @@ struct v4l2_dbg_chip_ident struct v4l2_dbg_match struct v4l2_dbg_register -struct v4l2_dv_enum_preset -struct v4l2_dv_preset -struct v4l2_dv_timings struct v4l2_enc_idx struct v4l2_enc_idx_entry struct v4l2_encoder_cmd diff --git a/trunk/Documentation/DocBook/procfs-guide.tmpl b/trunk/Documentation/DocBook/procfs-guide.tmpl new file mode 100644 index 000000000000..9eba4b7af73d --- /dev/null +++ b/trunk/Documentation/DocBook/procfs-guide.tmpl @@ -0,0 +1,626 @@ + + +]> + + + + Linux Kernel Procfs Guide + + + + Erik + (J.A.K.) + Mouw + +
+ mouw@nl.linux.org +
+ + + + + This software and documentation were written while working on the + LART computing board + (http://www.lartmaker.nl/), + which was sponsored by the Delt University of Technology projects + Mobile Multi-media Communications and Ubiquitous Communications. + + + + + + + 1.0 + May 30, 2001 + Initial revision posted to linux-kernel + + + 1.1 + June 3, 2001 + Revised after comments from linux-kernel + + + + + 2001 + Erik Mouw + + + + + + This documentation is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public + License as published by the Free Software Foundation; either + version 2 of the License, or (at your option) any later + version. + + + + This documentation is distributed in the hope that it will be + useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + PURPOSE. See the GNU General Public License for more details. + + + + You should have received a copy of the GNU General Public + License along with this program; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, + MA 02111-1307 USA + + + + For more details see the file COPYING in the source + distribution of Linux. + + + + + + + + + + + + + + + Preface + + + This guide describes the use of the procfs file system from + within the Linux kernel. The idea to write this guide came up on + the #kernelnewbies IRC channel (see http://www.kernelnewbies.org/), + when Jeff Garzik explained the use of procfs and forwarded me a + message Alexander Viro wrote to the linux-kernel mailing list. I + agreed to write it up nicely, so here it is. + + + + I'd like to thank Jeff Garzik + jgarzik@pobox.com and Alexander Viro + viro@parcelfarce.linux.theplanet.co.uk for their input, + Tim Waugh twaugh@redhat.com for his Selfdocbook, + and Marc Joosen marcj@historia.et.tudelft.nl for + proofreading. + + + + Erik + + + + + + + + Introduction + + + The /proc file system + (procfs) is a special file system in the linux kernel. It's a + virtual file system: it is not associated with a block device + but exists only in memory. The files in the procfs are there to + allow userland programs access to certain information from the + kernel (like process information in /proc/[0-9]+/), but also for debug + purposes (like /proc/ksyms). + + + + This guide describes the use of the procfs file system from + within the Linux kernel. It starts by introducing all relevant + functions to manage the files within the file system. After that + it shows how to communicate with userland, and some tips and + tricks will be pointed out. Finally a complete example will be + shown. + + + + Note that the files in /proc/sys are sysctl files: they + don't belong to procfs and are governed by a completely + different API described in the Kernel API book. + + + + + + + + Managing procfs entries + + + This chapter describes the functions that various kernel + components use to populate the procfs with files, symlinks, + device nodes, and directories. + + + + A minor note before we start: if you want to use any of the + procfs functions, be sure to include the correct header file! + This should be one of the first lines in your code: + + + +#include <linux/proc_fs.h> + + + + + + + Creating a regular file + + + + struct proc_dir_entry* create_proc_entry + const char* name + mode_t mode + struct proc_dir_entry* parent + + + + + This function creates a regular file with the name + name, file mode + mode in the directory + parent. To create a file in the root of + the procfs, use NULL as + parent parameter. When successful, the + function will return a pointer to the freshly created + struct proc_dir_entry; otherwise it + will return NULL. describes how to do something useful with + regular files. + + + + Note that it is specifically supported that you can pass a + path that spans multiple directories. For example + create_proc_entry("drivers/via0/info") + will create the via0 + directory if necessary, with standard + 0755 permissions. + + + + If you only want to be able to read the file, the function + create_proc_read_entry described in may be used to create and initialise + the procfs entry in one single call. + + + + + + + + Creating a symlink + + + + struct proc_dir_entry* + proc_symlink const + char* name + struct proc_dir_entry* + parent const + char* dest + + + + + This creates a symlink in the procfs directory + parent that points from + name to + dest. This translates in userland to + ln -s dest + name. + + + + + Creating a directory + + + + struct proc_dir_entry* proc_mkdir + const char* name + struct proc_dir_entry* parent + + + + + Create a directory name in the procfs + directory parent. + + + + + + + + Removing an entry + + + + void remove_proc_entry + const char* name + struct proc_dir_entry* parent + + + + + Removes the entry name in the directory + parent from the procfs. Entries are + removed by their name, not by the + struct proc_dir_entry returned by the + various create functions. Note that this function doesn't + recursively remove entries. + + + + Be sure to free the data entry from + the struct proc_dir_entry before + remove_proc_entry is called (that is: if + there was some data allocated, of + course). See for more information + on using the data entry. + + + + + + + + + Communicating with userland + + + Instead of reading (or writing) information directly from + kernel memory, procfs works with call back + functions for files: functions that are called when + a specific file is being read or written. Such functions have + to be initialised after the procfs file is created by setting + the read_proc and/or + write_proc fields in the + struct proc_dir_entry* that the + function create_proc_entry returned: + + + +struct proc_dir_entry* entry; + +entry->read_proc = read_proc_foo; +entry->write_proc = write_proc_foo; + + + + If you only want to use a the + read_proc, the function + create_proc_read_entry described in may be used to create and initialise the + procfs entry in one single call. + + + + + + Reading data + + + The read function is a call back function that allows userland + processes to read data from the kernel. The read function + should have the following format: + + + + + int read_func + char* buffer + char** start + off_t off + int count + int* peof + void* data + + + + + The read function should write its information into the + buffer, which will be exactly + PAGE_SIZE bytes long. + + + + The parameter + peof should be used to signal that the + end of the file has been reached by writing + 1 to the memory location + peof points to. + + + + The data + parameter can be used to create a single call back function for + several files, see . + + + + The rest of the parameters and the return value are described + by a comment in fs/proc/generic.c as follows: + + +
+ + You have three ways to return data: + + + + + Leave *start = NULL. (This is the default.) + Put the data of the requested offset at that + offset within the buffer. Return the number (n) + of bytes there are from the beginning of the + buffer up to the last byte of data. If the + number of supplied bytes (= n - offset) is + greater than zero and you didn't signal eof + and the reader is prepared to take more data + you will be called again with the requested + offset advanced by the number of bytes + absorbed. This interface is useful for files + no larger than the buffer. + + + + + Set *start to an unsigned long value less than + the buffer address but greater than zero. + Put the data of the requested offset at the + beginning of the buffer. Return the number of + bytes of data placed there. If this number is + greater than zero and you didn't signal eof + and the reader is prepared to take more data + you will be called again with the requested + offset advanced by *start. This interface is + useful when you have a large file consisting + of a series of blocks which you want to count + and return as wholes. + (Hack by Paul.Russell@rustcorp.com.au) + + + + + Set *start to an address within the buffer. + Put the data of the requested offset at *start. + Return the number of bytes of data placed there. + If this number is greater than zero and you + didn't signal eof and the reader is prepared to + take more data you will be called again with the + requested offset advanced by the number of bytes + absorbed. + + + +
+ + + shows how to use a read call back + function. + + + + + + + + Writing data + + + The write call back function allows a userland process to write + data to the kernel, so it has some kind of control over the + kernel. The write function should have the following format: + + + + + int write_func + struct file* file + const char* buffer + unsigned long count + void* data + + + + + The write function should read count + bytes at maximum from the buffer. Note + that the buffer doesn't live in the + kernel's memory space, so it should first be copied to kernel + space with copy_from_user. The + file parameter is usually + ignored. shows how to use the + data parameter. + + + + Again, shows how to use this call back + function. + + + + + + + + A single call back for many files + + + When a large number of almost identical files is used, it's + quite inconvenient to use a separate call back function for + each file. A better approach is to have a single call back + function that distinguishes between the files by using the + data field in struct + proc_dir_entry. First of all, the + data field has to be initialised: + + + +struct proc_dir_entry* entry; +struct my_file_data *file_data; + +file_data = kmalloc(sizeof(struct my_file_data), GFP_KERNEL); +entry->data = file_data; + + + + The data field is a void + *, so it can be initialised with anything. + + + + Now that the data field is set, the + read_proc and + write_proc can use it to distinguish + between files because they get it passed into their + data parameter: + + + +int foo_read_func(char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int len; + + if(data == file_data) { + /* special case for this file */ + } else { + /* normal processing */ + } + + return len; +} + + + + Be sure to free the data data field + when removing the procfs entry. + + + + + + + + + Tips and tricks + + + + + + Convenience functions + + + + struct proc_dir_entry* create_proc_read_entry + const char* name + mode_t mode + struct proc_dir_entry* parent + read_proc_t* read_proc + void* data + + + + + This function creates a regular file in exactly the same way + as create_proc_entry from does, but also allows to set the read + function read_proc in one call. This + function can set the data as well, like + explained in . + + + + + + + Modules + + + If procfs is being used from within a module, be sure to set + the owner field in the + struct proc_dir_entry to + THIS_MODULE. + + + +struct proc_dir_entry* entry; + +entry->owner = THIS_MODULE; + + + + + + + + Mode and ownership + + + Sometimes it is useful to change the mode and/or ownership of + a procfs entry. Here is an example that shows how to achieve + that: + + + +struct proc_dir_entry* entry; + +entry->mode = S_IWUSR |S_IRUSR | S_IRGRP | S_IROTH; +entry->uid = 0; +entry->gid = 100; + + + + + + + + + + Example + + + +&procfsexample; + + + diff --git a/trunk/Documentation/DocBook/procfs_example.c b/trunk/Documentation/DocBook/procfs_example.c new file mode 100644 index 000000000000..a5b11793b1e0 --- /dev/null +++ b/trunk/Documentation/DocBook/procfs_example.c @@ -0,0 +1,201 @@ +/* + * procfs_example.c: an example proc interface + * + * Copyright (C) 2001, Erik Mouw (mouw@nl.linux.org) + * + * This file accompanies the procfs-guide in the Linux kernel + * source. Its main use is to demonstrate the concepts and + * functions described in the guide. + * + * This software has been developed while working on the LART + * computing board (http://www.lartmaker.nl), which was sponsored + * by the Delt University of Technology projects Mobile Multi-media + * Communications and Ubiquitous Communications. + * + * This program is free software; you can redistribute + * it and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the + * Free Software Foundation, Inc., 59 Temple Place, + * Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#include +#include +#include +#include +#include + + +#define MODULE_VERS "1.0" +#define MODULE_NAME "procfs_example" + +#define FOOBAR_LEN 8 + +struct fb_data_t { + char name[FOOBAR_LEN + 1]; + char value[FOOBAR_LEN + 1]; +}; + + +static struct proc_dir_entry *example_dir, *foo_file, + *bar_file, *jiffies_file, *symlink; + + +struct fb_data_t foo_data, bar_data; + + +static int proc_read_jiffies(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + int len; + + len = sprintf(page, "jiffies = %ld\n", + jiffies); + + return len; +} + + +static int proc_read_foobar(char *page, char **start, + off_t off, int count, + int *eof, void *data) +{ + int len; + struct fb_data_t *fb_data = (struct fb_data_t *)data; + + /* DON'T DO THAT - buffer overruns are bad */ + len = sprintf(page, "%s = '%s'\n", + fb_data->name, fb_data->value); + + return len; +} + + +static int proc_write_foobar(struct file *file, + const char *buffer, + unsigned long count, + void *data) +{ + int len; + struct fb_data_t *fb_data = (struct fb_data_t *)data; + + if(count > FOOBAR_LEN) + len = FOOBAR_LEN; + else + len = count; + + if(copy_from_user(fb_data->value, buffer, len)) + return -EFAULT; + + fb_data->value[len] = '\0'; + + return len; +} + + +static int __init init_procfs_example(void) +{ + int rv = 0; + + /* create directory */ + example_dir = proc_mkdir(MODULE_NAME, NULL); + if(example_dir == NULL) { + rv = -ENOMEM; + goto out; + } + /* create jiffies using convenience function */ + jiffies_file = create_proc_read_entry("jiffies", + 0444, example_dir, + proc_read_jiffies, + NULL); + if(jiffies_file == NULL) { + rv = -ENOMEM; + goto no_jiffies; + } + + /* create foo and bar files using same callback + * functions + */ + foo_file = create_proc_entry("foo", 0644, example_dir); + if(foo_file == NULL) { + rv = -ENOMEM; + goto no_foo; + } + + strcpy(foo_data.name, "foo"); + strcpy(foo_data.value, "foo"); + foo_file->data = &foo_data; + foo_file->read_proc = proc_read_foobar; + foo_file->write_proc = proc_write_foobar; + + bar_file = create_proc_entry("bar", 0644, example_dir); + if(bar_file == NULL) { + rv = -ENOMEM; + goto no_bar; + } + + strcpy(bar_data.name, "bar"); + strcpy(bar_data.value, "bar"); + bar_file->data = &bar_data; + bar_file->read_proc = proc_read_foobar; + bar_file->write_proc = proc_write_foobar; + + /* create symlink */ + symlink = proc_symlink("jiffies_too", example_dir, + "jiffies"); + if(symlink == NULL) { + rv = -ENOMEM; + goto no_symlink; + } + + /* everything OK */ + printk(KERN_INFO "%s %s initialised\n", + MODULE_NAME, MODULE_VERS); + return 0; + +no_symlink: + remove_proc_entry("bar", example_dir); +no_bar: + remove_proc_entry("foo", example_dir); +no_foo: + remove_proc_entry("jiffies", example_dir); +no_jiffies: + remove_proc_entry(MODULE_NAME, NULL); +out: + return rv; +} + + +static void __exit cleanup_procfs_example(void) +{ + remove_proc_entry("jiffies_too", example_dir); + remove_proc_entry("bar", example_dir); + remove_proc_entry("foo", example_dir); + remove_proc_entry("jiffies", example_dir); + remove_proc_entry(MODULE_NAME, NULL); + + printk(KERN_INFO "%s %s removed\n", + MODULE_NAME, MODULE_VERS); +} + + +module_init(init_procfs_example); +module_exit(cleanup_procfs_example); + +MODULE_AUTHOR("Erik Mouw"); +MODULE_DESCRIPTION("procfs examples"); +MODULE_LICENSE("GPL"); diff --git a/trunk/Documentation/DocBook/v4l/common.xml b/trunk/Documentation/DocBook/v4l/common.xml index c65f0ac9b6ee..b1a81d246d58 100644 --- a/trunk/Documentation/DocBook/v4l/common.xml +++ b/trunk/Documentation/DocBook/v4l/common.xml @@ -716,41 +716,6 @@ if (-1 == ioctl (fd, &VIDIOC-S-STD;, &std_id)) { } -
- Digital Video (DV) Timings - - The video standards discussed so far has been dealing with Analog TV and the -corresponding video timings. Today there are many more different hardware interfaces -such as High Definition TV interfaces (HDMI), VGA, DVI connectors etc., that carry -video signals and there is a need to extend the API to select the video timings -for these interfaces. Since it is not possible to extend the &v4l2-std-id; due to -the limited bits available, a new set of IOCTLs is added to set/get video timings at -the input and output: - - DV Presets: Digital Video (DV) presets. These are IDs representing a -video timing at the input/output. Presets are pre-defined timings implemented -by the hardware according to video standards. A __u32 data type is used to represent -a preset unlike the bit mask that is used in &v4l2-std-id; allowing future extensions -to support as many different presets as needed. - - - Custom DV Timings: This will allow applications to define more detailed -custom video timings for the interface. This includes parameters such as width, height, -polarities, frontporch, backporch etc. - - - - To enumerate and query the attributes of DV presets supported by a device, -applications use the &VIDIOC-ENUM-DV-PRESETS; ioctl. To get the current DV preset, -applications use the &VIDIOC-G-DV-PRESET; ioctl and to set a preset they use the -&VIDIOC-S-DV-PRESET; ioctl. - To set custom DV timings for the device, applications use the -&VIDIOC-S-DV-TIMINGS; ioctl and to get current custom DV timings they use the -&VIDIOC-G-DV-TIMINGS; ioctl. - Applications can make use of the and - flags to decide what ioctls are available to set the -video timings for the device. -
&sub-controls; diff --git a/trunk/Documentation/DocBook/v4l/compat.xml b/trunk/Documentation/DocBook/v4l/compat.xml index b9dbdf9e6d29..4d1902a54d61 100644 --- a/trunk/Documentation/DocBook/v4l/compat.xml +++ b/trunk/Documentation/DocBook/v4l/compat.xml @@ -2291,8 +2291,8 @@ was renamed to v4l2_chip_ident_old New control V4L2_CID_COLORFX was added. - - + +
V4L2 in Linux 2.6.32 @@ -2322,16 +2322,8 @@ more information. Added Remote Controller chapter, describing the default Remote Controller mapping for media devices. - -
-
- V4L2 in Linux 2.6.33 - - - Added support for Digital Video timings in order to support HDTV receivers and transmitters. - - -
+ +
diff --git a/trunk/Documentation/DocBook/v4l/v4l2.xml b/trunk/Documentation/DocBook/v4l/v4l2.xml index 060105af49e5..937b4157a5d0 100644 --- a/trunk/Documentation/DocBook/v4l/v4l2.xml +++ b/trunk/Documentation/DocBook/v4l/v4l2.xml @@ -74,17 +74,6 @@ Remote Controller chapter. - - - Muralidharan - Karicheri - Documented the Digital Video timings API. - -
- m-karicheri2@ti.com -
- - @@ -100,7 +89,7 @@ Remote Controller chapter. 2008 2009 Bill Dirks, Michael H. Schimek, Hans Verkuil, Martin -Rubli, Andy Walls, Muralidharan Karicheri, Mauro Carvalho Chehab +Rubli, Andy Walls, Mauro Carvalho Chehab Except when explicitly stated as GPL, programming examples within @@ -113,13 +102,6 @@ structs, ioctls) must be noted in more detail in the history chapter (compat.sgml), along with the possible impact on existing drivers and applications. --> - - 2.6.33 - 2009-12-03 - mk - Added documentation for the Digital Video timings API. - - 2.6.32 2009-08-31 @@ -373,7 +355,7 @@ and discussions on the V4L mailing list. Video for Linux Two API Specification - Revision 2.6.33 + Revision 2.6.32 &sub-common; @@ -429,7 +411,6 @@ and discussions on the V4L mailing list. &sub-encoder-cmd; &sub-enumaudio; &sub-enumaudioout; - &sub-enum-dv-presets; &sub-enum-fmt; &sub-enum-framesizes; &sub-enum-frameintervals; @@ -440,8 +421,6 @@ and discussions on the V4L mailing list. &sub-g-audioout; &sub-g-crop; &sub-g-ctrl; - &sub-g-dv-preset; - &sub-g-dv-timings; &sub-g-enc-index; &sub-g-ext-ctrls; &sub-g-fbuf; @@ -462,7 +441,6 @@ and discussions on the V4L mailing list. &sub-querybuf; &sub-querycap; &sub-queryctrl; - &sub-query-dv-preset; &sub-querystd; &sub-reqbufs; &sub-s-hw-freq-seek; diff --git a/trunk/Documentation/DocBook/v4l/videodev2.h.xml b/trunk/Documentation/DocBook/v4l/videodev2.h.xml index 068325940658..3e282ed9f593 100644 --- a/trunk/Documentation/DocBook/v4l/videodev2.h.xml +++ b/trunk/Documentation/DocBook/v4l/videodev2.h.xml @@ -733,99 +733,6 @@ struct v4l2_standard { __u32 reserved[4]; }; -/* - * V I D E O T I M I N G S D V P R E S E T - */ -struct v4l2_dv_preset { - __u32 preset; - __u32 reserved[4]; -}; - -/* - * D V P R E S E T S E N U M E R A T I O N - */ -struct v4l2_dv_enum_preset { - __u32 index; - __u32 preset; - __u8 name[32]; /* Name of the preset timing */ - __u32 width; - __u32 height; - __u32 reserved[4]; -}; - -/* - * D V P R E S E T V A L U E S - */ -#define V4L2_DV_INVALID 0 -#define V4L2_DV_480P59_94 1 /* BT.1362 */ -#define V4L2_DV_576P50 2 /* BT.1362 */ -#define V4L2_DV_720P24 3 /* SMPTE 296M */ -#define V4L2_DV_720P25 4 /* SMPTE 296M */ -#define V4L2_DV_720P30 5 /* SMPTE 296M */ -#define V4L2_DV_720P50 6 /* SMPTE 296M */ -#define V4L2_DV_720P59_94 7 /* SMPTE 274M */ -#define V4L2_DV_720P60 8 /* SMPTE 274M/296M */ -#define V4L2_DV_1080I29_97 9 /* BT.1120/ SMPTE 274M */ -#define V4L2_DV_1080I30 10 /* BT.1120/ SMPTE 274M */ -#define V4L2_DV_1080I25 11 /* BT.1120 */ -#define V4L2_DV_1080I50 12 /* SMPTE 296M */ -#define V4L2_DV_1080I60 13 /* SMPTE 296M */ -#define V4L2_DV_1080P24 14 /* SMPTE 296M */ -#define V4L2_DV_1080P25 15 /* SMPTE 296M */ -#define V4L2_DV_1080P30 16 /* SMPTE 296M */ -#define V4L2_DV_1080P50 17 /* BT.1120 */ -#define V4L2_DV_1080P60 18 /* BT.1120 */ - -/* - * D V B T T I M I N G S - */ - -/* BT.656/BT.1120 timing data */ -struct v4l2_bt_timings { - __u32 width; /* width in pixels */ - __u32 height; /* height in lines */ - __u32 interlaced; /* Interlaced or progressive */ - __u32 polarities; /* Positive or negative polarity */ - __u64 pixelclock; /* Pixel clock in HZ. Ex. 74.25MHz->74250000 */ - __u32 hfrontporch; /* Horizpontal front porch in pixels */ - __u32 hsync; /* Horizontal Sync length in pixels */ - __u32 hbackporch; /* Horizontal back porch in pixels */ - __u32 vfrontporch; /* Vertical front porch in pixels */ - __u32 vsync; /* Vertical Sync length in lines */ - __u32 vbackporch; /* Vertical back porch in lines */ - __u32 il_vfrontporch; /* Vertical front porch for bottom field of - * interlaced field formats - */ - __u32 il_vsync; /* Vertical sync length for bottom field of - * interlaced field formats - */ - __u32 il_vbackporch; /* Vertical back porch for bottom field of - * interlaced field formats - */ - __u32 reserved[16]; -} __attribute__ ((packed)); - -/* Interlaced or progressive format */ -#define V4L2_DV_PROGRESSIVE 0 -#define V4L2_DV_INTERLACED 1 - -/* Polarities. If bit is not set, it is assumed to be negative polarity */ -#define V4L2_DV_VSYNC_POS_POL 0x00000001 -#define V4L2_DV_HSYNC_POS_POL 0x00000002 - - -/* DV timings */ -struct v4l2_dv_timings { - __u32 type; - union { - struct v4l2_bt_timings bt; - __u32 reserved[32]; - }; -} __attribute__ ((packed)); - -/* Values for the type field */ -#define V4L2_DV_BT_656_1120 0 /* BT.656/1120 timing type */ - /* * V I D E O I N P U T S */ @@ -837,8 +744,7 @@ struct v4l2_input { __u32 tuner; /* Associated tuner */ v4l2_std_id std; __u32 status; - __u32 capabilities; - __u32 reserved[3]; + __u32 reserved[4]; }; /* Values for the 'type' field */ @@ -869,11 +775,6 @@ struct v4l2_input { #define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */ #define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */ -/* capabilities flags */ -#define V4L2_IN_CAP_PRESETS 0x00000001 /* Supports S_DV_PRESET */ -#define V4L2_IN_CAP_CUSTOM_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ -#define V4L2_IN_CAP_STD 0x00000004 /* Supports S_STD */ - /* * V I D E O O U T P U T S */ @@ -884,19 +785,13 @@ struct v4l2_output { __u32 audioset; /* Associated audios (bitfield) */ __u32 modulator; /* Associated modulator */ v4l2_std_id std; - __u32 capabilities; - __u32 reserved[3]; + __u32 reserved[4]; }; /* Values for the 'type' field */ #define V4L2_OUTPUT_TYPE_MODULATOR 1 #define V4L2_OUTPUT_TYPE_ANALOG 2 #define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 -/* capabilities flags */ -#define V4L2_OUT_CAP_PRESETS 0x00000001 /* Supports S_DV_PRESET */ -#define V4L2_OUT_CAP_CUSTOM_TIMINGS 0x00000002 /* Supports S_DV_TIMINGS */ -#define V4L2_OUT_CAP_STD 0x00000004 /* Supports S_STD */ - /* * C O N T R O L S */ @@ -1731,13 +1626,6 @@ struct v4l2_dbg_chip_ident { #endif #define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek) -#define VIDIOC_ENUM_DV_PRESETS _IOWR('V', 83, struct v4l2_dv_enum_preset) -#define VIDIOC_S_DV_PRESET _IOWR('V', 84, struct v4l2_dv_preset) -#define VIDIOC_G_DV_PRESET _IOWR('V', 85, struct v4l2_dv_preset) -#define VIDIOC_QUERY_DV_PRESET _IOR('V', 86, struct v4l2_dv_preset) -#define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings) -#define VIDIOC_G_DV_TIMINGS _IOWR('V', 88, struct v4l2_dv_timings) - /* Reminder: when adding new ioctls please add support for them to drivers/media/video/v4l2-compat-ioctl32.c as well! */ diff --git a/trunk/Documentation/DocBook/v4l/vidioc-enum-dv-presets.xml b/trunk/Documentation/DocBook/v4l/vidioc-enum-dv-presets.xml deleted file mode 100644 index 1d31427edd1b..000000000000 --- a/trunk/Documentation/DocBook/v4l/vidioc-enum-dv-presets.xml +++ /dev/null @@ -1,238 +0,0 @@ - - - ioctl VIDIOC_ENUM_DV_PRESETS - &manvol; - - - - VIDIOC_ENUM_DV_PRESETS - Enumerate supported Digital Video presets - - - - - - int ioctl - int fd - int request - struct v4l2_dv_enum_preset *argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_ENUM_DV_PRESETS - - - - argp - - - - - - - - - Description - - To query the attributes of a DV preset, applications initialize the -index field and zero the reserved array of &v4l2-dv-enum-preset; -and call the VIDIOC_ENUM_DV_PRESETS ioctl with a pointer to this -structure. Drivers fill the rest of the structure or return an -&EINVAL; when the index is out of bounds. To enumerate all DV Presets supported, -applications shall begin at index zero, incrementing by one until the -driver returns EINVAL. Drivers may enumerate a -different set of DV presets after switching the video input or -output. - - - struct <structname>v4l2_dv_enum_presets</structname> - - &cs-str; - - - __u32 - index - Number of the DV preset, set by the -application. - - - __u32 - preset - This field identifies one of the DV preset values listed in . - - - __u8 - name[24] - Name of the preset, a NUL-terminated ASCII string, for example: "720P-60", "1080I-60". This information is -intended for the user. - - - __u32 - width - Width of the active video in pixels for the DV preset. - - - __u32 - height - Height of the active video in lines for the DV preset. - - - __u32 - reserved[4] - Reserved for future extensions. Drivers must set the array to zero. - - - -
- - - struct <structname>DV Presets</structname> - - &cs-str; - - - Preset - Preset value - Description - - - - - - - - V4L2_DV_INVALID - 0 - Invalid preset value. - - - V4L2_DV_480P59_94 - 1 - 720x480 progressive video at 59.94 fps as per BT.1362. - - - V4L2_DV_576P50 - 2 - 720x576 progressive video at 50 fps as per BT.1362. - - - V4L2_DV_720P24 - 3 - 1280x720 progressive video at 24 fps as per SMPTE 296M. - - - V4L2_DV_720P25 - 4 - 1280x720 progressive video at 25 fps as per SMPTE 296M. - - - V4L2_DV_720P30 - 5 - 1280x720 progressive video at 30 fps as per SMPTE 296M. - - - V4L2_DV_720P50 - 6 - 1280x720 progressive video at 50 fps as per SMPTE 296M. - - - V4L2_DV_720P59_94 - 7 - 1280x720 progressive video at 59.94 fps as per SMPTE 274M. - - - V4L2_DV_720P60 - 8 - 1280x720 progressive video at 60 fps as per SMPTE 274M/296M. - - - V4L2_DV_1080I29_97 - 9 - 1920x1080 interlaced video at 29.97 fps as per BT.1120/SMPTE 274M. - - - V4L2_DV_1080I30 - 10 - 1920x1080 interlaced video at 30 fps as per BT.1120/SMPTE 274M. - - - V4L2_DV_1080I25 - 11 - 1920x1080 interlaced video at 25 fps as per BT.1120. - - - V4L2_DV_1080I50 - 12 - 1920x1080 interlaced video at 50 fps as per SMPTE 296M. - - - V4L2_DV_1080I60 - 13 - 1920x1080 interlaced video at 60 fps as per SMPTE 296M. - - - V4L2_DV_1080P24 - 14 - 1920x1080 progressive video at 24 fps as per SMPTE 296M. - - - V4L2_DV_1080P25 - 15 - 1920x1080 progressive video at 25 fps as per SMPTE 296M. - - - V4L2_DV_1080P30 - 16 - 1920x1080 progressive video at 30 fps as per SMPTE 296M. - - - V4L2_DV_1080P50 - 17 - 1920x1080 progressive video at 50 fps as per BT.1120. - - - V4L2_DV_1080P60 - 18 - 1920x1080 progressive video at 60 fps as per BT.1120. - - - -
- - - - &return-value; - - - - EINVAL - - The &v4l2-dv-enum-preset; index -is out of bounds. - - - - - - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-enuminput.xml b/trunk/Documentation/DocBook/v4l/vidioc-enuminput.xml index 71b868e2fb8f..414856b82473 100644 --- a/trunk/Documentation/DocBook/v4l/vidioc-enuminput.xml +++ b/trunk/Documentation/DocBook/v4l/vidioc-enuminput.xml @@ -124,13 +124,7 @@ current input. __u32 - capabilities - This field provides capabilities for the -input. See for flags. - - - __u32 - reserved[3] + reserved[4] Reserved for future extensions. Drivers must set the array to zero. @@ -267,34 +261,6 @@ flag is set Macrovision has been detected. - - - - Input capabilities - - &cs-def; - - - V4L2_IN_CAP_PRESETS - 0x00000001 - This input supports setting DV presets by using VIDIOC_S_DV_PRESET. - - - V4L2_OUT_CAP_CUSTOM_TIMINGS - 0x00000002 - This input supports setting custom video timings by using VIDIOC_S_DV_TIMINGS. - - - V4L2_IN_CAP_STD - 0x00000004 - This input supports setting the TV standard by using VIDIOC_S_STD. - - - -
diff --git a/trunk/Documentation/DocBook/v4l/vidioc-enumoutput.xml b/trunk/Documentation/DocBook/v4l/vidioc-enumoutput.xml index a281d26a195f..e8d16dcd50cf 100644 --- a/trunk/Documentation/DocBook/v4l/vidioc-enumoutput.xml +++ b/trunk/Documentation/DocBook/v4l/vidioc-enumoutput.xml @@ -114,13 +114,7 @@ details on video standards and how to switch see __u32 - capabilities - This field provides capabilities for the -output. See for flags. - - - __u32 - reserved[3] + reserved[4] Reserved for future extensions. Drivers must set the array to zero. @@ -153,34 +147,6 @@ CVBS, S-Video, RGB. - - - Output capabilities - - &cs-def; - - - V4L2_OUT_CAP_PRESETS - 0x00000001 - This output supports setting DV presets by using VIDIOC_S_DV_PRESET. - - - V4L2_OUT_CAP_CUSTOM_TIMINGS - 0x00000002 - This output supports setting custom video timings by using VIDIOC_S_DV_TIMINGS. - - - V4L2_OUT_CAP_STD - 0x00000004 - This output supports setting the TV standard by using VIDIOC_S_STD. - - - -
- &return-value; diff --git a/trunk/Documentation/DocBook/v4l/vidioc-g-dv-preset.xml b/trunk/Documentation/DocBook/v4l/vidioc-g-dv-preset.xml deleted file mode 100644 index 3c6784e132f3..000000000000 --- a/trunk/Documentation/DocBook/v4l/vidioc-g-dv-preset.xml +++ /dev/null @@ -1,111 +0,0 @@ - - - ioctl VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET - &manvol; - - - - VIDIOC_G_DV_PRESET - VIDIOC_S_DV_PRESET - Query or select the DV preset of the current input or output - - - - - - int ioctl - int fd - int request - &v4l2-dv-preset; -*argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_G_DV_PRESET, VIDIOC_S_DV_PRESET - - - - argp - - - - - - - - - Description - To query and select the current DV preset, applications -use the VIDIOC_G_DV_PRESET and VIDIOC_S_DV_PRESET -ioctls which take a pointer to a &v4l2-dv-preset; type as argument. -Applications must zero the reserved array in &v4l2-dv-preset;. -VIDIOC_G_DV_PRESET returns a dv preset in the field -preset of &v4l2-dv-preset;. - - VIDIOC_S_DV_PRESET accepts a pointer to a &v4l2-dv-preset; -that has the preset value to be set. Applications must zero the reserved array in &v4l2-dv-preset;. -If the preset is not supported, it returns an &EINVAL; - - - - &return-value; - - - - EINVAL - - This ioctl is not supported, or the -VIDIOC_S_DV_PRESET,VIDIOC_S_DV_PRESET parameter was unsuitable. - - - - EBUSY - - The device is busy and therefore can not change the preset. - - - - - - struct <structname>v4l2_dv_preset</structname> - - &cs-str; - - - __u32 - preset - Preset value to represent the digital video timings - - - __u32 - reserved[4] - Reserved fields for future use - - - -
- - - - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-g-dv-timings.xml b/trunk/Documentation/DocBook/v4l/vidioc-g-dv-timings.xml deleted file mode 100644 index ecc19576bb8f..000000000000 --- a/trunk/Documentation/DocBook/v4l/vidioc-g-dv-timings.xml +++ /dev/null @@ -1,224 +0,0 @@ - - - ioctl VIDIOC_G_DV_TIMINGS, VIDIOC_S_DV_TIMINGS - &manvol; - - - - VIDIOC_G_DV_TIMINGS - VIDIOC_S_DV_TIMINGS - Get or set custom DV timings for input or output - - - - - - int ioctl - int fd - int request - &v4l2-dv-timings; -*argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_G_DV_TIMINGS, VIDIOC_S_DV_TIMINGS - - - - argp - - - - - - - - - Description - To set custom DV timings for the input or output, applications use the -VIDIOC_S_DV_TIMINGS ioctl and to get the current custom timings, -applications use the VIDIOC_G_DV_TIMINGS ioctl. The detailed timing -information is filled in using the structure &v4l2-dv-timings;. These ioctls take -a pointer to the &v4l2-dv-timings; structure as argument. If the ioctl is not supported -or the timing values are not correct, the driver returns &EINVAL;. - - - - &return-value; - - - - EINVAL - - This ioctl is not supported, or the -VIDIOC_S_DV_TIMINGS parameter was unsuitable. - - - - EBUSY - - The device is busy and therefore can not change the timings. - - - - - - struct <structname>v4l2_bt_timings</structname> - - &cs-str; - - - __u32 - width - Width of the active video in pixels - - - __u32 - height - Height of the active video in lines - - - __u32 - interlaced - Progressive (0) or interlaced (1) - - - __u32 - polarities - This is a bit mask that defines polarities of sync signals. -bit 0 (V4L2_DV_VSYNC_POS_POL) is for vertical sync polarity and bit 1 (V4L2_DV_HSYNC_POS_POL) is for horizontal sync polarity. If the bit is set -(1) it is positive polarity and if is cleared (0), it is negative polarity. - - - __u64 - pixelclock - Pixel clock in Hz. Ex. 74.25MHz->74250000 - - - __u32 - hfrontporch - Horizontal front porch in pixels - - - __u32 - hsync - Horizontal sync length in pixels - - - __u32 - hbackporch - Horizontal back porch in pixels - - - __u32 - vfrontporch - Vertical front porch in lines - - - __u32 - vsync - Vertical sync length in lines - - - __u32 - vbackporch - Vertical back porch in lines - - - __u32 - il_vfrontporch - Vertical front porch in lines for bottom field of interlaced field formats - - - __u32 - il_vsync - Vertical sync length in lines for bottom field of interlaced field formats - - - __u32 - il_vbackporch - Vertical back porch in lines for bottom field of interlaced field formats - - - -
- - - struct <structname>v4l2_dv_timings</structname> - - &cs-str; - - - __u32 - type - - Type of DV timings as listed in . - - - union - - - - - - &v4l2-bt-timings; - bt - Timings defined by BT.656/1120 specifications - - - - __u32 - reserved[32] - - - - -
- - - DV Timing types - - &cs-str; - - - Timing type - value - Description - - - - - - - - V4L2_DV_BT_656_1120 - 0 - BT.656/1120 timings - - - -
- - - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-g-std.xml b/trunk/Documentation/DocBook/v4l/vidioc-g-std.xml index 912f8513e5da..b6f5d267e856 100644 --- a/trunk/Documentation/DocBook/v4l/vidioc-g-std.xml +++ b/trunk/Documentation/DocBook/v4l/vidioc-g-std.xml @@ -86,12 +86,6 @@ standards. VIDIOC_S_STD parameter was unsuitable. - - EBUSY - - The device is busy and therefore can not change the standard - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-query-dv-preset.xml b/trunk/Documentation/DocBook/v4l/vidioc-query-dv-preset.xml deleted file mode 100644 index 87e4f0f6151c..000000000000 --- a/trunk/Documentation/DocBook/v4l/vidioc-query-dv-preset.xml +++ /dev/null @@ -1,85 +0,0 @@ - - - ioctl VIDIOC_QUERY_DV_PRESET - &manvol; - - - - VIDIOC_QUERY_DV_PRESET - Sense the DV preset received by the current -input - - - - - - int ioctl - int fd - int request - &v4l2-dv-preset; *argp - - - - - - Arguments - - - - fd - - &fd; - - - - request - - VIDIOC_QUERY_DV_PRESET - - - - argp - - - - - - - - - Description - - The hardware may be able to detect the current DV preset -automatically, similar to sensing the video standard. To do so, applications -call VIDIOC_QUERY_DV_PRESET with a pointer to a -&v4l2-dv-preset; type. Once the hardware detects a preset, that preset is -returned in the preset field of &v4l2-dv-preset;. When detection is not -possible or fails, the value V4L2_DV_INVALID is returned. - - - - &return-value; - - - EINVAL - - This ioctl is not supported. - - - - EBUSY - - The device is busy and therefore can not sense the preset - - - - - - - diff --git a/trunk/Documentation/DocBook/v4l/vidioc-querystd.xml b/trunk/Documentation/DocBook/v4l/vidioc-querystd.xml index 1a9e60393091..b5a7ff934486 100644 --- a/trunk/Documentation/DocBook/v4l/vidioc-querystd.xml +++ b/trunk/Documentation/DocBook/v4l/vidioc-querystd.xml @@ -70,12 +70,6 @@ current video input or output. This ioctl is not supported. - - EBUSY - - The device is busy and therefore can not detect the standard - - diff --git a/trunk/Documentation/SubmitChecklist b/trunk/Documentation/SubmitChecklist index 1053a56be3b1..78a9168ff377 100644 --- a/trunk/Documentation/SubmitChecklist +++ b/trunk/Documentation/SubmitChecklist @@ -15,7 +15,7 @@ kernel patches. 2: Passes allnoconfig, allmodconfig 3: Builds on multiple CPU architectures by using local cross-compile tools - or some other build farm. + or something like PLM at OSDL. 4: ppc64 is a good architecture for cross-compilation checking because it tends to use `unsigned long' for 64-bit quantities. @@ -88,6 +88,3 @@ kernel patches. 24: All memory barriers {e.g., barrier(), rmb(), wmb()} need a comment in the source code that explains the logic of what they are doing and why. - -25: If any ioctl's are added by the patch, then also update - Documentation/ioctl/ioctl-number.txt. diff --git a/trunk/Documentation/blackfin/00-INDEX b/trunk/Documentation/blackfin/00-INDEX index c34e12440fec..d6840a91e1e1 100644 --- a/trunk/Documentation/blackfin/00-INDEX +++ b/trunk/Documentation/blackfin/00-INDEX @@ -1,6 +1,9 @@ 00-INDEX - This file +cache-lock.txt + - HOWTO for blackfin cache locking. + cachefeatures.txt - Supported cache features. diff --git a/trunk/Documentation/blackfin/Makefile b/trunk/Documentation/blackfin/Makefile deleted file mode 100644 index 773dbb103f1c..000000000000 --- a/trunk/Documentation/blackfin/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -obj-m := gptimers-example.o - -all: modules - -modules clean: - $(MAKE) -C ../.. SUBDIRS=$(PWD) $@ diff --git a/trunk/Documentation/blackfin/cache-lock.txt b/trunk/Documentation/blackfin/cache-lock.txt new file mode 100644 index 000000000000..88ba1e6c31c3 --- /dev/null +++ b/trunk/Documentation/blackfin/cache-lock.txt @@ -0,0 +1,48 @@ +/* + * File: Documentation/blackfin/cache-lock.txt + * Based on: + * Author: + * + * Created: + * Description: This file contains the simple DMA Implementation for Blackfin + * + * Rev: $Id: cache-lock.txt 2384 2006-11-01 04:12:43Z magicyang $ + * + * Modified: + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * + */ + +How to lock your code in cache in uClinux/blackfin +-------------------------------------------------- + +There are only a few steps required to lock your code into the cache. +Currently you can lock the code by Way. + +Below are the interface provided for locking the cache. + + +1. cache_grab_lock(int Ways); + +This function grab the lock for locking your code into the cache specified +by Ways. + + +2. cache_lock(int Ways); + +This function should be called after your critical code has been executed. +Once the critical code exits, the code is now loaded into the cache. This +function locks the code into the cache. + + +So, the example sequence will be: + + cache_grab_lock(WAY0_L); /* Grab the lock */ + + critical_code(); /* Execute the code of interest */ + + cache_lock(WAY0_L); /* Lock the cache */ + +Where WAY0_L signifies WAY0 locking. diff --git a/trunk/Documentation/blackfin/cachefeatures.txt b/trunk/Documentation/blackfin/cachefeatures.txt index 75de51f94515..0fbec23becb5 100644 --- a/trunk/Documentation/blackfin/cachefeatures.txt +++ b/trunk/Documentation/blackfin/cachefeatures.txt @@ -41,6 +41,16 @@ icplb_flush(); dcplb_flush(); + - Locking the cache. + + cache_grab_lock(); + cache_lock(); + + Please refer linux-2.6.x/Documentation/blackfin/cache-lock.txt for how to + lock the cache. + + Locking the cache is optional feature. + - Miscellaneous cache functions. flush_cache_all(); diff --git a/trunk/Documentation/blackfin/gptimers-example.c b/trunk/Documentation/blackfin/gptimers-example.c deleted file mode 100644 index b1bd6340e748..000000000000 --- a/trunk/Documentation/blackfin/gptimers-example.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Simple gptimers example - * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:gptimers - * - * Copyright 2007-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#include -#include - -/* ... random driver includes ... */ - -#define DRIVER_NAME "gptimer_example" - -struct gptimer_data { - uint32_t period, width; -}; -static struct gptimer_data data; - -/* ... random driver state ... */ - -static irqreturn_t gptimer_example_irq(int irq, void *dev_id) -{ - struct gptimer_data *data = dev_id; - - /* make sure it was our timer which caused the interrupt */ - if (!get_gptimer_intr(TIMER5_id)) - return IRQ_NONE; - - /* read the width/period values that were captured for the waveform */ - data->width = get_gptimer_pwidth(TIMER5_id); - data->period = get_gptimer_period(TIMER5_id); - - /* acknowledge the interrupt */ - clear_gptimer_intr(TIMER5_id); - - /* tell the upper layers we took care of things */ - return IRQ_HANDLED; -} - -/* ... random driver code ... */ - -static int __init gptimer_example_init(void) -{ - int ret; - - /* grab the peripheral pins */ - ret = peripheral_request(P_TMR5, DRIVER_NAME); - if (ret) { - printk(KERN_NOTICE DRIVER_NAME ": peripheral request failed\n"); - return ret; - } - - /* grab the IRQ for the timer */ - ret = request_irq(IRQ_TIMER5, gptimer_example_irq, IRQF_SHARED, DRIVER_NAME, &data); - if (ret) { - printk(KERN_NOTICE DRIVER_NAME ": IRQ request failed\n"); - peripheral_free(P_TMR5); - return ret; - } - - /* setup the timer and enable it */ - set_gptimer_config(TIMER5_id, WDTH_CAP | PULSE_HI | PERIOD_CNT | IRQ_ENA); - enable_gptimers(TIMER5bit); - - return 0; -} -module_init(gptimer_example_init); - -static void __exit gptimer_example_exit(void) -{ - disable_gptimers(TIMER5bit); - free_irq(IRQ_TIMER5, &data); - peripheral_free(P_TMR5); -} -module_exit(gptimer_example_exit); - -MODULE_LICENSE("BSD"); diff --git a/trunk/Documentation/fb/viafb.txt b/trunk/Documentation/fb/viafb.txt index f3e046a6a987..67dbf442b0b6 100644 --- a/trunk/Documentation/fb/viafb.txt +++ b/trunk/Documentation/fb/viafb.txt @@ -7,7 +7,7 @@ VIA UniChrome Family(CLE266, PM800 / CN400 / CN300, P4M800CE / P4M800Pro / CN700 / VN800, CX700 / VX700, K8M890, P4M890, - CN896 / P4M900, VX800, VX855) + CN896 / P4M900, VX800) [Driver features] ------------------------ @@ -154,6 +154,13 @@ 0 : No Dual Edge Panel (default) 1 : Dual Edge Panel + viafb_video_dev: + This option is used to specify video output devices(CRT, DVI, LCD) for + duoview case. + For example: + To output video on DVI, we should use: + modprobe viafb viafb_video_dev=DVI... + viafb_lcd_port: This option is used to specify LCD output port, available values are "DVP0" "DVP1" "DFP_HIGHLOW" "DFP_HIGH" "DFP_LOW". @@ -174,6 +181,9 @@ Notes: and bpp, need to call VIAFB specified ioctl interface VIAFB_SET_DEVICE instead of calling common ioctl function FBIOPUT_VSCREENINFO since viafb doesn't support multi-head well, or it will cause screen crush. + 4. VX800 2D accelerator hasn't been supported in this driver yet. When + using driver on VX800, the driver will disable the acceleration + function as default. [Configure viafb with "fbset" tool] diff --git a/trunk/Documentation/filesystems/00-INDEX b/trunk/Documentation/filesystems/00-INDEX index 875d49696b6e..7001782ab932 100644 --- a/trunk/Documentation/filesystems/00-INDEX +++ b/trunk/Documentation/filesystems/00-INDEX @@ -1,5 +1,7 @@ 00-INDEX - this file (info on some of the filesystems supported by linux). +Exporting + - explanation of how to make filesystems exportable. Locking - info on locking rules as they pertain to Linux VFS. 9p.txt @@ -66,8 +68,12 @@ mandatory-locking.txt - info on the Linux implementation of Sys V mandatory file locking. ncpfs.txt - info on Novell Netware(tm) filesystem using NCP protocol. -nfs/ - - nfs-related documentation. +nfs41-server.txt + - info on the Linux server implementation of NFSv4 minor version 1. +nfs-rdma.txt + - how to install and setup the Linux NFS/RDMA client and server software. +nfsroot.txt + - short guide on setting up a diskless box with NFS root filesystem. nilfs2.txt - info and mount options for the NILFS2 filesystem. ntfs.txt @@ -86,6 +92,8 @@ relay.txt - info on relay, for efficient streaming from kernel to user space. romfs.txt - description of the ROMFS filesystem. +rpc-cache.txt + - introduction to the caching mechanisms in the sunrpc layer. seq_file.txt - how to use the seq_file API sharedsubtree.txt diff --git a/trunk/Documentation/filesystems/nfs/Exporting b/trunk/Documentation/filesystems/Exporting similarity index 100% rename from trunk/Documentation/filesystems/nfs/Exporting rename to trunk/Documentation/filesystems/Exporting diff --git a/trunk/Documentation/filesystems/nfs/knfsd-stats.txt b/trunk/Documentation/filesystems/knfsd-stats.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/knfsd-stats.txt rename to trunk/Documentation/filesystems/knfsd-stats.txt diff --git a/trunk/Documentation/filesystems/nfs/nfs-rdma.txt b/trunk/Documentation/filesystems/nfs-rdma.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/nfs-rdma.txt rename to trunk/Documentation/filesystems/nfs-rdma.txt diff --git a/trunk/Documentation/filesystems/nfs/nfs.txt b/trunk/Documentation/filesystems/nfs.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/nfs.txt rename to trunk/Documentation/filesystems/nfs.txt diff --git a/trunk/Documentation/filesystems/nfs/00-INDEX b/trunk/Documentation/filesystems/nfs/00-INDEX deleted file mode 100644 index 2f68cd688769..000000000000 --- a/trunk/Documentation/filesystems/nfs/00-INDEX +++ /dev/null @@ -1,16 +0,0 @@ -00-INDEX - - this file (nfs-related documentation). -Exporting - - explanation of how to make filesystems exportable. -knfsd-stats.txt - - statistics which the NFS server makes available to user space. -nfs.txt - - nfs client, and DNS resolution for fs_locations. -nfs41-server.txt - - info on the Linux server implementation of NFSv4 minor version 1. -nfs-rdma.txt - - how to install and setup the Linux NFS/RDMA client and server software -nfsroot.txt - - short guide on setting up a diskless box with NFS root filesystem. -rpc-cache.txt - - introduction to the caching mechanisms in the sunrpc layer. diff --git a/trunk/Documentation/filesystems/nfs/nfs41-server.txt b/trunk/Documentation/filesystems/nfs41-server.txt similarity index 96% rename from trunk/Documentation/filesystems/nfs/nfs41-server.txt rename to trunk/Documentation/filesystems/nfs41-server.txt index 1bd0d0c05171..5920fe26e6ff 100644 --- a/trunk/Documentation/filesystems/nfs/nfs41-server.txt +++ b/trunk/Documentation/filesystems/nfs41-server.txt @@ -41,7 +41,7 @@ interoperability problems with future clients. Known issues: conformant with the spec (for example, we don't use kerberos on the backchannel correctly). - no trunking support: no clients currently take advantage of - trunking, but this is a mandatory feature, and its use is + trunking, but this is a mandatory failure, and its use is recommended to clients in a number of places. (E.g. to ensure timely renewal in case an existing connection's retry timeouts have gotten too long; see section 8.3 of the draft.) @@ -213,10 +213,3 @@ The following cases aren't supported yet: DESTROY_CLIENTID, DESTROY_SESSION, EXCHANGE_ID. * DESTROY_SESSION MUST be the final operation in the COMPOUND request. -Nonstandard compound limitations: -* No support for a sessions fore channel RPC compound that requires both a - ca_maxrequestsize request and a ca_maxresponsesize reply, so we may - fail to live up to the promise we made in CREATE_SESSION fore channel - negotiation. -* No more than one IO operation (read, write, readdir) allowed per - compound. diff --git a/trunk/Documentation/filesystems/nfs/nfsroot.txt b/trunk/Documentation/filesystems/nfsroot.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/nfsroot.txt rename to trunk/Documentation/filesystems/nfsroot.txt diff --git a/trunk/Documentation/filesystems/porting b/trunk/Documentation/filesystems/porting index a7e9746ee7ea..92b888d540a6 100644 --- a/trunk/Documentation/filesystems/porting +++ b/trunk/Documentation/filesystems/porting @@ -140,7 +140,7 @@ Callers of notify_change() need ->i_mutex now. New super_block field "struct export_operations *s_export_op" for explicit support for exporting, e.g. via NFS. The structure is fully documented at its declaration in include/linux/fs.h, and in -Documentation/filesystems/nfs/Exporting. +Documentation/filesystems/Exporting. Briefly it allows for the definition of decode_fh and encode_fh operations to encode and decode filehandles, and allows the filesystem to use diff --git a/trunk/Documentation/filesystems/nfs/rpc-cache.txt b/trunk/Documentation/filesystems/rpc-cache.txt similarity index 100% rename from trunk/Documentation/filesystems/nfs/rpc-cache.txt rename to trunk/Documentation/filesystems/rpc-cache.txt diff --git a/trunk/Documentation/filesystems/seq_file.txt b/trunk/Documentation/filesystems/seq_file.txt index a1e2e0dda907..0d15ebccf5b0 100644 --- a/trunk/Documentation/filesystems/seq_file.txt +++ b/trunk/Documentation/filesystems/seq_file.txt @@ -248,7 +248,9 @@ code, that is done in the initialization code in the usual way: { struct proc_dir_entry *entry; - proc_create("sequence", 0, NULL, &ct_file_ops); + entry = create_proc_entry("sequence", 0, NULL); + if (entry) + entry->proc_fops = &ct_file_ops; return 0; } diff --git a/trunk/Documentation/gpio.txt b/trunk/Documentation/gpio.txt index 1866c27eec69..e4e7daed2ba8 100644 --- a/trunk/Documentation/gpio.txt +++ b/trunk/Documentation/gpio.txt @@ -531,13 +531,6 @@ and have the following read/write attributes: This file exists only if the pin can be configured as an interrupt generating input pin. - "active_low" ... reads as either 0 (false) or 1 (true). Write - any nonzero value to invert the value attribute both - for reading and writing. Existing and subsequent - poll(2) support configuration via the edge attribute - for "rising" and "falling" edges will follow this - setting. - GPIO controllers have paths like /sys/class/gpio/gpiochip42/ (for the controller implementing GPIOs starting at #42) and have the following read-only attributes: @@ -573,8 +566,6 @@ requested using gpio_request(): int gpio_export_link(struct device *dev, const char *name, unsigned gpio) - /* change the polarity of a GPIO node in sysfs */ - int gpio_sysfs_set_active_low(unsigned gpio, int value); After a kernel driver requests a GPIO, it may only be made available in the sysfs interface by gpio_export(). The driver can control whether the @@ -589,9 +580,3 @@ After the GPIO has been exported, gpio_export_link() allows creating symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can use this to provide the interface under their own device in sysfs with a descriptive name. - -Drivers can use gpio_sysfs_set_active_low() to hide GPIO line polarity -differences between boards from user space. This only affects the -sysfs interface. Polarity change can be done both before and after -gpio_export(), and previously enabled poll(2) support for either -rising or falling edge will be reconfigured to follow this setting. diff --git a/trunk/Documentation/infiniband/ipoib.txt b/trunk/Documentation/infiniband/ipoib.txt index 64eeb55d0c09..6d40f00b358c 100644 --- a/trunk/Documentation/infiniband/ipoib.txt +++ b/trunk/Documentation/infiniband/ipoib.txt @@ -36,11 +36,11 @@ Datagram vs Connected modes fabric with a 2K MTU, the IPoIB MTU will be 2048 - 4 = 2044 bytes. In connected mode, the IB RC (Reliable Connected) transport is used. - Connected mode takes advantage of the connected nature of the IB - transport and allows an MTU up to the maximal IP packet size of 64K, - which reduces the number of IP packets needed for handling large UDP - datagrams, TCP segments, etc and increases the performance for large - messages. + Connected mode is to takes advantage of the connected nature of the + IB transport and allows an MTU up to the maximal IP packet size of + 64K, which reduces the number of IP packets needed for handling + large UDP datagrams, TCP segments, etc and increases the performance + for large messages. In connected mode, the interface's UD QP is still used for multicast and communication with peers that don't support connected mode. In diff --git a/trunk/Documentation/kernel-parameters.txt b/trunk/Documentation/kernel-parameters.txt index 5ba4d9dff113..ab95d3ada5c7 100644 --- a/trunk/Documentation/kernel-parameters.txt +++ b/trunk/Documentation/kernel-parameters.txt @@ -1032,7 +1032,7 @@ and is between 256 and 4096 characters. It is defined in the file No delay ip= [IP_PNP] - See Documentation/filesystems/nfs/nfsroot.txt. + See Documentation/filesystems/nfsroot.txt. ip2= [HW] Set IO/IRQ pairs for up to 4 IntelliPort boards See comment before ip2_setup() in @@ -1553,10 +1553,10 @@ and is between 256 and 4096 characters. It is defined in the file going to be removed in 2.6.29. nfsaddrs= [NFS] - See Documentation/filesystems/nfs/nfsroot.txt. + See Documentation/filesystems/nfsroot.txt. nfsroot= [NFS] nfs root filesystem for disk-less boxes. - See Documentation/filesystems/nfs/nfsroot.txt. + See Documentation/filesystems/nfsroot.txt. nfs.callback_tcpport= [NFS] set the TCP port on which the NFSv4 callback @@ -2729,11 +2729,6 @@ and is between 256 and 4096 characters. It is defined in the file vmpoff= [KNL,S390] Perform z/VM CP command after power off. Format: - vt.cur_default= [VT] Default cursor shape. - Format: 0xCCBBAA, where AA, BB, and CC are the same as - the parameters of the [?A;B;Cc escape sequence; - see VGA-softcursor.txt. Default: 2 = underline. - vt.default_blu= [VT] Format: ,,,..., Change the default blue palette of the console. diff --git a/trunk/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt b/trunk/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt deleted file mode 100644 index 515ebcf1b97d..000000000000 --- a/trunk/Documentation/powerpc/dts-bindings/4xx/ppc440spe-adma.txt +++ /dev/null @@ -1,93 +0,0 @@ -PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator) - -Device nodes needed for operation of the ppc440spe-adma driver -are specified hereby. These are I2O/DMA, DMA and XOR nodes -for DMA engines and Memory Queue Module node. The latter is used -by ADMA driver for configuration of RAID-6 H/W capabilities of -the PPC440SPe. In addition to the nodes and properties described -below, the ranges property of PLB node must specify ranges for -DMA devices. - - i) The I2O node - - Required properties: - - - compatible : "ibm,i2o-440spe"; - - reg : - - dcr-reg : - - Example: - - I2O: i2o@400100000 { - compatible = "ibm,i2o-440spe"; - reg = <0x00000004 0x00100000 0x100>; - dcr-reg = <0x060 0x020>; - }; - - - ii) The DMA node - - Required properties: - - - compatible : "ibm,dma-440spe"; - - cell-index : 1 cell, hardware index of the DMA engine - (typically 0x0 and 0x1 for DMA0 and DMA1) - - reg : - - dcr-reg : - - interrupts : . - - interrupt-parent : needed for interrupt mapping - - Example: - - DMA0: dma0@400100100 { - compatible = "ibm,dma-440spe"; - cell-index = <0>; - reg = <0x00000004 0x00100100 0x100>; - dcr-reg = <0x060 0x020>; - interrupt-parent = <&DMA0>; - interrupts = <0 1>; - #interrupt-cells = <1>; - #address-cells = <0>; - #size-cells = <0>; - interrupt-map = < - 0 &UIC0 0x14 4 - 1 &UIC1 0x16 4>; - }; - - - iii) XOR Accelerator node - - Required properties: - - - compatible : "amcc,xor-accelerator"; - - reg : - - interrupts : - - interrupt-parent : for interrupt mapping - - Example: - - xor-accel@400200000 { - compatible = "amcc,xor-accelerator"; - reg = <0x00000004 0x00200000 0x400>; - interrupt-parent = <&UIC1>; - interrupts = <0x1f 4>; - }; - - - iv) Memory Queue Module node - - Required properties: - - - compatible : "ibm,mq-440spe"; - - dcr-reg : - - Example: - - MQ0: mq { - compatible = "ibm,mq-440spe"; - dcr-reg = <0x040 0x020>; - }; - diff --git a/trunk/Documentation/video4linux/gspca.txt b/trunk/Documentation/video4linux/gspca.txt index 1800a62cf135..319d9838e87e 100644 --- a/trunk/Documentation/video4linux/gspca.txt +++ b/trunk/Documentation/video4linux/gspca.txt @@ -12,7 +12,6 @@ m5602 0402:5602 ALi Video Camera Controller spca501 040a:0002 Kodak DVC-325 spca500 040a:0300 Kodak EZ200 zc3xx 041e:041e Creative WebCam Live! -ov519 041e:4003 Video Blaster WebCam Go Plus spca500 041e:400a Creative PC-CAM 300 sunplus 041e:400b Creative PC-CAM 600 sunplus 041e:4012 PC-Cam350 @@ -169,14 +168,10 @@ sunplus 055f:c650 Mustek MDC5500Z zc3xx 055f:d003 Mustek WCam300A zc3xx 055f:d004 Mustek WCam300 AN conex 0572:0041 Creative Notebook cx11646 -ov519 05a9:0511 Video Blaster WebCam 3/WebCam Plus, D-Link USB Digital Video Camera -ov519 05a9:0518 Creative WebCam ov519 05a9:0519 OV519 Microphone ov519 05a9:0530 OmniVision -ov519 05a9:2800 OmniVision SuperCAM ov519 05a9:4519 Webcam Classic ov519 05a9:8519 OmniVision -ov519 05a9:a511 D-Link USB Digital Video Camera ov519 05a9:a518 D-Link DSB-C310 Webcam sunplus 05da:1018 Digital Dream Enigma 1.3 stk014 05e1:0893 Syntek DV4000 @@ -192,7 +187,7 @@ ov534 06f8:3002 Hercules Blog Webcam ov534 06f8:3003 Hercules Dualpix HD Weblog sonixj 06f8:3004 Hercules Classic Silver sonixj 06f8:3008 Hercules Deluxe Optical Glass -pac7302 06f8:3009 Hercules Classic Link +pac7311 06f8:3009 Hercules Classic Link spca508 0733:0110 ViewQuest VQ110 spca501 0733:0401 Intel Create and Share spca501 0733:0402 ViewQuest M318B @@ -204,7 +199,6 @@ sunplus 0733:2221 Mercury Digital Pro 3.1p sunplus 0733:3261 Concord 3045 spca536a sunplus 0733:3281 Cyberpix S550V spca506 0734:043b 3DeMon USB Capture aka -ov519 0813:0002 Dual Mode USB Camera Plus spca500 084d:0003 D-Link DSC-350 spca500 08ca:0103 Aiptek PocketDV sunplus 08ca:0104 Aiptek PocketDVII 1.3 @@ -242,15 +236,15 @@ pac7311 093a:2603 Philips SPC 500 NC pac7311 093a:2608 Trust WB-3300p pac7311 093a:260e Gigaware VGA PC Camera, Trust WB-3350p, SIGMA cam 2350 pac7311 093a:260f SnakeCam -pac7302 093a:2620 Apollo AC-905 -pac7302 093a:2621 PAC731x -pac7302 093a:2622 Genius Eye 312 -pac7302 093a:2624 PAC7302 -pac7302 093a:2626 Labtec 2200 -pac7302 093a:2628 Genius iLook 300 -pac7302 093a:2629 Genious iSlim 300 -pac7302 093a:262a Webcam 300k -pac7302 093a:262c Philips SPC 230 NC +pac7311 093a:2620 Apollo AC-905 +pac7311 093a:2621 PAC731x +pac7311 093a:2622 Genius Eye 312 +pac7311 093a:2624 PAC7302 +pac7311 093a:2626 Labtec 2200 +pac7311 093a:2628 Genius iLook 300 +pac7311 093a:2629 Genious iSlim 300 +pac7311 093a:262a Webcam 300k +pac7311 093a:262c Philips SPC 230 NC jeilinj 0979:0280 Sakar 57379 zc3xx 0ac8:0302 Z-star Vimicro zc0302 vc032x 0ac8:0321 Vimicro generic vc0321 @@ -265,7 +259,6 @@ vc032x 0ac8:c002 Sony embedded vimicro vc032x 0ac8:c301 Samsung Q1 Ultra Premium spca508 0af9:0010 Hama USB Sightcam 100 spca508 0af9:0011 Hama USB Sightcam 100 -ov519 0b62:0059 iBOT2 Webcam sonixb 0c45:6001 Genius VideoCAM NB sonixb 0c45:6005 Microdia Sweex Mini Webcam sonixb 0c45:6007 Sonix sn9c101 + Tas5110D @@ -325,10 +318,8 @@ sn9c20x 0c45:62b3 PC Camera (SN9C202 + OV9655) sn9c20x 0c45:62bb PC Camera (SN9C202 + OV7660) sn9c20x 0c45:62bc PC Camera (SN9C202 + HV7131R) sunplus 0d64:0303 Sunplus FashionCam DXG -ov519 0e96:c001 TRUST 380 USB2 SPACEC@M etoms 102c:6151 Qcam Sangha CIF etoms 102c:6251 Qcam xxxxxx VGA -ov519 1046:9967 W9967CF/W9968CF WebCam IC, Video Blaster WebCam Go zc3xx 10fd:0128 Typhoon Webshot II USB 300k 0x0128 spca561 10fd:7e50 FlyCam Usb 100 zc3xx 10fd:8050 Typhoon Webshot II USB 300k @@ -341,12 +332,7 @@ spca501 1776:501c Arowana 300K CMOS Camera t613 17a1:0128 TASCORP JPEG Webcam, NGS Cyclops vc032x 17ef:4802 Lenovo Vc0323+MI1310_SOC pac207 2001:f115 D-Link DSB-C120 -sq905c 2770:9050 sq905c -sq905c 2770:905c DualCamera -sq905 2770:9120 Argus Digital Camera DC1512 -sq905c 2770:913d sq905c spca500 2899:012c Toptro Industrial -ov519 8020:ef04 ov519 spca508 8086:0110 Intel Easy PC Camera spca500 8086:0630 Intel Pocket PC Camera spca506 99fa:8988 Grandtec V.cap diff --git a/trunk/Documentation/video4linux/sh_mobile_ceu_camera.txt b/trunk/Documentation/video4linux/sh_mobile_ceu_camera.txt deleted file mode 100644 index 2ae16349a78d..000000000000 --- a/trunk/Documentation/video4linux/sh_mobile_ceu_camera.txt +++ /dev/null @@ -1,157 +0,0 @@ - Cropping and Scaling algorithm, used in the sh_mobile_ceu_camera driver - ======================================================================= - -Terminology ------------ - -sensor scales: horizontal and vertical scales, configured by the sensor driver -host scales: -"- host driver -combined scales: sensor_scale * host_scale - - -Generic scaling / cropping scheme ---------------------------------- - --1-- -| --2-- -\ -| --\ -| --\ -+-5-- -\ -- -3-- -| ---\ -| --- -4-- -\ -| -\ -| - -6-- -| -| - -6'- -| -/ -| --- -4'- -/ -| ---/ -+-5'- -/ -| -- -3'- -| --/ -| --/ --2'- -/ -| -| --1'- - -Produced by user requests: - -S_CROP(left / top = (5) - (1), width / height = (5') - (5)) -S_FMT(width / height = (6') - (6)) - -Here: - -(1) to (1') - whole max width or height -(1) to (2) - sensor cropped left or top -(2) to (2') - sensor cropped width or height -(3) to (3') - sensor scale -(3) to (4) - CEU cropped left or top -(4) to (4') - CEU cropped width or height -(5) to (5') - reverse sensor scale applied to CEU cropped width or height -(2) to (5) - reverse sensor scale applied to CEU cropped left or top -(6) to (6') - CEU scale - user window - - -S_FMT ------ - -Do not touch input rectangle - it is already optimal. - -1. Calculate current sensor scales: - - scale_s = ((3') - (3)) / ((2') - (2)) - -2. Calculate "effective" input crop (sensor subwindow) - CEU crop scaled back at -current sensor scales onto input window - this is user S_CROP: - - width_u = (5') - (5) = ((4') - (4)) * scale_s - -3. Calculate new combined scales from "effective" input window to requested user -window: - - scale_comb = width_u / ((6') - (6)) - -4. Calculate sensor output window by applying combined scales to real input -window: - - width_s_out = ((2') - (2)) / scale_comb - -5. Apply iterative sensor S_FMT for sensor output window. - - subdev->video_ops->s_fmt(.width = width_s_out) - -6. Retrieve sensor output window (g_fmt) - -7. Calculate new sensor scales: - - scale_s_new = ((3')_new - (3)_new) / ((2') - (2)) - -8. Calculate new CEU crop - apply sensor scales to previously calculated -"effective" crop: - - width_ceu = (4')_new - (4)_new = width_u / scale_s_new - left_ceu = (4)_new - (3)_new = ((5) - (2)) / scale_s_new - -9. Use CEU cropping to crop to the new window: - - ceu_crop(.width = width_ceu, .left = left_ceu) - -10. Use CEU scaling to scale to the requested user window: - - scale_ceu = width_ceu / width - - -S_CROP ------- - -If old scale applied to new crop is invalid produce nearest new scale possible - -1. Calculate current combined scales. - - scale_comb = (((4') - (4)) / ((6') - (6))) * (((2') - (2)) / ((3') - (3))) - -2. Apply iterative sensor S_CROP for new input window. - -3. If old combined scales applied to new crop produce an impossible user window, -adjust scales to produce nearest possible window. - - width_u_out = ((5') - (5)) / scale_comb - - if (width_u_out > max) - scale_comb = ((5') - (5)) / max; - else if (width_u_out < min) - scale_comb = ((5') - (5)) / min; - -4. Issue G_CROP to retrieve actual input window. - -5. Using actual input window and calculated combined scales calculate sensor -target output window. - - width_s_out = ((3') - (3)) = ((2') - (2)) / scale_comb - -6. Apply iterative S_FMT for new sensor target output window. - -7. Issue G_FMT to retrieve the actual sensor output window. - -8. Calculate sensor scales. - - scale_s = ((3') - (3)) / ((2') - (2)) - -9. Calculate sensor output subwindow to be cropped on CEU by applying sensor -scales to the requested window. - - width_ceu = ((5') - (5)) / scale_s - -10. Use CEU cropping for above calculated window. - -11. Calculate CEU scales from sensor scales from results of (10) and user window -from (3) - - scale_ceu = calc_scale(((5') - (5)), &width_u_out) - -12. Apply CEU scales. - --- -Author: Guennadi Liakhovetski diff --git a/trunk/Documentation/video4linux/v4l2-framework.txt b/trunk/Documentation/video4linux/v4l2-framework.txt index 74d677c8b036..b806edaf3e75 100644 --- a/trunk/Documentation/video4linux/v4l2-framework.txt +++ b/trunk/Documentation/video4linux/v4l2-framework.txt @@ -561,8 +561,6 @@ video_device helper functions There are a few useful helper functions: -- file/video_device private data - You can set/get driver private data in the video_device struct using: void *video_get_drvdata(struct video_device *vdev); @@ -577,7 +575,8 @@ struct video_device *video_devdata(struct file *file); returns the video_device belonging to the file struct. -The video_drvdata function combines video_get_drvdata with video_devdata: +The final helper function combines video_get_drvdata with +video_devdata: void *video_drvdata(struct file *file); @@ -585,17 +584,6 @@ You can go from a video_device struct to the v4l2_device struct using: struct v4l2_device *v4l2_dev = vdev->v4l2_dev; -- Device node name - -The video_device node kernel name can be retrieved using - -const char *video_device_node_name(struct video_device *vdev); - -The name is used as a hint by userspace tools such as udev. The function -should be used where possible instead of accessing the video_device::num and -video_device::minor fields. - - video buffer helper functions ----------------------------- diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index d6a27110a747..0a32c3ec6b1c 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -5991,9 +5991,9 @@ F: sound/soc/codecs/wm8350.* F: sound/soc/codecs/wm8400.* X.25 NETWORK LAYER -M: Andrew Hendry +M: Henner Eisen L: linux-x25@vger.kernel.org -S: Odd Fixes +S: Maintained F: Documentation/networking/x25* F: include/net/x25* F: net/x25/ diff --git a/trunk/arch/alpha/include/asm/elf.h b/trunk/arch/alpha/include/asm/elf.h index 9baae8afe8a3..5c75c1b2352a 100644 --- a/trunk/arch/alpha/include/asm/elf.h +++ b/trunk/arch/alpha/include/asm/elf.h @@ -81,6 +81,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_ALPHA +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 8192 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/arm/include/asm/elf.h b/trunk/arch/arm/include/asm/elf.h index a399bb5730f1..6aac3f5bb2f3 100644 --- a/trunk/arch/arm/include/asm/elf.h +++ b/trunk/arch/arm/include/asm/elf.h @@ -101,6 +101,7 @@ extern int arm_elf_read_implies_exec(const struct elf32_hdr *, int); int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs); #define ELF_CORE_COPY_TASK_REGS dump_task_regs +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/arm/kernel/armksyms.c b/trunk/arch/arm/kernel/armksyms.c index 8214bfebfaca..0e627705f746 100644 --- a/trunk/arch/arm/kernel/armksyms.c +++ b/trunk/arch/arm/kernel/armksyms.c @@ -48,7 +48,27 @@ extern void __aeabi_uidivmod(void); extern void __aeabi_ulcmp(void); extern void fpundefinstr(void); +extern void fp_enter(void); +/* + * This has a special calling convention; it doesn't + * modify any of the usual registers, except for LR. + */ +#define EXPORT_CRC_ALIAS(sym) __CRC_SYMBOL(sym, "") + +#define EXPORT_SYMBOL_ALIAS(sym,orig) \ + EXPORT_CRC_ALIAS(sym) \ + static const struct kernel_symbol __ksymtab_##sym \ + __used __attribute__((section("__ksymtab"))) = \ + { (unsigned long)&orig, #sym }; + +/* + * floating point math emulator support. + * These symbols will never change their calling convention... + */ +EXPORT_SYMBOL_ALIAS(kern_fp_enter,fp_enter); +EXPORT_SYMBOL_ALIAS(fp_printk,printk); +EXPORT_SYMBOL_ALIAS(fp_send_sig,send_sig); EXPORT_SYMBOL(__backtrace); diff --git a/trunk/arch/arm/kernel/vmlinux.lds.S b/trunk/arch/arm/kernel/vmlinux.lds.S index 4957e13ef55b..71151bd87a36 100644 --- a/trunk/arch/arm/kernel/vmlinux.lds.S +++ b/trunk/arch/arm/kernel/vmlinux.lds.S @@ -65,11 +65,11 @@ SECTIONS __init_end = .; #endif - /* - * unwind exit sections must be discarded before the rest of the - * unwind sections get included. - */ - /DISCARD/ : { + /DISCARD/ : { /* Exit code and data */ + EXIT_TEXT + EXIT_DATA + *(.exitcall.exit) + *(.discard) *(.ARM.exidx.exit.text) *(.ARM.extab.exit.text) #ifndef CONFIG_HOTPLUG_CPU @@ -238,9 +238,6 @@ SECTIONS STABS_DEBUG .comment 0 : { *(.comment) } - - /* Default discards */ - DISCARDS } /* diff --git a/trunk/arch/arm/mach-bcmring/arch.c b/trunk/arch/arm/mach-bcmring/arch.c index 53dd2a9eecf9..fbe6fa02c882 100644 --- a/trunk/arch/arm/mach-bcmring/arch.c +++ b/trunk/arch/arm/mach-bcmring/arch.c @@ -70,19 +70,9 @@ static struct ctl_table bcmring_sysctl_reboot[] = { {} }; -static struct resource nand_resource[] = { - [0] = { - .start = MM_ADDR_IO_NAND, - .end = MM_ADDR_IO_NAND + 0x1000 - 1, - .flags = IORESOURCE_MEM, - }, -}; - static struct platform_device nand_device = { .name = "bcm-nand", .id = -1, - .resource = nand_resource, - .num_resources = ARRAY_SIZE(nand_resource), }; static struct platform_device *devices[] __initdata = { diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h deleted file mode 100644 index 387376ffb56b..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h +++ /dev/null @@ -1,66 +0,0 @@ -/***************************************************************************** -* Copyright 2001 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* -* -***************************************************************************** -* -* REG_NAND.h -* -* PURPOSE: -* -* This file contains definitions for the nand registers: -* -* NOTES: -* -*****************************************************************************/ - -#if !defined(__ASM_ARCH_REG_NAND_H) -#define __ASM_ARCH_REG_NAND_H - -/* ---- Include Files ---------------------------------------------------- */ -#include -#include - -/* ---- Constants and Types ---------------------------------------------- */ - -#define HW_NAND_BASE MM_IO_BASE_NAND /* NAND Flash */ - -/* DMA accesses by the bootstrap need hard nonvirtual addresses */ -#define REG_NAND_CMD __REG16(HW_NAND_BASE + 0) -#define REG_NAND_ADDR __REG16(HW_NAND_BASE + 4) - -#define REG_NAND_PHYS_DATA16 (HW_NAND_BASE + 8) -#define REG_NAND_PHYS_DATA8 (HW_NAND_BASE + 8) -#define REG_NAND_DATA16 __REG16(REG_NAND_PHYS_DATA16) -#define REG_NAND_DATA8 __REG8(REG_NAND_PHYS_DATA8) - -/* use appropriate offset to make sure it start at the 1K boundary */ -#define REG_NAND_PHYS_DATA_DMA (HW_NAND_BASE + 0x400) -#define REG_NAND_DATA_DMA __REG32(REG_NAND_PHYS_DATA_DMA) - -/* Linux DMA requires physical address of the data register */ -#define REG_NAND_DATA16_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16) -#define REG_NAND_DATA8_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8) -#define REG_NAND_DATA_PADDR HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA) - -#define NAND_BUS_16BIT() (0) -#define NAND_BUS_8BIT() (!NAND_BUS_16BIT()) - -/* Register offsets */ -#define REG_NAND_CMD_OFFSET (0) -#define REG_NAND_ADDR_OFFSET (4) -#define REG_NAND_DATA8_OFFSET (8) - -#endif diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h deleted file mode 100644 index 06a355481ea6..000000000000 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ /dev/null @@ -1,237 +0,0 @@ -/***************************************************************************** -* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved. -* -* Unless you and Broadcom execute a separate written software license -* agreement governing use of this software, this software is licensed to you -* under the terms of the GNU General Public License version 2, available at -* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -* -* Notwithstanding the above, under no circumstances may you combine this -* software in any way with any other Broadcom software provided under a -* license other than the GPL, without Broadcom's express prior written -* consent. -*****************************************************************************/ - -/* -* -***************************************************************************** -* -* REG_UMI.h -* -* PURPOSE: -* -* This file contains definitions for the nand registers: -* -* NOTES: -* -*****************************************************************************/ - -#if !defined(__ASM_ARCH_REG_UMI_H) -#define __ASM_ARCH_REG_UMI_H - -/* ---- Include Files ---------------------------------------------------- */ -#include -#include - -/* ---- Constants and Types ---------------------------------------------- */ - -/* Unified Memory Interface Ctrl Register */ -#define HW_UMI_BASE MM_IO_BASE_UMI - -/* Flash bank 0 timing and control register */ -#define REG_UMI_FLASH0_TCR __REG32(HW_UMI_BASE + 0x00) -/* Flash bank 1 timing and control register */ -#define REG_UMI_FLASH1_TCR __REG32(HW_UMI_BASE + 0x04) -/* Flash bank 2 timing and control register */ -#define REG_UMI_FLASH2_TCR __REG32(HW_UMI_BASE + 0x08) -/* MMD interface and control register */ -#define REG_UMI_MMD_ICR __REG32(HW_UMI_BASE + 0x0c) -/* NAND timing and control register */ -#define REG_UMI_NAND_TCR __REG32(HW_UMI_BASE + 0x18) -/* NAND ready/chip select register */ -#define REG_UMI_NAND_RCSR __REG32(HW_UMI_BASE + 0x1c) -/* NAND ECC control & status register */ -#define REG_UMI_NAND_ECC_CSR __REG32(HW_UMI_BASE + 0x20) -/* NAND ECC data register XXB2B1B0 */ -#define REG_UMI_NAND_ECC_DATA __REG32(HW_UMI_BASE + 0x24) -/* BCH ECC Parameter N */ -#define REG_UMI_BCH_N __REG32(HW_UMI_BASE + 0x40) -/* BCH ECC Parameter T */ -#define REG_UMI_BCH_K __REG32(HW_UMI_BASE + 0x44) -/* BCH ECC Parameter K */ -#define REG_UMI_BCH_T __REG32(HW_UMI_BASE + 0x48) -/* BCH ECC Contro Status */ -#define REG_UMI_BCH_CTRL_STATUS __REG32(HW_UMI_BASE + 0x4C) -/* BCH WR ECC 31:0 */ -#define REG_UMI_BCH_WR_ECC_0 __REG32(HW_UMI_BASE + 0x50) -/* BCH WR ECC 63:32 */ -#define REG_UMI_BCH_WR_ECC_1 __REG32(HW_UMI_BASE + 0x54) -/* BCH WR ECC 95:64 */ -#define REG_UMI_BCH_WR_ECC_2 __REG32(HW_UMI_BASE + 0x58) -/* BCH WR ECC 127:96 */ -#define REG_UMI_BCH_WR_ECC_3 __REG32(HW_UMI_BASE + 0x5c) -/* BCH WR ECC 155:128 */ -#define REG_UMI_BCH_WR_ECC_4 __REG32(HW_UMI_BASE + 0x60) -/* BCH Read Error Location 1,0 */ -#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE + 0x64) -/* BCH Read Error Location 3,2 */ -#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE + 0x68) -/* BCH Read Error Location 5,4 */ -#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE + 0x6c) -/* BCH Read Error Location 7,6 */ -#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE + 0x70) -/* BCH Read Error Location 9,8 */ -#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE + 0x74) -/* BCH Read Error Location 11,10 */ -#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE + 0x78) - -/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */ -/* Enable wait pin during burst write or read */ -#define REG_UMI_TCR_WAITEN 0x80000000 -/* Enable mem ctrlr to work iwth ext mem of lower freq than AHB clk */ -#define REG_UMI_TCR_LOWFREQ 0x40000000 -/* 1=synch write, 0=async write */ -#define REG_UMI_TCR_MEMTYPE_SYNCWRITE 0x20000000 -/* 1=synch read, 0=async read */ -#define REG_UMI_TCR_MEMTYPE_SYNCREAD 0x10000000 -/* 1=page mode read, 0=normal mode read */ -#define REG_UMI_TCR_MEMTYPE_PAGEREAD 0x08000000 -/* page size/burst size (wrap only) */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK 0x07000000 -/* 4 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_4 0x00000000 -/* 8 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_8 0x01000000 -/* 16 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_16 0x02000000 -/* 32 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_32 0x03000000 -/* 64 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_64 0x04000000 -/* 128 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_128 0x05000000 -/* 256 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_256 0x06000000 -/* 512 word */ -#define REG_UMI_TCR_MEMTYPE_PGSZ_512 0x07000000 -/* Page read access cycle / Burst write latency (n+2 / n+1) */ -#define REG_UMI_TCR_TPRC_TWLC_MASK 0x00f80000 -/* Bus turnaround cycle (n) */ -#define REG_UMI_TCR_TBTA_MASK 0x00070000 -/* Write pulse width cycle (n+1) */ -#define REG_UMI_TCR_TWP_MASK 0x0000f800 -/* Write recovery cycle (n+1) */ -#define REG_UMI_TCR_TWR_MASK 0x00000600 -/* Write address setup cycle (n+1) */ -#define REG_UMI_TCR_TAS_MASK 0x00000180 -/* Output enable delay cycle (n) */ -#define REG_UMI_TCR_TOE_MASK 0x00000060 -/* Read access cycle / Burst read latency (n+2 / n+1) */ -#define REG_UMI_TCR_TRC_TLC_MASK 0x0000001f - -/* REG_UMI_MMD_ICR bits */ -/* Flash write protection pin control */ -#define REG_UMI_MMD_ICR_FLASH_WP 0x8000 -/* Extend hold time for sram0, sram1 csn (39 MHz operation) */ -#define REG_UMI_MMD_ICR_XHCS 0x4000 -/* Enable SDRAM 2 interface control */ -#define REG_UMI_MMD_ICR_SDRAM2EN 0x2000 -/* Enable merge of flash banks 0/1 to 512 MBit bank */ -#define REG_UMI_MMD_ICR_INST512 0x1000 -/* Enable merge of flash banks 1/2 to 512 MBit bank */ -#define REG_UMI_MMD_ICR_DATA512 0x0800 -/* Enable SDRAM interface control */ -#define REG_UMI_MMD_ICR_SDRAMEN 0x0400 -/* Polarity of busy state of Burst Wait Signal */ -#define REG_UMI_MMD_ICR_WAITPOL 0x0200 -/* Enable burst clock stopped when not accessing external burst flash/sram */ -#define REG_UMI_MMD_ICR_BCLKSTOP 0x0100 -/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */ -#define REG_UMI_MMD_ICR_PERI1EN 0x0080 -/* Enable the peri2_csn to replace sdram_csn */ -#define REG_UMI_MMD_ICR_PERI2EN 0x0040 -/* Enable the peri3_csn to replace sdram2_csn */ -#define REG_UMI_MMD_ICR_PERI3EN 0x0020 -/* Enable sram bank1 for H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSB1 0x0010 -/* Enable sram bank0 for H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSB0 0x0008 -/* Polarity for assert3ed state of H/W controlled MRS */ -#define REG_UMI_MMD_ICR_MRSPOL 0x0004 -/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */ -/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */ -#define REG_UMI_MMD_ICR_MRSMODE 0x0002 -/* MRS state for S/W controlled mode */ -#define REG_UMI_MMD_ICR_MRSSTATE 0x0001 - -/* REG_UMI_NAND_TCR bits */ -/* Enable software to control CS */ -#define REG_UMI_NAND_TCR_CS_SWCTRL 0x80000000 -/* 16-bit nand wordsize if set */ -#define REG_UMI_NAND_TCR_WORD16 0x40000000 -/* Bus turnaround cycle (n) */ -#define REG_UMI_NAND_TCR_TBTA_MASK 0x00070000 -/* Write pulse width cycle (n+1) */ -#define REG_UMI_NAND_TCR_TWP_MASK 0x0000f800 -/* Write recovery cycle (n+1) */ -#define REG_UMI_NAND_TCR_TWR_MASK 0x00000600 -/* Write address setup cycle (n+1) */ -#define REG_UMI_NAND_TCR_TAS_MASK 0x00000180 -/* Output enable delay cycle (n) */ -#define REG_UMI_NAND_TCR_TOE_MASK 0x00000060 -/* Read access cycle (n+2) */ -#define REG_UMI_NAND_TCR_TRC_TLC_MASK 0x0000001f - -/* REG_UMI_NAND_RCSR bits */ -/* Status: Ready=1, Busy=0 */ -#define REG_UMI_NAND_RCSR_RDY 0x02 -/* Keep CS asserted during operation */ -#define REG_UMI_NAND_RCSR_CS_ASSERTED 0x01 - -/* REG_UMI_NAND_ECC_CSR bits */ -/* Interrupt status - read-only */ -#define REG_UMI_NAND_ECC_CSR_NANDINT 0x80000000 -/* Read: Status of ECC done, Write: clear ECC interrupt */ -#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW 0x00800000 -/* Read: Status of R/B, Write: clear R/B interrupt */ -#define REG_UMI_NAND_ECC_CSR_RBINT_RAW 0x00400000 -/* 1 = Enable ECC Interrupt */ -#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE 0x00008000 -/* 1 = Assert interrupt at rising edge of R/B_ */ -#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE 0x00004000 -/* Calculate ECC by 0=512 bytes, 1=256 bytes */ -#define REG_UMI_NAND_ECC_CSR_256BYTE 0x00000080 -/* Enable ECC in hardware */ -#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE 0x00000001 - -/* REG_UMI_BCH_CTRL_STATUS bits */ -/* Shift to Indicate Number of correctable errors detected */ -#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20 -/* Indicate Number of correctable errors detected */ -#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000 -/* Indicate Errors detected during read but uncorrectable */ -#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR 0x00080000 -/* Indicate Errors detected during read and are correctable */ -#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR 0x00040000 -/* Flag indicates BCH's ECC status of read process are valid */ -#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID 0x00020000 -/* Flag indicates BCH's ECC status of write process are valid */ -#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID 0x00010000 -/* Pause ECC calculation */ -#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010 -/* Enable Interrupt */ -#define REG_UMI_BCH_CTRL_STATUS_INT_EN 0x00000004 -/* Enable ECC during read */ -#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN 0x00000002 -/* Enable ECC during write */ -#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN 0x00000001 -/* Mask for location */ -#define REG_UMI_BCH_ERR_LOC_MASK 0x00001FFF -/* location within a byte */ -#define REG_UMI_BCH_ERR_LOC_BYTE 0x00000007 -/* location within a word */ -#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 -/* location within a page (512 byte) */ -#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 -#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) -#endif diff --git a/trunk/arch/arm/mach-davinci/board-da850-evm.c b/trunk/arch/arm/mach-davinci/board-da850-evm.c index 07de8db14581..62b98bffc158 100644 --- a/trunk/arch/arm/mach-davinci/board-da850-evm.c +++ b/trunk/arch/arm/mach-davinci/board-da850-evm.c @@ -339,15 +339,6 @@ static struct davinci_mmc_config da850_mmc_config = { .version = MMC_CTLR_VERSION_2, }; -static void da850_panel_power_ctrl(int val) -{ - /* lcd backlight */ - gpio_set_value(DA850_LCD_BL_PIN, val); - - /* lcd power */ - gpio_set_value(DA850_LCD_PWR_PIN, val); -} - static int da850_lcd_hw_init(void) { int status; @@ -365,11 +356,17 @@ static int da850_lcd_hw_init(void) gpio_direction_output(DA850_LCD_BL_PIN, 0); gpio_direction_output(DA850_LCD_PWR_PIN, 0); - /* Switch off panel power and backlight */ - da850_panel_power_ctrl(0); + /* disable lcd backlight */ + gpio_set_value(DA850_LCD_BL_PIN, 0); + + /* disable lcd power */ + gpio_set_value(DA850_LCD_PWR_PIN, 0); + + /* enable lcd power */ + gpio_set_value(DA850_LCD_PWR_PIN, 1); - /* Switch on panel power and backlight */ - da850_panel_power_ctrl(1); + /* enable lcd backlight */ + gpio_set_value(DA850_LCD_BL_PIN, 1); return 0; } @@ -677,7 +674,6 @@ static __init void da850_evm_init(void) pr_warning("da850_evm_init: lcd initialization failed: %d\n", ret); - sharp_lk043t1dg01_pdata.panel_power_ctrl = da850_panel_power_ctrl, ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata); if (ret) pr_warning("da850_evm_init: lcdc registration failed: %d\n", diff --git a/trunk/arch/arm/mach-davinci/include/mach/nand.h b/trunk/arch/arm/mach-davinci/include/mach/nand.h index b2ad8090bd10..b520c4b5678a 100644 --- a/trunk/arch/arm/mach-davinci/include/mach/nand.h +++ b/trunk/arch/arm/mach-davinci/include/mach/nand.h @@ -79,10 +79,6 @@ struct davinci_nand_pdata { /* platform_data */ /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ unsigned options; - - /* Main and mirror bbt descriptor overrides */ - struct nand_bbt_descr *bbt_td; - struct nand_bbt_descr *bbt_md; }; #endif /* __ARCH_ARM_DAVINCI_NAND_H */ diff --git a/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h b/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h index 62d17421e48c..83f31cd0a274 100644 --- a/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h +++ b/trunk/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h @@ -5,6 +5,9 @@ #ifndef __ASM_ARCH_EP93XX_KEYPAD_H #define __ASM_ARCH_EP93XX_KEYPAD_H +#define MAX_MATRIX_KEY_ROWS (8) +#define MAX_MATRIX_KEY_COLS (8) + /* flags for the ep93xx_keypad driver */ #define EP93XX_KEYPAD_DISABLE_3_KEY (1<<0) /* disable 3-key reset */ #define EP93XX_KEYPAD_DIAG_MODE (1<<1) /* diagnostic mode */ @@ -15,6 +18,8 @@ /** * struct ep93xx_keypad_platform_data - platform specific device structure + * @matrix_key_rows: number of rows in the keypad matrix + * @matrix_key_cols: number of columns in the keypad matrix * @matrix_key_map: array of keycodes defining the keypad matrix * @matrix_key_map_size: ARRAY_SIZE(matrix_key_map) * @debounce: debounce start count; terminal count is 0xff @@ -22,6 +27,8 @@ * @flags: see above */ struct ep93xx_keypad_platform_data { + unsigned int matrix_key_rows; + unsigned int matrix_key_cols; unsigned int *matrix_key_map; int matrix_key_map_size; unsigned int debounce; @@ -29,7 +36,7 @@ struct ep93xx_keypad_platform_data { unsigned int flags; }; -#define EP93XX_MATRIX_ROWS (8) -#define EP93XX_MATRIX_COLS (8) +/* macro for creating the matrix_key_map table */ +#define KEY(row, col, val) (((row) << 28) | ((col) << 24) | (val)) #endif /* __ASM_ARCH_EP93XX_KEYPAD_H */ diff --git a/trunk/arch/arm/mach-nomadik/board-nhk8815.c b/trunk/arch/arm/mach-nomadik/board-nhk8815.c index 9438bf6613a3..116394484e71 100644 --- a/trunk/arch/arm/mach-nomadik/board-nhk8815.c +++ b/trunk/arch/arm/mach-nomadik/board-nhk8815.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -150,7 +149,7 @@ static struct mtd_partition nhk8815_onenand_partitions[] = { } }; -static struct onenand_platform_data nhk8815_onenand_data = { +static struct flash_platform_data nhk8815_onenand_data = { .parts = nhk8815_onenand_partitions, .nr_parts = ARRAY_SIZE(nhk8815_onenand_partitions), }; @@ -164,7 +163,7 @@ static struct resource nhk8815_onenand_resource[] = { }; static struct platform_device nhk8815_onenand_device = { - .name = "onenand-flash", + .name = "onenand", .id = -1, .dev = { .platform_data = &nhk8815_onenand_data, @@ -175,10 +174,10 @@ static struct platform_device nhk8815_onenand_device = { static void __init nhk8815_onenand_init(void) { -#ifdef CONFIG_MTD_ONENAND +#ifdef CONFIG_ONENAND /* Set up SMCS0 for OneNand */ - writel(0x000030db, FSMC_BCR(0)); - writel(0x02100551, FSMC_BTR(0)); + writel(0x000030db, FSMC_BCR0); + writel(0x02100551, FSMC_BTR0); #endif } diff --git a/trunk/arch/arm/mach-u300/include/mach/coh901318.h b/trunk/arch/arm/mach-u300/include/mach/coh901318.h deleted file mode 100644 index f4cfee9c7d28..000000000000 --- a/trunk/arch/arm/mach-u300/include/mach/coh901318.h +++ /dev/null @@ -1,281 +0,0 @@ -/* - * - * include/linux/coh901318.h - * - * - * Copyright (C) 2007-2009 ST-Ericsson - * License terms: GNU General Public License (GPL) version 2 - * DMA driver for COH 901 318 - * Author: Per Friden - */ - -#ifndef COH901318_H -#define COH901318_H - -#include -#include - -#define MAX_DMA_PACKET_SIZE_SHIFT 11 -#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT) - -/** - * struct coh901318_lli - linked list item for DMAC - * @control: control settings for DMAC - * @src_addr: transfer source address - * @dst_addr: transfer destination address - * @link_addr: physical address to next lli - * @virt_link_addr: virtual addres of next lli (only used by pool_free) - * @phy_this: physical address of current lli (only used by pool_free) - */ -struct coh901318_lli { - u32 control; - dma_addr_t src_addr; - dma_addr_t dst_addr; - dma_addr_t link_addr; - - void *virt_link_addr; - dma_addr_t phy_this; -}; -/** - * struct coh901318_params - parameters for DMAC configuration - * @config: DMA config register - * @ctrl_lli_last: DMA control register for the last lli in the list - * @ctrl_lli: DMA control register for an lli - * @ctrl_lli_chained: DMA control register for a chained lli - */ -struct coh901318_params { - u32 config; - u32 ctrl_lli_last; - u32 ctrl_lli; - u32 ctrl_lli_chained; -}; -/** - * struct coh_dma_channel - dma channel base - * @name: ascii name of dma channel - * @number: channel id number - * @desc_nbr_max: number of preallocated descriptortors - * @priority_high: prio of channel, 0 low otherwise high. - * @param: configuration parameters - * @dev_addr: physical address of periphal connected to channel - */ -struct coh_dma_channel { - const char name[32]; - const int number; - const int desc_nbr_max; - const int priority_high; - const struct coh901318_params param; - const dma_addr_t dev_addr; -}; - -/** - * dma_access_memory_state_t - register dma for memory access - * - * @dev: The dma device - * @active: 1 means dma intends to access memory - * 0 means dma wont access memory - */ -typedef void (*dma_access_memory_state_t)(struct device *dev, - bool active); - -/** - * struct powersave - DMA power save structure - * @lock: lock protecting data in this struct - * @started_channels: bit mask indicating active dma channels - */ -struct powersave { - spinlock_t lock; - u64 started_channels; -}; -/** - * struct coh901318_platform - platform arch structure - * @chans_slave: specifying dma slave channels - * @chans_memcpy: specifying dma memcpy channels - * @access_memory_state: requesting DMA memeory access (on / off) - * @chan_conf: dma channel configurations - * @max_channels: max number of dma chanenls - */ -struct coh901318_platform { - const int *chans_slave; - const int *chans_memcpy; - const dma_access_memory_state_t access_memory_state; - const struct coh_dma_channel *chan_conf; - const int max_channels; -}; - -/** - * coh901318_get_bytes_left() - Get number of bytes left on a current transfer - * @chan: dma channel handle - * return number of bytes left, or negative on error - */ -u32 coh901318_get_bytes_left(struct dma_chan *chan); - -/** - * coh901318_stop() - Stops dma transfer - * @chan: dma channel handle - * return 0 on success otherwise negative value - */ -void coh901318_stop(struct dma_chan *chan); - -/** - * coh901318_continue() - Resumes a stopped dma transfer - * @chan: dma channel handle - * return 0 on success otherwise negative value - */ -void coh901318_continue(struct dma_chan *chan); - -/** - * coh901318_filter_id() - DMA channel filter function - * @chan: dma channel handle - * @chan_id: id of dma channel to be filter out - * - * In dma_request_channel() it specifies what channel id to be requested - */ -bool coh901318_filter_id(struct dma_chan *chan, void *chan_id); - -/* - * DMA Controller - this access the static mappings of the coh901318 dma. - * - */ - -#define COH901318_MOD32_MASK (0x1F) -#define COH901318_WORD_MASK (0xFFFFFFFF) -/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */ -#define COH901318_INT_STATUS1 (0x0000) -#define COH901318_INT_STATUS2 (0x0004) -/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */ -#define COH901318_TC_INT_STATUS1 (0x0008) -#define COH901318_TC_INT_STATUS2 (0x000C) -/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */ -#define COH901318_TC_INT_CLEAR1 (0x0010) -#define COH901318_TC_INT_CLEAR2 (0x0014) -/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ -#define COH901318_RAW_TC_INT_STATUS1 (0x0018) -#define COH901318_RAW_TC_INT_STATUS2 (0x001C) -/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */ -#define COH901318_BE_INT_STATUS1 (0x0020) -#define COH901318_BE_INT_STATUS2 (0x0024) -/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */ -#define COH901318_BE_INT_CLEAR1 (0x0028) -#define COH901318_BE_INT_CLEAR2 (0x002C) -/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */ -#define COH901318_RAW_BE_INT_STATUS1 (0x0030) -#define COH901318_RAW_BE_INT_STATUS2 (0x0034) - -/* - * CX_CFG - Channel Configuration Registers 32bit (R/W) - */ -#define COH901318_CX_CFG (0x0100) -#define COH901318_CX_CFG_SPACING (0x04) -/* Channel enable activates tha dma job */ -#define COH901318_CX_CFG_CH_ENABLE (0x00000001) -#define COH901318_CX_CFG_CH_DISABLE (0x00000000) -/* Request Mode */ -#define COH901318_CX_CFG_RM_MASK (0x00000006) -#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1) -#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1) -#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1) -#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1) -#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1) -/* Linked channel request field. RM must == 11 */ -#define COH901318_CX_CFG_LCRF_SHIFT 3 -#define COH901318_CX_CFG_LCRF_MASK (0x000001F8) -#define COH901318_CX_CFG_LCR_DISABLE (0x00000000) -/* Terminal Counter Interrupt Request Mask */ -#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200) -#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000) -/* Bus Error interrupt Mask */ -#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400) -#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000) - -/* - * CX_STAT - Channel Status Registers 32bit (R/-) - */ -#define COH901318_CX_STAT (0x0200) -#define COH901318_CX_STAT_SPACING (0x04) -#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008) -#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004) -#define COH901318_CX_STAT_ACTIVE (0x00000002) -#define COH901318_CX_STAT_ENABLED (0x00000001) - -/* - * CX_CTRL - Channel Control Registers 32bit (R/W) - */ -#define COH901318_CX_CTRL (0x0400) -#define COH901318_CX_CTRL_SPACING (0x10) -/* Transfer Count Enable */ -#define COH901318_CX_CTRL_TC_ENABLE (0x00001000) -#define COH901318_CX_CTRL_TC_DISABLE (0x00000000) -/* Transfer Count Value 0 - 4095 */ -#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF) -/* Burst count */ -#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000) -#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13) -#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13) -/* Source bus size */ -#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000) -#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16) -#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16) -#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16) -/* Source address increment */ -#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000) -#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000) -/* Destination Bus Size */ -#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000) -#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19) -#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19) -#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19) -/* Destination address increment */ -#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000) -#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000) -/* Master Mode (Master2 is only connected to MSL) */ -#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000) -#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22) -#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22) -#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22) -#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22) -/* Terminal Count flag to PER enable */ -#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000) -#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000) -/* Terminal Count flags to CPU enable */ -#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000) -#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000) -/* Hand shake to peripheral */ -#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000) -#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000) -#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000) -#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000) -/* DMA mode */ -#define COH901318_CX_CTRL_DDMA_MASK (0x30000000) -#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28) -#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28) -#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28) -/* Primary Request Data Destination */ -#define COH901318_CX_CTRL_PRDD_MASK (0x40000000) -#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30) -#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30) - -/* - * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W) - */ -#define COH901318_CX_SRC_ADDR (0x0404) -#define COH901318_CX_SRC_ADDR_SPACING (0x10) - -/* - * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W - */ -#define COH901318_CX_DST_ADDR (0x0408) -#define COH901318_CX_DST_ADDR_SPACING (0x10) - -/* - * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W) - */ -#define COH901318_CX_LNK_ADDR (0x040C) -#define COH901318_CX_LNK_ADDR_SPACING (0x10) -#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001) -#endif /* COH901318_H */ diff --git a/trunk/arch/arm/plat-mxc/include/mach/mxc_nand.h b/trunk/arch/arm/plat-mxc/include/mach/mxc_nand.h index 5d2d21d414e0..2b972df22d12 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mxc_nand.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mxc_nand.h @@ -22,7 +22,6 @@ struct mxc_nand_platform_data { int width; /* data bus width in bytes */ - int hw_ecc:1; /* 0 if supress hardware ECC */ - int flash_bbt:1; /* set to 1 to use a flash based bbt */ + int hw_ecc; /* 0 if supress hardware ECC */ }; #endif /* __ASM_ARCH_NAND_H */ diff --git a/trunk/arch/arm/plat-s3c/include/plat/nand.h b/trunk/arch/arm/plat-s3c/include/plat/nand.h index 226147b7e026..065985978413 100644 --- a/trunk/arch/arm/plat-s3c/include/plat/nand.h +++ b/trunk/arch/arm/plat-s3c/include/plat/nand.h @@ -17,7 +17,6 @@ * Setting this flag will allow the kernel to * look for it at boot time and also skip the NAND * scan. - * @options: Default value to set into 'struct nand_chip' options. * @nr_chips: Number of chips in this set * @nr_partitions: Number of partitions pointed to by @partitions * @name: Name of set (optional) @@ -32,7 +31,6 @@ struct s3c2410_nand_set { unsigned int disable_ecc:1; unsigned int flash_bbt:1; - unsigned int options; int nr_chips; int nr_partitions; char *name; diff --git a/trunk/arch/avr32/include/asm/elf.h b/trunk/arch/avr32/include/asm/elf.h index 3b3159b710d4..d5d1d41c600a 100644 --- a/trunk/arch/avr32/include/asm/elf.h +++ b/trunk/arch/avr32/include/asm/elf.h @@ -77,6 +77,7 @@ typedef struct user_fpu_struct elf_fpregset_t; #endif #define ELF_ARCH EM_AVR32 +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/blackfin/Kconfig b/trunk/arch/blackfin/Kconfig index 53c1e1d45c68..ae6a60f10120 100644 --- a/trunk/arch/blackfin/Kconfig +++ b/trunk/arch/blackfin/Kconfig @@ -5,10 +5,6 @@ mainmenu "Blackfin Kernel Configuration" -config SYMBOL_PREFIX - string - default "_" - config MMU def_bool n @@ -32,9 +28,6 @@ config BLACKFIN select HAVE_OPROFILE select ARCH_WANT_OPTIONAL_GPIOLIB -config GENERIC_CSUM - def_bool y - config GENERIC_BUG def_bool y depends on BUG @@ -180,7 +173,7 @@ config BF539 help BF539 Processor Support. -config BF542_std +config BF542 bool "BF542" help BF542 Processor Support. @@ -190,7 +183,7 @@ config BF542M help BF542 Processor Support. -config BF544_std +config BF544 bool "BF544" help BF544 Processor Support. @@ -200,7 +193,7 @@ config BF544M help BF544 Processor Support. -config BF547_std +config BF547 bool "BF547" help BF547 Processor Support. @@ -210,7 +203,7 @@ config BF547M help BF547 Processor Support. -config BF548_std +config BF548 bool "BF548" help BF548 Processor Support. @@ -220,7 +213,7 @@ config BF548M help BF548 Processor Support. -config BF549_std +config BF549 bool "BF549" help BF549 Processor Support. @@ -314,11 +307,31 @@ config BF_REV_NONE endchoice +config BF51x + bool + depends on (BF512 || BF514 || BF516 || BF518) + default y + +config BF52x + bool + depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) + default y + config BF53x bool depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) default y +config BF54xM + bool + depends on (BF542M || BF544M || BF547M || BF548M || BF549M) + default y + +config BF54x + bool + depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM) + default y + config MEM_GENERIC_BOARD bool depends on GENERIC_BOARD @@ -900,12 +913,6 @@ config DMA_UNCACHED_2M bool "Enable 2M DMA region" config DMA_UNCACHED_1M bool "Enable 1M DMA region" -config DMA_UNCACHED_512K - bool "Enable 512K DMA region" -config DMA_UNCACHED_256K - bool "Enable 256K DMA region" -config DMA_UNCACHED_128K - bool "Enable 128K DMA region" config DMA_UNCACHED_NONE bool "Disable DMA region" endchoice @@ -1267,8 +1274,6 @@ source "net/Kconfig" source "drivers/Kconfig" -source "drivers/firmware/Kconfig" - source "fs/Kconfig" source "arch/blackfin/Kconfig.debug" diff --git a/trunk/arch/blackfin/Makefile b/trunk/arch/blackfin/Makefile index d4c7177e7656..f063b772934b 100644 --- a/trunk/arch/blackfin/Makefile +++ b/trunk/arch/blackfin/Makefile @@ -16,7 +16,6 @@ GZFLAGS := -9 KBUILD_CFLAGS += $(call cc-option,-mno-fdpic) KBUILD_AFLAGS += $(call cc-option,-mno-fdpic) CFLAGS_MODULE += -mlong-calls -LDFLAGS_MODULE += -m elf32bfin KALLSYMS += --symbol-prefix=_ KBUILD_DEFCONFIG := BF537-STAMP_defconfig @@ -138,7 +137,7 @@ archclean: INSTALL_PATH ?= /tftpboot boot := arch/$(ARCH)/boot -BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma +BOOT_TARGETS = vmImage vmImage.bz2 vmImage.gz vmImage.lzma PHONY += $(BOOT_TARGETS) install KBUILD_IMAGE := $(boot)/vmImage @@ -152,7 +151,6 @@ install: define archhelp echo '* vmImage - Alias to selected kernel format (vmImage.gz by default)' - echo ' vmImage.bin - Uncompressed Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bin)' echo ' vmImage.bz2 - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.bz2)' echo '* vmImage.gz - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.gz)' echo ' vmImage.lzma - Kernel-only image for U-Boot (arch/$(ARCH)/boot/vmImage.lzma)' diff --git a/trunk/arch/blackfin/boot/Makefile b/trunk/arch/blackfin/boot/Makefile index e9c48c6f8c1f..fd9ccc5fea10 100644 --- a/trunk/arch/blackfin/boot/Makefile +++ b/trunk/arch/blackfin/boot/Makefile @@ -8,7 +8,7 @@ MKIMAGE := $(srctree)/scripts/mkuboot.sh -targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma +targets := vmImage vmImage.bz2 vmImage.gz vmImage.lzma extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma quiet_cmd_uimage = UIMAGE $@ @@ -29,9 +29,6 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE $(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE $(call if_changed,lzma) -$(obj)/vmImage.bin: $(obj)/vmlinux.bin - $(call if_changed,uimage,none) - $(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2 $(call if_changed,uimage,bzip2) @@ -41,7 +38,6 @@ $(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz $(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma $(call if_changed,uimage,lzma) -suffix-y := bin suffix-$(CONFIG_KERNEL_GZIP) := gz suffix-$(CONFIG_KERNEL_BZIP2) := bz2 suffix-$(CONFIG_KERNEL_LZMA) := lzma diff --git a/trunk/arch/blackfin/configs/BF518F-EZBRD_defconfig b/trunk/arch/blackfin/configs/BF518F-EZBRD_defconfig index e31559419817..9905b26009e5 100644 --- a/trunk/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/trunk/arch/blackfin/configs/BF518F-EZBRD_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -317,7 +316,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -440,7 +438,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set +CONFIG_NET_DSA=y +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_DSA_TAG_TRAILER is not set +CONFIG_NET_DSA_TAG_STPID=y +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_NET_DSA_KSZ8893M=y # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set diff --git a/trunk/arch/blackfin/configs/BF526-EZBRD_defconfig b/trunk/arch/blackfin/configs/BF526-EZBRD_defconfig index 075e0fdcb399..9dc682088023 100644 --- a/trunk/arch/blackfin/configs/BF526-EZBRD_defconfig +++ b/trunk/arch/blackfin/configs/BF526-EZBRD_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -322,7 +321,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF527-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF527-EZKIT_defconfig index 6d1a623fb149..77e35d4baf53 100644 --- a/trunk/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF527-EZKIT_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -322,7 +321,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF533-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF533-EZKIT_defconfig index 50f9a23ccdbd..4c044805cb5c 100644 --- a/trunk/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF533-EZKIT_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -284,7 +283,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF533-STAMP_defconfig b/trunk/arch/blackfin/configs/BF533-STAMP_defconfig index 6c60c8286318..c99bbcd09a68 100644 --- a/trunk/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/trunk/arch/blackfin/configs/BF533-STAMP_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -284,7 +283,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF537-STAMP_defconfig b/trunk/arch/blackfin/configs/BF537-STAMP_defconfig index 2908595b67c5..092ffda80e68 100644 --- a/trunk/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/trunk/arch/blackfin/configs/BF537-STAMP_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -291,7 +290,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -706,7 +704,10 @@ CONFIG_CONFIG_INPUT_PCF8574=m # # Hardware I/O ports # -# CONFIG_SERIO is not set +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set # CONFIG_GAMEPORT is not set # diff --git a/trunk/arch/blackfin/configs/BF538-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF538-EZKIT_defconfig index 09ea2499555e..fa698a89f6fe 100644 --- a/trunk/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF538-EZKIT_defconfig @@ -67,7 +67,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -302,7 +301,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/BF548-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF548-EZKIT_defconfig index eb3e98b6f3f0..f773ad1155d4 100644 --- a/trunk/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF548-EZKIT_defconfig @@ -1,29 +1,22 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.31.5 -# Mon Nov 2 22:02:56 2009 +# Linux kernel version: 2.6.28.10 +# Thu May 21 05:50:01 2009 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y # # General setup @@ -33,40 +26,22 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -87,28 +62,17 @@ CONFIG_EPOLL=y # CONFIG_TIMERFD is not set # CONFIG_EVENTFD is not set # CONFIG_AIO is not set - -# -# Performance Counters -# CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -116,8 +80,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y -# CONFIG_LBDAF is not set +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -127,12 +94,13 @@ CONFIG_BLOCK=y CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y # CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -169,7 +137,7 @@ CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_BF544M is not set # CONFIG_BF547 is not set # CONFIG_BF547M is not set -CONFIG_BF548_std=y +CONFIG_BF548=y # CONFIG_BF548M is not set # CONFIG_BF549 is not set # CONFIG_BF549M is not set @@ -227,7 +195,7 @@ CONFIG_BFIN548_EZKIT=y # # BF548 Specific Configuration # -CONFIG_DEB_DMA_URGENT=y +# CONFIG_DEB_DMA_URGENT is not set # CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set # @@ -384,11 +352,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set CONFIG_DMA_UNCACHED_2M=y @@ -399,13 +366,14 @@ CONFIG_DMA_UNCACHED_2M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y -# CONFIG_BFIN_EXTMEM_WRITEBACK is not set -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set # CONFIG_BFIN_L2_DCACHEABLE is not set # @@ -414,7 +382,7 @@ CONFIG_BFIN_EXTMEM_WRITETHROUGH=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -473,6 +441,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -496,11 +469,13 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -518,10 +493,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -576,10 +548,14 @@ CONFIG_SIR_BFIN_DMA=y # CONFIG_MCS_FIR is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y -CONFIG_LIB80211=m -# CONFIG_WIMAX is not set +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -602,7 +578,6 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set @@ -678,6 +653,7 @@ CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_BFIN is not set CONFIG_MTD_NAND_IDS=y CONFIG_MTD_NAND_BF5XX=y CONFIG_MTD_NAND_BF5XX_HWECC=y @@ -688,11 +664,6 @@ CONFIG_MTD_NAND_BF5XX_HWECC=y # CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -711,20 +682,10 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_ISL29003 is not set -# CONFIG_AD525X_DPOT is not set # CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -748,6 +709,10 @@ CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set @@ -764,7 +729,6 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_SATA_PMP=y @@ -780,34 +744,13 @@ CONFIG_NETDEVICES=y # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set +# CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_SMC91X is not set +CONFIG_SMSC911X=y # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -816,8 +759,6 @@ CONFIG_SMSC911X=y # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -830,15 +771,12 @@ CONFIG_LIBERTAS=m # CONFIG_LIBERTAS_USB is not set CONFIG_LIBERTAS_SDIO=m CONFIG_POWEROF2_BLOCKSIZE_ONLY=y -# CONFIG_LIBERTAS_SPI is not set # CONFIG_LIBERTAS_DEBUG is not set # CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_HOSTAP is not set -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - # # USB Network Adapters # @@ -875,31 +813,28 @@ CONFIG_INPUT_EVBUG=m # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_BFIN=y +# CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_KEYBOARD_BFIN=y +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set CONFIG_TOUCHSCREEN_AD7877=m # CONFIG_TOUCHSCREEN_AD7879_I2C is not set # CONFIG_TOUCHSCREEN_AD7879_SPI is not set # CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set @@ -909,8 +844,6 @@ CONFIG_TOUCHSCREEN_AD7877=m # CONFIG_TOUCHSCREEN_WM97XX is not set # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_W90X900 is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_ATI_REMOTE is not set # CONFIG_INPUT_ATI_REMOTE2 is not set @@ -919,11 +852,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_INPUT_BFIN_ROTARY is not set -# CONFIG_INPUT_AD714X is not set -# CONFIG_INPUT_ADXL34X is not set -# CONFIG_INPUT_PCF8574 is not set +# CONFIG_CONFIG_INPUT_PCF8574 is not set # # Hardware I/O ports @@ -934,13 +863,16 @@ CONFIG_INPUT_MISC=y # # Character devices # +# CONFIG_AD9960 is not set CONFIG_BFIN_DMA_INTERFACE=m # CONFIG_BFIN_PPI is not set # CONFIG_BFIN_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set # CONFIG_BFIN_SPI_ADC is not set CONFIG_BFIN_SPORT=m +# CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_BFIN_TWI_LCD is not set +CONFIG_SIMPLE_GPIO=m CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y @@ -958,7 +890,6 @@ CONFIG_BFIN_JTAG_COMM=m # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -972,7 +903,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_OTP=y # CONFIG_BFIN_OTP_WRITE_ENABLE is not set @@ -1021,9 +951,14 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_EEPROM_AT24 is not set +# CONFIG_SENSORS_AD5252 is not set +# CONFIG_EEPROM_LEGACY is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1040,18 +975,13 @@ CONFIG_SPI_BFIN=y # CONFIG_SPI_BFIN_LOCK is not set # CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -1067,7 +997,6 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -1109,19 +1038,28 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set -# CONFIG_UCB1400_CORE is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_PMIC_DA903X is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set # CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set # # Graphics support @@ -1158,7 +1096,6 @@ CONFIG_FB_BF54X_LQ043=y # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set -# CONFIG_FB_BROADSHEET is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -1195,7 +1132,6 @@ CONFIG_SOUND_OSS_CORE=y CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y -CONFIG_SND_JACK=y # CONFIG_SND_SEQUENCER is not set CONFIG_SND_OSSEMUL=y CONFIG_SND_MIXER_OSS=y @@ -1206,11 +1142,6 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set # CONFIG_SND_MTPAV is not set @@ -1221,6 +1152,7 @@ CONFIG_SND_SPI=y # # ALSA Blackfin devices # +# CONFIG_SND_BLACKFIN_AD1836 is not set # CONFIG_SND_BFIN_AD73322 is not set CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set @@ -1228,17 +1160,15 @@ CONFIG_SND_USB=y CONFIG_SND_SOC=y CONFIG_SND_SOC_AC97_BUS=y # CONFIG_SND_BF5XX_I2S is not set -# CONFIG_SND_BF5XX_TDM is not set CONFIG_SND_BF5XX_AC97=y CONFIG_SND_BF5XX_MMAP_SUPPORT=y # CONFIG_SND_BF5XX_MULTICHAN_SUPPORT is not set -CONFIG_SND_BF5XX_HAVE_COLD_RESET=y -CONFIG_SND_BF5XX_RESET_GPIO_NUM=19 -CONFIG_SND_BF5XX_SOC_AD1980=y CONFIG_SND_BF5XX_SOC_SPORT=y CONFIG_SND_BF5XX_SOC_AC97=y +CONFIG_SND_BF5XX_SOC_AD1980=y CONFIG_SND_BF5XX_SPORT_NUM=0 -CONFIG_SND_SOC_I2C_AND_SPI=y +CONFIG_SND_BF5XX_HAVE_COLD_RESET=y +CONFIG_SND_BF5XX_RESET_GPIO_NUM=19 # CONFIG_SND_SOC_ALL_CODECS is not set CONFIG_SND_SOC_AD1980=y # CONFIG_SOUND_PRIME is not set @@ -1258,34 +1188,30 @@ CONFIG_USB_HID=y # # Special HID drivers # +CONFIG_HID_COMPAT=y CONFIG_HID_A4TECH=y CONFIG_HID_APPLE=y CONFIG_HID_BELKIN=y +CONFIG_HID_BRIGHT=y CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set +CONFIG_HID_DELL=y CONFIG_HID_EZKEY=y -# CONFIG_HID_KYE is not set CONFIG_HID_GYRATION=y -# CONFIG_HID_KENSINGTON is not set CONFIG_HID_LOGITECH=y # CONFIG_LOGITECH_FF is not set # CONFIG_LOGIRUMBLEPAD2_FF is not set CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y -# CONFIG_HID_NTRIG is not set CONFIG_HID_PANTHERLORD=y # CONFIG_PANTHERLORD_FF is not set CONFIG_HID_PETALYNX=y CONFIG_HID_SAMSUNG=y CONFIG_HID_SONY=y CONFIG_HID_SUNPLUS=y -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set +CONFIG_THRUSTMASTER_FF=m +CONFIG_ZEROPLUS_FF=m CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set @@ -1311,7 +1237,6 @@ CONFIG_USB_MON=y # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set @@ -1342,17 +1267,18 @@ CONFIG_USB_INVENTRA_DMA=y # CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # -# also be needed; see USB_STORAGE Help for more info +# see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set @@ -1388,6 +1314,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set @@ -1399,13 +1326,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -CONFIG_NOP_USB_XCEIV=y CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set @@ -1460,7 +1380,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set # # SPI RTC drivers @@ -1492,20 +1411,9 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_BFIN=y # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set -# -# Firmware Drivers -# -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_SIGMA is not set - # # File systems # @@ -1519,11 +1427,9 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1532,11 +1438,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -1566,7 +1467,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1585,8 +1489,17 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +CONFIG_YAFFS_FS=m +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -1595,7 +1508,6 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y @@ -1610,6 +1522,7 @@ CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1683,15 +1596,11 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set @@ -1699,21 +1608,16 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_NOMMU_REGIONS is not set # CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_FRAME_POINTER is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set @@ -1721,16 +1625,17 @@ CONFIG_DEBUG_INFO=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set + +# +# Tracers +# +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_VERBOSE=y @@ -1752,15 +1657,17 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set -# CONFIG_SECURITY is not set +CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_SECURITY_ROOTPLUG is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 CONFIG_CRYPTO=y # @@ -1839,7 +1746,6 @@ CONFIG_CRYPTO=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -1847,13 +1753,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1863,8 +1767,6 @@ CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m -CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/BF561-ACVILON_defconfig b/trunk/arch/blackfin/configs/BF561-ACVILON_defconfig deleted file mode 100644 index b9b0f93d0bd3..000000000000 --- a/trunk/arch/blackfin/configs/BF561-ACVILON_defconfig +++ /dev/null @@ -1,1643 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.31.4 -# Sat Oct 24 12:15:32 2009 -# -# CONFIG_MMU is not set -# CONFIG_FPU is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set -CONFIG_BLACKFIN=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_BUG=y -CONFIG_ZONE_DMA=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_GENERIC_GPIO=y -CONFIG_FORCE_MAX_ZONEORDER=14 -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_EMBEDDED=y -CONFIG_UID16=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -# CONFIG_ELF_CORE is not set -CONFIG_BASE_FULL=y -# CONFIG_FUTEX is not set -CONFIG_EPOLL=y -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set - -# -# Performance Counters -# -CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_COMPAT_BRK=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_BLOCK=y -CONFIG_LBDAF=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -# CONFIG_IOSCHED_DEADLINE is not set -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y -# CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set - -# -# Blackfin Processor Options -# - -# -# Processor and Board Settings -# -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set -# CONFIG_BF522 is not set -# CONFIG_BF523 is not set -# CONFIG_BF524 is not set -# CONFIG_BF525 is not set -# CONFIG_BF526 is not set -# CONFIG_BF527 is not set -# CONFIG_BF531 is not set -# CONFIG_BF532 is not set -# CONFIG_BF533 is not set -# CONFIG_BF534 is not set -# CONFIG_BF536 is not set -# CONFIG_BF537 is not set -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set -# CONFIG_BF542 is not set -# CONFIG_BF542M is not set -# CONFIG_BF544 is not set -# CONFIG_BF544M is not set -# CONFIG_BF547 is not set -# CONFIG_BF547M is not set -# CONFIG_BF548 is not set -# CONFIG_BF548M is not set -# CONFIG_BF549 is not set -# CONFIG_BF549M is not set -CONFIG_BF561=y -# CONFIG_SMP is not set -CONFIG_BF_REV_MIN=3 -CONFIG_BF_REV_MAX=5 -# CONFIG_BF_REV_0_0 is not set -# CONFIG_BF_REV_0_1 is not set -# CONFIG_BF_REV_0_2 is not set -# CONFIG_BF_REV_0_3 is not set -# CONFIG_BF_REV_0_4 is not set -CONFIG_BF_REV_0_5=y -# CONFIG_BF_REV_0_6 is not set -# CONFIG_BF_REV_ANY is not set -# CONFIG_BF_REV_NONE is not set -CONFIG_IRQ_PLL_WAKEUP=7 -CONFIG_IRQ_SPORT0_ERROR=7 -CONFIG_IRQ_SPORT1_ERROR=7 -CONFIG_IRQ_TIMER0=10 -CONFIG_IRQ_TIMER1=10 -CONFIG_IRQ_TIMER2=10 -CONFIG_IRQ_TIMER3=10 -CONFIG_IRQ_TIMER4=10 -CONFIG_IRQ_TIMER5=10 -CONFIG_IRQ_TIMER6=10 -CONFIG_IRQ_TIMER7=10 -CONFIG_IRQ_SPI_ERROR=7 -# CONFIG_BFIN561_EZKIT is not set -# CONFIG_BFIN561_TEPLA is not set -# CONFIG_BFIN561_BLUETECHNIX_CM is not set -CONFIG_BFIN561_ACVILON=y - -# -# BF561 Specific Configuration -# - -# -# Core B Support -# -# CONFIG_BF561_COREB is not set - -# -# Interrupt Priority Assignment -# - -# -# Priority -# -CONFIG_IRQ_DMA1_ERROR=7 -CONFIG_IRQ_DMA2_ERROR=7 -CONFIG_IRQ_IMDMA_ERROR=7 -CONFIG_IRQ_PPI0_ERROR=7 -CONFIG_IRQ_PPI1_ERROR=7 -CONFIG_IRQ_UART_ERROR=7 -CONFIG_IRQ_RESERVED_ERROR=7 -CONFIG_IRQ_DMA1_0=8 -CONFIG_IRQ_DMA1_1=8 -CONFIG_IRQ_DMA1_2=8 -CONFIG_IRQ_DMA1_3=8 -CONFIG_IRQ_DMA1_4=8 -CONFIG_IRQ_DMA1_5=8 -CONFIG_IRQ_DMA1_6=8 -CONFIG_IRQ_DMA1_7=8 -CONFIG_IRQ_DMA1_8=8 -CONFIG_IRQ_DMA1_9=8 -CONFIG_IRQ_DMA1_10=8 -CONFIG_IRQ_DMA1_11=8 -CONFIG_IRQ_DMA2_0=9 -CONFIG_IRQ_DMA2_1=9 -CONFIG_IRQ_DMA2_2=9 -CONFIG_IRQ_DMA2_3=9 -CONFIG_IRQ_DMA2_4=9 -CONFIG_IRQ_DMA2_5=9 -CONFIG_IRQ_DMA2_6=9 -CONFIG_IRQ_DMA2_7=9 -CONFIG_IRQ_DMA2_8=9 -CONFIG_IRQ_DMA2_9=9 -CONFIG_IRQ_DMA2_10=9 -CONFIG_IRQ_DMA2_11=9 -CONFIG_IRQ_TIMER8=10 -CONFIG_IRQ_TIMER9=10 -CONFIG_IRQ_TIMER10=10 -CONFIG_IRQ_TIMER11=10 -CONFIG_IRQ_PROG0_INTA=11 -CONFIG_IRQ_PROG0_INTB=11 -CONFIG_IRQ_PROG1_INTA=11 -CONFIG_IRQ_PROG1_INTB=11 -CONFIG_IRQ_PROG2_INTA=11 -CONFIG_IRQ_PROG2_INTB=11 -CONFIG_IRQ_DMA1_WRRD0=8 -CONFIG_IRQ_DMA1_WRRD1=8 -CONFIG_IRQ_DMA2_WRRD0=9 -CONFIG_IRQ_DMA2_WRRD1=9 -CONFIG_IRQ_IMDMA_WRRD0=12 -CONFIG_IRQ_IMDMA_WRRD1=12 -CONFIG_IRQ_WDTIMER=13 - -# -# Board customizations -# -# CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 - -# -# Clock/PLL Setup -# -CONFIG_CLKIN_HZ=12000000 -# CONFIG_BFIN_KERNEL_CLOCK is not set -CONFIG_MAX_VCO_HZ=600000000 -CONFIG_MIN_VCO_HZ=50000000 -CONFIG_MAX_SCLK_HZ=133333333 -CONFIG_MIN_SCLK_HZ=27000000 - -# -# Kernel Timer/Scheduler -# -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_SCHED_HRTICK=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y -CONFIG_CYCLES_CLOCKSOURCE=y -# CONFIG_GPTMR0_CLOCKSOURCE is not set -CONFIG_TICK_ONESHOT=y -# CONFIG_NO_HZ is not set -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y - -# -# Misc -# -CONFIG_BFIN_SCRATCH_REG_RETN=y -# CONFIG_BFIN_SCRATCH_REG_RETE is not set -# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set - -# -# Blackfin Kernel Optimizations -# - -# -# Memory Optimizations -# -CONFIG_I_ENTRY_L1=y -CONFIG_EXCPT_IRQ_SYSC_L1=y -CONFIG_DO_IRQ_L1=y -CONFIG_CORE_TIMER_IRQ_L1=y -CONFIG_IDLE_L1=y -CONFIG_SCHEDULE_L1=y -CONFIG_ARITHMETIC_OPS_L1=y -CONFIG_ACCESS_OK_L1=y -CONFIG_MEMSET_L1=y -CONFIG_MEMCPY_L1=y -CONFIG_SYS_BFIN_SPINLOCK_L1=y -# CONFIG_IP_CHECKSUM_L1 is not set -CONFIG_CACHELINE_ALIGNED_L1=y -# CONFIG_SYSCALL_TAB_L1 is not set -# CONFIG_CPLB_SWITCH_TAB_L1 is not set -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y -CONFIG_RAMKERNEL=y -# CONFIG_ROMKERNEL is not set -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 -CONFIG_VIRT_TO_BUS=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 -CONFIG_BFIN_GPTIMERS=y -CONFIG_DMA_UNCACHED_4M=y -# CONFIG_DMA_UNCACHED_2M is not set -# CONFIG_DMA_UNCACHED_1M is not set -# CONFIG_DMA_UNCACHED_NONE is not set - -# -# Cache Support -# -CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set -CONFIG_BFIN_DCACHE=y -# CONFIG_BFIN_DCACHE_BANKA is not set -CONFIG_BFIN_EXTMEM_DCACHEABLE=y -CONFIG_BFIN_EXTMEM_WRITEBACK=y -# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set -# CONFIG_BFIN_L2_DCACHEABLE is not set - -# -# Memory Protection Unit -# -# CONFIG_MPU is not set - -# -# Asynchronous Memory Configuration -# - -# -# EBIU_AMGCTL Global Control -# -CONFIG_C_AMCKEN=y -CONFIG_C_CDPRIO=y -CONFIG_C_B0PEN=y -CONFIG_C_B1PEN=y -CONFIG_C_B2PEN=y -# CONFIG_C_B3PEN is not set -# CONFIG_C_AMBEN is not set -# CONFIG_C_AMBEN_B0 is not set -# CONFIG_C_AMBEN_B0_B1 is not set -# CONFIG_C_AMBEN_B0_B1_B2 is not set -CONFIG_C_AMBEN_ALL=y - -# -# EBIU_AMBCTL Control -# -CONFIG_BANK_0=0x99b2 -CONFIG_BANK_1=0x3350 -CONFIG_BANK_2=0x7BB0 -CONFIG_BANK_3=0xAAC2 - -# -# Bus options (PCI, PCMCIA, EISA, MCA, ISA) -# -# CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF_FDPIC=y -CONFIG_BINFMT_FLAT=y -CONFIG_BINFMT_ZFLAT=y -# CONFIG_BINFMT_SHARED_FLAT is not set -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set - -# -# Power management options -# -# CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y - -# -# CPU Frequency scaling -# -# CONFIG_CPU_FREQ is not set -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -CONFIG_SYN_COOKIES=y -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETLABEL is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLKDEVS=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_RAM=y -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_UCLINUX is not set -CONFIG_MTD_PLATRAM=y - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set -# CONFIG_MTD_SLRAM is not set -CONFIG_MTD_PHRAM=y -# CONFIG_MTD_MTDRAM is not set -CONFIG_MTD_BLOCK2MTD=y - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -CONFIG_MTD_NAND=y -CONFIG_MTD_NAND_VERIFY_WRITE=y -# CONFIG_MTD_NAND_ECC_SMC is not set -# CONFIG_MTD_NAND_MUSEUM_IDS is not set -CONFIG_MTD_NAND_IDS=y -# CONFIG_MTD_NAND_DISKONCHIP is not set -# CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_PLATFORM=y -# CONFIG_MTD_ALAUDA is not set -# CONFIG_MTD_ONENAND is not set - -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=2 -CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_BLK_DEV_XIP is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_PROC_FS is not set - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=y - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -# CONFIG_BFIN_DMA_INTERFACE is not set -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set -CONFIG_BFIN_SIMPLE_TIMER=y -# CONFIG_BFIN_SPI_ADC is not set -# CONFIG_BFIN_SPORT is not set -# CONFIG_BFIN_TWI_LCD is not set -# CONFIG_VT is not set -# CONFIG_DEVKMEM is not set -# CONFIG_BFIN_JTAG_COMM is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_MAX3100 is not set -CONFIG_SERIAL_BFIN=y -CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_SERIAL_BFIN_DMA is not set -CONFIG_SERIAL_BFIN_PIO=y -CONFIG_SERIAL_BFIN_UART0=y -# CONFIG_BFIN_UART0_CTSRTS is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_BFIN_SPORT is not set -CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# CAN, the car bus and industrial fieldbus -# -# CONFIG_CAN4LINUX is not set -# CONFIG_IPMI_HANDLER is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_R3964 is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_ALGOPCA=y - -# -# I2C Hardware Bus support -# - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -CONFIG_I2C_PCA_PLATFORM=y -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -CONFIG_GPIOLIB=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -CONFIG_GPIO_PCF857X=y -# CONFIG_GPIO_ADP5588 is not set - -# -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -CONFIG_SENSORS_LM75=y -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_NOWAYOUT is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -CONFIG_BFIN_WDT=y - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_AB3100_CORE is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -# CONFIG_SND_SEQUENCER is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -# CONFIG_SND_DRIVERS is not set -CONFIG_SND_SPI=y - -# -# ALSA Blackfin devices -# -# CONFIG_SND_BFIN_AD73322 is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=y -CONFIG_SND_BF5XX_I2S=y -# CONFIG_SND_BF5XX_SOC_SSM2602 is not set -# CONFIG_SND_BF5XX_SOC_AD73311 is not set -# CONFIG_SND_BF5XX_SOC_ADAU1371 is not set -# CONFIG_SND_BF5XX_SOC_ADAU1761 is not set -# CONFIG_SND_BF5XX_TDM is not set -# CONFIG_SND_BF5XX_AC97 is not set -CONFIG_SND_BF5XX_SOC_SPORT=y -CONFIG_SND_BF5XX_SPORT_NUM=1 -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -# CONFIG_USB_DEVICEFS is not set -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=y -# CONFIG_USB_SERIAL_CONSOLE is not set -# CONFIG_USB_EZUSB is not set -# CONFIG_USB_SERIAL_GENERIC is not set -# CONFIG_USB_SERIAL_AIRCABLE is not set -# CONFIG_USB_SERIAL_ARK3116 is not set -# CONFIG_USB_SERIAL_BELKIN is not set -# CONFIG_USB_SERIAL_CH341 is not set -# CONFIG_USB_SERIAL_WHITEHEAT is not set -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -# CONFIG_USB_SERIAL_CP210X is not set -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -# CONFIG_USB_SERIAL_EMPEG is not set -CONFIG_USB_SERIAL_FTDI_SIO=y -# CONFIG_USB_SERIAL_FUNSOFT is not set -# CONFIG_USB_SERIAL_VISOR is not set -# CONFIG_USB_SERIAL_IPAQ is not set -# CONFIG_USB_SERIAL_IR is not set -# CONFIG_USB_SERIAL_EDGEPORT is not set -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -# CONFIG_USB_SERIAL_GARMIN is not set -# CONFIG_USB_SERIAL_IPW is not set -# CONFIG_USB_SERIAL_IUU is not set -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -# CONFIG_USB_SERIAL_KEYSPAN is not set -# CONFIG_USB_SERIAL_KLSI is not set -# CONFIG_USB_SERIAL_KOBIL_SCT is not set -# CONFIG_USB_SERIAL_MCT_U232 is not set -# CONFIG_USB_SERIAL_MOS7720 is not set -# CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set -# CONFIG_USB_SERIAL_NAVMAN is not set -CONFIG_USB_SERIAL_PL2303=y -# CONFIG_USB_SERIAL_OTI6858 is not set -# CONFIG_USB_SERIAL_QUALCOMM is not set -# CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set -# CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -# CONFIG_USB_SERIAL_SYMBOL is not set -# CONFIG_USB_SERIAL_TI is not set -# CONFIG_USB_SERIAL_CYBERJACK is not set -# CONFIG_USB_SERIAL_XIRCOM is not set -# CONFIG_USB_SERIAL_OPTION is not set -# CONFIG_USB_SERIAL_OMNINET is not set -# CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_DEBUG is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -# CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -CONFIG_RTC_DRV_DS1307=y -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set - -# -# TI VLYNQ -# -# CONFIG_STAGING is not set - -# -# Firmware Drivers -# -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_SIGMA is not set - -# -# File systems -# -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -# CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y -# CONFIG_DNOTIFY is not set -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set -# CONFIG_FUSE_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=866 -CONFIG_FAT_DEFAULT_IOCHARSET="cp1251" -CONFIG_NTFS_FS=y -# CONFIG_NTFS_DEBUG is not set -# CONFIG_NTFS_RW is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_SYSFS=y -# CONFIG_TMPFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_CONFIGFS_FS=y -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -# CONFIG_JFFS2_ZLIB is not set -CONFIG_JFFS2_LZO=y -# CONFIG_JFFS2_RTIME is not set -# CONFIG_JFFS2_RUBIN is not set -# CONFIG_JFFS2_CMODE_NONE is not set -# CONFIG_JFFS2_CMODE_PRIORITY is not set -# CONFIG_JFFS2_CMODE_SIZE is not set -CONFIG_JFFS2_CMODE_FAVOURLZO=y -CONFIG_CRAMFS=y -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -CONFIG_MINIX_FS=y -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -CONFIG_ROOT_NFS=y -# CONFIG_NFSD is not set -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="cp1251" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -CONFIG_NLS_CODEPAGE_866=y -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -CONFIG_NLS_CODEPAGE_1251=y -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -CONFIG_NLS_KOI8_R=y -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_SHIRQ=y -CONFIG_DETECT_SOFTLOCKUP=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -CONFIG_SCHED_DEBUG=y -# CONFIG_SCHEDSTATS is not set -# CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_DEBUG_SLAB is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_NOMMU_REGIONS is not set -# CONFIG_DEBUG_WRITECOUNT is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_FRAME_POINTER is not set -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_BOOT_TRACER is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set -# CONFIG_DEBUG_STACKOVERFLOW is not set -# CONFIG_DEBUG_STACK_USAGE is not set -CONFIG_DEBUG_VERBOSE=y -CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_HWERR is not set -# CONFIG_DEBUG_DOUBLEFAULT is not set -CONFIG_DEBUG_HUNT_FOR_ZERO=y -CONFIG_DEBUG_BFIN_HWTRACE_ON=y -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y -# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set -# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set -CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 -# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set -# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -# CONFIG_EARLY_PRINTK is not set -CONFIG_CPLB_INFO=y -CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set - -# -# Security options -# -# CONFIG_KEYS is not set -CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_ROOTPLUG is not set -# CONFIG_SECURITY_TOMOYO is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -# CONFIG_CRC_CCITT is not set -# CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC7 is not set -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/BF561-EZKIT_defconfig b/trunk/arch/blackfin/configs/BF561-EZKIT_defconfig index e3ecdcc3e76b..0313cd1d9824 100644 --- a/trunk/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/trunk/arch/blackfin/configs/BF561-EZKIT_defconfig @@ -1,29 +1,22 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.31.5 -# Mon Nov 2 21:59:31 2009 +# Linux kernel version: 2.6.28.10 +# Thu May 21 05:50:01 2009 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_CONSTRUCTORS=y # # General setup @@ -33,40 +26,22 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -87,28 +62,17 @@ CONFIG_EPOLL=y # CONFIG_TIMERFD is not set # CONFIG_EVENTFD is not set # CONFIG_AIO is not set - -# -# Performance Counters -# CONFIG_VM_EVENT_COUNTERS=y -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -116,8 +80,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y -# CONFIG_LBDAF is not set +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -127,12 +94,13 @@ CONFIG_BLOCK=y CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y # CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -202,7 +170,6 @@ CONFIG_IRQ_SPI_ERROR=7 CONFIG_BFIN561_EZKIT=y # CONFIG_BFIN561_TEPLA is not set # CONFIG_BFIN561_BLUETECHNIX_CM is not set -# CONFIG_BFIN561_ACVILON is not set # # BF561 Specific Configuration @@ -350,11 +317,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=m # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -365,13 +331,14 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set # CONFIG_BFIN_L2_DCACHEABLE is not set # @@ -380,7 +347,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -440,6 +407,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -463,11 +435,13 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -485,10 +459,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -532,8 +503,13 @@ CONFIG_IRTTY_SIR=m # # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -554,7 +530,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set @@ -627,11 +602,6 @@ CONFIG_MTD_PHYSMAP=m # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -649,14 +619,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -680,11 +645,9 @@ CONFIG_NETDEVICES=y CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_SMC91X=y +# CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -693,8 +656,6 @@ CONFIG_SMC91X=y # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -703,10 +664,7 @@ CONFIG_SMC91X=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -750,12 +708,15 @@ CONFIG_INPUT_EVDEV=m # # Character devices # +# CONFIG_AD9960 is not set CONFIG_BFIN_DMA_INTERFACE=m # CONFIG_BFIN_PPI is not set # CONFIG_BFIN_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set # CONFIG_BFIN_SPI_ADC is not set # CONFIG_BFIN_SPORT is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +CONFIG_SIMPLE_GPIO=m # CONFIG_VT is not set # CONFIG_DEVKMEM is not set CONFIG_BFIN_JTAG_COMM=m @@ -769,7 +730,6 @@ CONFIG_BFIN_JTAG_COMM=m # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -780,7 +740,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # @@ -804,18 +763,13 @@ CONFIG_SPI_BFIN=y # CONFIG_SPI_BFIN_LOCK is not set # CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set - -# -# PPS support -# -# CONFIG_PPS is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -828,6 +782,9 @@ CONFIG_GPIO_SYSFS=y # # I2C GPIO expanders: # +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set # # PCI GPIO expanders: @@ -865,9 +822,23 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set -# CONFIG_EZX_PCAP is not set # CONFIG_REGULATOR is not set -# CONFIG_MEDIA_SUPPORT is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set # # Graphics support @@ -891,6 +862,7 @@ CONFIG_HID=m # # Special HID drivers # +CONFIG_HID_COMPAT=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -898,19 +870,9 @@ CONFIG_HID=m # CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set - -# -# TI VLYNQ -# # CONFIG_STAGING is not set -# -# Firmware Drivers -# -# CONFIG_FIRMWARE_MEMMAP is not set - # # File systems # @@ -920,11 +882,9 @@ CONFIG_HID=m # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -CONFIG_FSNOTIFY=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -933,11 +893,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -960,7 +915,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -979,8 +937,17 @@ CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set +CONFIG_YAFFS_FS=m +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_9BYTE_TAGS is not set +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -989,7 +956,6 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y @@ -1000,6 +966,7 @@ CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1067,15 +1034,11 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_SHIRQ=y CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set @@ -1083,21 +1046,16 @@ CONFIG_SCHED_DEBUG=y # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_NOMMU_REGIONS is not set # CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_FRAME_POINTER is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set @@ -1105,19 +1063,17 @@ CONFIG_DEBUG_INFO=y # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_FAULT_INJECTION is not set -# CONFIG_PAGE_POISONING is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y -# CONFIG_FTRACE is not set -# CONFIG_BRANCH_PROFILE_NONE is not set -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_DYNAMIC_DEBUG is not set + +# +# Tracers +# +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -# CONFIG_KMEMCHECK is not set # CONFIG_DEBUG_STACKOVERFLOW is not set # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_VERBOSE=y @@ -1139,15 +1095,16 @@ CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE=y CONFIG_EARLY_PRINTK=y CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set -# CONFIG_SECURITY is not set +CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_NETWORK is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 CONFIG_CRYPTO=y # @@ -1226,7 +1183,6 @@ CONFIG_CRYPTO=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -1234,13 +1190,11 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set @@ -1250,8 +1204,6 @@ CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m -CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/BlackStamp_defconfig b/trunk/arch/blackfin/configs/BlackStamp_defconfig index 9e65d885ec0b..5d944ffd4ab0 100644 --- a/trunk/arch/blackfin/configs/BlackStamp_defconfig +++ b/trunk/arch/blackfin/configs/BlackStamp_defconfig @@ -66,7 +66,6 @@ CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -276,7 +275,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/CM-BF527_defconfig b/trunk/arch/blackfin/configs/CM-BF527_defconfig index 4432150d89e3..648a31d01bf4 100644 --- a/trunk/arch/blackfin/configs/CM-BF527_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF527_defconfig @@ -1,13 +1,12 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.28 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y @@ -16,9 +15,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,72 +25,55 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_GROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y CONFIG_UID16=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y # CONFIG_AIO is not set CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -102,8 +81,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -119,6 +101,7 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_CLASSIC_RCU=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -282,10 +265,7 @@ CONFIG_HZ=250 # CONFIG_SCHED_HRTICK is not set CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y # CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -335,12 +315,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -351,9 +329,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -364,7 +343,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -382,7 +361,7 @@ CONFIG_C_AMBEN_ALL=y # EBIU_AMBCTL Control # CONFIG_BANK_0=0x7BB0 -CONFIG_BANK_1=0x7BB0 +CONFIG_BANK_1=0x5554 CONFIG_BANK_2=0x7BB0 CONFIG_BANK_3=0xFFC0 @@ -407,6 +386,7 @@ CONFIG_BINFMT_ZFLAT=y # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling @@ -420,6 +400,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -443,6 +428,7 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" @@ -466,9 +452,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -479,8 +463,13 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -495,21 +484,22 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # -CONFIG_MTD_CHAR=y +CONFIG_MTD_CHAR=m CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set @@ -522,9 +512,9 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI is not set +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y @@ -536,11 +526,9 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_INTELEXT is not set # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y CONFIG_MTD_ROM=m # CONFIG_MTD_ABSENT is not set @@ -550,7 +538,7 @@ CONFIG_MTD_ROM=m # CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_GPIO_ADDR=y +# CONFIG_MTD_GPIO_ADDR is not set # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -573,11 +561,6 @@ CONFIG_MTD_GPIO_ADDR=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -603,46 +586,12 @@ CONFIG_HAVE_IDE=y # SCSI device support # # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -664,9 +613,6 @@ CONFIG_PHYLIB=y # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y @@ -677,11 +623,9 @@ CONFIG_BFIN_TX_DESC_NUM=10 CONFIG_BFIN_RX_DESC_NUM=20 CONFIG_BFIN_MAC_RMII=y # CONFIG_SMC91X is not set +# CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set # CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -689,7 +633,6 @@ CONFIG_BFIN_MAC_RMII=y # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -698,10 +641,7 @@ CONFIG_BFIN_MAC_RMII=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# +# CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters @@ -734,13 +674,17 @@ CONFIG_BFIN_MAC_RMII=y # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set +# CONFIG_BF5xx_EPPI is not set # CONFIG_BFIN_SPORT is not set -# CONFIG_BFIN_TWI_LCD is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_TWI_LCD is not set +CONFIG_BFIN_DMA_INTERFACE=m +CONFIG_SIMPLE_GPIO=m # CONFIG_VT is not set # CONFIG_DEVKMEM is not set # CONFIG_BFIN_JTAG_COMM is not set @@ -754,7 +698,6 @@ CONFIG_BFIN_DMA_INTERFACE=m # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -767,7 +710,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set CONFIG_BFIN_OTP=y # CONFIG_BFIN_OTP_WRITE_ENABLE is not set @@ -816,9 +758,13 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_AD5252 is not set +# CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set @@ -826,6 +772,7 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y # @@ -833,17 +780,17 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_BFIN=y # CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_SPI_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y # @@ -856,7 +803,6 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: @@ -883,13 +829,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set -# CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_G760A is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set @@ -905,16 +849,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set @@ -946,12 +885,6 @@ CONFIG_BFIN_WDT=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set # # Multifunction device drivers @@ -959,14 +892,10 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set -# CONFIG_TPS65010 is not set -# CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set # CONFIG_REGULATOR is not set # @@ -1002,20 +931,20 @@ CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=m +CONFIG_USB=y # CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set CONFIG_USB_OTG_BLACKLIST_HUB=y -CONFIG_USB_MON=m +CONFIG_USB_MON=y # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set @@ -1023,24 +952,24 @@ CONFIG_USB_MON=m # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SOC=y # # Blackfin high speed USB Support # -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_PERIPHERAL=y +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_PERIPHERAL is not set # CONFIG_USB_MUSB_OTG is not set -CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_MUSB_HDRC_HCD=y CONFIG_MUSB_PIO_ONLY=y +CONFIG_MUSB_DMA_POLL=y # CONFIG_USB_MUSB_DEBUG is not set # @@ -1052,31 +981,18 @@ CONFIG_MUSB_PIO_ONLY=y # CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # -# also be needed; see USB_STORAGE Help for more info +# see USB_STORAGE Help for more information # -CONFIG_USB_STORAGE=m -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set # # USB port drivers @@ -1097,6 +1013,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set @@ -1104,50 +1021,9 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2272 is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GADGET is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set @@ -1214,7 +1090,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_BFIN=y # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -1227,10 +1102,9 @@ CONFIG_RTC_DRV_BFIN=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -1239,11 +1113,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -1253,11 +1122,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -1269,7 +1135,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1277,19 +1146,9 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -1298,7 +1157,6 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y @@ -1309,6 +1167,7 @@ CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_REGISTER_V4 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m @@ -1323,9 +1182,9 @@ CONFIG_SMB_FS=m # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y +CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set @@ -1349,7 +1208,7 @@ CONFIG_NLS_CODEPAGE_437=y # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set @@ -1376,34 +1235,55 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_FRAME_POINTER is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set # # Tracers # -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set # CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_DEBUG_STACKOVERFLOW is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_KGDB_TESTCASE is not set CONFIG_DEBUG_VERBOSE=y -# CONFIG_DEBUG_MMRS is not set +CONFIG_DEBUG_MMRS=y +# CONFIG_DEBUG_HWERR is not set # CONFIG_DEBUG_DOUBLEFAULT is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y @@ -1413,10 +1293,9 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_CPLB_INFO is not set CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options @@ -1425,9 +1304,9 @@ CONFIG_ACCESS_CHECK=y CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_ROOTPLUG is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 CONFIG_CRYPTO=y # @@ -1506,7 +1385,6 @@ CONFIG_CRYPTO=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -1514,24 +1392,20 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF533_defconfig b/trunk/arch/blackfin/configs/CM-BF533_defconfig index df56639ab2f2..ae665b93b875 100644 --- a/trunk/arch/blackfin/configs/CM-BF533_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF533_defconfig @@ -1,110 +1,94 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# General setup +# Code maturity level options # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y -CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -# CONFIG_MODULE_UNLOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# CONFIG_BLOCK=y # CONFIG_LBD is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # # IO Schedulers @@ -112,7 +96,7 @@ CONFIG_BLOCK=y CONFIG_IOSCHED_NOOP=y # CONFIG_IOSCHED_AS is not set # CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_IOSCHED_CFQ is not set +CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set @@ -121,7 +105,6 @@ CONFIG_DEFAULT_IOSCHED="noop" CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set # # Blackfin Processor Options @@ -130,10 +113,6 @@ CONFIG_PREEMPT_NONE=y # # Processor and Board Settings # -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set # CONFIG_BF522 is not set # CONFIG_BF523 is not set # CONFIG_BF524 is not set @@ -146,38 +125,28 @@ CONFIG_BF533=y # CONFIG_BF534 is not set # CONFIG_BF536 is not set # CONFIG_BF537 is not set -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set # CONFIG_BF548 is not set -# CONFIG_BF548M is not set # CONFIG_BF549 is not set -# CONFIG_BF549M is not set # CONFIG_BF561 is not set -CONFIG_BF_REV_MIN=3 -CONFIG_BF_REV_MAX=6 # CONFIG_BF_REV_0_0 is not set # CONFIG_BF_REV_0_1 is not set # CONFIG_BF_REV_0_2 is not set CONFIG_BF_REV_0_3=y # CONFIG_BF_REV_0_4 is not set # CONFIG_BF_REV_0_5 is not set -# CONFIG_BF_REV_0_6 is not set # CONFIG_BF_REV_ANY is not set # CONFIG_BF_REV_NONE is not set CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y CONFIG_MEM_MT48LC16M16A2TG_75=y # CONFIG_BFIN533_EZKIT is not set # CONFIG_BFIN533_STAMP is not set -# CONFIG_BLACKSTAMP is not set CONFIG_BFIN533_BLUETECHNIX_CM=y # CONFIG_H8606_HVSISTEMAS is not set -# CONFIG_BFIN532_IP0X is not set +# CONFIG_GENERIC_BF533_BOARD is not set # # BF533/2/1 Specific Configuration @@ -219,7 +188,6 @@ CONFIG_WDTIMER=13 # Board customizations # # CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 # # Clock/PLL Setup @@ -239,20 +207,13 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # -# Misc +# Memory Setup # +CONFIG_MAX_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set @@ -279,12 +240,6 @@ CONFIG_IP_CHECKSUM_L1=y CONFIG_CACHELINE_ALIGNED_L1=y CONFIG_SYSCALL_TAB_L1=y CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y CONFIG_RAMKERNEL=y # CONFIG_ROMKERNEL is not set CONFIG_SELECT_MEMORY_MODEL=y @@ -293,16 +248,12 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_LARGE_ALLOCS=y # CONFIG_BFIN_GPTIMERS is not set -# CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set @@ -311,9 +262,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -324,7 +276,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -349,8 +301,12 @@ CONFIG_BANK_3=0xFFC2 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # +# CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set + +# +# PCCARD (PCMCIA/CardBus) support +# # # Executable file formats @@ -359,19 +315,22 @@ CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_SHARED_FLAT=y -# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set + +# +# Networking +# CONFIG_NET=y # @@ -380,13 +339,45 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set -# CONFIG_INET is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -394,23 +385,31 @@ CONFIG_UNIX=y # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set +# CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set + +# +# QoS and/or fair queueing +# # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set # # Device Drivers @@ -419,22 +418,20 @@ CONFIG_UNIX=y # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set # # User Modules And Translation Layers @@ -447,15 +444,12 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI is not set # CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -466,11 +460,6 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set @@ -479,16 +468,12 @@ CONFIG_MTD_RAM=y # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_UCLINUX is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -504,25 +489,36 @@ CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_ONENAND is not set # -# LPDDR flash memory drivers +# UBI - Unsorted block images # -# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set # -# UBI - Unsorted block images +# Parallel port support # -# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y + +# +# Misc devices +# # CONFIG_IDE is not set # @@ -530,19 +526,34 @@ CONFIG_HAVE_IDE=y # # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# # CONFIG_MD is not set + +# +# Network device support +# CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set -# CONFIG_MACVLAN is not set +# CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_NET_ETHERNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y +# CONFIG_SMSC911X is not set +# CONFIG_DM9000 is not set # CONFIG_NETDEV_1000 is not set +# CONFIG_AX88180 is not set # CONFIG_NETDEV_10000 is not set # @@ -550,17 +561,22 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# # CONFIG_ISDN is not set + +# +# Telephony Support +# # CONFIG_PHONE is not set # @@ -577,15 +593,16 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # Character devices # -# CONFIG_BFIN_DMA_INTERFACE is not set -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set -# CONFIG_BFIN_SPORT is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set -# CONFIG_BFIN_JTAG_COMM is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -596,7 +613,6 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -607,140 +623,175 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # # CAN, the car bus and industrial fieldbus # # CONFIG_CAN4LINUX is not set + +# +# IPMI +# # CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y # -# SPI Master Controller Drivers +# TPM devices # -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set + +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y # -# SPI Protocol Masters +# SPI support # -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # -# Sonics Silicon Backplane +# Dallas's 1-wire bus # -# CONFIG_SSB is not set +# CONFIG_W1 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# +# CONFIG_DVB_CORE is not set # CONFIG_DAB is not set # # Graphics support # -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# # CONFIG_SOUND is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD/SDIO Card Drivers +# USB support # -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB is not set # -# MMC/SD/SDIO Host Controller Drivers +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set + +# +# LED devices # -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set + +# +# LED drivers +# + +# +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# # CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set # # File systems # -# CONFIG_EXT2_FS is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +# CONFIG_EXT2_FS_POSIX_ACL is not set +# CONFIG_EXT2_FS_SECURITY is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set +CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -750,11 +801,8 @@ CONFIG_FILE_LOCKING=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y # CONFIG_MSDOS_FS is not set -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -765,8 +813,12 @@ CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -774,106 +826,60 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Network File Systems +# +# CONFIG_NFS_FS is not set +# CONFIG_NFSD is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# +# CONFIG_DLM is not set + +# +# Profiling support +# +# CONFIG_PROFILING is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_DEBUG_VERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_DOUBLEFAULT is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y @@ -882,39 +888,34 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# # CONFIG_CRYPTO is not set -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=y +CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF537E_defconfig b/trunk/arch/blackfin/configs/CM-BF537E_defconfig index 22e565c51d66..d74b6f4db35d 100644 --- a/trunk/arch/blackfin/configs/CM-BF537E_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF537E_defconfig @@ -1,13 +1,13 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.28.10 +# Wed Jun 3 06:27:41 2009 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y @@ -16,9 +16,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,40 +26,21 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_ANON_INODES=y @@ -71,8 +49,7 @@ CONFIG_EMBEDDED=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set @@ -88,13 +65,12 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -102,8 +78,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -119,6 +98,7 @@ CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_CFQ is not set CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -201,8 +181,7 @@ CONFIG_IRQ_MEM_DMA1=13 CONFIG_IRQ_WATCH=13 CONFIG_IRQ_SPI=10 # CONFIG_BFIN537_STAMP is not set -CONFIG_BFIN537_BLUETECHNIX_CM_E=y -# CONFIG_BFIN537_BLUETECHNIX_CM_U is not set +CONFIG_BFIN537_BLUETECHNIX_CM=y # CONFIG_BFIN537_BLUETECHNIX_TCM is not set # CONFIG_PNAV10 is not set # CONFIG_CAMSIG_MINOTAUR is not set @@ -304,12 +283,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 # CONFIG_BFIN_GPTIMERS is not set # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -320,9 +297,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -333,7 +311,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -359,7 +337,6 @@ CONFIG_BANK_3=0xFFC2 # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set # # Executable file formats @@ -389,6 +366,11 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -412,6 +394,7 @@ CONFIG_IP_PNP=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" @@ -435,9 +418,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing @@ -448,8 +429,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set # CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -460,21 +441,16 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set # @@ -510,26 +486,22 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m +# CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_GPIO_ADDR=y -# CONFIG_MTD_UCLINUX is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -544,11 +516,6 @@ CONFIG_MTD_GPIO_ADDR=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -566,14 +533,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -587,7 +549,6 @@ CONFIG_HAVE_IDE=y # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set @@ -609,9 +570,6 @@ CONFIG_PHYLIB=y # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y @@ -622,11 +580,8 @@ CONFIG_BFIN_TX_DESC_NUM=10 CONFIG_BFIN_RX_DESC_NUM=20 # CONFIG_BFIN_MAC_RMII is not set # CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set # CONFIG_SMSC911X is not set -# CONFIG_DNET is not set +# CONFIG_DM9000 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -643,10 +598,7 @@ CONFIG_BFIN_RX_DESC_NUM=20 # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -670,12 +622,15 @@ CONFIG_BFIN_RX_DESC_NUM=20 # # Character devices # +# CONFIG_AD9960 is not set CONFIG_BFIN_DMA_INTERFACE=m # CONFIG_BFIN_PPI is not set # CONFIG_BFIN_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set # CONFIG_BFIN_SPI_ADC is not set CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set # CONFIG_BFIN_JTAG_COMM is not set @@ -689,7 +644,6 @@ CONFIG_BFIN_SPORT=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -702,7 +656,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # @@ -715,23 +668,7 @@ CONFIG_UNIX98_PTYS=y # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set - -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y @@ -751,21 +688,15 @@ CONFIG_GPIO_SYSFS=y # # SPI GPIO expanders: # -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_VT1211 is not set @@ -827,74 +758,21 @@ CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -CONFIG_USB_GADGET_NET2272=y -CONFIG_USB_NET2272=m -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -# CONFIG_MMC_BLOCK_BOUNCE is not set -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -911,10 +789,9 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -923,11 +800,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -937,11 +809,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -953,7 +822,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -961,19 +833,9 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_YAFFS_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -982,70 +844,14 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -# CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set -CONFIG_LOCKD=m -CONFIG_LOCKD_V4=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=m -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set +# CONFIG_NLS is not set # CONFIG_DLM is not set # @@ -1061,28 +867,14 @@ CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y # # Tracers # -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_DEBUG_VERBOSE=y @@ -1096,10 +888,9 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options @@ -1108,9 +899,8 @@ CONFIG_ACCESS_CHECK=y CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 CONFIG_CRYPTO=y # @@ -1189,7 +979,6 @@ CONFIG_CRYPTO=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -1197,24 +986,19 @@ CONFIG_CRYPTO=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF537U_defconfig b/trunk/arch/blackfin/configs/CM-BF537U_defconfig index efcc90d2f345..7fc8dfa1719f 100644 --- a/trunk/arch/blackfin/configs/CM-BF537U_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF537U_defconfig @@ -1,111 +1,94 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.22.16 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_TIME=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# General setup +# Code maturity level options # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y +# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set -# CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y -CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 + +# +# Loadable module support +# CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y + +# +# Block layer +# CONFIG_BLOCK=y # CONFIG_LBD is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # # IO Schedulers @@ -122,7 +105,6 @@ CONFIG_DEFAULT_IOSCHED="noop" CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set # # Blackfin Processor Options @@ -131,10 +113,6 @@ CONFIG_PREEMPT_NONE=y # # Processor and Board Settings # -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set # CONFIG_BF522 is not set # CONFIG_BF523 is not set # CONFIG_BF524 is not set @@ -147,31 +125,22 @@ CONFIG_PREEMPT_NONE=y # CONFIG_BF534 is not set # CONFIG_BF536 is not set CONFIG_BF537=y -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set # CONFIG_BF548 is not set -# CONFIG_BF548M is not set # CONFIG_BF549 is not set -# CONFIG_BF549M is not set # CONFIG_BF561 is not set -CONFIG_BF_REV_MIN=2 -CONFIG_BF_REV_MAX=3 # CONFIG_BF_REV_0_0 is not set # CONFIG_BF_REV_0_1 is not set CONFIG_BF_REV_0_2=y # CONFIG_BF_REV_0_3 is not set # CONFIG_BF_REV_0_4 is not set # CONFIG_BF_REV_0_5 is not set -# CONFIG_BF_REV_0_6 is not set # CONFIG_BF_REV_ANY is not set # CONFIG_BF_REV_NONE is not set CONFIG_BF53x=y +CONFIG_BFIN_SINGLE_CORE=y CONFIG_MEM_MT48LC16M16A2TG_75=y CONFIG_IRQ_PLL_WAKEUP=7 CONFIG_IRQ_RTC=8 @@ -181,6 +150,7 @@ CONFIG_IRQ_SPORT0_TX=9 CONFIG_IRQ_SPORT1_RX=9 CONFIG_IRQ_SPORT1_TX=9 CONFIG_IRQ_TWI=10 +CONFIG_IRQ_SPI=10 CONFIG_IRQ_UART0_RX=10 CONFIG_IRQ_UART0_TX=10 CONFIG_IRQ_UART1_RX=10 @@ -199,13 +169,11 @@ CONFIG_IRQ_PORTG_INTB=12 CONFIG_IRQ_MEM_DMA0=13 CONFIG_IRQ_MEM_DMA1=13 CONFIG_IRQ_WATCH=13 -CONFIG_IRQ_SPI=10 # CONFIG_BFIN537_STAMP is not set -# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set -CONFIG_BFIN537_BLUETECHNIX_CM_U=y -# CONFIG_BFIN537_BLUETECHNIX_TCM is not set +CONFIG_BFIN537_BLUETECHNIX_CM=y # CONFIG_PNAV10 is not set # CONFIG_CAMSIG_MINOTAUR is not set +# CONFIG_GENERIC_BF537_BOARD is not set # # BF537 Specific Configuration @@ -228,7 +196,6 @@ CONFIG_IRQ_PROG_INTA=12 # Board customizations # # CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 # # Clock/PLL Setup @@ -248,20 +215,13 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y -# CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set -# CONFIG_NO_HZ is not set -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # -# Misc +# Memory Setup # +CONFIG_MAX_MEM_SIZE=32 +CONFIG_MEM_ADD_WIDTH=9 +CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set @@ -288,12 +248,6 @@ CONFIG_IP_CHECKSUM_L1=y CONFIG_CACHELINE_ALIGNED_L1=y CONFIG_SYSCALL_TAB_L1=y CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y CONFIG_RAMKERNEL=y # CONFIG_ROMKERNEL is not set CONFIG_SELECT_MEMORY_MODEL=y @@ -302,16 +256,12 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_LARGE_ALLOCS=y # CONFIG_BFIN_GPTIMERS is not set -# CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set @@ -320,9 +270,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -333,7 +284,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -358,8 +309,12 @@ CONFIG_BANK_3=0xFFC2 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # +# CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set + +# +# PCCARD (PCMCIA/CardBus) support +# # # Executable file formats @@ -368,19 +323,22 @@ CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_SHARED_FLAT=y -# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set + +# +# Networking +# CONFIG_NET=y # @@ -389,6 +347,10 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -407,13 +369,15 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set -CONFIG_INET_LRO=y # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set @@ -422,7 +386,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -432,23 +395,29 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set + +# +# QoS and/or fair queueing +# # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set # # Device Drivers @@ -457,22 +426,20 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set + +# +# Connector - unified userspace <-> kernelspace linker +# # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set # # User Modules And Translation Layers @@ -485,15 +452,12 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI is not set # CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -504,29 +468,20 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m +# CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # # Mapping drivers for chip access # -CONFIG_MTD_COMPLEX_MAPPINGS=y -# CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_GPIO_ADDR=y -# CONFIG_MTD_UCLINUX is not set +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -542,36 +497,36 @@ CONFIG_MTD_GPIO_ADDR=y # CONFIG_MTD_ONENAND is not set # -# LPDDR flash memory drivers +# UBI - Unsorted block images # -# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_UBI is not set # -# UBI - Unsorted block images +# Parallel port support # -# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y + +# +# Plug and Play support +# +# CONFIG_PNPACPI is not set + +# +# Block devices +# # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -CONFIG_MISC_DEVICES=y -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_C2PORT is not set # -# EEPROM support +# Misc devices # -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -579,20 +534,35 @@ CONFIG_HAVE_IDE=y # # CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set -# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set + +# +# Multi-device support (RAID and LVM) +# # CONFIG_MD is not set + +# +# Network device support +# CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_VETH is not set -# CONFIG_NET_ETHERNET is not set +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_SMC91X=y +# CONFIG_BFIN_MAC is not set +# CONFIG_SMSC911X is not set +# CONFIG_DM9000 is not set # CONFIG_NETDEV_1000 is not set +# CONFIG_AX88180 is not set # CONFIG_NETDEV_10000 is not set # @@ -600,17 +570,22 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# # CONFIG_ISDN is not set + +# +# Telephony Support +# # CONFIG_PHONE is not set # @@ -627,15 +602,16 @@ CONFIG_COMPAT_NET_DEV_OPS=y # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PFLAGS is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set -# CONFIG_BFIN_JTAG_COMM is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -646,7 +622,6 @@ CONFIG_BFIN_SPORT=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -659,201 +634,165 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # # CAN, the car bus and industrial fieldbus # # CONFIG_CAN4LINUX is not set + +# +# IPMI +# # CONFIG_IPMI_HANDLER is not set +# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_I2C is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y # -# SPI Master Controller Drivers +# TPM devices # -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y # -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: +# SPI support # +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # -# PCI GPIO expanders: +# Dallas's 1-wire bus # - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# # CONFIG_DAB is not set # # Graphics support # -# CONFIG_VGASTATE is not set -# CONFIG_VIDEO_OUTPUT_CONTROL is not set -# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_FB is not set + +# +# Sound +# # CONFIG_SOUND is not set -CONFIG_USB_SUPPORT=y + +# +# USB support +# CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set # CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_GADGET_MUSB_HDRC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support # CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set # CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set CONFIG_USB_GADGET_NET2272=y CONFIG_USB_NET2272=y # CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_PXA2XX is not set # CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH is not set # CONFIG_USB_GADGETFS is not set # CONFIG_USB_FILE_STORAGE is not set # CONFIG_USB_G_SERIAL is not set # CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_MMC is not set # -# OTG and related infrastructure +# LED devices # -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set +# CONFIG_NEW_LEDS is not set # -# MMC/SD/SDIO Card Drivers +# LED drivers # -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set # -# MMC/SD/SDIO Host Controller Drivers +# LED Triggers +# + +# +# InfiniBand support +# + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock # -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set -# CONFIG_STAGING is not set + +# +# DMA Engine support +# +# CONFIG_DMA_ENGINE is not set + +# +# DMA Clients +# + +# +# DMA Devices +# + +# +# PBX support +# +# CONFIG_PBX is not set # # File systems @@ -863,28 +802,24 @@ CONFIG_EXT2_FS_XATTR=y # CONFIG_EXT2_FS_POSIX_ACL is not set # CONFIG_EXT2_FS_SECURITY is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -# CONFIG_DNOTIFY is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -894,11 +829,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -909,8 +841,12 @@ CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -918,29 +854,18 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y + +# +# Network File Systems +# # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set @@ -948,94 +873,41 @@ CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set + +# +# Native Language Support +# +# CONFIG_NLS is not set + +# +# Distributed Lock Manager +# # CONFIG_DLM is not set +# +# Profiling support +# +# CONFIG_PROFILING is not set + # # Kernel hacking # # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_DEBUG_VERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_DOUBLEFAULT is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y @@ -1044,40 +916,34 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_CAPABILITIES=y + +# +# Cryptographic options +# # CONFIG_CRYPTO is not set -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF548_defconfig b/trunk/arch/blackfin/configs/CM-BF548_defconfig index 7f579cf51127..acca4e51a45a 100644 --- a/trunk/arch/blackfin/configs/CM-BF548_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF548_defconfig @@ -1,14 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.24.4 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y @@ -16,9 +16,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,100 +26,79 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y -# CONFIG_UID16 is not set +CONFIG_UID16=y # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y CONFIG_EVENTFD=y -CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set +CONFIG_IOSCHED_AS=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set +CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set -CONFIG_DEFAULT_NOOP=y -CONFIG_DEFAULT_IOSCHED="noop" -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set # # Blackfin Processor Options @@ -131,10 +107,6 @@ CONFIG_PREEMPT_NONE=y # # Processor and Board Settings # -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set # CONFIG_BF522 is not set # CONFIG_BF523 is not set # CONFIG_BF524 is not set @@ -147,29 +119,19 @@ CONFIG_PREEMPT_NONE=y # CONFIG_BF534 is not set # CONFIG_BF536 is not set # CONFIG_BF537 is not set -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set -CONFIG_BF548_std=y -# CONFIG_BF548M is not set +CONFIG_BF548=y # CONFIG_BF549 is not set -# CONFIG_BF549M is not set # CONFIG_BF561 is not set -CONFIG_BF_REV_MIN=0 -CONFIG_BF_REV_MAX=2 # CONFIG_BF_REV_0_0 is not set # CONFIG_BF_REV_0_1 is not set -# CONFIG_BF_REV_0_2 is not set +CONFIG_BF_REV_0_2=y # CONFIG_BF_REV_0_3 is not set # CONFIG_BF_REV_0_4 is not set # CONFIG_BF_REV_0_5 is not set -# CONFIG_BF_REV_0_6 is not set -CONFIG_BF_REV_ANY=y +# CONFIG_BF_REV_ANY is not set # CONFIG_BF_REV_NONE is not set CONFIG_BF54x=y CONFIG_IRQ_PLL_WAKEUP=7 @@ -178,12 +140,15 @@ CONFIG_IRQ_SPORT0_RX=9 CONFIG_IRQ_SPORT0_TX=9 CONFIG_IRQ_SPORT1_RX=9 CONFIG_IRQ_SPORT1_TX=9 -CONFIG_IRQ_SPI0=10 CONFIG_IRQ_UART0_RX=10 CONFIG_IRQ_UART0_TX=10 CONFIG_IRQ_UART1_RX=10 CONFIG_IRQ_UART1_TX=10 CONFIG_IRQ_CNT=8 +CONFIG_IRQ_USB_INT0=11 +CONFIG_IRQ_USB_INT1=11 +CONFIG_IRQ_USB_INT2=11 +CONFIG_IRQ_USB_DMA=11 CONFIG_IRQ_TIMER0=11 CONFIG_IRQ_TIMER1=11 CONFIG_IRQ_TIMER2=11 @@ -192,21 +157,9 @@ CONFIG_IRQ_TIMER4=11 CONFIG_IRQ_TIMER5=11 CONFIG_IRQ_TIMER6=11 CONFIG_IRQ_TIMER7=11 -CONFIG_IRQ_USB_INT0=11 -CONFIG_IRQ_USB_INT1=11 -CONFIG_IRQ_USB_INT2=11 -CONFIG_IRQ_USB_DMA=11 CONFIG_IRQ_TIMER8=11 CONFIG_IRQ_TIMER9=11 CONFIG_IRQ_TIMER10=11 -CONFIG_IRQ_SPORT2_RX=9 -CONFIG_IRQ_SPORT2_TX=9 -CONFIG_IRQ_SPORT3_RX=9 -CONFIG_IRQ_SPORT3_TX=9 -CONFIG_IRQ_SPI1=10 -CONFIG_IRQ_SPI2=10 -CONFIG_IRQ_TWI0=11 -CONFIG_IRQ_TWI1=11 # CONFIG_BFIN548_EZKIT is not set CONFIG_BFIN548_BLUETECHNIX_CM=y @@ -214,7 +167,6 @@ CONFIG_BFIN548_BLUETECHNIX_CM=y # BF548 Specific Configuration # # CONFIG_DEB_DMA_URGENT is not set -# CONFIG_BF548_ATAPI_ALTERNATIVE_PORT is not set # # Interrupt Priority Assignment @@ -230,6 +182,7 @@ CONFIG_IRQ_SPORT1_ERR=7 CONFIG_IRQ_SPI0_ERR=7 CONFIG_IRQ_UART0_ERR=7 CONFIG_IRQ_EPPI0=8 +CONFIG_IRQ_SPI0=10 CONFIG_IRQ_PINT0=12 CONFIG_IRQ_PINT1=12 CONFIG_IRQ_MDMAS0=13 @@ -244,10 +197,18 @@ CONFIG_IRQ_SPI2_ERR=7 CONFIG_IRQ_UART1_ERR=7 CONFIG_IRQ_UART2_ERR=7 CONFIG_IRQ_CAN0_ERR=7 +CONFIG_IRQ_SPORT2_RX=9 +CONFIG_IRQ_SPORT2_TX=9 +CONFIG_IRQ_SPORT3_RX=9 +CONFIG_IRQ_SPORT3_TX=9 CONFIG_IRQ_EPPI1=9 CONFIG_IRQ_EPPI2=9 +CONFIG_IRQ_SPI1=10 +CONFIG_IRQ_SPI2=10 CONFIG_IRQ_ATAPI_RX=10 CONFIG_IRQ_ATAPI_TX=10 +CONFIG_IRQ_TWI0=11 +CONFIG_IRQ_TWI1=11 CONFIG_IRQ_CAN0_RX=11 CONFIG_IRQ_CAN0_TX=11 CONFIG_IRQ_MDMAS2=13 @@ -294,7 +255,6 @@ CONFIG_PINT3_ASSIGN=0x02020303 # Board customizations # # CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 # # Clock/PLL Setup @@ -314,12 +274,16 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set # CONFIG_GENERIC_TIME is not set +# CONFIG_TICK_ONESHOT is not set # -# Misc +# Memory Setup # +CONFIG_MAX_MEM_SIZE=64 +# CONFIG_MEM_MT46V32M16_6T is not set +CONFIG_MEM_MT46V32M16_5B=y +CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set @@ -346,12 +310,6 @@ CONFIG_ACCESS_OK_L1=y CONFIG_CACHELINE_ALIGNED_L1=y # CONFIG_SYSCALL_TAB_L1 is not set # CONFIG_CPLB_SWITCH_TAB_L1 is not set -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y CONFIG_RAMKERNEL=y # CONFIG_ROMKERNEL is not set CONFIG_SELECT_MEMORY_MODEL=y @@ -360,16 +318,13 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 # CONFIG_BFIN_GPTIMERS is not set -# CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set @@ -378,13 +333,14 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y -# CONFIG_BFIN_EXTMEM_WRITEBACK -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set # CONFIG_BFIN_L2_DCACHEABLE is not set # @@ -393,7 +349,7 @@ CONFIG_BFIN_EXTMEM_WRITETHROUGH=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -413,7 +369,7 @@ CONFIG_C_AMBEN_ALL=y CONFIG_BANK_0=0x7BB0 CONFIG_BANK_1=0x5554 CONFIG_BANK_2=0x7BB0 -CONFIG_BANK_3=0x99B3 +CONFIG_BANK_3=0x99B2 CONFIG_EBIU_MBSCTLVAL=0x0 CONFIG_EBIU_MODEVAL=0x1 CONFIG_EBIU_FCTLVAL=0x6 @@ -421,6 +377,7 @@ CONFIG_EBIU_FCTLVAL=0x6 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # +# CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCCARD is not set @@ -431,19 +388,23 @@ CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y # CONFIG_BINFMT_SHARED_FLAT is not set -# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_SUSPEND_UP_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set + +# +# Networking +# CONFIG_NET=y # @@ -456,7 +417,6 @@ CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -475,16 +435,19 @@ CONFIG_IP_PNP=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set @@ -493,7 +456,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -503,21 +465,24 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -536,12 +501,10 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -576,7 +539,6 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y # CONFIG_MTD_ROM is not set @@ -587,8 +549,9 @@ CONFIG_MTD_RAM=y # CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_GPIO_ADDR is not set +CONFIG_MTD_PHYSMAP_START=0x20000000 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 # CONFIG_MTD_UCLINUX is not set # CONFIG_MTD_PLATRAM is not set @@ -611,11 +574,6 @@ CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -629,31 +587,31 @@ CONFIG_BLK_DEV=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set # CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=m +CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y +# CONFIG_SCSI_PROC_FS is not set # # SCSI support type (disk, tape, CD-ROM) # -CONFIG_BLK_DEV_SD=m +CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set @@ -674,54 +632,29 @@ CONFIG_SCSI_WAIT_SCAN=m # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_SCSI_DEBUG is not set # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set +# CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set CONFIG_SMSC911X=y -# CONFIG_DNET is not set +# CONFIG_DM9000 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -732,10 +665,6 @@ CONFIG_SMSC911X=y # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - # # USB Network Adapters # @@ -747,6 +676,7 @@ CONFIG_SMSC911X=y # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -781,7 +711,6 @@ CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_GPIO is not set # CONFIG_KEYBOARD_BFIN is not set # CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_ADP5588 is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set @@ -797,16 +726,19 @@ CONFIG_INPUT_KEYBOARD=y # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set +CONFIG_BFIN_OTP=y +# CONFIG_BFIN_OTP_WRITE_ENABLE is not set # CONFIG_BFIN_SPORT is not set -# CONFIG_BFIN_TWI_LCD is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_TWI_LCD is not set +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set -CONFIG_DEVKMEM=y -# CONFIG_BFIN_JTAG_COMM is not set +# CONFIG_DEVKMEM is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -817,11 +749,10 @@ CONFIG_DEVKMEM=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y -# CONFIG_SERIAL_BFIN_DMA is not set -CONFIG_SERIAL_BFIN_PIO=y +CONFIG_SERIAL_BFIN_DMA=y +# CONFIG_SERIAL_BFIN_PIO is not set # CONFIG_SERIAL_BFIN_UART0 is not set CONFIG_SERIAL_BFIN_UART1=y # CONFIG_BFIN_UART1_CTSRTS is not set @@ -831,10 +762,7 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set -CONFIG_BFIN_OTP=y -# CONFIG_BFIN_OTP_WRITE_ENABLE is not set # # CAN, the car bus and industrial fieldbus @@ -842,53 +770,61 @@ CONFIG_BFIN_OTP=y # CONFIG_CAN4LINUX is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y -CONFIG_I2C_HELPER_AUTO=y # -# I2C Hardware Bus support +# I2C Algorithms # +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set # -# I2C system bus drivers (mostly embedded / system-on-chip) +# I2C Hardware Bus support # CONFIG_I2C_BLACKFIN_TWI=y -CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50 +CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# # CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set +# CONFIG_I2C_TINY_USB is not set # # Miscellaneous I2C Chip support # +# CONFIG_SENSORS_DS1337 is not set +# CONFIG_SENSORS_DS1374 is not set # CONFIG_DS1682 is not set +# CONFIG_SENSORS_AD5252 is not set +# CONFIG_EEPROM_LEGACY is not set # CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCF8575 is not set +# CONFIG_SENSORS_PCA9543 is not set # CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set + +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# SPI support +# CONFIG_SPI=y CONFIG_SPI_MASTER=y @@ -896,23 +832,64 @@ CONFIG_SPI_MASTER=y # SPI Master Controller Drivers # CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set -CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_HWMON_DEBUG_CHIP is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set @@ -926,43 +903,25 @@ CONFIG_BFIN_WDT=y # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# # CONFIG_DAB is not set +# CONFIG_USB_DABUSB is not set # # Graphics support @@ -976,75 +935,80 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# # CONFIG_SOUND is not set -# CONFIG_HID_SUPPORT is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_USB_HIDINPUT_POWERBOOK is not set +# CONFIG_HID_FF is not set +# CONFIG_USB_HIDDEV is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set -CONFIG_USB=m +CONFIG_USB=y # CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=m -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set -CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SOC=y # -# Blackfin high speed USB Support +# Blackfin BF54x, BF525 and BF527 high speed USB support # -# CONFIG_USB_MUSB_HOST is not set -CONFIG_USB_MUSB_PERIPHERAL=y +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_PERIPHERAL is not set # CONFIG_USB_MUSB_OTG is not set -CONFIG_USB_GADGET_MUSB_HDRC=y +CONFIG_USB_MUSB_HDRC_HCD=y # CONFIG_MUSB_PIO_ONLY is not set -CONFIG_USB_INVENTRA_DMA=y +# CONFIG_USB_INVENTRA_DMA is not set # CONFIG_USB_TI_CPPI_DMA is not set -# CONFIG_USB_MUSB_DEBUG is not set +CONFIG_USB_MUSB_LOGLEVEL=0 # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set # -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # -# also be needed; see USB_STORAGE Help for more info +# may also be needed; see USB_STORAGE Help for more information # -CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set @@ -1052,7 +1016,6 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # @@ -1060,10 +1023,15 @@ CONFIG_USB_STORAGE=m # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set +CONFIG_USB_MON=y # # USB port drivers # + +# +# USB Serial Converter support +# # CONFIG_USB_SERIAL is not set # @@ -1072,7 +1040,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_AUERSWALD is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set @@ -1080,6 +1048,7 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set @@ -1087,75 +1056,38 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -# CONFIG_USB_GADGET_NET2272 is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_ZERO=m -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -# CONFIG_USB_ETH_RNDIS is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -CONFIG_USB_OTG_UTILS=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=m + +# +# USB DSL modem support +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set # CONFIG_MMC_UNSAFE_RESUME is not set # -# MMC/SD/SDIO Card Drivers +# MMC/SD Card Drivers # -CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set # -# MMC/SD/SDIO Host Controller Drivers +# MMC/SD Host Controller Drivers # -# CONFIG_MMC_SDHCI is not set -CONFIG_SDH_BFIN=m -# CONFIG_SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND is not set -# CONFIG_SDH_BFIN_ENABLE_SDIO_IRQ is not set +CONFIG_SDH_BFIN=y # CONFIG_MMC_SPI is not set -# CONFIG_MEMSTICK is not set +# CONFIG_SPI_MMC is not set # CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -CONFIG_RTC_LIB=m -CONFIG_RTC_CLASS=m +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # # RTC interfaces @@ -1179,74 +1111,66 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set # # SPI RTC drivers # -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_R9701 is not set # CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_MAX6902 is not set # # Platform RTC drivers # -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # -CONFIG_RTC_DRV_BFIN=m -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set +CONFIG_RTC_DRV_BFIN=y + +# +# Userspace I/O +# # CONFIG_UIO is not set -# CONFIG_STAGING is not set + +# +# PBX support +# +# CONFIG_PBX is not set # # File systems # -CONFIG_EXT2_FS=m -# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # -# CONFIG_ISO9660_FS is not set +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y # CONFIG_UDF_FS is not set # @@ -1270,7 +1194,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -1278,7 +1205,17 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y +CONFIG_YAFFS_FS=m +CONFIG_YAFFS_YAFFS1=y +# CONFIG_YAFFS_DOES_ECC is not set +CONFIG_YAFFS_YAFFS2=y +CONFIG_YAFFS_AUTO_YAFFS2=y +# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set +CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10 +# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set +CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +CONFIG_JFFS2_FS=m CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y # CONFIG_JFFS2_FS_WBUF_VERIFY is not set @@ -1290,30 +1227,34 @@ CONFIG_JFFS2_ZLIB=y CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFSD is not set +# CONFIG_NFS_DIRECTIO is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +# CONFIG_NFSD_V4 is not set +CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m +# CONFIG_SUNRPC_BIND34 is not set # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -CONFIG_CIFS=m +CONFIG_SMB_FS=m +CONFIG_SMB_NLS_DEFAULT=y +CONFIG_SMB_NLS_REMOTE="cp437" +CONFIG_CIFS=y # CONFIG_CIFS_STATS is not set # CONFIG_CIFS_WEAK_PW_HASH is not set # CONFIG_CIFS_XATTR is not set @@ -1326,8 +1267,24 @@ CONFIG_CIFS=m # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m @@ -1369,6 +1326,9 @@ CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m # CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking @@ -1376,39 +1336,14 @@ CONFIG_NLS_UTF8=m # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_DEBUG_VERBOSE=y -# CONFIG_DEBUG_MMRS is not set -# CONFIG_DEBUG_DOUBLEFAULT is not set +CONFIG_DEBUG_MMRS=y CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y @@ -1417,125 +1352,33 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -# CONFIG_CRYPTO_HW is not set -# CONFIG_BINARY_PRINTF is not set +# CONFIG_SECURITY_CAPABILITIES is not set +# CONFIG_SECURITY_ROOTPLUG is not set +# CONFIG_CRYPTO is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/CM-BF561_defconfig b/trunk/arch/blackfin/configs/CM-BF561_defconfig index a6df01dac98a..bae4ee6e68bb 100644 --- a/trunk/arch/blackfin/configs/CM-BF561_defconfig +++ b/trunk/arch/blackfin/configs/CM-BF561_defconfig @@ -1,14 +1,15 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.24.4 +# Tue Apr 1 10:50:11 2008 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y +CONFIG_SEMAPHORE_SLEEPERS=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_HARDIRQS=y @@ -16,9 +17,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,83 +27,62 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set # CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set -# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FAIR_USER_SCHED=y +# CONFIG_FAIR_CGROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set -# CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y -# CONFIG_SIGNALFD is not set -# CONFIG_TIMERFD is not set -# CONFIG_EVENTFD is not set -# CONFIG_AIO is not set +CONFIG_SIGNALFD=y +CONFIG_EVENTFD=y CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y +CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 +# CONFIG_NP2 is not set CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y -# CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set -CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -122,7 +99,6 @@ CONFIG_DEFAULT_IOSCHED="noop" CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -# CONFIG_FREEZER is not set # # Blackfin Processor Options @@ -131,10 +107,6 @@ CONFIG_PREEMPT_NONE=y # # Processor and Board Settings # -# CONFIG_BF512 is not set -# CONFIG_BF514 is not set -# CONFIG_BF516 is not set -# CONFIG_BF518 is not set # CONFIG_BF522 is not set # CONFIG_BF523 is not set # CONFIG_BF524 is not set @@ -147,56 +119,44 @@ CONFIG_PREEMPT_NONE=y # CONFIG_BF534 is not set # CONFIG_BF536 is not set # CONFIG_BF537 is not set -# CONFIG_BF538 is not set -# CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set # CONFIG_BF548 is not set -# CONFIG_BF548M is not set # CONFIG_BF549 is not set -# CONFIG_BF549M is not set CONFIG_BF561=y -# CONFIG_SMP is not set -CONFIG_BF_REV_MIN=3 -CONFIG_BF_REV_MAX=5 # CONFIG_BF_REV_0_0 is not set # CONFIG_BF_REV_0_1 is not set # CONFIG_BF_REV_0_2 is not set CONFIG_BF_REV_0_3=y # CONFIG_BF_REV_0_4 is not set # CONFIG_BF_REV_0_5 is not set -# CONFIG_BF_REV_0_6 is not set # CONFIG_BF_REV_ANY is not set # CONFIG_BF_REV_NONE is not set +CONFIG_BFIN_DUAL_CORE=y CONFIG_MEM_MT48LC8M32B2B5_7=y CONFIG_IRQ_PLL_WAKEUP=7 CONFIG_IRQ_SPORT0_ERROR=7 CONFIG_IRQ_SPORT1_ERROR=7 -CONFIG_IRQ_TIMER0=10 -CONFIG_IRQ_TIMER1=10 -CONFIG_IRQ_TIMER2=10 -CONFIG_IRQ_TIMER3=10 -CONFIG_IRQ_TIMER4=10 -CONFIG_IRQ_TIMER5=10 -CONFIG_IRQ_TIMER6=10 -CONFIG_IRQ_TIMER7=10 CONFIG_IRQ_SPI_ERROR=7 # CONFIG_BFIN561_EZKIT is not set # CONFIG_BFIN561_TEPLA is not set CONFIG_BFIN561_BLUETECHNIX_CM=y +# CONFIG_GENERIC_BF561_BOARD is not set # # BF561 Specific Configuration # +# +# Core B Support +# + # # Core B Support # CONFIG_BF561_COREB=y +# CONFIG_BF561_COREB_RESET is not set # # Interrupt Priority Assignment @@ -236,6 +196,14 @@ CONFIG_IRQ_DMA2_8=9 CONFIG_IRQ_DMA2_9=9 CONFIG_IRQ_DMA2_10=9 CONFIG_IRQ_DMA2_11=9 +CONFIG_IRQ_TIMER0=10 +CONFIG_IRQ_TIMER1=10 +CONFIG_IRQ_TIMER2=10 +CONFIG_IRQ_TIMER3=10 +CONFIG_IRQ_TIMER4=10 +CONFIG_IRQ_TIMER5=10 +CONFIG_IRQ_TIMER6=10 +CONFIG_IRQ_TIMER7=10 CONFIG_IRQ_TIMER8=10 CONFIG_IRQ_TIMER9=10 CONFIG_IRQ_TIMER10=10 @@ -258,7 +226,6 @@ CONFIG_IRQ_WDTIMER=13 # Board customizations # # CONFIG_CMDLINE_BOOL is not set -CONFIG_BOOT_LOAD=0x1000 # # Clock/PLL Setup @@ -278,20 +245,19 @@ CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set CONFIG_HZ=250 -# CONFIG_SCHED_HRTICK is not set CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y # CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set +# CONFIG_TICK_ONESHOT is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # -# Misc +# Memory Setup # +CONFIG_MAX_MEM_SIZE=32 +CONFIG_BOOT_LOAD=0x1000 CONFIG_BFIN_SCRATCH_REG_RETN=y # CONFIG_BFIN_SCRATCH_REG_RETE is not set # CONFIG_BFIN_SCRATCH_REG_CYCLES is not set @@ -318,12 +284,6 @@ CONFIG_IP_CHECKSUM_L1=y CONFIG_CACHELINE_ALIGNED_L1=y CONFIG_SYSCALL_TAB_L1=y CONFIG_CPLB_SWITCH_TAB_L1=y -CONFIG_APP_STACK_L1=y - -# -# Speed Optimizations -# -CONFIG_BFIN_INS_LOWOVERHEAD=y CONFIG_RAMKERNEL=y # CONFIG_ROMKERNEL is not set CONFIG_SELECT_MEMORY_MODEL=y @@ -332,16 +292,14 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_PAGEFLAGS_EXTENDED=y +# CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 +CONFIG_LARGE_ALLOCS=y # CONFIG_BFIN_GPTIMERS is not set -# CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y # CONFIG_DMA_UNCACHED_NONE is not set @@ -350,16 +308,15 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y -# CONFIG_BFIN_L2_ICACHEABLE is not set +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y -# CONFIG_BFIN_EXTMEM_WRITEBACK is not set -CONFIG_BFIN_EXTMEM_WRITETHROUGH=y +CONFIG_BFIN_EXTMEM_WRITEBACK=y +# CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set +# CONFIG_BFIN_L2_ICACHEABLE is not set # CONFIG_BFIN_L2_DCACHEABLE is not set -# CONFIG_BFIN_L2_WRITEBACK is not set -# CONFIG_BFIN_L2_WRITETHROUGH is not set # # Memory Protection Unit @@ -367,7 +324,7 @@ CONFIG_BFIN_EXTMEM_WRITETHROUGH=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -396,8 +353,8 @@ CONFIG_BANK_3=0xFFC2 # # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # +# CONFIG_PCI is not set # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set # # Executable file formats @@ -406,19 +363,18 @@ CONFIG_BINFMT_ELF_FDPIC=y CONFIG_BINFMT_FLAT=y CONFIG_BINFMT_ZFLAT=y CONFIG_BINFMT_SHARED_FLAT=y -# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_SUSPEND_UP_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # -# CPU Frequency scaling +# Networking # -# CONFIG_CPU_FREQ is not set CONFIG_NET=y # @@ -427,6 +383,10 @@ CONFIG_NET=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set @@ -447,11 +407,14 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_LRO is not set # CONFIG_INET_DIAG is not set +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set # CONFIG_NETLABEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set @@ -460,7 +423,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -470,21 +432,24 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set +# CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -495,22 +460,16 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set # # User Modules And Translation Layers @@ -528,10 +487,8 @@ CONFIG_MTD_BLOCK=y # # RAM/ROM/Flash chip drivers # -CONFIG_MTD_CFI=y +# CONFIG_MTD_CFI is not set # CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_GEN_PROBE=y -# CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -542,29 +499,20 @@ CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set -CONFIG_MTD_CFI_INTELEXT=y -# CONFIG_MTD_CFI_AMDSTD is not set -# CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set -CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m +# CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=y -# CONFIG_MTD_PHYSMAP_COMPAT is not set -# CONFIG_MTD_UCLINUX is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # -# CONFIG_MTD_DATAFLASH is not set -# CONFIG_MTD_M25P80 is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -579,11 +527,6 @@ CONFIG_MTD_PHYSMAP=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -596,21 +539,14 @@ CONFIG_BLK_DEV=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set +CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_93CX6 is not set -CONFIG_HAVE_IDE=y # CONFIG_IDE is not set +# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE0 is not set +# CONFIG_BFIN_IDE_ADDRESS_MAPPING_MODE1 is not set # # SCSI device support @@ -622,50 +558,26 @@ CONFIG_HAVE_IDE=y # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set +# CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y -# CONFIG_SMC91X is not set +CONFIG_SMC91X=y +# CONFIG_SMSC911X is not set # CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -CONFIG_SMSC911X=m -# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_NETDEV_1000 is not set +# CONFIG_AX88180 is not set # CONFIG_NETDEV_10000 is not set # @@ -673,13 +585,10 @@ CONFIG_SMSC911X=m # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set +# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set @@ -700,15 +609,16 @@ CONFIG_SMSC911X=m # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set # CONFIG_BFIN_SPORT is not set +# CONFIG_BFIN_TIMER_LATENCY is not set +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set -# CONFIG_BFIN_JTAG_COMM is not set # CONFIG_SERIAL_NONSTANDARD is not set # @@ -719,7 +629,6 @@ CONFIG_BFIN_DMA_INTERFACE=m # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -730,7 +639,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # @@ -739,100 +647,54 @@ CONFIG_UNIX98_PTYS=y # CONFIG_CAN4LINUX is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set +# CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set -CONFIG_SPI=y -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -CONFIG_SPI_BFIN=y -# CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set -# -# SPI Protocol Masters -# -# CONFIG_SPI_SPIDEV is not set -# CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y # -# Memory mapped GPIO expanders: -# - -# -# I2C GPIO expanders: -# - +# SPI support # -# PCI GPIO expanders: -# - -# -# SPI GPIO expanders: -# -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_SHT15 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # +CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # -# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set # # Multimedia devices # - -# -# Multimedia core support -# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# # CONFIG_DAB is not set # @@ -847,85 +709,42 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set + +# +# Sound +# # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_EHCI is not set # CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -CONFIG_USB_GADGET_NET2272=y -CONFIG_USB_NET2272=m -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -CONFIG_USB_FILE_STORAGE=m -# CONFIG_USB_FILE_STORAGE_TEST is not set -CONFIG_USB_G_SERIAL=m -# CONFIG_USB_MIDI_GADGET is not set -CONFIG_USB_G_PRINTER=m -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m -# CONFIG_MEMSTICK is not set + +# +# Enable Host or Gadget support to see Inventra options +# + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set +# CONFIG_MMC is not set # CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set -# CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set + +# +# Userspace I/O +# # CONFIG_UIO is not set -# CONFIG_STAGING is not set + +# +# PBX support +# +# CONFIG_PBX is not set # # File systems @@ -935,28 +754,24 @@ CONFIG_EXT2_FS_XATTR=y # CONFIG_EXT2_FS_POSIX_ACL is not set # CONFIG_EXT2_FS_SECURITY is not set # CONFIG_EXT3_FS is not set -# CONFIG_EXT4_FS is not set +# CONFIG_EXT4DEV_FS is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -CONFIG_FILE_LOCKING=y -# CONFIG_DNOTIFY is not set +# CONFIG_MINIX_FS is not set +# CONFIG_ROMFS_FS is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -966,11 +781,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -982,7 +794,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -990,28 +805,14 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set @@ -1026,47 +827,11 @@ CONFIG_NETWORK_FILESYSTEMS=y # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set +# CONFIG_NLS is not set # CONFIG_DLM is not set +CONFIG_INSTRUMENTATION=y +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set # # Kernel hacking @@ -1074,40 +839,14 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_DEBUG_VERBOSE=y CONFIG_DEBUG_MMRS=y -# CONFIG_DEBUG_DOUBLEFAULT is not set CONFIG_DEBUG_HUNT_FOR_ZERO=y CONFIG_DEBUG_BFIN_HWTRACE_ON=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y @@ -1116,40 +855,33 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DUAL_CORE_TEST_MODULE is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options # # CONFIG_KEYS is not set CONFIG_SECURITY=y -# CONFIG_SECURITYFS is not set # CONFIG_SECURITY_NETWORK is not set -# CONFIG_SECURITY_PATH is not set +CONFIG_SECURITY_CAPABILITIES=y # CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_SECURITY_TOMOYO is not set # CONFIG_CRYPTO is not set -# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m # CONFIG_CRC16 is not set -# CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_CRC7=y +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/configs/H8606_defconfig b/trunk/arch/blackfin/configs/H8606_defconfig index bc7fae3d8b83..a6a7c8ede705 100644 --- a/trunk/arch/blackfin/configs/H8606_defconfig +++ b/trunk/arch/blackfin/configs/H8606_defconfig @@ -67,7 +67,6 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y CONFIG_RT_MUTEXES=y CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 @@ -250,7 +249,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_LARGE_ALLOCS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y diff --git a/trunk/arch/blackfin/configs/IP0X_defconfig b/trunk/arch/blackfin/configs/IP0X_defconfig index a7e49d631229..1ec9ae2e964b 100644 --- a/trunk/arch/blackfin/configs/IP0X_defconfig +++ b/trunk/arch/blackfin/configs/IP0X_defconfig @@ -68,7 +68,6 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y CONFIG_RT_MUTEXES=y CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 @@ -262,7 +261,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_LARGE_ALLOCS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 # CONFIG_BFIN_GPTIMERS is not set # CONFIG_DMA_UNCACHED_2M is not set CONFIG_DMA_UNCACHED_1M=y diff --git a/trunk/arch/blackfin/configs/PNAV-10_defconfig b/trunk/arch/blackfin/configs/PNAV-10_defconfig index 67d12768602a..ff377fae061b 100644 --- a/trunk/arch/blackfin/configs/PNAV-10_defconfig +++ b/trunk/arch/blackfin/configs/PNAV-10_defconfig @@ -63,7 +63,6 @@ CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y @@ -286,7 +285,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_BFIN_GPTIMERS=y # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set diff --git a/trunk/arch/blackfin/configs/SRV1_defconfig b/trunk/arch/blackfin/configs/SRV1_defconfig index 52bfa6bf18da..814f9cacf407 100644 --- a/trunk/arch/blackfin/configs/SRV1_defconfig +++ b/trunk/arch/blackfin/configs/SRV1_defconfig @@ -72,7 +72,6 @@ CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3 CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y CONFIG_RT_MUTEXES=y CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 @@ -272,7 +271,6 @@ CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_LARGE_ALLOCS=y -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 CONFIG_DMA_UNCACHED_2M=y # CONFIG_DMA_UNCACHED_1M is not set # CONFIG_DMA_UNCACHED_NONE is not set @@ -702,7 +700,7 @@ CONFIG_INPUT_MISC=y # CONFIG_INPUT_YEALINK is not set CONFIG_INPUT_UINPUT=y # CONFIG_BF53X_PFBUTTONS is not set -# CONFIG_INPUT_PCF8574 is not set +# CONFIG_TWI_KEYPAD is not set # # Hardware I/O ports diff --git a/trunk/arch/blackfin/configs/TCM-BF537_defconfig b/trunk/arch/blackfin/configs/TCM-BF537_defconfig index 60adfad54db9..375e75a27abc 100644 --- a/trunk/arch/blackfin/configs/TCM-BF537_defconfig +++ b/trunk/arch/blackfin/configs/TCM-BF537_defconfig @@ -1,13 +1,13 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.30.5 +# Linux kernel version: 2.6.28-rc2 +# Tue Jan 6 09:22:17 2009 # # CONFIG_MMU is not set # CONFIG_FPU is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BLACKFIN=y -CONFIG_GENERIC_BUG=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y @@ -16,9 +16,6 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_GPIO=y CONFIG_FORCE_MAX_ZONEORDER=14 CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # @@ -29,72 +26,49 @@ CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -# CONFIG_KERNEL_GZIP is not set -# CONFIG_KERNEL_BZIP2 is not set -CONFIG_KERNEL_LZMA=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set - -# -# RCU Subsystem -# -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_RD_GZIP is not set -# CONFIG_RD_BZIP2 is not set -CONFIG_RD_LZMA=y +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y +# CONFIG_SYSCTL is not set CONFIG_EMBEDDED=y # CONFIG_UID16 is not set # CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_HOTPLUG=y +# CONFIG_HOTPLUG is not set CONFIG_PRINTK=y CONFIG_BUG=y # CONFIG_ELF_CORE is not set +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y # CONFIG_FUTEX is not set +CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y # CONFIG_AIO is not set CONFIG_VM_EVENT_COUNTERS=y -CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set -CONFIG_MMAP_ALLOW_UNINITIALIZED=y # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_TINY_SHMEM=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set @@ -102,8 +76,11 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -119,6 +96,7 @@ CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_CFQ is not set CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set @@ -150,15 +128,10 @@ CONFIG_BF537=y # CONFIG_BF538 is not set # CONFIG_BF539 is not set # CONFIG_BF542 is not set -# CONFIG_BF542M is not set # CONFIG_BF544 is not set -# CONFIG_BF544M is not set # CONFIG_BF547 is not set -# CONFIG_BF547M is not set # CONFIG_BF548 is not set -# CONFIG_BF548M is not set # CONFIG_BF549 is not set -# CONFIG_BF549M is not set # CONFIG_BF561 is not set CONFIG_BF_REV_MIN=2 CONFIG_BF_REV_MAX=3 @@ -200,11 +173,11 @@ CONFIG_IRQ_MEM_DMA1=13 CONFIG_IRQ_WATCH=13 CONFIG_IRQ_SPI=10 # CONFIG_BFIN537_STAMP is not set -# CONFIG_BFIN537_BLUETECHNIX_CM_E is not set -# CONFIG_BFIN537_BLUETECHNIX_CM_U is not set +# CONFIG_BFIN537_BLUETECHNIX_CM is not set CONFIG_BFIN537_BLUETECHNIX_TCM=y # CONFIG_PNAV10 is not set # CONFIG_CAMSIG_MINOTAUR is not set +# CONFIG_GENERIC_BF537_BOARD is not set # # BF537 Specific Configuration @@ -250,10 +223,7 @@ CONFIG_HZ=250 # CONFIG_SCHED_HRTICK is not set CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -# CONFIG_TICKSOURCE_GPTMR0 is not set -CONFIG_TICKSOURCE_CORETMR=y # CONFIG_CYCLES_CLOCKSOURCE is not set -# CONFIG_GPTMR0_CLOCKSOURCE is not set # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -303,12 +273,10 @@ CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_RESOURCES_64BIT is not set # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0 # CONFIG_BFIN_GPTIMERS is not set # CONFIG_DMA_UNCACHED_4M is not set # CONFIG_DMA_UNCACHED_2M is not set @@ -319,9 +287,10 @@ CONFIG_DMA_UNCACHED_1M=y # Cache Support # CONFIG_BFIN_ICACHE=y -CONFIG_BFIN_EXTMEM_ICACHEABLE=y +# CONFIG_BFIN_ICACHE_LOCK is not set CONFIG_BFIN_DCACHE=y # CONFIG_BFIN_DCACHE_BANKA is not set +CONFIG_BFIN_EXTMEM_ICACHEABLE=y CONFIG_BFIN_EXTMEM_DCACHEABLE=y CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_BFIN_EXTMEM_WRITETHROUGH is not set @@ -332,7 +301,7 @@ CONFIG_BFIN_EXTMEM_WRITEBACK=y # CONFIG_MPU is not set # -# Asynchronous Memory Configuration +# Asynchonous Memory Configuration # # @@ -358,7 +327,6 @@ CONFIG_BANK_3=0xFFC2 # Bus options (PCI, PCMCIA, EISA, MCA, ISA) # # CONFIG_ARCH_SUPPORTS_MSI is not set -# CONFIG_PCCARD is not set # # Executable file formats @@ -375,83 +343,13 @@ CONFIG_BINFMT_SHARED_FLAT=y # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM_WAKEUP_BY_GPIO is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_LRO=y -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set +# CONFIG_NET is not set # # Device Drivers @@ -460,21 +358,15 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set # @@ -510,10 +402,9 @@ CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set -# CONFIG_MTD_PSD4256G is not set CONFIG_MTD_CFI_UTIL=y CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=m +# CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # @@ -522,7 +413,7 @@ CONFIG_MTD_ROM=m CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_GPIO_ADDR=y -# CONFIG_MTD_UCLINUX is not set +CONFIG_MTD_UCLINUX=y # CONFIG_MTD_PLATRAM is not set # @@ -544,11 +435,6 @@ CONFIG_MTD_GPIO_ADDR=y # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set -# -# LPDDR flash memory drivers -# -# CONFIG_MTD_LPDDR is not set - # # UBI - Unsorted block images # @@ -557,23 +443,15 @@ CONFIG_MTD_GPIO_ADDR=y CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set -# CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -586,74 +464,6 @@ CONFIG_HAVE_IDE=y # CONFIG_SCSI_NETLINK is not set # CONFIG_ATA is not set # CONFIG_MD is not set -CONFIG_NETDEVICES=y -CONFIG_COMPAT_NET_DEV_OPS=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -CONFIG_BFIN_MAC=y -CONFIG_BFIN_MAC_USE_L1=y -CONFIG_BFIN_TX_DESC_NUM=10 -CONFIG_BFIN_RX_DESC_NUM=20 -# CONFIG_BFIN_MAC_RMII is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMSC911X is not set -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set # CONFIG_PHONE is not set # @@ -670,12 +480,15 @@ CONFIG_BFIN_RX_DESC_NUM=20 # # Character devices # -CONFIG_BFIN_DMA_INTERFACE=m -# CONFIG_BFIN_PPI is not set -# CONFIG_BFIN_PPIFCD is not set +# CONFIG_AD9960 is not set +# CONFIG_SPI_ADC_BF533 is not set +# CONFIG_BF5xx_PPIFCD is not set # CONFIG_BFIN_SIMPLE_TIMER is not set -# CONFIG_BFIN_SPI_ADC is not set +# CONFIG_BF5xx_PPI is not set CONFIG_BFIN_SPORT=y +# CONFIG_BFIN_TIMER_LATENCY is not set +CONFIG_BFIN_DMA_INTERFACE=m +# CONFIG_SIMPLE_GPIO is not set # CONFIG_VT is not set # CONFIG_DEVKMEM is not set # CONFIG_BFIN_JTAG_COMM is not set @@ -689,7 +502,6 @@ CONFIG_BFIN_SPORT=y # # Non-8250 serial port support # -# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_BFIN=y CONFIG_SERIAL_BFIN_CONSOLE=y CONFIG_SERIAL_BFIN_DMA=y @@ -702,7 +514,6 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_BFIN_SPORT is not set CONFIG_UNIX98_PTYS=y -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set # @@ -723,17 +534,39 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_BFIN=y # CONFIG_SPI_BFIN_LOCK is not set -# CONFIG_SPI_BFIN_SPORT is not set # CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_GPIO is not set # # SPI Protocol Masters # +# CONFIG_EEPROM_AT25 is not set # CONFIG_SPI_SPIDEV is not set # CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -# CONFIG_GPIOLIB is not set +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set @@ -747,12 +580,6 @@ CONFIG_WATCHDOG=y # # CONFIG_SOFT_WATCHDOG is not set CONFIG_BFIN_WDT=y -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set # # Multifunction device drivers @@ -761,7 +588,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set -# CONFIG_REGULATOR is not set +# CONFIG_MFD_WM8400 is not set # # Multimedia devices @@ -771,7 +598,6 @@ CONFIG_SSB_POSSIBLE=y # Multimedia core support # # CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set # CONFIG_VIDEO_MEDIA is not set # @@ -792,81 +618,13 @@ CONFIG_SSB_POSSIBLE=y # # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB_ARCH_HAS_EHCI is not set -# CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_GADGET_MUSB_HDRC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_SELECTED=y -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_ATMEL_USBA is not set -# CONFIG_USB_GADGET_FSL_USB2 is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_PXA25X is not set -# CONFIG_USB_GADGET_PXA27X is not set -# CONFIG_USB_GADGET_S3C2410 is not set -# CONFIG_USB_GADGET_IMX is not set -# CONFIG_USB_GADGET_M66592 is not set -# CONFIG_USB_GADGET_AMD5536UDC is not set -# CONFIG_USB_GADGET_FSL_QE is not set -# CONFIG_USB_GADGET_CI13XXX is not set -CONFIG_USB_GADGET_NET2272=y -CONFIG_USB_NET2272=y -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -CONFIG_USB_GADGET_DUALSPEED=y -# CONFIG_USB_ZERO is not set -# CONFIG_USB_AUDIO is not set -CONFIG_USB_ETH=y -CONFIG_USB_ETH_RNDIS=y -# CONFIG_USB_GADGETFS is not set -# CONFIG_USB_FILE_STORAGE is not set -# CONFIG_USB_G_SERIAL is not set -# CONFIG_USB_MIDI_GADGET is not set -# CONFIG_USB_G_PRINTER is not set -# CONFIG_USB_CDC_COMPOSITE is not set - -# -# OTG and related infrastructure -# -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_UNSAFE_RESUME is not set - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_BOUNCE=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_SDHCI is not set -CONFIG_MMC_SPI=m +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set -# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -883,10 +641,8 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set -# CONFIG_XFS_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set # CONFIG_DNOTIFY is not set CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -895,11 +651,6 @@ CONFIG_INOTIFY_USER=y # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -# -# Caches -# -# CONFIG_FSCACHE is not set - # # CD-ROM/DVD Filesystems # @@ -909,11 +660,8 @@ CONFIG_INOTIFY_USER=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -925,7 +673,10 @@ CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -CONFIG_MISC_FILESYSTEMS=y + +# +# Miscellaneous filesystems +# # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set @@ -933,19 +684,9 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -# CONFIG_JFFS2_SUMMARY is not set -# CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -# CONFIG_JFFS2_LZO is not set -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set +# CONFIG_YAFFS_FS is not set +# CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set @@ -954,62 +695,13 @@ CONFIG_JFFS2_RTIME=y # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set -# CONFIG_NILFS2_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -# CONFIG_NFS_FS is not set -# CONFIG_NFSD is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set -# CONFIG_DLM is not set +# CONFIG_NLS is not set # # Kernel hacking @@ -1022,30 +714,12 @@ CONFIG_FRAME_WARN=1024 # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set -CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_TRACING_SUPPORT=y - -# -# Tracers -# -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set -# CONFIG_EVENT_TRACER is not set -# CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_KMEMTRACE is not set -# CONFIG_WORKQUEUE_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_DEBUG_VERBOSE=y @@ -1059,10 +733,9 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0 # CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set -CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK is not set CONFIG_CPLB_INFO=y CONFIG_ACCESS_CHECK=y -# CONFIG_BFIN_ISRAM_SELF_TEST is not set # # Security options @@ -1071,110 +744,20 @@ CONFIG_ACCESS_CHECK=y # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -# CONFIG_CRYPTO_FIPS is not set -# CONFIG_CRYPTO_MANAGER is not set -# CONFIG_CRYPTO_MANAGER2 is not set -# CONFIG_CRYPTO_GF128MUL is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -# CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set -# CONFIG_CRYPTO_GCM is not set -# CONFIG_CRYPTO_SEQIV is not set - -# -# Block modes -# -# CONFIG_CRYPTO_CBC is not set -# CONFIG_CRYPTO_CTR is not set -# CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set - -# -# Hash modes -# -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_HW=y -# CONFIG_BINARY_PRINTF is not set +# CONFIG_CRYPTO is not set # # Library routines # -CONFIG_BITREVERSE=y -CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -CONFIG_CRC7=y +# CONFIG_CRC_ITU_T is not set +# CONFIG_CRC32 is not set +# CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_DECOMPRESS_LZMA=y +CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/trunk/arch/blackfin/include/asm/bfin-global.h b/trunk/arch/blackfin/include/asm/bfin-global.h index e6485c305ea6..10064f902d20 100644 --- a/trunk/arch/blackfin/include/asm/bfin-global.h +++ b/trunk/arch/blackfin/include/asm/bfin-global.h @@ -11,6 +11,9 @@ #ifndef __ASSEMBLY__ +#include +#include +#include #include #include @@ -20,12 +23,6 @@ # define DMA_UNCACHED_REGION (2 * 1024 * 1024) #elif defined(CONFIG_DMA_UNCACHED_1M) # define DMA_UNCACHED_REGION (1024 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_512K) -# define DMA_UNCACHED_REGION (512 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_256K) -# define DMA_UNCACHED_REGION (256 * 1024) -#elif defined(CONFIG_DMA_UNCACHED_128K) -# define DMA_UNCACHED_REGION (128 * 1024) #else # define DMA_UNCACHED_REGION (0) #endif @@ -38,7 +35,6 @@ extern unsigned long get_sclk(void); extern unsigned long sclk_to_usecs(unsigned long sclk); extern unsigned long usecs_to_sclk(unsigned long usecs); -struct pt_regs; extern void dump_bfin_process(struct pt_regs *regs); extern void dump_bfin_mem(struct pt_regs *regs); extern void dump_bfin_trace_buffer(void); diff --git a/trunk/arch/blackfin/include/asm/bfin-lq035q1.h b/trunk/arch/blackfin/include/asm/bfin-lq035q1.h deleted file mode 100644 index 57bc21ac2296..000000000000 --- a/trunk/arch/blackfin/include/asm/bfin-lq035q1.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02 - * - * Copyright 2008-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -#ifndef BFIN_LQ035Q1_H -#define BFIN_LQ035Q1_H - -#define LQ035_RL (0 << 8) /* Right -> Left Scan */ -#define LQ035_LR (1 << 8) /* Left -> Right Scan */ -#define LQ035_TB (1 << 9) /* Top -> Botton Scan */ -#define LQ035_BT (0 << 9) /* Botton -> Top Scan */ -#define LQ035_BGR (1 << 11) /* Use BGR format */ -#define LQ035_RGB (0 << 11) /* Use RGB format */ -#define LQ035_NORM (1 << 13) /* Reversal */ -#define LQ035_REV (0 << 13) /* Reversal */ - -struct bfin_lq035q1fb_disp_info { - - unsigned mode; - /* GPIOs */ - int use_bl; - unsigned gpio_bl; -}; - -#endif /* BFIN_LQ035Q1_H */ diff --git a/trunk/arch/blackfin/include/asm/bug.h b/trunk/arch/blackfin/include/asm/bug.h index 75f6dc336d46..6f4548a13555 100644 --- a/trunk/arch/blackfin/include/asm/bug.h +++ b/trunk/arch/blackfin/include/asm/bug.h @@ -47,7 +47,7 @@ #define BUG() \ do { \ _BUG_OR_WARN(0); \ - unreachable(); \ + for (;;); \ } while (0) #define WARN_ON(condition) \ diff --git a/trunk/arch/blackfin/include/asm/cacheflush.h b/trunk/arch/blackfin/include/asm/cacheflush.h index 2666ff8ea952..417eaac7fe99 100644 --- a/trunk/arch/blackfin/include/asm/cacheflush.h +++ b/trunk/arch/blackfin/include/asm/cacheflush.h @@ -10,7 +10,6 @@ #define _BLACKFIN_CACHEFLUSH_H #include /* for SSYNC() */ -#include /* for _ramend */ extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address); extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address); diff --git a/trunk/arch/blackfin/include/asm/checksum.h b/trunk/arch/blackfin/include/asm/checksum.h index 623cc7fb00bc..a23415be0de1 100644 --- a/trunk/arch/blackfin/include/asm/checksum.h +++ b/trunk/arch/blackfin/include/asm/checksum.h @@ -8,13 +8,64 @@ #ifndef _BFIN_CHECKSUM_H #define _BFIN_CHECKSUM_H +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +__wsum csum_partial(const void *buff, int len, __wsum sum); + +/* + * the same as csum_partial, but copies from src while it + * checksums + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +__wsum csum_partial_copy(const void *src, void *dst, + int len, __wsum sum); + +/* + * the same as csum_partial_copy, but copies from user space. + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, int *csum_err); + +#define csum_partial_copy_nocheck(src, dst, len, sum) \ + csum_partial_copy((src), (dst), (len), (sum)) + +__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl); + +/* + * Fold a partial checksum + */ + +static inline __sum16 csum_fold(__wsum sum) +{ + while (sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + return ((~(sum << 16)) >> 16); +} + /* * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ static inline __wsum -__csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, unsigned short proto, __wsum sum) { unsigned int carry; @@ -37,8 +88,19 @@ __csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, return (sum); } -#define csum_tcpudp_nofold __csum_tcpudp_nofold -#include +static inline __sum16 +csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum)); +} + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ + +extern __sum16 ip_compute_csum(const void *buff, int len); -#endif +#endif /* _BFIN_CHECKSUM_H */ diff --git a/trunk/arch/blackfin/include/asm/clocks.h b/trunk/arch/blackfin/include/asm/clocks.h index 6f0b61852f58..f80dad5ff257 100644 --- a/trunk/arch/blackfin/include/asm/clocks.h +++ b/trunk/arch/blackfin/include/asm/clocks.h @@ -9,8 +9,6 @@ #ifndef _BFIN_CLOCKS_H #define _BFIN_CLOCKS_H -#include - #ifdef CONFIG_CCLK_DIV_1 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1 # define CONFIG_CCLK_DIV 1 diff --git a/trunk/arch/blackfin/include/asm/dma-mapping.h b/trunk/arch/blackfin/include/asm/dma-mapping.h index f9172ff30e5c..7a23d824ac96 100644 --- a/trunk/arch/blackfin/include/asm/dma-mapping.h +++ b/trunk/arch/blackfin/include/asm/dma-mapping.h @@ -7,9 +7,9 @@ #ifndef _BLACKFIN_DMA_MAPPING_H #define _BLACKFIN_DMA_MAPPING_H -#include -struct scatterlist; +#include +void dma_alloc_init(unsigned long start, unsigned long end); void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t gfp); void dma_free_coherent(struct device *dev, size_t size, void *vaddr, @@ -20,51 +20,13 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr, */ #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) -#define dma_supported(d, m) (1) -#define dma_get_cache_alignment() (32) -#define dma_is_consistent(d, h) (1) -static inline int -dma_set_mask(struct device *dev, u64 dma_mask) +static inline +int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) { - if (!dev->dma_mask || !dma_supported(dev, dma_mask)) - return -EIO; - - *dev->dma_mask = dma_mask; - return 0; } -static inline int -dma_mapping_error(struct device *dev, dma_addr_t dma_addr) -{ - return 0; -} - -extern void -__dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir); -static inline void -_dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir) -{ - if (!__builtin_constant_p(dir)) { - __dma_sync(addr, size, dir); - return; - } - - switch (dir) { - case DMA_NONE: - BUG(); - case DMA_TO_DEVICE: /* writeback only */ - flush_dcache_range(addr, addr + size); - break; - case DMA_FROM_DEVICE: /* invalidate only */ - case DMA_BIDIRECTIONAL: /* flush and invalidate */ - /* Blackfin has no dedicated invalidate (it includes a flush) */ - invalidate_dcache_range(addr, addr + size); - break; - } -} - /* * Map a single buffer of the indicated size for DMA in streaming mode. * The 32-bit bus address to use is returned. @@ -72,13 +34,8 @@ _dma_sync(dma_addr_t addr, size_t size, enum dma_data_direction dir) * Once the device is given the dma address, the device owns this memory * until either pci_unmap_single or pci_dma_sync_single is performed. */ -static inline dma_addr_t -dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction dir) -{ - _dma_sync((dma_addr_t)ptr, size, dir); - return (dma_addr_t) ptr; -} +extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction); static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, @@ -96,12 +53,8 @@ dma_map_page(struct device *dev, struct page *page, * After this call, reads by the cpu to the buffer are guarenteed to see * whatever the device wrote there. */ -static inline void -dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction dir) -{ - BUG_ON(!valid_dma_direction(dir)); -} +extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction); static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, @@ -127,66 +80,38 @@ dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, * the same here. */ extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir); + enum dma_data_direction direction); /* * Unmap a set of streaming mode DMA translations. * Again, cpu read rules concerning calls here are the same as for * pci_unmap_single() above. */ -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, - int nhwentries, enum dma_data_direction dir) -{ - BUG_ON(!valid_dma_direction(dir)); -} +extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, enum dma_data_direction direction); -static inline void -dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t handle, - unsigned long offset, size_t size, - enum dma_data_direction dir) +static inline void dma_sync_single_for_cpu(struct device *dev, + dma_addr_t handle, size_t size, + enum dma_data_direction dir) { - BUG_ON(!valid_dma_direction(dir)); } -static inline void -dma_sync_single_range_for_device(struct device *dev, dma_addr_t handle, - unsigned long offset, size_t size, - enum dma_data_direction dir) +static inline void dma_sync_single_for_device(struct device *dev, + dma_addr_t handle, size_t size, + enum dma_data_direction dir) { - _dma_sync(handle + offset, size, dir); } -static inline void -dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, - enum dma_data_direction dir) +static inline void dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, + int nents, enum dma_data_direction dir) { - dma_sync_single_range_for_cpu(dev, handle, 0, size, dir); } -static inline void -dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, - enum dma_data_direction dir) -{ - dma_sync_single_range_for_device(dev, handle, 0, size, dir); -} - -static inline void -dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir) -{ - BUG_ON(!valid_dma_direction(dir)); -} - -extern void -dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, - int nents, enum dma_data_direction dir); - -static inline void -dma_cache_sync(struct device *dev, void *vaddr, size_t size, - enum dma_data_direction dir) +static inline void dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, + int nents, enum dma_data_direction dir) { - _dma_sync((dma_addr_t)vaddr, size, dir); } #endif /* _BLACKFIN_DMA_MAPPING_H */ diff --git a/trunk/arch/blackfin/include/asm/dma.h b/trunk/arch/blackfin/include/asm/dma.h index bd2e62243abe..c9a59622e23f 100644 --- a/trunk/arch/blackfin/include/asm/dma.h +++ b/trunk/arch/blackfin/include/asm/dma.h @@ -10,70 +10,46 @@ #include #include -#include #include #include -#include - -/* DMA_CONFIG Masks */ -#define DMAEN 0x0001 /* DMA Channel Enable */ -#define WNR 0x0002 /* Channel Direction (W/R*) */ -#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ -#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ -#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ -#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ -#define RESTART 0x0020 /* DMA Buffer Clear */ -#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ -#define DI_EN 0x0080 /* Data Interrupt Enable */ -#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ -#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ -#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ -#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ -#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ -#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ -#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ -#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ -#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ -#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ -#define NDSIZE 0x0f00 /* Next Descriptor Size */ -#define DMAFLOW 0x7000 /* Flow Control */ -#define DMAFLOW_STOP 0x0000 /* Stop Mode */ -#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ -#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ -#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ -#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ - -/* DMA_IRQ_STATUS Masks */ -#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ -#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ -#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ -#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + +#define MAX_DMA_ADDRESS PAGE_OFFSET + +/***************************************************************************** +* Generic DMA Declarations +* +****************************************************************************/ +enum dma_chan_status { + DMA_CHANNEL_FREE, + DMA_CHANNEL_REQUESTED, + DMA_CHANNEL_ENABLED, +}; /*------------------------- * config reg bits value *-------------------------*/ -#define DATA_SIZE_8 0 -#define DATA_SIZE_16 1 -#define DATA_SIZE_32 2 +#define DATA_SIZE_8 0 +#define DATA_SIZE_16 1 +#define DATA_SIZE_32 2 -#define DMA_FLOW_STOP 0 -#define DMA_FLOW_AUTO 1 -#define DMA_FLOW_ARRAY 4 -#define DMA_FLOW_SMALL 6 -#define DMA_FLOW_LARGE 7 +#define DMA_FLOW_STOP 0 +#define DMA_FLOW_AUTO 1 +#define DMA_FLOW_ARRAY 4 +#define DMA_FLOW_SMALL 6 +#define DMA_FLOW_LARGE 7 -#define DIMENSION_LINEAR 0 -#define DIMENSION_2D 1 +#define DIMENSION_LINEAR 0 +#define DIMENSION_2D 1 -#define DIR_READ 0 -#define DIR_WRITE 1 +#define DIR_READ 0 +#define DIR_WRITE 1 -#define INTR_DISABLE 0 -#define INTR_ON_BUF 2 -#define INTR_ON_ROW 3 +#define INTR_DISABLE 0 +#define INTR_ON_BUF 2 +#define INTR_ON_ROW 3 #define DMA_NOSYNC_KEEP_DMA_BUF 0 -#define DMA_SYNC_RESTART 1 +#define DMA_SYNC_RESTART 1 struct dmasg { void *next_desc_addr; @@ -128,9 +104,11 @@ struct dma_register { }; +struct mutex; struct dma_channel { + struct mutex dmalock; const char *device_id; - atomic_t chan_status; + enum dma_chan_status chan_status; volatile struct dma_register *regs; struct dmasg *sg; /* large mode descriptor */ unsigned int irq; @@ -242,20 +220,27 @@ static inline void set_dma_sg(unsigned int channel, struct dmasg *sg, int ndsize static inline int dma_channel_active(unsigned int channel) { - return atomic_read(&dma_ch[channel].chan_status); + if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) + return 0; + else + return 1; } static inline void disable_dma(unsigned int channel) { dma_ch[channel].regs->cfg &= ~DMAEN; SSYNC(); + dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED; } static inline void enable_dma(unsigned int channel) { dma_ch[channel].regs->curr_x_count = 0; dma_ch[channel].regs->curr_y_count = 0; dma_ch[channel].regs->cfg |= DMAEN; + dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED; } +void free_dma(unsigned int channel); +int request_dma(unsigned int channel, const char *device_id); int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data); static inline void dma_disable_irq(unsigned int channel) diff --git a/trunk/arch/blackfin/include/asm/dpmc.h b/trunk/arch/blackfin/include/asm/dpmc.h index 1597ae5041ee..925e66cb2d49 100644 --- a/trunk/arch/blackfin/include/asm/dpmc.h +++ b/trunk/arch/blackfin/include/asm/dpmc.h @@ -1,7 +1,7 @@ /* * Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver * - * Copyright (C) 2004-2009 Analog Device Inc. + * Copyright (C) 2004-2008 Analog Device Inc. * * Licensed under the GPL-2 */ @@ -9,109 +9,7 @@ #ifndef _BLACKFIN_DPMC_H_ #define _BLACKFIN_DPMC_H_ -/* PLL_CTL Masks */ -#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ -#define PLL_OFF 0x0002 /* PLL Not Powered */ -#define STOPCK 0x0008 /* Core Clock Off */ -#define PDWN 0x0020 /* Enter Deep Sleep Mode */ -#ifdef __ADSPBF539__ -# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */ -# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */ -#else -# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ -# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ -#endif -#define BYPASS 0x0100 /* Bypass the PLL */ -#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ -#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */ -#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ - -/* PLL_DIV Masks */ -#define SSEL 0x000F /* System Select */ -#define CSEL 0x0030 /* Core Select */ -#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ -#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ -#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ -#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ - -#define CCLK_DIV1 CSEL_DIV1 -#define CCLK_DIV2 CSEL_DIV2 -#define CCLK_DIV4 CSEL_DIV4 -#define CCLK_DIV8 CSEL_DIV8 - -#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ -#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ - -/* PLL_STAT Masks */ -#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ -#define FULL_ON 0x0002 /* Processor In Full On Mode */ -#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ -#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ - -#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */ -#define CANWS 0x0800 /* CAN Wake-Up Status */ -#define USBWS 0x2000 /* USB Wake-Up Status */ -#define KPADWS 0x4000 /* Keypad Wake-Up Status */ -#define ROTWS 0x8000 /* Rotary Wake-Up Status */ -#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ - -/* VR_CTL Masks */ -#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ -#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */ -#else -#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ -#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ -#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ -#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ -#endif -#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ - -#define GAIN 0x000C /* Voltage Level Gain */ -#define GAIN_5 0x0000 /* GAIN = 5 */ -#define GAIN_10 0x0004 /* GAIN = 1 */ -#define GAIN_20 0x0008 /* GAIN = 2 */ -#define GAIN_50 0x000C /* GAIN = 5 */ - -#define VLEV 0x00F0 /* Internal Voltage Level */ -#ifdef __ADSPBF52x__ -#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#else -#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ -#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ -#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ -#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ -#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ -#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ -#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ -#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ -#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ -#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ -#endif - -#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ -#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ -#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ -#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */ -#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ -#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ -#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ -#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ -#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ - -#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__) -#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ -#else -#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */ -#endif - +#ifdef __KERNEL__ #ifndef __ASSEMBLY__ void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); @@ -156,5 +54,6 @@ struct bfin_dpmc_platform_data { w[P0 + (x - PLL_CTL)] = R0;\ #endif +#endif /* __KERNEL__ */ #endif /*_BLACKFIN_DPMC_H_*/ diff --git a/trunk/arch/blackfin/include/asm/elf.h b/trunk/arch/blackfin/include/asm/elf.h index 5b50f0ecacf8..8e0764c81eaf 100644 --- a/trunk/arch/blackfin/include/asm/elf.h +++ b/trunk/arch/blackfin/include/asm/elf.h @@ -55,6 +55,7 @@ do { \ _regs->p2 = _dynamic_addr; \ } while(0) +#define USE_ELF_CORE_DUMP #define ELF_FDPIC_CORE_EFLAGS EF_BFIN_FDPIC #define ELF_EXEC_PAGESIZE 4096 diff --git a/trunk/arch/blackfin/include/asm/gpio.h b/trunk/arch/blackfin/include/asm/gpio.h index 539468a05057..5b44d05ca53e 100644 --- a/trunk/arch/blackfin/include/asm/gpio.h +++ b/trunk/arch/blackfin/include/asm/gpio.h @@ -159,11 +159,6 @@ struct gpio_port_t { }; #endif -#ifdef BFIN_SPECIAL_GPIO_BANKS -void bfin_special_gpio_free(unsigned gpio); -int bfin_special_gpio_request(unsigned gpio, const char *label); -#endif - #ifdef CONFIG_PM unsigned int bfin_pm_standby_setup(void); diff --git a/trunk/arch/blackfin/include/asm/gptimers.h b/trunk/arch/blackfin/include/asm/gptimers.h index c722acdda0d3..89f08decb8e0 100644 --- a/trunk/arch/blackfin/include/asm/gptimers.h +++ b/trunk/arch/blackfin/include/asm/gptimers.h @@ -172,25 +172,25 @@ /* The actual gptimer API */ -void set_gptimer_pwidth(unsigned int timer_id, uint32_t width); -uint32_t get_gptimer_pwidth(unsigned int timer_id); -void set_gptimer_period(unsigned int timer_id, uint32_t period); -uint32_t get_gptimer_period(unsigned int timer_id); -uint32_t get_gptimer_count(unsigned int timer_id); -int get_gptimer_intr(unsigned int timer_id); -void clear_gptimer_intr(unsigned int timer_id); -int get_gptimer_over(unsigned int timer_id); -void clear_gptimer_over(unsigned int timer_id); -void set_gptimer_config(unsigned int timer_id, uint16_t config); -uint16_t get_gptimer_config(unsigned int timer_id); -int get_gptimer_run(unsigned int timer_id); -void set_gptimer_pulse_hi(unsigned int timer_id); -void clear_gptimer_pulse_hi(unsigned int timer_id); +void set_gptimer_pwidth(int timer_id, uint32_t width); +uint32_t get_gptimer_pwidth(int timer_id); +void set_gptimer_period(int timer_id, uint32_t period); +uint32_t get_gptimer_period(int timer_id); +uint32_t get_gptimer_count(int timer_id); +int get_gptimer_intr(int timer_id); +void clear_gptimer_intr(int timer_id); +int get_gptimer_over(int timer_id); +void clear_gptimer_over(int timer_id); +void set_gptimer_config(int timer_id, uint16_t config); +uint16_t get_gptimer_config(int timer_id); +int get_gptimer_run(int timer_id); +void set_gptimer_pulse_hi(int timer_id); +void clear_gptimer_pulse_hi(int timer_id); void enable_gptimers(uint16_t mask); void disable_gptimers(uint16_t mask); void disable_gptimers_sync(uint16_t mask); uint16_t get_enabled_gptimers(void); -uint32_t get_gptimer_status(unsigned int group); -void set_gptimer_status(unsigned int group, uint32_t value); +uint32_t get_gptimer_status(int group); +void set_gptimer_status(int group, uint32_t value); #endif diff --git a/trunk/arch/blackfin/include/asm/io.h b/trunk/arch/blackfin/include/asm/io.h index 29e55b9d88bc..d1f5029189a7 100644 --- a/trunk/arch/blackfin/include/asm/io.h +++ b/trunk/arch/blackfin/include/asm/io.h @@ -31,14 +31,12 @@ static inline unsigned char readb(const volatile void __iomem *addr) unsigned int val; int tmp; - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = b [%2] (z);" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); + __asm__ __volatile__ ("cli %1;\n\t" + "NOP; NOP; SSYNC;\n\t" + "%0 = b [%2] (z);\n\t" + "sti %1;\n\t" + : "=d"(val), "=d"(tmp): "a"(addr) + ); return (unsigned char) val; } @@ -48,14 +46,12 @@ static inline unsigned short readw(const volatile void __iomem *addr) unsigned int val; int tmp; - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = w [%2] (z);" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); + __asm__ __volatile__ ("cli %1;\n\t" + "NOP; NOP; SSYNC;\n\t" + "%0 = w [%2] (z);\n\t" + "sti %1;\n\t" + : "=d"(val), "=d"(tmp): "a"(addr) + ); return (unsigned short) val; } @@ -65,23 +61,20 @@ static inline unsigned int readl(const volatile void __iomem *addr) unsigned int val; int tmp; - __asm__ __volatile__ ( - "cli %1;" - "NOP; NOP; SSYNC;" - "%0 = [%2];" - "sti %1;" - : "=d"(val), "=d"(tmp) - : "a"(addr) - ); - + __asm__ __volatile__ ("cli %1;\n\t" + "NOP; NOP; SSYNC;\n\t" + "%0 = [%2];\n\t" + "sti %1;\n\t" + : "=d"(val), "=d"(tmp): "a"(addr) + ); return val; } #endif /* __ASSEMBLY__ */ -#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) +#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) #define __raw_readb readb #define __raw_readw readw @@ -89,9 +82,9 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel -#define memset_io(a, b, c) memset((void *)(a), (b), (c)) -#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) -#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) /* Convert "I/O port addresses" to actual addresses. i.e. ugly casts. */ #define __io(port) ((void *)(unsigned long)(port)) @@ -99,30 +92,30 @@ static inline unsigned int readl(const volatile void __iomem *addr) #define inb(port) readb(__io(port)) #define inw(port) readw(__io(port)) #define inl(port) readl(__io(port)) -#define outb(x, port) writeb(x, __io(port)) -#define outw(x, port) writew(x, __io(port)) -#define outl(x, port) writel(x, __io(port)) +#define outb(x,port) writeb(x,__io(port)) +#define outw(x,port) writew(x,__io(port)) +#define outl(x,port) writel(x,__io(port)) #define inb_p(port) inb(__io(port)) #define inw_p(port) inw(__io(port)) #define inl_p(port) inl(__io(port)) -#define outb_p(x, port) outb(x, __io(port)) -#define outw_p(x, port) outw(x, __io(port)) -#define outl_p(x, port) outl(x, __io(port)) - -#define ioread8_rep(a, d, c) readsb(a, d, c) -#define ioread16_rep(a, d, c) readsw(a, d, c) -#define ioread32_rep(a, d, c) readsl(a, d, c) -#define iowrite8_rep(a, s, c) writesb(a, s, c) -#define iowrite16_rep(a, s, c) writesw(a, s, c) -#define iowrite32_rep(a, s, c) writesl(a, s, c) - -#define ioread8(x) readb(x) -#define ioread16(x) readw(x) -#define ioread32(x) readl(x) -#define iowrite8(val, x) writeb(val, x) -#define iowrite16(val, x) writew(val, x) -#define iowrite32(val, x) writel(val, x) +#define outb_p(x,port) outb(x,__io(port)) +#define outw_p(x,port) outw(x,__io(port)) +#define outl_p(x,port) outl(x,__io(port)) + +#define ioread8_rep(a,d,c) readsb(a,d,c) +#define ioread16_rep(a,d,c) readsw(a,d,c) +#define ioread32_rep(a,d,c) readsl(a,d,c) +#define iowrite8_rep(a,s,c) writesb(a,s,c) +#define iowrite16_rep(a,s,c) writesw(a,s,c) +#define iowrite32_rep(a,s,c) writesl(a,s,c) + +#define ioread8(X) readb(X) +#define ioread16(X) readw(X) +#define ioread32(X) readl(X) +#define iowrite8(val,X) writeb(val,X) +#define iowrite16(val,X) writew(val,X) +#define iowrite32(val,X) writel(val,X) #define mmiowb() wmb() diff --git a/trunk/arch/blackfin/include/asm/ipipe.h b/trunk/arch/blackfin/include/asm/ipipe.h index d3b40449ca0e..4617ba66278f 100644 --- a/trunk/arch/blackfin/include/asm/ipipe.h +++ b/trunk/arch/blackfin/include/asm/ipipe.h @@ -35,9 +35,9 @@ #include #include -#define IPIPE_ARCH_STRING "1.12-00" +#define IPIPE_ARCH_STRING "1.11-00" #define IPIPE_MAJOR_NUMBER 1 -#define IPIPE_MINOR_NUMBER 12 +#define IPIPE_MINOR_NUMBER 11 #define IPIPE_PATCH_NUMBER 0 #ifdef CONFIG_SMP @@ -124,6 +124,16 @@ static inline int __ipipe_check_tickdev(const char *devname) return 1; } +static inline void __ipipe_lock_root(void) +{ + set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)); +} + +static inline void __ipipe_unlock_root(void) +{ + clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)); +} + void __ipipe_enable_pipeline(void); #define __ipipe_hook_critical_ipi(ipd) do { } while (0) diff --git a/trunk/arch/blackfin/include/asm/ipipe_base.h b/trunk/arch/blackfin/include/asm/ipipe_base.h index 00409201d9ed..490098f532a7 100644 --- a/trunk/arch/blackfin/include/asm/ipipe_base.h +++ b/trunk/arch/blackfin/include/asm/ipipe_base.h @@ -51,15 +51,23 @@ extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ -void __ipipe_stall_root(void); - -unsigned long __ipipe_test_and_stall_root(void); - -unsigned long __ipipe_test_root(void); - -void __ipipe_lock_root(void); - -void __ipipe_unlock_root(void); +#define __ipipe_stall_root() \ + do { \ + volatile unsigned long *p = &__ipipe_root_status; \ + set_bit(0, p); \ + } while (0) + +#define __ipipe_test_and_stall_root() \ + ({ \ + volatile unsigned long *p = &__ipipe_root_status; \ + test_and_set_bit(0, p); \ + }) + +#define __ipipe_test_root() \ + ({ \ + const unsigned long *p = &__ipipe_root_status; \ + test_bit(0, p); \ + }) #endif /* !__ASSEMBLY__ */ diff --git a/trunk/arch/blackfin/include/asm/irqflags.h b/trunk/arch/blackfin/include/asm/irqflags.h index 813a1af3e865..9b19a19d9ae9 100644 --- a/trunk/arch/blackfin/include/asm/irqflags.h +++ b/trunk/arch/blackfin/include/asm/irqflags.h @@ -33,7 +33,6 @@ static inline unsigned long bfin_cli(void) #ifdef CONFIG_IPIPE -#include #include #include @@ -50,12 +49,12 @@ static inline unsigned long bfin_cli(void) barrier(); \ } while (0) -#define raw_local_irq_enable() \ - do { \ - barrier(); \ - ipipe_check_context(ipipe_root_domain); \ - __ipipe_unstall_root(); \ - } while (0) +static inline void raw_local_irq_enable(void) +{ + barrier(); + ipipe_check_context(ipipe_root_domain); + __ipipe_unstall_root(); +} #define raw_local_save_flags_ptr(x) \ do { \ diff --git a/trunk/arch/blackfin/include/asm/kgdb.h b/trunk/arch/blackfin/include/asm/kgdb.h index 8651afe12990..c8b256d2ea30 100644 --- a/trunk/arch/blackfin/include/asm/kgdb.h +++ b/trunk/arch/blackfin/include/asm/kgdb.h @@ -10,6 +10,9 @@ #include +/* gdb locks */ +#define KGDB_MAX_NO_CPUS 8 + /* * BUFMAX defines the maximum number of characters in inbound/outbound buffers. * At least NUMREGBYTES*2 are needed for register packets. diff --git a/trunk/arch/blackfin/include/asm/mem_init.h b/trunk/arch/blackfin/include/asm/mem_init.h index 7c8fe834ff22..4179e329b9c9 100644 --- a/trunk/arch/blackfin/include/asm/mem_init.h +++ b/trunk/arch/blackfin/include/asm/mem_init.h @@ -295,3 +295,156 @@ #else #define PLL_BYPASS 0 #endif + +/***************************************Currently Not Being Used *********************************/ + +#if defined(CONFIG_FLASH_SPEED_BWAT) && \ +defined(CONFIG_FLASH_SPEED_BRAT) && \ +defined(CONFIG_FLASH_SPEED_BHT) && \ +defined(CONFIG_FLASH_SPEED_BST) && \ +defined(CONFIG_FLASH_SPEED_BTT) + +#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) +#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 +#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 + +#if (flash_EBIU_AMBCTL_TT > 3) +#define flash_EBIU_AMBCTL0_TT B0TT_4 +#endif +#if (flash_EBIU_AMBCTL_TT == 3) +#define flash_EBIU_AMBCTL0_TT B0TT_3 +#endif +#if (flash_EBIU_AMBCTL_TT == 2) +#define flash_EBIU_AMBCTL0_TT B0TT_2 +#endif +#if (flash_EBIU_AMBCTL_TT < 2) +#define flash_EBIU_AMBCTL0_TT B0TT_1 +#endif + +#if (flash_EBIU_AMBCTL_ST > 3) +#define flash_EBIU_AMBCTL0_ST B0ST_4 +#endif +#if (flash_EBIU_AMBCTL_ST == 3) +#define flash_EBIU_AMBCTL0_ST B0ST_3 +#endif +#if (flash_EBIU_AMBCTL_ST == 2) +#define flash_EBIU_AMBCTL0_ST B0ST_2 +#endif +#if (flash_EBIU_AMBCTL_ST < 2) +#define flash_EBIU_AMBCTL0_ST B0ST_1 +#endif + +#if (flash_EBIU_AMBCTL_HT > 2) +#define flash_EBIU_AMBCTL0_HT B0HT_3 +#endif +#if (flash_EBIU_AMBCTL_HT == 2) +#define flash_EBIU_AMBCTL0_HT B0HT_2 +#endif +#if (flash_EBIU_AMBCTL_HT == 1) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0) +#define flash_EBIU_AMBCTL0_HT B0HT_0 +#endif +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0) +#define flash_EBIU_AMBCTL0_HT B0HT_1 +#endif + +#if (flash_EBIU_AMBCTL_WAT > 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_15 +#endif +#if (flash_EBIU_AMBCTL_WAT == 14) +#define flash_EBIU_AMBCTL0_WAT B0WAT_14 +#endif +#if (flash_EBIU_AMBCTL_WAT == 13) +#define flash_EBIU_AMBCTL0_WAT B0WAT_13 +#endif +#if (flash_EBIU_AMBCTL_WAT == 12) +#define flash_EBIU_AMBCTL0_WAT B0WAT_12 +#endif +#if (flash_EBIU_AMBCTL_WAT == 11) +#define flash_EBIU_AMBCTL0_WAT B0WAT_11 +#endif +#if (flash_EBIU_AMBCTL_WAT == 10) +#define flash_EBIU_AMBCTL0_WAT B0WAT_10 +#endif +#if (flash_EBIU_AMBCTL_WAT == 9) +#define flash_EBIU_AMBCTL0_WAT B0WAT_9 +#endif +#if (flash_EBIU_AMBCTL_WAT == 8) +#define flash_EBIU_AMBCTL0_WAT B0WAT_8 +#endif +#if (flash_EBIU_AMBCTL_WAT == 7) +#define flash_EBIU_AMBCTL0_WAT B0WAT_7 +#endif +#if (flash_EBIU_AMBCTL_WAT == 6) +#define flash_EBIU_AMBCTL0_WAT B0WAT_6 +#endif +#if (flash_EBIU_AMBCTL_WAT == 5) +#define flash_EBIU_AMBCTL0_WAT B0WAT_5 +#endif +#if (flash_EBIU_AMBCTL_WAT == 4) +#define flash_EBIU_AMBCTL0_WAT B0WAT_4 +#endif +#if (flash_EBIU_AMBCTL_WAT == 3) +#define flash_EBIU_AMBCTL0_WAT B0WAT_3 +#endif +#if (flash_EBIU_AMBCTL_WAT == 2) +#define flash_EBIU_AMBCTL0_WAT B0WAT_2 +#endif +#if (flash_EBIU_AMBCTL_WAT == 1) +#define flash_EBIU_AMBCTL0_WAT B0WAT_1 +#endif + +#if (flash_EBIU_AMBCTL_RAT > 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_15 +#endif +#if (flash_EBIU_AMBCTL_RAT == 14) +#define flash_EBIU_AMBCTL0_RAT B0RAT_14 +#endif +#if (flash_EBIU_AMBCTL_RAT == 13) +#define flash_EBIU_AMBCTL0_RAT B0RAT_13 +#endif +#if (flash_EBIU_AMBCTL_RAT == 12) +#define flash_EBIU_AMBCTL0_RAT B0RAT_12 +#endif +#if (flash_EBIU_AMBCTL_RAT == 11) +#define flash_EBIU_AMBCTL0_RAT B0RAT_11 +#endif +#if (flash_EBIU_AMBCTL_RAT == 10) +#define flash_EBIU_AMBCTL0_RAT B0RAT_10 +#endif +#if (flash_EBIU_AMBCTL_RAT == 9) +#define flash_EBIU_AMBCTL0_RAT B0RAT_9 +#endif +#if (flash_EBIU_AMBCTL_RAT == 8) +#define flash_EBIU_AMBCTL0_RAT B0RAT_8 +#endif +#if (flash_EBIU_AMBCTL_RAT == 7) +#define flash_EBIU_AMBCTL0_RAT B0RAT_7 +#endif +#if (flash_EBIU_AMBCTL_RAT == 6) +#define flash_EBIU_AMBCTL0_RAT B0RAT_6 +#endif +#if (flash_EBIU_AMBCTL_RAT == 5) +#define flash_EBIU_AMBCTL0_RAT B0RAT_5 +#endif +#if (flash_EBIU_AMBCTL_RAT == 4) +#define flash_EBIU_AMBCTL0_RAT B0RAT_4 +#endif +#if (flash_EBIU_AMBCTL_RAT == 3) +#define flash_EBIU_AMBCTL0_RAT B0RAT_3 +#endif +#if (flash_EBIU_AMBCTL_RAT == 2) +#define flash_EBIU_AMBCTL0_RAT B0RAT_2 +#endif +#if (flash_EBIU_AMBCTL_RAT == 1) +#define flash_EBIU_AMBCTL0_RAT B0RAT_1 +#endif + +#define flash_EBIU_AMBCTL0 \ + (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ + flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) +#endif diff --git a/trunk/arch/blackfin/include/asm/mmu_context.h b/trunk/arch/blackfin/include/asm/mmu_context.h index ae8ef4ffd806..4a3be376ad5b 100644 --- a/trunk/arch/blackfin/include/asm/mmu_context.h +++ b/trunk/arch/blackfin/include/asm/mmu_context.h @@ -66,8 +66,8 @@ activate_l1stack(struct mm_struct *mm, unsigned long sp_base) #define activate_mm(prev, next) switch_mm(prev, next, NULL) -static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, - struct task_struct *tsk) +static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm, + struct task_struct *tsk) { #ifdef CONFIG_MPU unsigned int cpu = smp_processor_id(); @@ -95,24 +95,7 @@ static inline void __switch_mm(struct mm_struct *prev_mm, struct mm_struct *next #endif } -#ifdef CONFIG_IPIPE -#define lock_mm_switch(flags) local_irq_save_hw_cond(flags) -#define unlock_mm_switch(flags) local_irq_restore_hw_cond(flags) -#else -#define lock_mm_switch(flags) do { (void)(flags); } while (0) -#define unlock_mm_switch(flags) do { (void)(flags); } while (0) -#endif /* CONFIG_IPIPE */ - #ifdef CONFIG_MPU -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - unsigned long flags; - lock_mm_switch(flags); - __switch_mm(prev, next, tsk); - unlock_mm_switch(flags); -} - static inline void protect_page(struct mm_struct *mm, unsigned long addr, unsigned long flags) { @@ -145,12 +128,6 @@ static inline void update_protections(struct mm_struct *mm) set_mask_dcplbs(mm->context.page_rwx_mask, cpu); } } -#else /* !CONFIG_MPU */ -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - __switch_mm(prev, next, tsk); -} #endif static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) @@ -196,10 +173,4 @@ static inline void destroy_context(struct mm_struct *mm) #endif } -#define ipipe_mm_switch_protect(flags) \ - local_irq_save_hw_cond(flags) - -#define ipipe_mm_switch_unprotect(flags) \ - local_irq_restore_hw_cond(flags) - #endif diff --git a/trunk/arch/blackfin/include/asm/module.h b/trunk/arch/blackfin/include/asm/module.h index 4282b169ead9..9c1cfffddd9b 100644 --- a/trunk/arch/blackfin/include/asm/module.h +++ b/trunk/arch/blackfin/include/asm/module.h @@ -7,6 +7,8 @@ #ifndef _ASM_BFIN_MODULE_H #define _ASM_BFIN_MODULE_H +#define MODULE_SYMBOL_PREFIX "_" + #define Elf_Shdr Elf32_Shdr #define Elf_Sym Elf32_Sym #define Elf_Ehdr Elf32_Ehdr diff --git a/trunk/arch/blackfin/include/asm/pci.h b/trunk/arch/blackfin/include/asm/pci.h index 99cae2e3bac7..61277358c865 100644 --- a/trunk/arch/blackfin/include/asm/pci.h +++ b/trunk/arch/blackfin/include/asm/pci.h @@ -4,19 +4,145 @@ #define _ASM_BFIN_PCI_H #include -#include -#include +/* + * + * Written by Wout Klaren. + */ + +/* Added by Chang Junxiao */ #define PCIBIOS_MIN_IO 0x00001000 #define PCIBIOS_MIN_MEM 0x10000000 +#define PCI_DMA_BUS_IS_PHYS (1) +struct pci_ops; + +/* + * Structure with hardware dependent information and functions of the + * PCI bus. + */ +struct pci_bus_info { + + /* + * Resources of the PCI bus. + */ + struct resource mem_space; + struct resource io_space; + + /* + * System dependent functions. + */ + struct pci_ops *bfin_pci_ops; + void (*fixup) (int pci_modify); + void (*conf_device) (unsigned char bus, unsigned char device_fn); +}; + +#define pcibios_assign_all_busses() 0 static inline void pcibios_set_master(struct pci_dev *dev) { + /* No special bus mastering setup handling */ } static inline void pcibios_penalize_isa_irq(int irq) { + /* We don't do dynamic PCI IRQ allocation */ } +static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, + size_t size, int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* return virt_to_bus(ptr); */ + return (dma_addr_t) ptr; +} + +/* Unmap a single streaming mode DMA translation. The dma_addr and size + * must match what was provided for in a previous pci_map_single call. All + * other usages are undefined. + * + * After this call, reads by the cpu to the buffer are guarenteed to see + * whatever the device wrote there. + */ +static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, + size_t size, int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* Nothing to do */ +} + +/* Map a set of buffers described by scatterlist in streaming + * mode for DMA. This is the scather-gather version of the + * above pci_map_single interface. Here the scatter gather list + * elements are each tagged with the appropriate dma address + * and length. They are obtained via sg_dma_{address,length}(SG). + * + * NOTE: An implementation may be able to use a smaller number of + * DMA address/length pairs than there are SG table elements. + * (for example via virtual mapping capabilities) + * The routine returns the number of addr/length pairs actually + * used, at most nents. + * + * Device ownership issues as mentioned above for pci_map_single are + * the same here. + */ +static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + return nents; +} + +/* Unmap a set of streaming mode DMA translations. + * Again, cpu read rules concerning calls here are the same as for + * pci_unmap_single() above. + */ +static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* Nothing to do */ +} + +/* Make physical memory consistent for a single + * streaming mode DMA translation after a transfer. + * + * If you perform a pci_map_single() but wish to interrogate the + * buffer using the cpu, yet do not wish to teardown the PCI dma + * mapping, you must call this function before doing so. At the + * next point you give the PCI dma address back to the card, the + * device again owns the buffer. + */ +static inline void pci_dma_sync_single(struct pci_dev *hwdev, + dma_addr_t dma_handle, size_t size, + int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* Nothing to do */ +} + +/* Make physical memory consistent for a set of streaming + * mode DMA translations after a transfer. + * + * The same as pci_dma_sync_single but for a scatter-gather list, + * same rules and usage. + */ +static inline void pci_dma_sync_sg(struct pci_dev *hwdev, + struct scatterlist *sg, int nelems, + int direction) +{ + if (direction == PCI_DMA_NONE) + BUG(); + + /* Nothing to do */ +} #endif /* _ASM_BFIN_PCI_H */ diff --git a/trunk/arch/blackfin/include/asm/ptrace.h b/trunk/arch/blackfin/include/asm/ptrace.h index b33a4488f498..27290c955a7a 100644 --- a/trunk/arch/blackfin/include/asm/ptrace.h +++ b/trunk/arch/blackfin/include/asm/ptrace.h @@ -89,9 +89,9 @@ struct pt_regs { #define PTRACE_GETREGS 12 #define PTRACE_SETREGS 13 /* ptrace signal */ -#define PTRACE_GETFDPIC 31 /* get the ELF fdpic loadmap address */ -#define PTRACE_GETFDPIC_EXEC 0 /* [addr] request the executable loadmap */ -#define PTRACE_GETFDPIC_INTERP 1 /* [addr] request the interpreter loadmap */ +#define PTRACE_GETFDPIC 31 +#define PTRACE_GETFDPIC_EXEC 0 +#define PTRACE_GETFDPIC_INTERP 1 #define PS_S (0x0002) diff --git a/trunk/arch/blackfin/include/asm/sections.h b/trunk/arch/blackfin/include/asm/sections.h index 42f6c53c59c6..1f5381fbb4a7 100644 --- a/trunk/arch/blackfin/include/asm/sections.h +++ b/trunk/arch/blackfin/include/asm/sections.h @@ -13,18 +13,10 @@ extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size; extern unsigned long _ramstart, _ramend, _rambase; extern unsigned long memory_start, memory_end, physical_mem_end; -/* - * The weak markings on the lengths might seem weird, but this is required - * in order to make gcc accept the fact that these may actually have a value - * of 0 (since they aren't actually addresses, but sizes of sections). - */ -extern char _stext_l1[], _etext_l1[], _text_l1_lma[], __weak _text_l1_len[]; -extern char _sdata_l1[], _edata_l1[], _sbss_l1[], _ebss_l1[], - _data_l1_lma[], __weak _data_l1_len[]; -extern char _sdata_b_l1[], _edata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], - _data_b_l1_lma[], __weak _data_b_l1_len[]; -extern char _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], - _sbss_l2[], _ebss_l2[], _l2_lma[], __weak _l2_len[]; +extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[], + _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _sbss_b_l1[], _ebss_b_l1[], + _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[], + _ebss_l2[], _l2_lma_start[]; #include diff --git a/trunk/arch/blackfin/include/asm/thread_info.h b/trunk/arch/blackfin/include/asm/thread_info.h index a40d9368c38a..afb3a8626380 100644 --- a/trunk/arch/blackfin/include/asm/thread_info.h +++ b/trunk/arch/blackfin/include/asm/thread_info.h @@ -103,13 +103,11 @@ static inline struct thread_info *current_thread_info(void) #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ #define TIF_FREEZE 6 /* is freezing for suspend */ #define TIF_IRQ_SYNC 7 /* sync pipeline stage */ -#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */ /* as above, but as bit values */ #define _TIF_SYSCALL_TRACE (1< #include -#include +#ifdef CONFIG_ACCESS_CHECK +# include +#endif #define get_ds() (KERNEL_DS) #define get_fs() (current_thread_info()->addr_limit) diff --git a/trunk/arch/blackfin/include/asm/unistd.h b/trunk/arch/blackfin/include/asm/unistd.h index 22886cbdae7a..779be02a910a 100644 --- a/trunk/arch/blackfin/include/asm/unistd.h +++ b/trunk/arch/blackfin/include/asm/unistd.h @@ -388,9 +388,8 @@ #define __NR_pwritev 367 #define __NR_rt_tgsigqueueinfo 368 #define __NR_perf_event_open 369 -#define __NR_recvmmsg 370 -#define __NR_syscall 371 +#define __NR_syscall 370 #define NR_syscalls __NR_syscall /* Old optional stuff no one actually uses */ diff --git a/trunk/arch/blackfin/kernel/bfin_dma_5xx.c b/trunk/arch/blackfin/kernel/bfin_dma_5xx.c index 924c00286bab..3946aff4f414 100644 --- a/trunk/arch/blackfin/kernel/bfin_dma_5xx.c +++ b/trunk/arch/blackfin/kernel/bfin_dma_5xx.c @@ -37,8 +37,9 @@ static int __init blackfin_dma_init(void) printk(KERN_INFO "Blackfin DMA Controller\n"); for (i = 0; i < MAX_DMA_CHANNELS; i++) { - atomic_set(&dma_ch[i].chan_status, 0); + dma_ch[i].chan_status = DMA_CHANNEL_FREE; dma_ch[i].regs = dma_io_base_addr[i]; + mutex_init(&(dma_ch[i].dmalock)); } /* Mark MEMDMA Channel 0 as requested since we're using it internally */ request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy"); @@ -59,7 +60,7 @@ static int proc_dma_show(struct seq_file *m, void *v) int i; for (i = 0; i < MAX_DMA_CHANNELS; ++i) - if (dma_channel_active(i)) + if (dma_ch[i].chan_status != DMA_CHANNEL_FREE) seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id); return 0; @@ -106,11 +107,20 @@ int request_dma(unsigned int channel, const char *device_id) } #endif - if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) { + mutex_lock(&(dma_ch[channel].dmalock)); + + if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED) + || (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) { + mutex_unlock(&(dma_ch[channel].dmalock)); pr_debug("DMA CHANNEL IN USE \n"); return -EBUSY; + } else { + dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED; + pr_debug("DMA CHANNEL IS ALLOCATED \n"); } + mutex_unlock(&(dma_ch[channel].dmalock)); + #ifdef CONFIG_BF54x if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) { unsigned int per_map; @@ -138,20 +148,21 @@ EXPORT_SYMBOL(request_dma); int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data) { - int ret; - unsigned int irq; - - BUG_ON(channel >= MAX_DMA_CHANNELS || !callback || - !atomic_read(&dma_ch[channel].chan_status)); + BUG_ON(channel >= MAX_DMA_CHANNELS || + dma_ch[channel].chan_status == DMA_CHANNEL_FREE); - irq = channel2irq(channel); - ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data); - if (ret) - return ret; + if (callback != NULL) { + int ret; + unsigned int irq = channel2irq(channel); - dma_ch[channel].irq = irq; - dma_ch[channel].data = data; + ret = request_irq(irq, callback, IRQF_DISABLED, + dma_ch[channel].device_id, data); + if (ret) + return ret; + dma_ch[channel].irq = irq; + dma_ch[channel].data = data; + } return 0; } EXPORT_SYMBOL(set_dma_callback); @@ -173,7 +184,7 @@ void free_dma(unsigned int channel) { pr_debug("freedma() : BEGIN \n"); BUG_ON(channel >= MAX_DMA_CHANNELS || - !atomic_read(&dma_ch[channel].chan_status)); + dma_ch[channel].chan_status == DMA_CHANNEL_FREE); /* Halt the DMA */ disable_dma(channel); @@ -183,7 +194,9 @@ void free_dma(unsigned int channel) free_irq(dma_ch[channel].irq, dma_ch[channel].data); /* Clear the DMA Variable in the Channel */ - atomic_set(&dma_ch[channel].chan_status, 0); + mutex_lock(&(dma_ch[channel].dmalock)); + dma_ch[channel].chan_status = DMA_CHANNEL_FREE; + mutex_unlock(&(dma_ch[channel].dmalock)); pr_debug("freedma() : END \n"); } @@ -197,14 +210,13 @@ int blackfin_dma_suspend(void) { int i; - for (i = 0; i < MAX_DMA_CHANNELS; ++i) { - if (dma_ch[i].regs->cfg & DMAEN) { + for (i = 0; i < MAX_DMA_SUSPEND_CHANNELS; ++i) { + if (dma_ch[i].chan_status == DMA_CHANNEL_ENABLED) { printk(KERN_ERR "DMA Channel %d failed to suspend\n", i); return -EBUSY; } - if (i < MAX_DMA_SUSPEND_CHANNELS) - dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; + dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map; } return 0; diff --git a/trunk/arch/blackfin/kernel/bfin_gpio.c b/trunk/arch/blackfin/kernel/bfin_gpio.c index a174596cc009..22705eeff34f 100644 --- a/trunk/arch/blackfin/kernel/bfin_gpio.c +++ b/trunk/arch/blackfin/kernel/bfin_gpio.c @@ -100,12 +100,6 @@ u8 pmux_offset[][16] = { }; # endif -#elif defined(BF538_FAMILY) -static unsigned short * const port_fer[] = { - (unsigned short *) PORTCIO_FER, - (unsigned short *) PORTDIO_FER, - (unsigned short *) PORTEIO_FER, -}; #endif static unsigned short reserved_gpio_map[GPIO_BANK_NUM]; @@ -169,27 +163,6 @@ static int cmp_label(unsigned short ident, const char *label) static void port_setup(unsigned gpio, unsigned short usage) { -#if defined(BF538_FAMILY) - /* - * BF538/9 Port C,D and E are special. - * Inverted PORT_FER polarity on CDE and no PORF_FER on F - * Regular PORT F GPIOs are handled here, CDE are exclusively - * managed by GPIOLIB - */ - - if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES) - return; - - gpio -= MAX_BLACKFIN_GPIOS; - - if (usage == GPIO_USAGE) - *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio); - else - *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio); - SSYNC(); - return; -#endif - if (check_gpio(gpio)) return; @@ -789,8 +762,6 @@ int peripheral_request(unsigned short per, const char *label) if (!(per & P_DEFINED)) return -ENODEV; - BUG_ON(ident >= MAX_RESOURCES); - local_irq_save_hw(flags); /* If a pin can be muxed as either GPIO or peripheral, make @@ -1008,76 +979,6 @@ void bfin_gpio_free(unsigned gpio) } EXPORT_SYMBOL(bfin_gpio_free); -#ifdef BFIN_SPECIAL_GPIO_BANKS -static unsigned short reserved_special_gpio_map[gpio_bank(MAX_RESOURCES)]; - -int bfin_special_gpio_request(unsigned gpio, const char *label) -{ - unsigned long flags; - - local_irq_save_hw(flags); - - /* - * Allow that the identical GPIO can - * be requested from the same driver twice - * Do nothing and return - - */ - - if (cmp_label(gpio, label) == 0) { - local_irq_restore_hw(flags); - return 0; - } - - if (unlikely(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) { - local_irq_restore_hw(flags); - printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n", - gpio, get_label(gpio)); - - return -EBUSY; - } - if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) { - local_irq_restore_hw(flags); - printk(KERN_ERR - "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n", - gpio, get_label(gpio)); - - return -EBUSY; - } - - reserved_special_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio); - reserved_peri_map[gpio_bank(gpio)] |= gpio_bit(gpio); - - set_label(gpio, label); - local_irq_restore_hw(flags); - port_setup(gpio, GPIO_USAGE); - - return 0; -} -EXPORT_SYMBOL(bfin_special_gpio_request); - -void bfin_special_gpio_free(unsigned gpio) -{ - unsigned long flags; - - might_sleep(); - - local_irq_save_hw(flags); - - if (unlikely(!(reserved_special_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { - gpio_error(gpio); - local_irq_restore_hw(flags); - return; - } - - reserved_special_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); - reserved_peri_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); - set_label(gpio, "free"); - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(bfin_special_gpio_free); -#endif - - int bfin_gpio_irq_request(unsigned gpio, const char *label) { unsigned long flags; diff --git a/trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c index 8d42b9e50dfa..b52c1f8c4bc0 100644 --- a/trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c +++ b/trunk/arch/blackfin/kernel/cplb-mpu/cplbinit.c @@ -92,6 +92,6 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) icplb_tbl[cpu][i_i++].data = 0; } -void __init generate_cplb_tables_all(void) +void generate_cplb_tables_all(void) { } diff --git a/trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c index 930c01c06813..69e0e530d70f 100644 --- a/trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c +++ b/trunk/arch/blackfin/kernel/cplb-mpu/cplbmgr.c @@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu) addr = L2_START; d_data = L2_DMEMORY; } else if (addr >= physical_mem_end) { - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { - addr &= ~(4 * 1024 * 1024 - 1); + if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE + && (status & FAULT_USERSUPV)) { + addr &= ~0x3fffff; d_data &= ~PAGE_SIZE_4KB; d_data |= PAGE_SIZE_4MB; - d_data |= CPLB_USER_RD | CPLB_USER_WR; } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) { addr &= ~(1 * 1024 * 1024 - 1); @@ -203,12 +203,7 @@ static noinline int icplb_miss(unsigned int cpu) addr = L2_START; i_data = L2_IMEMORY; } else if (addr >= physical_mem_end) { - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { - addr &= ~(4 * 1024 * 1024 - 1); - i_data &= ~PAGE_SIZE_4KB; - i_data |= PAGE_SIZE_4MB; - i_data |= CPLB_USER_RD; - } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH + if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH && (status & FAULT_USERSUPV)) { addr &= ~(1 * 1024 * 1024 - 1); i_data &= ~PAGE_SIZE_4KB; diff --git a/trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 282a7919821b..fd9a2f31e686 100644 --- a/trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/trunk/arch/blackfin/kernel/cplb-nompu/cplbinit.c @@ -89,25 +89,15 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) void __init generate_cplb_tables_all(void) { - unsigned long uncached_end; int i_d, i_i; i_d = 0; /* Normal RAM, including MTD FS. */ #ifdef CONFIG_MTD_UCLINUX - uncached_end = memory_mtd_start + mtd_size; + dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size; #else - uncached_end = memory_end; + dcplb_bounds[i_d].eaddr = memory_end; #endif - /* - * if DMA uncached is less than 1MB, mark the 1MB chunk as uncached - * so that we don't have to use 4kB pages and cause CPLB thrashing - */ - if ((DMA_UNCACHED_REGION >= 1 * 1024 * 1024) || !DMA_UNCACHED_REGION || - ((_ramend - uncached_end) >= 1 * 1024 * 1024)) - dcplb_bounds[i_d].eaddr = uncached_end; - else - dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024); dcplb_bounds[i_d++].data = SDRAM_DGENERIC; /* DMA uncached region. */ if (DMA_UNCACHED_REGION) { @@ -145,15 +135,18 @@ void __init generate_cplb_tables_all(void) i_i = 0; /* Normal RAM, including MTD FS. */ - icplb_bounds[i_i].eaddr = uncached_end; +#ifdef CONFIG_MTD_UCLINUX + icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size; +#else + icplb_bounds[i_i].eaddr = memory_end; +#endif icplb_bounds[i_i++].data = SDRAM_IGENERIC; + /* DMA uncached region. */ + if (DMA_UNCACHED_REGION) { + icplb_bounds[i_i].eaddr = _ramend; + icplb_bounds[i_i++].data = 0; + } if (_ramend != physical_mem_end) { - /* DMA uncached region. */ - if (DMA_UNCACHED_REGION) { - /* Normally this hole is caught by the async below. */ - icplb_bounds[i_i].eaddr = _ramend; - icplb_bounds[i_i++].data = 0; - } /* Reserved memory. */ icplb_bounds[i_i].eaddr = physical_mem_end; icplb_bounds[i_i++].data = (reserved_mem_icache_on ? diff --git a/trunk/arch/blackfin/kernel/dma-mapping.c b/trunk/arch/blackfin/kernel/dma-mapping.c index e937f323d82c..e74e74d7733f 100644 --- a/trunk/arch/blackfin/kernel/dma-mapping.c +++ b/trunk/arch/blackfin/kernel/dma-mapping.c @@ -7,25 +7,30 @@ */ #include -#include +#include #include +#include #include +#include #include +#include #include +#include +#include static spinlock_t dma_page_lock; -static unsigned long *dma_page; +static unsigned int *dma_page; static unsigned int dma_pages; static unsigned long dma_base; static unsigned long dma_size; static unsigned int dma_initialized; -static void dma_alloc_init(unsigned long start, unsigned long end) +void dma_alloc_init(unsigned long start, unsigned long end) { spin_lock_init(&dma_page_lock); dma_initialized = 0; - dma_page = (unsigned long *)__get_free_page(GFP_KERNEL); + dma_page = (unsigned int *)__get_free_page(GFP_KERNEL); memset(dma_page, 0, PAGE_SIZE); dma_base = PAGE_ALIGN(start); dma_size = PAGE_ALIGN(end) - PAGE_ALIGN(start); @@ -53,11 +58,10 @@ static unsigned long __alloc_dma_pages(unsigned int pages) spin_lock_irqsave(&dma_page_lock, flags); for (i = 0; i < dma_pages;) { - if (test_bit(i++, dma_page) == 0) { + if (dma_page[i++] == 0) { if (++count == pages) { while (count--) - __set_bit(--i, dma_page); - + dma_page[--i] = 1; ret = dma_base + (i << PAGE_SHIFT); break; } @@ -80,14 +84,14 @@ static void __free_dma_pages(unsigned long addr, unsigned int pages) } spin_lock_irqsave(&dma_page_lock, flags); - for (i = page; i < page + pages; i++) - __clear_bit(i, dma_page); - + for (i = page; i < page + pages; i++) { + dma_page[i] = 0; + } spin_unlock_irqrestore(&dma_page_lock, flags); } void *dma_alloc_coherent(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t gfp) + dma_addr_t * dma_handle, gfp_t gfp) { void *ret; @@ -111,14 +115,21 @@ dma_free_coherent(struct device *dev, size_t size, void *vaddr, EXPORT_SYMBOL(dma_free_coherent); /* - * Streaming DMA mappings + * Dummy functions defined for some existing drivers */ -void __dma_sync(dma_addr_t addr, size_t size, - enum dma_data_direction dir) + +dma_addr_t +dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction) { - _dma_sync(addr, size, dir); + BUG_ON(direction == DMA_NONE); + + invalidate_dcache_range((unsigned long)ptr, + (unsigned long)ptr + size); + + return (dma_addr_t) ptr; } -EXPORT_SYMBOL(__dma_sync); +EXPORT_SYMBOL(dma_map_single); int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, @@ -126,23 +137,30 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, { int i; + BUG_ON(direction == DMA_NONE); + for (i = 0; i < nents; i++, sg++) { sg->dma_address = (dma_addr_t) sg_virt(sg); - __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); + + invalidate_dcache_range(sg_dma_address(sg), + sg_dma_address(sg) + + sg_dma_len(sg)); } return nents; } EXPORT_SYMBOL(dma_map_sg); -void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, - int nelems, enum dma_data_direction direction) +void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction) { - int i; + BUG_ON(direction == DMA_NONE); +} +EXPORT_SYMBOL(dma_unmap_single); - for (i = 0; i < nelems; i++, sg++) { - sg->dma_address = (dma_addr_t) sg_virt(sg); - __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction); - } +void dma_unmap_sg(struct device *dev, struct scatterlist *sg, + int nhwentries, enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); } -EXPORT_SYMBOL(dma_sync_sg_for_device); +EXPORT_SYMBOL(dma_unmap_sg); diff --git a/trunk/arch/blackfin/kernel/gptimers.c b/trunk/arch/blackfin/kernel/gptimers.c index cdbe075de1dc..7281a91d26b5 100644 --- a/trunk/arch/blackfin/kernel/gptimers.c +++ b/trunk/arch/blackfin/kernel/gptimers.c @@ -137,7 +137,7 @@ static uint32_t const timil_mask[MAX_BLACKFIN_GPTIMERS] = #endif }; -void set_gptimer_pwidth(unsigned int timer_id, uint32_t value) +void set_gptimer_pwidth(int timer_id, uint32_t value) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->width = value; @@ -145,14 +145,14 @@ void set_gptimer_pwidth(unsigned int timer_id, uint32_t value) } EXPORT_SYMBOL(set_gptimer_pwidth); -uint32_t get_gptimer_pwidth(unsigned int timer_id) +uint32_t get_gptimer_pwidth(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return timer_regs[timer_id]->width; } EXPORT_SYMBOL(get_gptimer_pwidth); -void set_gptimer_period(unsigned int timer_id, uint32_t period) +void set_gptimer_period(int timer_id, uint32_t period) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->period = period; @@ -160,28 +160,28 @@ void set_gptimer_period(unsigned int timer_id, uint32_t period) } EXPORT_SYMBOL(set_gptimer_period); -uint32_t get_gptimer_period(unsigned int timer_id) +uint32_t get_gptimer_period(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return timer_regs[timer_id]->period; } EXPORT_SYMBOL(get_gptimer_period); -uint32_t get_gptimer_count(unsigned int timer_id) +uint32_t get_gptimer_count(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return timer_regs[timer_id]->counter; } EXPORT_SYMBOL(get_gptimer_count); -uint32_t get_gptimer_status(unsigned int group) +uint32_t get_gptimer_status(int group) { tassert(group < BFIN_TIMER_NUM_GROUP); return group_regs[group]->status; } EXPORT_SYMBOL(get_gptimer_status); -void set_gptimer_status(unsigned int group, uint32_t value) +void set_gptimer_status(int group, uint32_t value) { tassert(group < BFIN_TIMER_NUM_GROUP); group_regs[group]->status = value; @@ -189,42 +189,42 @@ void set_gptimer_status(unsigned int group, uint32_t value) } EXPORT_SYMBOL(set_gptimer_status); -int get_gptimer_intr(unsigned int timer_id) +int get_gptimer_intr(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & timil_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_intr); -void clear_gptimer_intr(unsigned int timer_id) +void clear_gptimer_intr(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); group_regs[BFIN_TIMER_OCTET(timer_id)]->status = timil_mask[timer_id]; } EXPORT_SYMBOL(clear_gptimer_intr); -int get_gptimer_over(unsigned int timer_id) +int get_gptimer_over(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & tovf_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_over); -void clear_gptimer_over(unsigned int timer_id) +void clear_gptimer_over(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); group_regs[BFIN_TIMER_OCTET(timer_id)]->status = tovf_mask[timer_id]; } EXPORT_SYMBOL(clear_gptimer_over); -int get_gptimer_run(unsigned int timer_id) +int get_gptimer_run(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return !!(group_regs[BFIN_TIMER_OCTET(timer_id)]->status & trun_mask[timer_id]); } EXPORT_SYMBOL(get_gptimer_run); -void set_gptimer_config(unsigned int timer_id, uint16_t config) +void set_gptimer_config(int timer_id, uint16_t config) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->config = config; @@ -232,7 +232,7 @@ void set_gptimer_config(unsigned int timer_id, uint16_t config) } EXPORT_SYMBOL(set_gptimer_config); -uint16_t get_gptimer_config(unsigned int timer_id) +uint16_t get_gptimer_config(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); return timer_regs[timer_id]->config; @@ -280,7 +280,7 @@ void disable_gptimers_sync(uint16_t mask) } EXPORT_SYMBOL(disable_gptimers_sync); -void set_gptimer_pulse_hi(unsigned int timer_id) +void set_gptimer_pulse_hi(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->config |= TIMER_PULSE_HI; @@ -288,7 +288,7 @@ void set_gptimer_pulse_hi(unsigned int timer_id) } EXPORT_SYMBOL(set_gptimer_pulse_hi); -void clear_gptimer_pulse_hi(unsigned int timer_id) +void clear_gptimer_pulse_hi(int timer_id) { tassert(timer_id < MAX_BLACKFIN_GPTIMERS); timer_regs[timer_id]->config &= ~TIMER_PULSE_HI; diff --git a/trunk/arch/blackfin/kernel/ipipe.c b/trunk/arch/blackfin/kernel/ipipe.c index a77307a4473b..5d7382396dc0 100644 --- a/trunk/arch/blackfin/kernel/ipipe.c +++ b/trunk/arch/blackfin/kernel/ipipe.c @@ -335,70 +335,3 @@ void __ipipe_enable_root_irqs_hw(void) __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); bfin_sti(bfin_irq_flags); } - -/* - * We could use standard atomic bitops in the following root status - * manipulation routines, but let's prepare for SMP support in the - * same move, preventing CPU migration as required. - */ -void __ipipe_stall_root(void) -{ - unsigned long *p, flags; - - local_irq_save_hw(flags); - p = &__ipipe_root_status; - __set_bit(IPIPE_STALL_FLAG, p); - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(__ipipe_stall_root); - -unsigned long __ipipe_test_and_stall_root(void) -{ - unsigned long *p, flags; - int x; - - local_irq_save_hw(flags); - p = &__ipipe_root_status; - x = __test_and_set_bit(IPIPE_STALL_FLAG, p); - local_irq_restore_hw(flags); - - return x; -} -EXPORT_SYMBOL(__ipipe_test_and_stall_root); - -unsigned long __ipipe_test_root(void) -{ - const unsigned long *p; - unsigned long flags; - int x; - - local_irq_save_hw_smp(flags); - p = &__ipipe_root_status; - x = test_bit(IPIPE_STALL_FLAG, p); - local_irq_restore_hw_smp(flags); - - return x; -} -EXPORT_SYMBOL(__ipipe_test_root); - -void __ipipe_lock_root(void) -{ - unsigned long *p, flags; - - local_irq_save_hw(flags); - p = &__ipipe_root_status; - __set_bit(IPIPE_SYNCDEFER_FLAG, p); - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(__ipipe_lock_root); - -void __ipipe_unlock_root(void) -{ - unsigned long *p, flags; - - local_irq_save_hw(flags); - p = &__ipipe_root_status; - __clear_bit(IPIPE_SYNCDEFER_FLAG, p); - local_irq_restore_hw(flags); -} -EXPORT_SYMBOL(__ipipe_unlock_root); diff --git a/trunk/arch/blackfin/kernel/kgdb.c b/trunk/arch/blackfin/kernel/kgdb.c index f1036b6b9293..cce79d05b90b 100644 --- a/trunk/arch/blackfin/kernel/kgdb.c +++ b/trunk/arch/blackfin/kernel/kgdb.c @@ -24,6 +24,16 @@ #include #include +/* Put the error code here just in case the user cares. */ +int gdb_bfin_errcode; +/* Likewise, the vector number here (since GDB only gets the signal + number through the usual means, and that's not very specific). */ +int gdb_bfin_vector = -1; + +#if KGDB_MAX_NO_CPUS != 8 +#error change the definition of slavecpulocks +#endif + void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs) { gdb_regs[BFIN_R0] = regs->r0; @@ -359,6 +369,13 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags) } #endif +void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code) +{ + /* Master processor is completely in the debugger */ + gdb_bfin_vector = eVector; + gdb_bfin_errcode = err_code; +} + int kgdb_arch_handle_exception(int vector, int signo, int err_code, char *remcom_in_buffer, char *remcom_out_buffer, diff --git a/trunk/arch/blackfin/kernel/kgdb_test.c b/trunk/arch/blackfin/kernel/kgdb_test.c index 9a4b07594389..59fc42dc5d6a 100644 --- a/trunk/arch/blackfin/kernel/kgdb_test.c +++ b/trunk/arch/blackfin/kernel/kgdb_test.c @@ -17,9 +17,8 @@ #include -/* Symbols are here for kgdb test to poke directly */ static char cmdline[256]; -static size_t len; +static unsigned long len; #ifndef CONFIG_SMP static int num1 __attribute__((l1_data)); @@ -28,10 +27,11 @@ void kgdb_l1_test(void) __attribute__((l1_text)); void kgdb_l1_test(void) { - pr_alert("L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); - pr_alert("L1 : code function addr = 0x%p\n", kgdb_l1_test); - num1 = num1 + 10; - pr_alert("L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); + printk(KERN_ALERT "L1(before change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); + printk(KERN_ALERT "L1 : code function addr = 0x%p\n", kgdb_l1_test); + num1 = num1 + 10 ; + printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); + return ; } #endif @@ -42,10 +42,11 @@ void kgdb_l2_test(void) __attribute__((l2)); void kgdb_l2_test(void) { - pr_alert("L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); - pr_alert("L2 : code function addr = 0x%p\n", kgdb_l2_test); - num2 = num2 + 20; - pr_alert("L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); + printk(KERN_ALERT "L2(before change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); + printk(KERN_ALERT "L2 : code function addr = 0x%p\n", kgdb_l2_test); + num2 = num2 + 20 ; + printk(KERN_ALERT "L2(after change) : data variable addr = 0x%p, data value is %d\n", &num2, num2); + return ; } #endif @@ -53,14 +54,12 @@ void kgdb_l2_test(void) int kgdb_test(char *name, int len, int count, int z) { - pr_alert("kgdb name(%d): %s, %d, %d\n", len, name, count, z); + printk(KERN_ALERT "kgdb name(%d): %s, %d, %d\n", len, name, count, z); count = z; return count; } -static ssize_t -kgdb_test_proc_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos) +static int test_proc_output(char *buf) { kgdb_test("hello world!", 12, 0x55, 0x10); #ifndef CONFIG_SMP @@ -73,31 +72,49 @@ kgdb_test_proc_read(struct file *file, char __user *buf, return 0; } -static ssize_t -kgdb_test_proc_write(struct file *file, const char __user *buffer, - size_t count, loff_t *pos) +static int test_read_proc(char *page, char **start, off_t off, + int count, int *eof, void *data) { - len = min_t(size_t, 255, count); + int len; + + len = test_proc_output(page); + if (len <= off+count) + *eof = 1; + *start = page + off; + len -= off; + if (len > count) + len = count; + if (len < 0) + len = 0; + return len; +} + +static int test_write_proc(struct file *file, const char *buffer, + unsigned long count, void *data) +{ + if (count >= 256) + len = 255; + else + len = count; + memcpy(cmdline, buffer, count); cmdline[len] = 0; return len; } -static const struct file_operations kgdb_test_proc_fops = { - .owner = THIS_MODULE, - .read = kgdb_test_proc_read, - .write = kgdb_test_proc_write, -}; - static int __init kgdbtest_init(void) { struct proc_dir_entry *entry; - entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops); + entry = create_proc_entry("kgdbtest", 0, NULL); if (entry == NULL) return -ENOMEM; + entry->read_proc = test_read_proc; + entry->write_proc = test_write_proc; + entry->data = NULL; + return 0; } diff --git a/trunk/arch/blackfin/kernel/process.c b/trunk/arch/blackfin/kernel/process.c index b56b0e485e0b..45876427eb2d 100644 --- a/trunk/arch/blackfin/kernel/process.c +++ b/trunk/arch/blackfin/kernel/process.c @@ -258,12 +258,9 @@ void finish_atomic_sections (struct pt_regs *regs) int __user *up0 = (int __user *)regs->p0; switch (regs->pc) { - default: - /* not in middle of an atomic step, so resume like normal */ - return; - case ATOMIC_XCHG32 + 2: put_user(regs->r1, up0); + regs->pc = ATOMIC_XCHG32 + 4; break; case ATOMIC_CAS32 + 2: @@ -271,6 +268,7 @@ void finish_atomic_sections (struct pt_regs *regs) if (regs->r0 == regs->r1) case ATOMIC_CAS32 + 6: put_user(regs->r2, up0); + regs->pc = ATOMIC_CAS32 + 8; break; case ATOMIC_ADD32 + 2: @@ -278,6 +276,7 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_ADD32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_ADD32 + 6; break; case ATOMIC_SUB32 + 2: @@ -285,6 +284,7 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_SUB32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_SUB32 + 6; break; case ATOMIC_IOR32 + 2: @@ -292,6 +292,7 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_IOR32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_IOR32 + 6; break; case ATOMIC_AND32 + 2: @@ -299,6 +300,7 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_AND32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_AND32 + 6; break; case ATOMIC_XOR32 + 2: @@ -306,15 +308,9 @@ void finish_atomic_sections (struct pt_regs *regs) /* fall through */ case ATOMIC_XOR32 + 4: put_user(regs->r0, up0); + regs->pc = ATOMIC_XOR32 + 6; break; } - - /* - * We've finished the atomic section, and the only thing left for - * userspace is to do a RTS, so we might as well handle that too - * since we need to update the PC anyways. - */ - regs->pc = regs->rets; } static inline @@ -336,58 +332,12 @@ int in_mem_const(unsigned long addr, unsigned long size, { return in_mem_const_off(addr, size, 0, const_addr, const_size); } -#define ASYNC_ENABLED(bnum, bctlnum) \ +#define IN_ASYNC(bnum, bctlnum) \ ({ \ - (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \ - bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \ - 1; \ + (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \ + bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \ + BFIN_MEM_ACCESS_CORE; \ }) -/* - * We can't read EBIU banks that aren't enabled or we end up hanging - * on the access to the async space. Make sure we validate accesses - * that cross async banks too. - * 0 - found, but unusable - * 1 - found & usable - * 2 - not found - */ -static -int in_async(unsigned long addr, unsigned long size) -{ - if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) { - if (!ASYNC_ENABLED(0, 0)) - return 0; - if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) - return 1; - size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr; - addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE; - } - if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) { - if (!ASYNC_ENABLED(1, 0)) - return 0; - if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) - return 1; - size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr; - addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE; - } - if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) { - if (!ASYNC_ENABLED(2, 1)) - return 0; - if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) - return 1; - size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr; - addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE; - } - if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) { - if (ASYNC_ENABLED(3, 1)) - return 0; - if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) - return 1; - return 0; - } - - /* not within async bounds */ - return 2; -} int bfin_mem_access_type(unsigned long addr, unsigned long size) { @@ -424,11 +374,17 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size) if (addr >= SYSMMR_BASE) return BFIN_MEM_ACCESS_CORE_ONLY; - switch (in_async(addr, size)) { - case 0: return -EFAULT; - case 1: return BFIN_MEM_ACCESS_CORE; - case 2: /* fall through */; - } + /* We can't read EBIU banks that aren't enabled or we end up hanging + * on the access to the async space. + */ + if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE)) + return IN_ASYNC(0, 0); + if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE)) + return IN_ASYNC(1, 0); + if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE)) + return IN_ASYNC(2, 1); + if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE)) + return IN_ASYNC(3, 1); if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH)) return BFIN_MEM_ACCESS_CORE; @@ -445,8 +401,6 @@ __attribute__((l1_text)) /* Return 1 if access to memory range is OK, 0 otherwise */ int _access_ok(unsigned long addr, unsigned long size) { - int aret; - if (size == 0) return 1; /* Check that things do not wrap around */ @@ -496,11 +450,6 @@ int _access_ok(unsigned long addr, unsigned long size) if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH)) return 1; #endif - - aret = in_async(addr, size); - if (aret < 2) - return aret; - if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH)) return 1; diff --git a/trunk/arch/blackfin/kernel/ptrace.c b/trunk/arch/blackfin/kernel/ptrace.c index 65567dc4b9f5..56b0ba12175f 100644 --- a/trunk/arch/blackfin/kernel/ptrace.c +++ b/trunk/arch/blackfin/kernel/ptrace.c @@ -316,6 +316,19 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) case BFIN_MEM_ACCESS_CORE_ONLY: copied = access_process_vm(child, addr, &data, to_copy, 1); + if (copied) + break; + + /* hrm, why didn't that work ... maybe no mapping */ + if (addr >= FIXED_CODE_START && + addr + to_copy <= FIXED_CODE_END) { + copy_to_user_page(0, 0, 0, paddr, &data, to_copy); + copied = to_copy; + } else if (addr >= BOOT_ROM_START) { + memcpy(paddr, &data, to_copy); + copied = to_copy; + } + break; case BFIN_MEM_ACCESS_DMA: if (safe_dma_memcpy(paddr, &data, to_copy)) diff --git a/trunk/arch/blackfin/kernel/setup.c b/trunk/arch/blackfin/kernel/setup.c index 95448ae9c43a..c202a44d1416 100644 --- a/trunk/arch/blackfin/kernel/setup.c +++ b/trunk/arch/blackfin/kernel/setup.c @@ -178,10 +178,10 @@ void __init bfin_cache_init(void) void __init bfin_relocate_l1_mem(void) { - unsigned long text_l1_len = (unsigned long)_text_l1_len; - unsigned long data_l1_len = (unsigned long)_data_l1_len; - unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len; - unsigned long l2_len = (unsigned long)_l2_len; + unsigned long l1_code_length; + unsigned long l1_data_a_length; + unsigned long l1_data_b_length; + unsigned long l2_length; early_shadow_stamp(); @@ -201,23 +201,30 @@ void __init bfin_relocate_l1_mem(void) blackfin_dma_early_init(); - /* if necessary, copy L1 text to L1 instruction SRAM */ - if (L1_CODE_LENGTH && text_l1_len) - early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len); + /* if necessary, copy _stext_l1 to _etext_l1 to L1 instruction SRAM */ + l1_code_length = _etext_l1 - _stext_l1; + if (l1_code_length) + early_dma_memcpy(_stext_l1, _l1_lma_start, l1_code_length); - /* if necessary, copy L1 data to L1 data bank A SRAM */ - if (L1_DATA_A_LENGTH && data_l1_len) - early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len); + /* if necessary, copy _sdata_l1 to _sbss_l1 to L1 data bank A SRAM */ + l1_data_a_length = _sbss_l1 - _sdata_l1; + if (l1_data_a_length) + early_dma_memcpy(_sdata_l1, _l1_lma_start + l1_code_length, l1_data_a_length); - /* if necessary, copy L1 data B to L1 data bank B SRAM */ - if (L1_DATA_B_LENGTH && data_b_l1_len) - early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len); + /* if necessary, copy _sdata_b_l1 to _sbss_b_l1 to L1 data bank B SRAM */ + l1_data_b_length = _sbss_b_l1 - _sdata_b_l1; + if (l1_data_b_length) + early_dma_memcpy(_sdata_b_l1, _l1_lma_start + l1_code_length + + l1_data_a_length, l1_data_b_length); early_dma_memcpy_done(); - /* if necessary, copy L2 text/data to L2 SRAM */ - if (L2_LENGTH && l2_len) - memcpy(_stext_l2, _l2_lma, l2_len); + /* if necessary, copy _stext_l2 to _edata_l2 to L2 SRAM */ + if (L2_LENGTH != 0) { + l2_length = _sbss_l2 - _stext_l2; + if (l2_length) + memcpy(_stext_l2, _l2_lma_start, l2_length); + } } /* add_memory_region to memmap */ @@ -601,6 +608,11 @@ static __init void memory_setup(void) page_mask_order = get_order(3 * page_mask_nelts * sizeof(long)); #endif +#if !defined(CONFIG_MTD_UCLINUX) + /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/ + memory_end -= SIZE_4K; +#endif + init_mm.start_code = (unsigned long)_stext; init_mm.end_code = (unsigned long)_etext; init_mm.end_data = (unsigned long)_edata; @@ -905,7 +917,7 @@ void __init setup_arch(char **cmdline_p) printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n"); if (bfin_compiled_revid() == 0xffff) - printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid()); + printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU); else if (bfin_compiled_revid() == -1) printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU); else diff --git a/trunk/arch/blackfin/kernel/signal.c b/trunk/arch/blackfin/kernel/signal.c index e0fd63e9e38a..9d90c18fab23 100644 --- a/trunk/arch/blackfin/kernel/signal.c +++ b/trunk/arch/blackfin/kernel/signal.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include @@ -333,20 +332,3 @@ asmlinkage void do_signal(struct pt_regs *regs) sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); } } - -/* - * notification of userspace execution resumption - */ -asmlinkage void do_notify_resume(struct pt_regs *regs) -{ - if (test_thread_flag(TIF_SIGPENDING) || test_thread_flag(TIF_RESTORE_SIGMASK)) - do_signal(regs); - - if (test_thread_flag(TIF_NOTIFY_RESUME)) { - clear_thread_flag(TIF_NOTIFY_RESUME); - tracehook_notify_resume(regs); - if (current->replacement_session_keyring) - key_replace_session_keyring(); - } -} - diff --git a/trunk/arch/blackfin/kernel/time-ts.c b/trunk/arch/blackfin/kernel/time-ts.c index 17c38c5b5b22..359cfb1815ca 100644 --- a/trunk/arch/blackfin/kernel/time-ts.c +++ b/trunk/arch/blackfin/kernel/time-ts.c @@ -22,6 +22,8 @@ #include #include +#if defined(CONFIG_CYCLES_CLOCKSOURCE) + /* Accelerators for sched_clock() * convert from cycles(64bits) => nanoseconds (64bits) * basic equation: @@ -44,11 +46,20 @@ * -johnstul@us.ibm.com "math is hard, lets go shopping!" */ +static unsigned long cyc2ns_scale; #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ -#if defined(CONFIG_CYCLES_CLOCKSOURCE) +static inline void set_cyc2ns_scale(unsigned long cpu_khz) +{ + cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR) / cpu_khz; +} -static notrace cycle_t bfin_read_cycles(struct clocksource *cs) +static inline unsigned long long cycles_2_ns(cycle_t cyc) +{ + return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; +} + +static cycle_t bfin_read_cycles(struct clocksource *cs) { return __bfin_cycles_off + (get_cycles() << __bfin_cycles_mod); } @@ -58,18 +69,19 @@ static struct clocksource bfin_cs_cycles = { .rating = 400, .read = bfin_read_cycles, .mask = CLOCKSOURCE_MASK(64), - .shift = CYC2NS_SCALE_FACTOR, + .shift = 22, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static inline unsigned long long bfin_cs_cycles_sched_clock(void) +unsigned long long sched_clock(void) { - return clocksource_cyc2ns(bfin_read_cycles(&bfin_cs_cycles), - bfin_cs_cycles.mult, bfin_cs_cycles.shift); + return cycles_2_ns(bfin_read_cycles(&bfin_cs_cycles)); } static int __init bfin_cs_cycles_init(void) { + set_cyc2ns_scale(get_cclk() / 1000); + bfin_cs_cycles.mult = \ clocksource_hz2mult(get_cclk(), bfin_cs_cycles.shift); @@ -96,7 +108,7 @@ void __init setup_gptimer0(void) enable_gptimers(TIMER0bit); } -static cycle_t bfin_read_gptimer0(struct clocksource *cs) +static cycle_t bfin_read_gptimer0(void) { return bfin_read_TIMER0_COUNTER(); } @@ -106,16 +118,10 @@ static struct clocksource bfin_cs_gptimer0 = { .rating = 350, .read = bfin_read_gptimer0, .mask = CLOCKSOURCE_MASK(32), - .shift = CYC2NS_SCALE_FACTOR, + .shift = 22, .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -static inline unsigned long long bfin_cs_gptimer0_sched_clock(void) -{ - return clocksource_cyc2ns(bfin_read_TIMER0_COUNTER(), - bfin_cs_gptimer0.mult, bfin_cs_gptimer0.shift); -} - static int __init bfin_cs_gptimer0_init(void) { setup_gptimer0(); @@ -132,19 +138,6 @@ static int __init bfin_cs_gptimer0_init(void) # define bfin_cs_gptimer0_init() #endif - -#if defined(CONFIG_GPTMR0_CLOCKSOURCE) || defined(CONFIG_CYCLES_CLOCKSOURCE) -/* prefer to use cycles since it has higher rating */ -notrace unsigned long long sched_clock(void) -{ -#if defined(CONFIG_CYCLES_CLOCKSOURCE) - return bfin_cs_cycles_sched_clock(); -#else - return bfin_cs_gptimer0_sched_clock(); -#endif -} -#endif - #ifdef CONFIG_CORE_TIMER_IRQ_L1 __attribute__((l1_text)) #endif diff --git a/trunk/arch/blackfin/kernel/time.c b/trunk/arch/blackfin/kernel/time.c index 13c1ee3e6408..bd3b53da295e 100644 --- a/trunk/arch/blackfin/kernel/time.c +++ b/trunk/arch/blackfin/kernel/time.c @@ -184,3 +184,11 @@ void __init time_init(void) time_sched_init(timer_interrupt); } + +/* + * Scheduler clock - returns current time in nanosec units. + */ +unsigned long long sched_clock(void) +{ + return (unsigned long long)jiffies *(NSEC_PER_SEC / HZ); +} diff --git a/trunk/arch/blackfin/kernel/traps.c b/trunk/arch/blackfin/kernel/traps.c index d3cbcd6bd985..9636bace00e8 100644 --- a/trunk/arch/blackfin/kernel/traps.c +++ b/trunk/arch/blackfin/kernel/traps.c @@ -119,15 +119,6 @@ static void decode_address(char *buf, unsigned long address) return; } - /* - * Don't walk any of the vmas if we are oopsing, it has been known - * to cause problems - corrupt vmas (kernel crashes) cause double faults - */ - if (oops_in_progress) { - strcat(buf, "/* kernel dynamic memory (maybe user-space) */"); - return; - } - /* looks like we're off in user-land, so let's walk all the * mappings of all our processes and see if we can't be a whee * bit more specific @@ -524,36 +515,6 @@ asmlinkage notrace void trap_c(struct pt_regs *fp) break; /* External Memory Addressing Error */ case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR): - if (ANOMALY_05000310) { - static unsigned long anomaly_rets; - - if ((fp->pc >= (L1_CODE_START + L1_CODE_LENGTH - 512)) && - (fp->pc < (L1_CODE_START + L1_CODE_LENGTH))) { - /* - * A false hardware error will happen while fetching at - * the L1 instruction SRAM boundary. Ignore it. - */ - anomaly_rets = fp->rets; - goto traps_done; - } else if (fp->rets == anomaly_rets) { - /* - * While boundary code returns to a function, at the ret - * point, a new false hardware error might occur too based - * on tests. Ignore it too. - */ - goto traps_done; - } else if ((fp->rets >= (L1_CODE_START + L1_CODE_LENGTH - 512)) && - (fp->rets < (L1_CODE_START + L1_CODE_LENGTH))) { - /* - * If boundary code calls a function, at the entry point, - * a new false hardware error maybe happen based on tests. - * Ignore it too. - */ - goto traps_done; - } else - anomaly_rets = 0; - } - info.si_code = BUS_ADRERR; sig = SIGBUS; strerror = KERN_NOTICE HWC_x3(KERN_NOTICE); @@ -1015,12 +976,12 @@ void dump_bfin_process(struct pt_regs *fp) !((unsigned long)current & 0x3) && current->pid) { verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n"); if (current->comm >= (char *)FIXED_CODE_START) - verbose_printk(KERN_NOTICE "COMM=%s PID=%d", + verbose_printk(KERN_NOTICE "COMM=%s PID=%d\n", current->comm, current->pid); else - verbose_printk(KERN_NOTICE "COMM= invalid"); + verbose_printk(KERN_NOTICE "COMM= invalid\n"); - printk(KERN_CONT " CPU=%d\n", current_thread_info()->cpu); + printk(KERN_NOTICE "CPU = %d\n", current_thread_info()->cpu); if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) verbose_printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" diff --git a/trunk/arch/blackfin/kernel/vmlinux.lds.S b/trunk/arch/blackfin/kernel/vmlinux.lds.S index 66799e763dc9..10e12539000e 100644 --- a/trunk/arch/blackfin/kernel/vmlinux.lds.S +++ b/trunk/arch/blackfin/kernel/vmlinux.lds.S @@ -4,6 +4,8 @@ * Licensed under the GPL-2 or later */ +#define VMLINUX_SYMBOL(_sym_) _##_sym_ + #include #include #include @@ -121,6 +123,8 @@ SECTIONS EXIT_DATA } + __l1_lma_start = .; + .text_l1 L1_CODE_START : AT(LOADADDR(.exit.data) + SIZEOF(.exit.data)) { . = ALIGN(4); @@ -132,11 +136,9 @@ SECTIONS . = ALIGN(4); __etext_l1 = .; } - __text_l1_lma = LOADADDR(.text_l1); - __text_l1_len = SIZEOF(.text_l1); - ASSERT (__text_l1_len <= L1_CODE_LENGTH, "L1 text overflow!") + ASSERT (SIZEOF(.text_l1) <= L1_CODE_LENGTH, "L1 text overflow!") - .data_l1 L1_DATA_A_START : AT(__text_l1_lma + __text_l1_len) + .data_l1 L1_DATA_A_START : AT(LOADADDR(.text_l1) + SIZEOF(.text_l1)) { . = ALIGN(4); __sdata_l1 = .; @@ -152,11 +154,9 @@ SECTIONS . = ALIGN(4); __ebss_l1 = .; } - __data_l1_lma = LOADADDR(.data_l1); - __data_l1_len = SIZEOF(.data_l1); - ASSERT (__data_l1_len <= L1_DATA_A_LENGTH, "L1 data A overflow!") + ASSERT (SIZEOF(.data_l1) <= L1_DATA_A_LENGTH, "L1 data A overflow!") - .data_b_l1 L1_DATA_B_START : AT(__data_l1_lma + __data_l1_len) + .data_b_l1 L1_DATA_B_START : AT(LOADADDR(.data_l1) + SIZEOF(.data_l1)) { . = ALIGN(4); __sdata_b_l1 = .; @@ -169,11 +169,11 @@ SECTIONS . = ALIGN(4); __ebss_b_l1 = .; } - __data_b_l1_lma = LOADADDR(.data_b_l1); - __data_b_l1_len = SIZEOF(.data_b_l1); - ASSERT (__data_b_l1_len <= L1_DATA_B_LENGTH, "L1 data B overflow!") + ASSERT (SIZEOF(.data_b_l1) <= L1_DATA_B_LENGTH, "L1 data B overflow!") + + __l2_lma_start = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); - .text_data_l2 L2_START : AT(__data_b_l1_lma + __data_b_l1_len) + .text_data_l2 L2_START : AT(LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1)) { . = ALIGN(4); __stext_l2 = .; @@ -195,14 +195,12 @@ SECTIONS . = ALIGN(4); __ebss_l2 = .; } - __l2_lma = LOADADDR(.text_data_l2); - __l2_len = SIZEOF(.text_data_l2); - ASSERT (__l2_len <= L2_LENGTH, "L2 overflow!") + ASSERT (SIZEOF(.text_data_l2) <= L2_LENGTH, "L2 overflow!") /* Force trailing alignment of our init section so that when we * free our init memory, we don't leave behind a partial page. */ - . = __l2_lma + __l2_len; + . = LOADADDR(.text_data_l2) + SIZEOF(.text_data_l2); . = ALIGN(PAGE_SIZE); ___init_end = .; diff --git a/trunk/arch/blackfin/lib/Makefile b/trunk/arch/blackfin/lib/Makefile index 42c47dc9e12f..635288fc5f54 100644 --- a/trunk/arch/blackfin/lib/Makefile +++ b/trunk/arch/blackfin/lib/Makefile @@ -5,7 +5,7 @@ lib-y := \ ashldi3.o ashrdi3.o lshrdi3.o \ muldi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \ - memcpy.o memset.o memcmp.o memchr.o memmove.o \ + checksum.o memcpy.o memset.o memcmp.o memchr.o memmove.o \ strcmp.o strcpy.o strncmp.o strncpy.o \ umulsi3_highpart.o smulsi3_highpart.o \ ins.o outs.o diff --git a/trunk/arch/blackfin/lib/checksum.c b/trunk/arch/blackfin/lib/checksum.c new file mode 100644 index 000000000000..c62969dc1bbb --- /dev/null +++ b/trunk/arch/blackfin/lib/checksum.c @@ -0,0 +1,125 @@ +/* + * Copyright 2004-2009 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + * + * An implementation of the TCP/IP protocol suite for the LINUX operating + * system. INET is implemented using the BSD Socket interface as the + * means of communication with the user level. + * + */ + +#include +#include +#include + +#ifdef CONFIG_IP_CHECKSUM_L1 +static unsigned short do_csum(const unsigned char *buff, int len)__attribute__((l1_text)); +#endif + +static unsigned short do_csum(const unsigned char *buff, int len) +{ + register unsigned long sum = 0; + int swappem = 0; + + if (1 & (unsigned long)buff) { + sum = *buff << 8; + buff++; + len--; + ++swappem; + } + + while (len > 1) { + sum += *(unsigned short *)buff; + buff += 2; + len -= 2; + } + + if (len > 0) + sum += *buff; + + /* Fold 32-bit sum to 16 bits */ + while (sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + + if (swappem) + sum = ((sum & 0xff00) >> 8) + ((sum & 0x00ff) << 8); + + return sum; + +} + +/* + * This is a version of ip_compute_csum() optimized for IP headers, + * which always checksum on 4 octet boundaries. + */ +__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl) +{ + return (__force __sum16)~do_csum(iph, ihl * 4); +} +EXPORT_SYMBOL(ip_fast_csum); + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +__wsum csum_partial(const void *buff, int len, __wsum sum) +{ + /* + * Just in case we get nasty checksum data... + * Like 0xffff6ec3 in the case of our IPv6 multicast header. + * We fold to begin with, as well as at the end. + */ + sum = (sum & 0xffff) + (sum >> 16); + + sum += do_csum(buff, len); + + sum = (sum & 0xffff) + (sum >> 16); + + return sum; +} +EXPORT_SYMBOL(csum_partial); + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ +__sum16 ip_compute_csum(const void *buff, int len) +{ + return (__force __sum16)~do_csum(buff, len); +} +EXPORT_SYMBOL(ip_compute_csum); + +/* + * copy from fs while checksumming, otherwise like csum_partial + */ + +__wsum +csum_partial_copy_from_user(const void __user *src, void *dst, + int len, __wsum sum, int *csum_err) +{ + if (csum_err) + *csum_err = 0; + memcpy(dst, (__force void *)src, len); + return csum_partial(dst, len, sum); +} +EXPORT_SYMBOL(csum_partial_copy_from_user); + +/* + * copy from ds while checksumming, otherwise like csum_partial + */ + +__wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum) +{ + memcpy(dst, src, len); + return csum_partial(dst, len, sum); +} +EXPORT_SYMBOL(csum_partial_copy); diff --git a/trunk/arch/blackfin/mach-bf518/Kconfig b/trunk/arch/blackfin/mach-bf518/Kconfig index 4ab2d166c832..4c76fefb7a3b 100644 --- a/trunk/arch/blackfin/mach-bf518/Kconfig +++ b/trunk/arch/blackfin/mach-bf518/Kconfig @@ -1,7 +1,3 @@ -config BF51x - def_bool y - depends on (BF512 || BF514 || BF516 || BF518) - if (BF51x) source "arch/blackfin/mach-bf518/boards/Kconfig" diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf518/include/mach/blackfin.h index 9053462be4b1..6cfb246aebec 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/blackfin.h @@ -58,4 +58,10 @@ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_GCTL 0x24 /* Global Control Register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF514.h index 108fa4bde277..e1d99911025d 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF514.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF514.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF514_H @@ -10,8 +10,15 @@ /* include all Core registers and bit definitions */ #include "defBF514.h" -/* BF514 is BF512 + RSI */ -#include "cdefBF512.h" +/* include core specific register pointer definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ + +/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "cdefBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF514 that are not in the common header */ /* Removable Storage Interface Registers */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF516.h index 2751592ef1c1..6b364eda4947 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF516.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF516.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF516_H @@ -10,8 +10,15 @@ /* include all Core registers and bit definitions */ #include "defBF516.h" -/* BF516 is BF514 + EMAC */ -#include "cdefBF514.h" +/* include core specific register pointer definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ + +/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "cdefBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF516 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ @@ -178,4 +185,71 @@ #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) +/* Removable Storage Interface Registers */ + +#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL) +#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) +#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) +#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) +#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) +#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) +#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) +#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) +#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) +#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) +#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) +#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) +#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) +#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) +#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) +#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) +#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) +#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) +#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) +#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) +#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) +#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) +#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) +#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) +#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) +#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) +#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) +#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) +#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) +#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) +#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) +#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) +#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) +#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) +#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) +#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) +#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL) +#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val) +#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) +#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) +#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT) +#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val) +#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK) +#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val) +#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) +#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) +#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) +#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) +#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) +#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) +#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) +#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) +#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) +#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) +#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) +#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) +#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4) +#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val) +#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5) +#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val) +#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6) +#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val) +#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7) +#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val) + #endif /* _CDEF_BF516_H */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF518.h index 7fb7f0eab990..929b90650bd4 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF518.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF518.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the ADI BSD license or the GPL-2 (or later) + * Licensed under the GPL-2 or later */ #ifndef _CDEF_BF518_H @@ -10,10 +10,181 @@ /* include all Core registers and bit definitions */ #include "defBF518.h" -/* BF518 is BF516 + IEEE-1588 */ -#include "cdefBF516.h" +/* include core specific register pointer definitions */ +#include -/* PTP TSYNC Registers */ +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ + +/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "cdefBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF518 that are not in the common header */ + + +/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ + +#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) +#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) +#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) +#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) +#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) +#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) +#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) +#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) +#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) +#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) +#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) +#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) +#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) +#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) +#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) +#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) +#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) +#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) +#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) +#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) +#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) +#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) +#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) +#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) +#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) +#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) +#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) +#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) +#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) +#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) +#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) +#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) +#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) +#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) +#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) +#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) +#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) +#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) + +#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) +#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) +#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) +#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) +#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) +#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) +#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) +#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) +#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) +#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) +#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) +#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) +#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) +#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) +#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) +#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) + +#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) +#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) +#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) +#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) +#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) +#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) +#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) +#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) +#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) +#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) + +#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) +#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) +#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) +#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) +#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) +#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) +#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) +#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) +#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) +#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) +#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) +#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) +#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) +#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) +#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) +#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) +#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) +#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) +#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) +#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) +#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) +#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) +#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) +#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) +#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) +#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) +#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) +#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) +#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) +#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) +#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) +#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) +#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) +#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) +#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) +#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) +#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) +#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) +#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) +#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) +#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) +#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) +#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) +#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) +#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) +#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) +#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) +#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) + +#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) +#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) +#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) +#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) +#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) +#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) +#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) +#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) +#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) +#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) +#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) +#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) +#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) +#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) +#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) +#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) +#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) +#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) +#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) +#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) +#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) +#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) +#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) +#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) +#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) +#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) +#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) +#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) +#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) +#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) +#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) +#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) +#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) +#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) +#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) +#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) +#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) +#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) +#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) +#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) +#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) +#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) +#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) +#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) +#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) +#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) #define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL) #define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) @@ -56,4 +227,72 @@ #define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD) #define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val) +/* Removable Storage Interface Registers */ + +#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL) +#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) +#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) +#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) +#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) +#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) +#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) +#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) +#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) +#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) +#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) +#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) +#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) +#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) +#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) +#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) +#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) +#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) +#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) +#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) +#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) +#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) +#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) +#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) +#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) +#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) +#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) +#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) +#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) +#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) +#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) +#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) +#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) +#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) +#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) +#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) +#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL) +#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val) +#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) +#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) +#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT) +#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val) +#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK) +#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val) +#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) +#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) +#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) +#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) +#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) +#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) +#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) +#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) +#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) +#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) +#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) +#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) +#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4) +#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val) +#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5) +#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val) +#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6) +#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val) +#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7) +#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val) + + #endif /* _CDEF_BF518_H */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h index e548e9d1d6fa..1d970df7aee9 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h @@ -131,6 +131,23 @@ #define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val) +/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ +#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL) +#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val) +#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG) +#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val) +#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT) +#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val) +#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR) +#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val) +#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR) +#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val) +#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD) +#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val) +#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW) +#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val) + + /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */ #define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) #define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) @@ -827,7 +844,6 @@ #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) @@ -1046,6 +1062,17 @@ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) +/* OTP/FUSE Registers */ + +#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) +#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) +#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) +#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) +#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) +#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) +#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) +#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) + /* Security Registers */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) @@ -1055,6 +1082,52 @@ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) +/* OTP Read/Write Data Buffer Registers */ + +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) + +/* NFC Registers */ + +#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) +#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val) +#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT) +#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val) +#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT) +#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val) +#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK) +#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val) +#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0) +#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val) +#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1) +#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val) +#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2) +#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val) +#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3) +#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val) +#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT) +#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val) +#define bfin_read_NFC_RST() bfin_read16(NFC_RST) +#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val) +#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL) +#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val) +#define bfin_read_NFC_READ() bfin_read16(NFC_READ) +#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val) +#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR) +#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val) +#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD) +#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val) +#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR) +#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val) +#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD) +#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val) + /* These need to be last due to the cdef/linux inter-dependencies */ #include diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h index 92e950d6e996..b5adca23a788 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF514.h @@ -7,8 +7,49 @@ #ifndef _DEF_BF514_H #define _DEF_BF514_H -/* BF514 is BF512 + RSI */ -#include "defBF512.h" +/* Include all Core registers and bit definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ + +/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "defBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF514 that are not in the common header */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ +#define SDH_COMMAND 0xFFC0390C /* SDH Command */ +#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ +#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ +#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ +#define SDH_STATUS 0xFFC03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ +#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ +#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ +#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ +#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ /* Removable Storage Interface Registers */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF516.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF516.h index 22a3aa0d2629..7eb18774d727 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF516.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF516.h @@ -7,8 +7,13 @@ #ifndef _DEF_BF516_H #define _DEF_BF516_H -/* BF516 is BF514 + EMAC */ -#include "defBF514.h" +/* Include all Core registers and bit definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ + +/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "defBF51x_base.h" /* The following are the #defines needed by ADSP-BF516 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ @@ -389,4 +394,208 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ +/* SDH Registers */ + +#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ +#define SDH_COMMAND 0xFFC0390C /* SDH Command */ +#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ +#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ +#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ +#define SDH_STATUS 0xFFC03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ +#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ +#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ +#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ +#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ + +/* Removable Storage Interface Registers */ + +#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ +#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ +#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ +#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ +#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ +#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ +#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ +#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ +#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ +#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ +#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ +#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ +#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ +#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ +#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ +#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ +#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ +#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ +#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ +#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ +#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ +#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ +#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ +#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ +#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ +#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ +#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ +#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ +#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ +#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ +#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ +#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + #endif /* _DEF_BF516_H */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF518.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF518.h index cb18270e55c2..794cf06eb5ba 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF518.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF518.h @@ -7,8 +7,461 @@ #ifndef _DEF_BF518_H #define _DEF_BF518_H -/* BF518 is BF516 + IEEE-1588 */ -#include "defBF516.h" +/* Include all Core registers and bit definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ + +/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ +#include "defBF51x_base.h" + +/* The following are the #defines needed by ADSP-BF518 that are not in the common header */ +/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ + +#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ +#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */ +#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */ +#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */ +#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */ +#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */ +#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */ +#define EMAC_FLC 0xFFC0301C /* Flow Control Register */ +#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */ +#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */ +#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */ +#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */ +#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */ +#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */ +#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */ +#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */ +#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */ +#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */ +#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */ + +#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */ +#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */ +#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */ +#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */ +#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */ +#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */ +#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */ +#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */ + +#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */ +#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */ +#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */ +#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */ +#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */ + +#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */ +#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */ +#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */ +#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */ +#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */ +#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */ +#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */ +#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */ +#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */ +#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */ +#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */ +#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */ +#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */ +#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */ +#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */ +#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */ +#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */ +#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */ +#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */ +#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */ +#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ +#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ +#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ +#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */ + +#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */ +#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */ +#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */ +#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */ +#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */ +#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */ +#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */ +#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */ +#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */ +#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */ +#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */ +#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */ +#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */ +#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */ +#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */ +#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */ +#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */ +#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */ +#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ +#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */ +#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ +#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */ +#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */ + +/* Listing for IEEE-Supported Count Registers */ + +#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */ +#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */ +#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */ +#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */ +#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */ +#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */ +#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */ +#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */ +#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */ +#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */ +#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */ +#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */ +#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */ +#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */ +#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */ +#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */ +#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */ +#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */ +#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */ +#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */ +#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */ +#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */ +#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */ +#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */ + +#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */ +#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */ +#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */ +#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */ +#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */ +#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */ +#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */ +#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */ +#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */ +#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */ +#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */ +#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */ +#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */ +#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */ +#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */ +#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */ +#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */ +#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */ +#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */ +#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */ +#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */ +#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */ +#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */ + +/*********************************************************************************** +** System MMR Register Bits And Macros +** +** Disclaimer: All macros are intended to make C and Assembly code more readable. +** Use these macros carefully, as any that do left shifts for field +** depositing will result in the lower order bits being destroyed. Any +** macro that shifts left to properly position the bit-field should be +** used as part of an OR to initialize a register and NOT as a dynamic +** modifier UNLESS the lower order bits are saved and ORed back in when +** the macro is used. +*************************************************************************************/ + +/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/ + +/* EMAC_OPMODE Masks */ + +#define RE 0x00000001 /* Receiver Enable */ +#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */ +#define HU 0x00000010 /* Hash Filter Unicast Address */ +#define HM 0x00000020 /* Hash Filter Multicast Address */ +#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */ +#define PR 0x00000080 /* Promiscuous Mode Enable */ +#define IFE 0x00000100 /* Inverse Filtering Enable */ +#define DBF 0x00000200 /* Disable Broadcast Frame Reception */ +#define PBF 0x00000400 /* Pass Bad Frames Enable */ +#define PSF 0x00000800 /* Pass Short Frames Enable */ +#define RAF 0x00001000 /* Receive-All Mode */ +#define TE 0x00010000 /* Transmitter Enable */ +#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */ +#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */ +#define DC 0x00080000 /* Deferral Check */ +#define BOLMT 0x00300000 /* Back-Off Limit */ +#define BOLMT_10 0x00000000 /* 10-bit range */ +#define BOLMT_8 0x00100000 /* 8-bit range */ +#define BOLMT_4 0x00200000 /* 4-bit range */ +#define BOLMT_1 0x00300000 /* 1-bit range */ +#define DRTY 0x00400000 /* Disable TX Retry On Collision */ +#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */ +#define RMII 0x01000000 /* RMII/MII* Mode */ +#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */ +#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */ +#define LB 0x08000000 /* Internal Loopback Enable */ +#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */ + +/* EMAC_STAADD Masks */ + +#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */ +#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */ +#define STADISPRE 0x00000004 /* Disable Preamble Generation */ +#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */ +#define REGAD 0x000007C0 /* STA Register Address */ +#define PHYAD 0x0000F800 /* PHY Device Address */ + +#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */ +#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */ + +/* EMAC_STADAT Mask */ + +#define STADATA 0x0000FFFF /* Station Management Data */ + +/* EMAC_FLC Masks */ + +#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */ +#define FLCE 0x00000002 /* Flow Control Enable */ +#define PCF 0x00000004 /* Pass Control Frames */ +#define BKPRSEN 0x00000008 /* Enable Backpressure */ +#define FLCPAUSE 0xFFFF0000 /* Pause Time */ + +#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */ + +/* EMAC_WKUP_CTL Masks */ + +#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */ +#define MPKE 0x00000002 /* Magic Packet Enable */ +#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */ +#define GUWKE 0x00000008 /* Global Unicast Wake Enable */ +#define MPKS 0x00000020 /* Magic Packet Received Status */ +#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */ + +/* EMAC_WKUP_FFCMD Masks */ + +#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */ +#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */ +#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */ +#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */ +#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */ +#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */ +#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */ +#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */ + +/* EMAC_WKUP_FFOFF Masks */ + +#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */ +#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */ +#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */ +#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */ + +#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */ +#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */ +#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */ +#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */ +/* Set ALL Offsets */ +#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3))) + +/* EMAC_WKUP_FFCRC0 Masks */ + +#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */ +#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */ + +#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */ +#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */ + +/* EMAC_WKUP_FFCRC1 Masks */ + +#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */ +#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */ + +#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */ +#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */ + +/* EMAC_SYSCTL Masks */ + +#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ +#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ +#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ +#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */ +#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ + +#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ + +/* EMAC_SYSTAT Masks */ + +#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */ +#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */ +#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */ +#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */ +#define WAKEDET 0x00000010 /* Wake-Up Detected Status */ +#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */ +#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */ +#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */ + +/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */ + +#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */ +#define RX_COMP 0x00001000 /* RX Frame Complete */ +#define RX_OK 0x00002000 /* RX Frame Received With No Errors */ +#define RX_LONG 0x00004000 /* RX Frame Too Long Error */ +#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */ +#define RX_CRC 0x00010000 /* RX Frame CRC Error */ +#define RX_LEN 0x00020000 /* RX Frame Length Error */ +#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */ +#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */ +#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */ +#define RX_PHY 0x00200000 /* RX Frame PHY Error */ +#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */ +#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */ +#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */ +#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */ +#define RX_CTL 0x04000000 /* RX Control Frame Indicator */ +#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */ +#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */ +#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */ +#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */ +#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */ + +/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */ + +#define TX_COMP 0x00000001 /* TX Frame Complete */ +#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */ +#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */ +#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */ +#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */ +#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */ +#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */ +#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */ +#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */ +#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */ +#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */ +#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */ +#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */ +#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */ +#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */ + +/* EMAC_MMC_CTL Masks */ +#define RSTC 0x00000001 /* Reset All Counters */ +#define CROLL 0x00000002 /* Counter Roll-Over Enable */ +#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */ +#define MMCE 0x00000008 /* Enable MMC Counter Operation */ + +/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */ +#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */ +#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */ +#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */ +#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */ +#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */ +#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */ +#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */ +#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */ +#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */ +#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */ +#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */ +#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */ +#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */ +#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */ +#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */ +#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */ +#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */ +#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */ +#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */ +#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */ +#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */ +#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */ +#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */ +#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */ + +/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */ + +#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */ +#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */ +#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */ +#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */ +#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */ +#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */ +#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */ +#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */ +#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */ +#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */ +#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */ +#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */ +#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */ +#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */ +#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */ +#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */ +#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */ +#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */ +#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */ +#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */ +#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */ +#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ +#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ +#define SDH_COMMAND 0xFFC0390C /* SDH Command */ +#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ +#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ +#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ +#define SDH_STATUS 0xFFC03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ +#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ +#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ +#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ +#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ + +/* Removable Storage Interface Registers */ + +#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ +#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ +#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ +#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ +#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ +#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ +#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ +#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ +#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ +#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ +#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ +#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ +#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ +#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ +#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ +#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ +#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ +#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ +#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ +#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ +#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ +#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ +#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ +#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ +#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ +#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ +#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ +#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ +#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ +#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ +#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ +#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ /* PTP TSYNC Registers */ @@ -36,6 +489,141 @@ #define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ #define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + /* Bit masks for EMAC_PTP_CTL */ #define PTP_EN 0x1 /* Enable the PTP_TSYNC module */ diff --git a/trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h index 9241205fb992..f9fd2b2a2956 100644 --- a/trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h +++ b/trunk/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h @@ -585,6 +585,58 @@ ** modifier UNLESS the lower order bits are saved and ORed back in when ** the macro is used. *************************************************************************************/ +/* +** ********************* PLL AND RESET MASKS ****************************************/ +/* PLL_CTL Masks */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* PLL Not Powered */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Enter Deep Sleep Mode */ +#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* VR_CTL Masks */ +#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ +#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ +#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ +#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ +#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 @@ -704,6 +756,66 @@ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ +/* ********* WATCHDOG TIMER MASKS ******************** */ + +/* Watchdog Timer WDOG_CTL Register Masks */ + +#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ +#define WDEV_RESET 0x0000 /* generate reset event on roll over */ +#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ +#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ +#define WDEV_NONE 0x0006 /* no event on roll over */ +#define WDEN 0x0FF0 /* enable watchdog */ +#define WDDIS 0x0AD0 /* disable watchdog */ +#define WDRO 0x8000 /* watchdog rolled over latch */ + +/* depreciated WDOG_CTL Register Masks for legacy code */ + + +#define ICTL WDEV +#define ENABLE_RESET WDEV_RESET +#define WDOG_RESET WDEV_RESET +#define ENABLE_NMI WDEV_NMI +#define WDOG_NMI WDEV_NMI +#define ENABLE_GPI WDEV_GPI +#define WDOG_GPI WDEV_GPI +#define DISABLE_EVT WDEV_NONE +#define WDOG_NONE WDEV_NONE + +#define TMR_EN WDEN +#define TMR_DIS WDDIS +#define TRO WDRO +#define ICTL_P0 0x01 + #define ICTL_P1 0x02 +#define TRO_P 0x0F + + + +/* *************** REAL TIME CLOCK MASKS **************************/ +/* RTC_STAT and RTC_ALARM Masks */ +#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ +#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ALARM Macro z=day y=hr x=min w=sec */ +#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F)) + +/* RTC_ICTL and RTC_ISTAT Masks */ +#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ +#define ALARM 0x0002 /* Alarm Interrupt Enable */ +#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MINUTE 0x0008 /* Minutes Interrupt Enable */ +#define HOUR 0x0010 /* Hours Interrupt Enable */ +#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WRITE_PENDING 0x4000 /* Write Pending Status */ +#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_FAST / RTC_PREN Mask */ +#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ + + /* ************** UART CONTROLLER MASKS *************************/ /* UARTx_LCR Masks */ #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ @@ -1260,6 +1372,33 @@ /* ************************** DMA CONTROLLER MASKS ********************************/ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0900 /* Next Descriptor Size */ +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ @@ -1277,6 +1416,13 @@ #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + + /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ /* PPI_CONTROL Masks */ #define PORT_EN 0x0001 /* PPI Port Enable */ @@ -1684,6 +1830,46 @@ #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ #define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ +/* Bit masks for OTP_CONTROL */ + +#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ +#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ +#define nFIEN 0x0 +#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ +#define nFTESTDEC 0x0 +#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ +#define nFWRTEST 0x0 +#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ +#define nFRDEN 0x0 +#define FWREN 0x8000 /* OTP/Fuse Write Enable */ +#define nFWREN 0x0 + +/* Bit masks for OTP_BEN */ + +#define FBEN 0xffff /* OTP/Fuse Byte Enable */ + +/* Bit masks for OTP_STATUS */ + +#define FCOMP 0x1 /* OTP/Fuse Access Complete */ +#define nFCOMP 0x0 +#define FERROR 0x2 /* OTP/Fuse Access Error */ +#define nFERROR 0x0 +#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ +#define nMMRGLOAD 0x0 +#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ +#define nMMRGLOCK 0x0 +#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ +#define nFPGMEN 0x0 + +/* Bit masks for OTP_TIMING */ + +#define USECDIV 0xff /* Micro Second Divider */ +#define READACC 0x7f00 /* Read Access Time */ +#define CPUMPRL 0x38000 /* Charge Pump Release Time */ +#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ +#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ +#define PGMTIME 0xff000000 /* Program Time */ + /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ diff --git a/trunk/arch/blackfin/mach-bf527/Kconfig b/trunk/arch/blackfin/mach-bf527/Kconfig index 1f8cbe9d6b9a..848ac6f86823 100644 --- a/trunk/arch/blackfin/mach-bf527/Kconfig +++ b/trunk/arch/blackfin/mach-bf527/Kconfig @@ -1,7 +1,3 @@ -config BF52x - def_bool y - depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) - if (BF52x) source "arch/blackfin/mach-bf527/boards/Kconfig" diff --git a/trunk/arch/blackfin/mach-bf527/boards/cm_bf527.c b/trunk/arch/blackfin/mach-bf527/boards/cm_bf527.c index 7ab0800e2914..f1996b13a3da 100644 --- a/trunk/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/trunk/arch/blackfin/mach-bf527/boards/cm_bf527.c @@ -15,6 +15,9 @@ #include #include #include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif #include #include #include @@ -62,7 +65,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -314,6 +317,45 @@ static struct platform_device sl811_hcd_device = { }; #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +static struct resource isp1362_hcd_resources[] = { + { + .start = 0x20360000, + .end = 0x20360000, + .flags = IORESOURCE_MEM, + }, { + .start = 0x20360004, + .end = 0x20360004, + .flags = IORESOURCE_MEM, + }, { + .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", @@ -799,6 +841,10 @@ static struct platform_device *cmbf527_devices[] __initdata = { &sl811_hcd_device, #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) + &isp1362_hcd_device, +#endif + #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) &bfin_isp1760_device, #endif diff --git a/trunk/arch/blackfin/mach-bf527/boards/ezkit.c b/trunk/arch/blackfin/mach-bf527/boards/ezkit.c index 5294fdd20732..f09665f74ba0 100644 --- a/trunk/arch/blackfin/mach-bf527/boards/ezkit.c +++ b/trunk/arch/blackfin/mach-bf527/boards/ezkit.c @@ -13,6 +13,9 @@ #include #include #include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif #include #include #include @@ -60,7 +63,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -370,6 +373,45 @@ static struct platform_device sl811_hcd_device = { }; #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +static struct resource isp1362_hcd_resources[] = { + { + .start = 0x20360000, + .end = 0x20360000, + .flags = IORESOURCE_MEM, + }, { + .start = 0x20360004, + .end = 0x20360004, + .flags = IORESOURCE_MEM, + }, { + .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", @@ -646,6 +688,12 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ +#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +static struct platform_device bfin_fb_device = { + .name = "bf537-lq035", +}; +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { #ifdef CONFIG_SERIAL_BFIN_UART0 @@ -802,7 +850,7 @@ static struct platform_device bfin_device_gpiokeys = { }; #endif -#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) #include #include @@ -876,6 +924,10 @@ static struct platform_device *stamp_devices[] __initdata = { &sl811_hcd_device, #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) + &isp1362_hcd_device, +#endif + #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) &bfin_isp1760_device, #endif @@ -905,6 +957,10 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_spi0_device, #endif +#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) + &bfin_fb_device, +#endif + #if defined(CONFIG_FB_BFIN_T350MCQB) || defined(CONFIG_FB_BFIN_T350MCQB_MODULE) &bf52x_t350mcqb_device, #endif @@ -935,7 +991,7 @@ static struct platform_device *stamp_devices[] __initdata = { &bfin_device_gpiokeys, #endif -#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) &bfin_rotary_device, #endif diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf527/include/mach/blackfin.h index f714c5de3073..e7d6034f268f 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/blackfin.h @@ -46,4 +46,10 @@ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_GCTL 0x24 /* Global Control Register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF525.h index d7e2751c6bcc..dc3119e9f663 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF525.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF525.h @@ -10,8 +10,15 @@ /* include all Core registers and bit definitions */ #include "defBF525.h" -/* BF525 is BF522 + USB */ -#include "cdefBF522.h" +/* include core specific register pointer definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ + +/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ +#include "cdefBF52x_base.h" + +/* The following are the #defines needed by ADSP-BF525 that are not in the common header */ /* USB Control Registers */ diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF527.h index c7ba544d50b6..d6579449ee46 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF527.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF527.h @@ -10,8 +10,15 @@ /* include all Core registers and bit definitions */ #include "defBF527.h" -/* BF527 is BF525 + EMAC */ -#include "cdefBF525.h" +/* include core specific register pointer definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ + +/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ +#include "cdefBF52x_base.h" + +/* The following are the #defines needed by ADSP-BF527 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ @@ -178,4 +185,417 @@ #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endpoint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) + +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) + +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endpoint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) + +/* USB Endpoint 1 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) + +/* USB Endpoint 2 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) + +/* USB Endpoint 3 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) + +/* USB Endpoint 4 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) + +/* USB Endpoint 5 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) + +/* USB Endpoint 6 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) + +/* USB Endpoint 7 Control Registers */ + +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) + +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + #endif /* _CDEF_BF527_H */ diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h index 12f2ad45314e..7014dde10dd6 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h @@ -844,7 +844,6 @@ #define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val) #define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS) #define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val) -#define bfin_clear_PPI_STATUS() bfin_write_PPI_STATUS(0xFFFF) #define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY) #define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val) #define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT) @@ -1063,6 +1062,17 @@ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) +/* OTP/FUSE Registers */ + +#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) +#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) +#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) +#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) +#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) +#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) +#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) +#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) + /* Security Registers */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) @@ -1072,6 +1082,17 @@ #define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS) #define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val) +/* OTP Read/Write Data Buffer Registers */ + +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) + /* NFC Registers */ #define bfin_read_NFC_CTL() bfin_read16(NFC_CTL) diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/defBF525.h b/trunk/arch/blackfin/mach-bf527/include/mach/defBF525.h index c136f7032962..82abefc1ef6c 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/defBF525.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/defBF525.h @@ -7,8 +7,15 @@ #ifndef _DEF_BF525_H #define _DEF_BF525_H -/* BF525 is BF522 + USB */ -#include "defBF522.h" +/* Include all Core registers and bit definitions */ +#include + +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */ + +/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ +#include "defBF52x_base.h" + +/* The following are the #defines needed by ADSP-BF525 that are not in the common header */ /* USB Control Registers */ diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/defBF527.h b/trunk/arch/blackfin/mach-bf527/include/mach/defBF527.h index 4dd58fb33156..570a125df025 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/defBF527.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/defBF527.h @@ -7,9 +7,15 @@ #ifndef _DEF_BF527_H #define _DEF_BF527_H -/* BF527 is BF525 + EMAC */ -#include "defBF525.h" +/* Include all Core registers and bit definitions */ +#include +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */ + +/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */ +#include "defBF52x_base.h" + +/* The following are the #defines needed by ADSP-BF527 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ #define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */ @@ -388,4 +394,673 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ +/* USB Control Registers */ + +#define USB_FADDR 0xffc03800 /* Function address register */ +#define USB_POWER 0xffc03804 /* Power management register */ +#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03820 /* USB frame number */ +#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */ + +#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */ + +#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ +#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ +#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ +#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ +#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ +#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ +#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ +#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ + +#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define nENABLE_SUSPENDM 0x0 +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define nSUSPEND_MODE 0x0 +#define RESUME_MODE 0x4 /* DMA Mode */ +#define nRESUME_MODE 0x0 +#define RESET 0x8 /* Reset indicator */ +#define nRESET 0x0 +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define nHS_MODE 0x0 +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define nHS_ENABLE 0x0 +#define SOFT_CONN 0x40 /* Soft connect */ +#define nSOFT_CONN 0x0 +#define ISO_UPDATE 0x80 /* Isochronous update */ +#define nISO_UPDATE 0x0 + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define nEP0_TX 0x0 +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define nEP1_TX 0x0 +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define nEP2_TX 0x0 +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define nEP3_TX 0x0 +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define nEP4_TX 0x0 +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define nEP5_TX 0x0 +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define nEP6_TX 0x0 +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ +#define nEP7_TX 0x0 + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define nEP1_RX 0x0 +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define nEP2_RX 0x0 +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define nEP3_RX 0x0 +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define nEP4_RX 0x0 +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define nEP5_RX 0x0 +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define nEP6_RX 0x0 +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ +#define nEP7_RX 0x0 + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define nEP0_TX_E 0x0 +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define nEP1_TX_E 0x0 +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define nEP2_TX_E 0x0 +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define nEP3_TX_E 0x0 +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define nEP4_TX_E 0x0 +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define nEP5_TX_E 0x0 +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define nEP6_TX_E 0x0 +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ +#define nEP7_TX_E 0x0 + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define nEP1_RX_E 0x0 +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define nEP2_RX_E 0x0 +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define nEP3_RX_E 0x0 +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define nEP4_RX_E 0x0 +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define nEP5_RX_E 0x0 +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define nEP6_RX_E 0x0 +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ +#define nEP7_RX_E 0x0 + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define nSUSPEND_B 0x0 +#define RESUME_B 0x2 /* Resume indicator */ +#define nRESUME_B 0x0 +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define nRESET_OR_BABLE_B 0x0 +#define SOF_B 0x8 /* Start of frame */ +#define nSOF_B 0x0 +#define CONN_B 0x10 /* Connection indicator */ +#define nCONN_B 0x0 +#define DISCON_B 0x20 /* Disconnect indicator */ +#define nDISCON_B 0x0 +#define SESSION_REQ_B 0x40 /* Session Request */ +#define nSESSION_REQ_B 0x0 +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ +#define nVBUS_ERROR_B 0x0 + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define nSUSPEND_BE 0x0 +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define nRESUME_BE 0x0 +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define nRESET_OR_BABLE_BE 0x0 +#define SOF_BE 0x8 /* Start of frame int enable */ +#define nSOF_BE 0x0 +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define nCONN_BE 0x0 +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define nDISCON_BE 0x0 +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define nSESSION_REQ_BE 0x0 +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ +#define nVBUS_ERROR_BE 0x0 + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define nGLOBAL_ENA 0x0 +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define nEP1_TX_ENA 0x0 +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define nEP2_TX_ENA 0x0 +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define nEP3_TX_ENA 0x0 +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define nEP4_TX_ENA 0x0 +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define nEP5_TX_ENA 0x0 +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define nEP6_TX_ENA 0x0 +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define nEP7_TX_ENA 0x0 +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define nEP1_RX_ENA 0x0 +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define nEP2_RX_ENA 0x0 +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define nEP3_RX_ENA 0x0 +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define nEP4_RX_ENA 0x0 +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define nEP5_RX_ENA 0x0 +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define nEP6_RX_ENA 0x0 +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ +#define nEP7_RX_ENA 0x0 + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define nSESSION 0x0 +#define HOST_REQ 0x2 /* Host negotiation request */ +#define nHOST_REQ 0x0 +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define nHOST_MODE 0x0 +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define nVBUS0 0x0 +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define nVBUS1 0x0 +#define LSDEV 0x20 /* Low-speed indicator */ +#define nLSDEV 0x0 +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define nFSDEV 0x0 +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ +#define nB_DEVICE 0x0 + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define nDRIVE_VBUS_ON 0x0 +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define nDRIVE_VBUS_OFF 0x0 +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define nCHRG_VBUS_START 0x0 +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define nCHRG_VBUS_END 0x0 +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define nDISCHRG_VBUS_START 0x0 +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ +#define nDISCHRG_VBUS_END 0x0 + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define nDRIVE_VBUS_ON_ENA 0x0 +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define nDRIVE_VBUS_OFF_ENA 0x0 +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define nCHRG_VBUS_START_ENA 0x0 +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define nCHRG_VBUS_END_ENA 0x0 +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define nDISCHRG_VBUS_START_ENA 0x0 +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ +#define nDISCHRG_VBUS_END_ENA 0x0 + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define nRXPKTRDY 0x0 +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define nTXPKTRDY 0x0 +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define nSTALL_SENT 0x0 +#define DATAEND 0x8 /* Data end indicator */ +#define nDATAEND 0x0 +#define SETUPEND 0x10 /* Setup end */ +#define nSETUPEND 0x0 +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define nSENDSTALL 0x0 +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define nSERVICED_RXPKTRDY 0x0 +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define nSERVICED_SETUPEND 0x0 +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define nFLUSHFIFO 0x0 +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define nSTALL_RECEIVED_H 0x0 +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define nSETUPPKT_H 0x0 +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define nERROR_H 0x0 +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define nREQPKT_H 0x0 +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define nSTATUSPKT_H 0x0 +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ +#define nNAK_TIMEOUT_H 0x0 + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define nTXPKTRDY_T 0x0 +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define nFIFO_NOT_EMPTY_T 0x0 +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define nUNDERRUN_T 0x0 +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define nFLUSHFIFO_T 0x0 +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define nSTALL_SEND_T 0x0 +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define nSTALL_SENT_T 0x0 +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define nCLEAR_DATATOGGLE_T 0x0 +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define nINCOMPTX_T 0x0 +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define nDMAREQMODE_T 0x0 +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define nFORCE_DATATOGGLE_T 0x0 +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define nDMAREQ_ENA_T 0x0 +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define nISO_T 0x0 +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define nAUTOSET_T 0x0 +#define ERROR_TH 0x4 /* error condition host mode */ +#define nERROR_TH 0x0 +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define nSTALL_RECEIVED_TH 0x0 +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ +#define nNAK_TIMEOUT_TH 0x0 + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define nRXPKTRDY_R 0x0 +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define nFIFO_FULL_R 0x0 +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define nOVERRUN_R 0x0 +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define nDATAERROR_R 0x0 +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define nFLUSHFIFO_R 0x0 +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define nSTALL_SEND_R 0x0 +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define nSTALL_SENT_R 0x0 +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define nCLEAR_DATATOGGLE_R 0x0 +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define nINCOMPRX_R 0x0 +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define nDMAREQMODE_R 0x0 +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define nDISNYET_R 0x0 +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define nDMAREQ_ENA_R 0x0 +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define nISO_R 0x0 +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define nAUTOCLEAR_R 0x0 +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define nERROR_RH 0x0 +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define nREQPKT_RH 0x0 +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define nSTALL_RECEIVED_RH 0x0 +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define nINCOMPRX_RH 0x0 +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define nDMAREQMODE_RH 0x0 +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ +#define nAUTOREQ_RH 0x0 + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define nDMA0_INT 0x0 +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define nDMA1_INT 0x0 +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define nDMA2_INT 0x0 +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define nDMA3_INT 0x0 +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define nDMA4_INT 0x0 +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define nDMA5_INT 0x0 +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define nDMA6_INT 0x0 +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ +#define nDMA7_INT 0x0 + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define nDMA_ENA 0x0 +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define nDIRECTION 0x0 +#define MODE 0x4 /* DMA Bus error */ +#define nMODE 0x0 +#define INT_ENA 0x8 /* Interrupt enable */ +#define nINT_ENA 0x0 +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ +#define nBUSERROR 0x0 + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + #endif /* _DEF_BF527_H */ diff --git a/trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h index 8b18b5359210..b9dbb73d7ef0 100644 --- a/trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h +++ b/trunk/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h @@ -586,6 +586,58 @@ ** modifier UNLESS the lower order bits are saved and ORed back in when ** the macro is used. *************************************************************************************/ +/* +** ********************* PLL AND RESET MASKS ****************************************/ +/* PLL_CTL Masks */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* PLL Not Powered */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Enter Deep Sleep Mode */ +#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* VR_CTL Masks */ +#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ +#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ +#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ +#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ +#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 @@ -705,6 +757,66 @@ #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ +/* ********* WATCHDOG TIMER MASKS ******************** */ + +/* Watchdog Timer WDOG_CTL Register Masks */ + +#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ +#define WDEV_RESET 0x0000 /* generate reset event on roll over */ +#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ +#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ +#define WDEV_NONE 0x0006 /* no event on roll over */ +#define WDEN 0x0FF0 /* enable watchdog */ +#define WDDIS 0x0AD0 /* disable watchdog */ +#define WDRO 0x8000 /* watchdog rolled over latch */ + +/* depreciated WDOG_CTL Register Masks for legacy code */ + + +#define ICTL WDEV +#define ENABLE_RESET WDEV_RESET +#define WDOG_RESET WDEV_RESET +#define ENABLE_NMI WDEV_NMI +#define WDOG_NMI WDEV_NMI +#define ENABLE_GPI WDEV_GPI +#define WDOG_GPI WDEV_GPI +#define DISABLE_EVT WDEV_NONE +#define WDOG_NONE WDEV_NONE + +#define TMR_EN WDEN +#define TMR_DIS WDDIS +#define TRO WDRO +#define ICTL_P0 0x01 + #define ICTL_P1 0x02 +#define TRO_P 0x0F + + + +/* *************** REAL TIME CLOCK MASKS **************************/ +/* RTC_STAT and RTC_ALARM Masks */ +#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */ +#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ALARM Macro z=day y=hr x=min w=sec */ +#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F)) + +/* RTC_ICTL and RTC_ISTAT Masks */ +#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */ +#define ALARM 0x0002 /* Alarm Interrupt Enable */ +#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MINUTE 0x0008 /* Minutes Interrupt Enable */ +#define HOUR 0x0010 /* Hours Interrupt Enable */ +#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WRITE_PENDING 0x4000 /* Write Pending Status */ +#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_FAST / RTC_PREN Mask */ +#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */ + + /* ************** UART CONTROLLER MASKS *************************/ /* UARTx_LCR Masks */ #define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ @@ -1269,6 +1381,33 @@ /* ************************** DMA CONTROLLER MASKS ********************************/ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0900 /* Next Descriptor Size */ +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ @@ -1286,6 +1425,13 @@ #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + + /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ /* PPI_CONTROL Masks */ #define PORT_EN 0x0001 /* PPI Port Enable */ @@ -1697,6 +1843,46 @@ #define BNDMODE_CAPT 0x2000 /* boundary capture mode */ #define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */ +/* Bit masks for OTP_CONTROL */ + +#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ +#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ +#define nFIEN 0x0 +#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ +#define nFTESTDEC 0x0 +#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ +#define nFWRTEST 0x0 +#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ +#define nFRDEN 0x0 +#define FWREN 0x8000 /* OTP/Fuse Write Enable */ +#define nFWREN 0x0 + +/* Bit masks for OTP_BEN */ + +#define FBEN 0xffff /* OTP/Fuse Byte Enable */ + +/* Bit masks for OTP_STATUS */ + +#define FCOMP 0x1 /* OTP/Fuse Access Complete */ +#define nFCOMP 0x0 +#define FERROR 0x2 /* OTP/Fuse Access Error */ +#define nFERROR 0x0 +#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ +#define nMMRGLOAD 0x0 +#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ +#define nMMRGLOCK 0x0 +#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ +#define nFPGMEN 0x0 + +/* Bit masks for OTP_TIMING */ + +#define USECDIV 0xff /* Micro Second Divider */ +#define READACC 0x7f00 /* Read Access Time */ +#define CPUMPRL 0x38000 /* Charge Pump Release Time */ +#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ +#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ +#define PGMTIME 0xff000000 /* Program Time */ + /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ diff --git a/trunk/arch/blackfin/mach-bf533/boards/H8606.c b/trunk/arch/blackfin/mach-bf533/boards/H8606.c index 4adceb0bdb6d..43f43a095a99 100644 --- a/trunk/arch/blackfin/mach-bf533/boards/H8606.c +++ b/trunk/arch/blackfin/mach-bf533/boards/H8606.c @@ -166,6 +166,7 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { #if defined(CONFIG_BFIN_SPI_ADC) || defined(CONFIG_BFIN_SPI_ADC_MODULE) /* SPI ADC chip */ static struct bfin5xx_spi_chip spi_adc_chip_info = { + .ctl_reg = 0x1000, .enable_dma = 1, /* use dma transfer with this chip*/ .bits_per_word = 16, }; @@ -173,6 +174,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { #if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) static struct bfin5xx_spi_chip ad1836_spi_chip_info = { + .ctl_reg = 0x1000, .enable_dma = 0, .bits_per_word = 16, }; @@ -256,6 +258,12 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ +#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +static struct platform_device bfin_fb_device = { + .name = "bf537-fb", +}; +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { { diff --git a/trunk/arch/blackfin/mach-bf533/boards/ip0x.c b/trunk/arch/blackfin/mach-bf533/boards/ip0x.c index 8ec42ba35b9e..644be5e5ab6f 100644 --- a/trunk/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/trunk/arch/blackfin/mach-bf533/boards/ip0x.c @@ -20,7 +20,6 @@ #endif #include #include -#include /* * Name the Board for the /proc/cpuinfo @@ -108,6 +107,20 @@ static struct platform_device dm9000_device2 = { #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) static struct bfin5xx_spi_chip mmc_spi_chip_info = { +/* + * CPOL (Clock Polarity) + * 0 - Active high SCK + * 1 - Active low SCK + * CPHA (Clock Phase) Selects transfer format and operation mode + * 0 - SCLK toggles from middle of the first data bit, slave select + * pins controlled by hardware. + * 1 - SCLK toggles from beginning of first data bit, slave select + * pins controller by user software. + * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work + * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0 + * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1 + */ + .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */ .enable_dma = 0, /* if 1 - block!!! */ .bits_per_word = 8, }; diff --git a/trunk/arch/blackfin/mach-bf533/boards/stamp.c b/trunk/arch/blackfin/mach-bf533/boards/stamp.c index 6d68dcfa2da2..82f70efd66e7 100644 --- a/trunk/arch/blackfin/mach-bf533/boards/stamp.c +++ b/trunk/arch/blackfin/mach-bf533/boards/stamp.c @@ -321,6 +321,12 @@ static struct platform_device bfin_spi0_device = { }; #endif /* spi master and devices */ +#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) +static struct platform_device bfin_fb_device = { + .name = "bf537-fb", +}; +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { { diff --git a/trunk/arch/blackfin/mach-bf533/include/mach/defBF532.h b/trunk/arch/blackfin/mach-bf533/include/mach/defBF532.h index e9ff491c0953..02b328eb0e07 100644 --- a/trunk/arch/blackfin/mach-bf533/include/mach/defBF532.h +++ b/trunk/arch/blackfin/mach-bf533/include/mach/defBF532.h @@ -370,6 +370,72 @@ /* System MMR Register Bits */ /******************************************************************************* */ +/* ********************* PLL AND RESET MASKS ************************ */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x0008 /* Core clock off */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */ +#if !defined(__ADSPBF538__) +/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */ +# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#endif +#define BYPASS 0x0100 /* Bypass the PLL */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ + +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ + +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5 */ +#define GAIN_10 0x0004 /* GAIN = 10 */ +#define GAIN_20 0x0008 /* GAIN = 20 */ +#define GAIN_50 0x000C /* GAIN = 50 */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 @@ -637,7 +703,54 @@ /* ********** DMA CONTROLLER MASKS *********************8 */ -/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ +/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define DMAFLOW 0x00007000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ + +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + +/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ diff --git a/trunk/arch/blackfin/mach-bf537/boards/pnav10.c b/trunk/arch/blackfin/mach-bf537/boards/pnav10.c index 4e0afda472ab..9ba290466b56 100644 --- a/trunk/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/trunk/arch/blackfin/mach-bf537/boards/pnav10.c @@ -13,6 +13,9 @@ #include #include #include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif #include #include #include @@ -144,6 +147,45 @@ static struct platform_device sl811_hcd_device = { }; #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +static struct resource isp1362_hcd_resources[] = { + { + .start = 0x20360000, + .end = 0x20360000, + .flags = IORESOURCE_MEM, + }, { + .start = 0x20360004, + .end = 0x20360004, + .flags = IORESOURCE_MEM, + }, { + .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", @@ -450,6 +492,10 @@ static struct platform_device *stamp_devices[] __initdata = { &sl811_hcd_device, #endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) + &isp1362_hcd_device, +#endif + #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, #endif diff --git a/trunk/arch/blackfin/mach-bf537/boards/stamp.c b/trunk/arch/blackfin/mach-bf537/boards/stamp.c index ac9b52e0087c..c46baa5e6d9b 100644 --- a/trunk/arch/blackfin/mach-bf537/boards/stamp.c +++ b/trunk/arch/blackfin/mach-bf537/boards/stamp.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include #include -#include -#include #include #include #include @@ -68,7 +65,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -79,6 +76,7 @@ static struct platform_device bfin_isp1760_device = { #endif #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#include #include static struct gpio_keys_button bfin_gpio_keys_table[] = { @@ -197,6 +195,28 @@ static struct platform_device dm9000_device = { }; #endif +#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) +static struct resource ax88180_resources[] = { + [0] = { + .start = 0x20300000, + .end = 0x20300000 + 0x8000, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PF7, + .end = IRQ_PF7, + .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL), + }, +}; + +static struct platform_device ax88180_device = { + .name = "ax88180", + .id = -1, + .num_resources = ARRAY_SIZE(ax88180_resources), + .resource = ax88180_resources, +}; +#endif + #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) static struct resource sl811_hcd_resources[] = { { @@ -252,8 +272,8 @@ static struct resource isp1362_hcd_resources[] = { .end = 0x20360004, .flags = IORESOURCE_MEM, }, { - .start = IRQ_PF3, - .end = IRQ_PF3, + .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, + .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, }, }; @@ -280,44 +300,6 @@ static struct platform_device isp1362_hcd_device = { }; #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN_RX, - .end = IRQ_CAN_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_TX, - .end = IRQ_CAN_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_ERROR, - .end = IRQ_CAN_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif - #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) static struct platform_device bfin_mii_bus = { .name = "bfin_mii_bus", @@ -532,14 +514,15 @@ static struct bfin5xx_spi_chip ad1938_spi_chip_info = { }; #endif -#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) +#if defined(CONFIG_INPUT_EVAL_AD7147EBZ) +#include #include static struct bfin5xx_spi_chip ad7147_spi_chip_info = { .enable_dma = 0, .bits_per_word = 16, }; -static struct ad714x_slider_plat ad7147_spi_slider_plat[] = { +static struct ad714x_slider_plat slider_plat[] = { { .start_stage = 0, .end_stage = 7, @@ -547,7 +530,7 @@ static struct ad714x_slider_plat ad7147_spi_slider_plat[] = { }, }; -static struct ad714x_button_plat ad7147_spi_button_plat[] = { +static struct ad714x_button_plat button_plat[] = { { .keycode = BTN_FORWARD, .l_mask = 0, @@ -574,11 +557,11 @@ static struct ad714x_button_plat ad7147_spi_button_plat[] = { .h_mask = 0x400, }, }; -static struct ad714x_platform_data ad7147_spi_platform_data = { +static struct ad714x_platform_data ad7147_platfrom_data = { .slider_num = 1, .button_num = 5, - .slider = ad7147_spi_slider_plat, - .button = ad7147_spi_button_plat, + .slider = slider_plat, + .button = button_plat, .stage_cfg_reg = { {0xFBFF, 0x1FFF, 0, 0x2626, 1600, 1600, 1600, 1600}, {0xEFFF, 0x1FFF, 0, 0x2626, 1650, 1650, 1650, 1650}, @@ -597,9 +580,10 @@ static struct ad714x_platform_data ad7147_spi_platform_data = { }; #endif -#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE) +#if defined(CONFIG_INPUT_EVAL_AD7142EB) +#include #include -static struct ad714x_button_plat ad7142_i2c_button_plat[] = { +static struct ad714x_button_plat button_plat[] = { { .keycode = BTN_1, .l_mask = 0, @@ -621,9 +605,9 @@ static struct ad714x_button_plat ad7142_i2c_button_plat[] = { .h_mask = 0x8, }, }; -static struct ad714x_platform_data ad7142_i2c_platform_data = { +static struct ad714x_platform_data ad7142_platfrom_data = { .button_num = 4, - .button = ad7142_i2c_button_plat, + .button = button_plat, .stage_cfg_reg = { /* fixme: figure out right setting for all comoponent according * to hardware feature of EVAL-AD7142EB board */ @@ -712,7 +696,8 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = { #endif #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) -#include +#include +#include static const struct adxl34x_platform_data adxl34x_info = { .x_axis_offset = 0, .y_axis_offset = 0, @@ -736,7 +721,9 @@ static const struct adxl34x_platform_data adxl34x_info = { .ev_code_y = ABS_Y, /* EV_REL */ .ev_code_z = ABS_Z, /* EV_REL */ - .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ + .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ + .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */ + .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */ /* .ev_code_ff = KEY_F,*/ /* EV_KEY */ /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ @@ -774,47 +761,6 @@ static struct bfin5xx_spi_chip enc28j60_spi_chip_info = { }; #endif -#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) -static struct bfin5xx_spi_chip adf7021_spi_chip_info = { - .bits_per_word = 16, - .cs_gpio = GPIO_PF10, -}; - -#include -#define TXREG 0x0160A470 -static const u32 adf7021_regs[] = { - 0x09608FA0, - 0x00575011, - 0x00A7F092, - 0x2B141563, - 0x81F29E94, - 0x00003155, - 0x050A4F66, - 0x00000007, - 0x00000008, - 0x000231E9, - 0x3296354A, - 0x891A2B3B, - 0x00000D9C, - 0x0000000D, - 0x0000000E, - 0x0000000F, -}; - -static struct adf702x_platform_data adf7021_platform_data = { - .regs_base = (void *)SPORT1_TCR1, - .dma_ch_rx = CH_SPORT1_RX, - .dma_ch_tx = CH_SPORT1_TX, - .irq_sport_err = IRQ_SPORT1_ERROR, - .gpio_int_rfs = GPIO_PF8, - .pin_req = {P_SPORT1_DTPRI, P_SPORT1_RFS, P_SPORT1_DRPRI, - P_SPORT1_RSCLK, P_SPORT1_TSCLK, 0}, - .adf702x_model = MODEL_ADF7021, - .adf702x_regs = adf7021_regs, - .tx_reg = TXREG, -}; -#endif - #if defined(CONFIG_MTD_DATAFLASH) \ || defined(CONFIG_MTD_DATAFLASH_MODULE) @@ -848,13 +794,6 @@ static struct bfin5xx_spi_chip data_flash_chip_info = { }; #endif -#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) -static struct bfin5xx_spi_chip spi_adxl34x_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip*/ - .bits_per_word = 8, -}; -#endif - static struct spi_board_info bfin_spi_board_info[] __initdata = { #if defined(CONFIG_MTD_M25P80) \ || defined(CONFIG_MTD_M25P80_MODULE) @@ -916,7 +855,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { }, #endif -#if defined(CONFIG_INPUT_AD714X_SPI) || defined(CONFIG_INPUT_AD714X_SPI_MODULE) +#if defined(CONFIG_INPUT_EVAL_AD7147EBZ) { .modalias = "ad714x_captouch", .max_speed_hz = 1000000, /* max spi clock (SCK) speed in HZ */ @@ -924,7 +863,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .bus_num = 0, .chip_select = 5, .mode = SPI_MODE_3, - .platform_data = &ad7147_spi_platform_data, + .platform_data = &ad7147_platfrom_data, .controller_data = &ad7147_spi_chip_info, }, #endif @@ -993,30 +932,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_MODE_0, }, #endif -#if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE) - { - .modalias = "adxl34x", - .platform_data = &adxl34x_info, - .irq = IRQ_PF6, - .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 2, - .controller_data = &spi_adxl34x_chip_info, - .mode = SPI_MODE_3, - }, -#endif -#if defined(CONFIG_ADF702X) || defined(CONFIG_ADF702X_MODULE) - { - .modalias = "adf702x", - .max_speed_hz = 16000000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 0, /* GPIO controlled SSEL */ - .controller_data = &adf7021_spi_chip_info, - .platform_data = &adf7021_platform_data, - .mode = SPI_MODE_0, - }, -#endif - }; #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) @@ -1260,6 +1175,7 @@ static struct platform_device i2c_bfin_twi_device = { #endif #if defined(CONFIG_KEYBOARD_ADP5588) || defined(CONFIG_KEYBOARD_ADP5588_MODULE) +#include #include static const unsigned short adp5588_keymap[ADP5588_KEYMAPSIZE] = { [0] = KEY_GRAVE, @@ -1352,33 +1268,35 @@ static struct adp5588_kpad_platform_data adp5588_kpad_data = { * ADP5520/5501 Backlight Data */ -static struct adp5520_backlight_platform_data adp5520_backlight_data = { - .fade_in = ADP5520_FADE_T_1200ms, - .fade_out = ADP5520_FADE_T_1200ms, - .fade_led_law = ADP5520_BL_LAW_LINEAR, - .en_ambl_sens = 1, - .abml_filt = ADP5520_BL_AMBL_FILT_640ms, - .l1_daylight_max = ADP5520_BL_CUR_mA(15), - .l1_daylight_dim = ADP5520_BL_CUR_mA(0), - .l2_office_max = ADP5520_BL_CUR_mA(7), - .l2_office_dim = ADP5520_BL_CUR_mA(0), - .l3_dark_max = ADP5520_BL_CUR_mA(3), - .l3_dark_dim = ADP5520_BL_CUR_mA(0), - .l2_trip = ADP5520_L2_COMP_CURR_uA(700), - .l2_hyst = ADP5520_L2_COMP_CURR_uA(50), - .l3_trip = ADP5520_L3_COMP_CURR_uA(80), - .l3_hyst = ADP5520_L3_COMP_CURR_uA(20), +static struct adp5520_backlight_platfrom_data adp5520_backlight_data = { + .fade_in = FADE_T_1200ms, + .fade_out = FADE_T_1200ms, + .fade_led_law = BL_LAW_LINEAR, + .en_ambl_sens = 1, + .abml_filt = BL_AMBL_FILT_640ms, + .l1_daylight_max = BL_CUR_mA(15), + .l1_daylight_dim = BL_CUR_mA(0), + .l2_office_max = BL_CUR_mA(7), + .l2_office_dim = BL_CUR_mA(0), + .l3_dark_max = BL_CUR_mA(3), + .l3_dark_dim = BL_CUR_mA(0), + .l2_trip = L2_COMP_CURR_uA(700), + .l2_hyst = L2_COMP_CURR_uA(50), + .l3_trip = L3_COMP_CURR_uA(80), + .l3_hyst = L3_COMP_CURR_uA(20), }; /* * ADP5520/5501 LEDs Data */ +#include + static struct led_info adp5520_leds[] = { { .name = "adp5520-led1", .default_trigger = "none", - .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | ADP5520_LED_OFFT_600ms, + .flags = FLAG_ID_ADP5520_LED1_ADP5501_LED0 | LED_OFFT_600ms, }, #ifdef ADP5520_EN_ALL_LEDS { @@ -1394,50 +1312,51 @@ static struct led_info adp5520_leds[] = { #endif }; -static struct adp5520_leds_platform_data adp5520_leds_data = { +static struct adp5520_leds_platfrom_data adp5520_leds_data = { .num_leds = ARRAY_SIZE(adp5520_leds), .leds = adp5520_leds, - .fade_in = ADP5520_FADE_T_600ms, - .fade_out = ADP5520_FADE_T_600ms, - .led_on_time = ADP5520_LED_ONT_600ms, + .fade_in = FADE_T_600ms, + .fade_out = FADE_T_600ms, + .led_on_time = LED_ONT_600ms, }; /* * ADP5520 GPIO Data */ -static struct adp5520_gpio_platform_data adp5520_gpio_data = { +static struct adp5520_gpio_platfrom_data adp5520_gpio_data = { .gpio_start = 50, - .gpio_en_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2, - .gpio_pullup_mask = ADP5520_GPIO_C1 | ADP5520_GPIO_C2 | ADP5520_GPIO_R2, + .gpio_en_mask = GPIO_C1 | GPIO_C2 | GPIO_R2, + .gpio_pullup_mask = GPIO_C1 | GPIO_C2 | GPIO_R2, }; /* * ADP5520 Keypad Data */ +#include static const unsigned short adp5520_keymap[ADP5520_KEYMAPSIZE] = { - [ADP5520_KEY(0, 0)] = KEY_GRAVE, - [ADP5520_KEY(0, 1)] = KEY_1, - [ADP5520_KEY(0, 2)] = KEY_2, - [ADP5520_KEY(0, 3)] = KEY_3, - [ADP5520_KEY(1, 0)] = KEY_4, - [ADP5520_KEY(1, 1)] = KEY_5, - [ADP5520_KEY(1, 2)] = KEY_6, - [ADP5520_KEY(1, 3)] = KEY_7, - [ADP5520_KEY(2, 0)] = KEY_8, - [ADP5520_KEY(2, 1)] = KEY_9, - [ADP5520_KEY(2, 2)] = KEY_0, - [ADP5520_KEY(2, 3)] = KEY_MINUS, - [ADP5520_KEY(3, 0)] = KEY_EQUAL, - [ADP5520_KEY(3, 1)] = KEY_BACKSLASH, - [ADP5520_KEY(3, 2)] = KEY_BACKSPACE, - [ADP5520_KEY(3, 3)] = KEY_ENTER, -}; - -static struct adp5520_keys_platform_data adp5520_keys_data = { - .rows_en_mask = ADP5520_ROW_R3 | ADP5520_ROW_R2 | ADP5520_ROW_R1 | ADP5520_ROW_R0, - .cols_en_mask = ADP5520_COL_C3 | ADP5520_COL_C2 | ADP5520_COL_C1 | ADP5520_COL_C0, + [KEY(0, 0)] = KEY_GRAVE, + [KEY(0, 1)] = KEY_1, + [KEY(0, 2)] = KEY_2, + [KEY(0, 3)] = KEY_3, + [KEY(1, 0)] = KEY_4, + [KEY(1, 1)] = KEY_5, + [KEY(1, 2)] = KEY_6, + [KEY(1, 3)] = KEY_7, + [KEY(2, 0)] = KEY_8, + [KEY(2, 1)] = KEY_9, + [KEY(2, 2)] = KEY_0, + [KEY(2, 3)] = KEY_MINUS, + [KEY(3, 0)] = KEY_EQUAL, + [KEY(3, 1)] = KEY_BACKSLASH, + [KEY(3, 2)] = KEY_BACKSPACE, + [KEY(3, 3)] = KEY_ENTER, +}; + +static struct adp5520_keys_platfrom_data adp5520_keys_data = { + .rows_en_mask = ROW_R3 | ROW_R2 | ROW_R1 | ROW_R0, + .cols_en_mask = COL_C3 | COL_C2 | COL_C1 | COL_C0, .keymap = adp5520_keymap, .keymapsize = ARRAY_SIZE(adp5520_keymap), .repeat = 0, @@ -1447,81 +1366,50 @@ static struct adp5520_keys_platform_data adp5520_keys_data = { * ADP5520/5501 Multifuction Device Init Data */ +static struct adp5520_subdev_info adp5520_subdevs[] = { + { + .name = "adp5520-backlight", + .id = ID_ADP5520, + .platform_data = &adp5520_backlight_data, + }, + { + .name = "adp5520-led", + .id = ID_ADP5520, + .platform_data = &adp5520_leds_data, + }, + { + .name = "adp5520-gpio", + .id = ID_ADP5520, + .platform_data = &adp5520_gpio_data, + }, + { + .name = "adp5520-keys", + .id = ID_ADP5520, + .platform_data = &adp5520_keys_data, + }, +}; + static struct adp5520_platform_data adp5520_pdev_data = { - .backlight = &adp5520_backlight_data, - .leds = &adp5520_leds_data, - .gpio = &adp5520_gpio_data, - .keys = &adp5520_keys_data, + .num_subdevs = ARRAY_SIZE(adp5520_subdevs), + .subdevs = adp5520_subdevs, }; #endif #if defined(CONFIG_GPIO_ADP5588) || defined(CONFIG_GPIO_ADP5588_MODULE) #include -static struct adp5588_gpio_platform_data adp5588_gpio_data = { +static struct adp5588_gpio_platfrom_data adp5588_gpio_data = { .gpio_start = 50, .pullup_dis_mask = 0, }; #endif -#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE) -#include -static struct led_info adp8870_leds[] = { - { - .name = "adp8870-led7", - .default_trigger = "none", - .flags = ADP8870_LED_D7 | ADP8870_LED_OFFT_600ms, - }, -}; - - -static struct adp8870_backlight_platform_data adp8870_pdata = { - .bl_led_assign = ADP8870_BL_D1 | ADP8870_BL_D2 | ADP8870_BL_D3 | - ADP8870_BL_D4 | ADP8870_BL_D5 | ADP8870_BL_D6, /* 1 = Backlight 0 = Individual LED */ - .pwm_assign = 0, /* 1 = Enables PWM mode */ - - .bl_fade_in = ADP8870_FADE_T_1200ms, /* Backlight Fade-In Timer */ - .bl_fade_out = ADP8870_FADE_T_1200ms, /* Backlight Fade-Out Timer */ - .bl_fade_law = ADP8870_FADE_LAW_CUBIC1, /* fade-on/fade-off transfer characteristic */ - - .en_ambl_sens = 1, /* 1 = enable ambient light sensor */ - .abml_filt = ADP8870_BL_AMBL_FILT_320ms, /* Light sensor filter time */ - - .l1_daylight_max = ADP8870_BL_CUR_mA(20), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l1_daylight_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l2_bright_max = ADP8870_BL_CUR_mA(14), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l2_bright_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l3_office_max = ADP8870_BL_CUR_mA(6), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l3_office_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l4_indoor_max = ADP8870_BL_CUR_mA(3), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l4_indor_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l5_dark_max = ADP8870_BL_CUR_mA(2), /* use BL_CUR_mA(I) 0 <= I <= 30 mA */ - .l5_dark_dim = ADP8870_BL_CUR_mA(0), /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */ - - .l2_trip = ADP8870_L2_COMP_CURR_uA(710), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ - .l2_hyst = ADP8870_L2_COMP_CURR_uA(73), /* use L2_COMP_CURR_uA(I) 0 <= I <= 1106 uA */ - .l3_trip = ADP8870_L3_COMP_CURR_uA(389), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */ - .l3_hyst = ADP8870_L3_COMP_CURR_uA(54), /* use L3_COMP_CURR_uA(I) 0 <= I <= 551 uA */ - .l4_trip = ADP8870_L4_COMP_CURR_uA(167), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */ - .l4_hyst = ADP8870_L4_COMP_CURR_uA(16), /* use L4_COMP_CURR_uA(I) 0 <= I <= 275 uA */ - .l5_trip = ADP8870_L5_COMP_CURR_uA(43), /* use L5_COMP_CURR_uA(I) 0 <= I <= 138 uA */ - .l5_hyst = ADP8870_L5_COMP_CURR_uA(11), /* use L6_COMP_CURR_uA(I) 0 <= I <= 138 uA */ - - .leds = adp8870_leds, - .num_leds = ARRAY_SIZE(adp8870_leds), - .led_fade_law = ADP8870_FADE_LAW_SQUARE, /* fade-on/fade-off transfer characteristic */ - .led_fade_in = ADP8870_FADE_T_600ms, - .led_fade_out = ADP8870_FADE_T_600ms, - .led_on_time = ADP8870_LED_ONT_200ms, -}; -#endif - static struct i2c_board_info __initdata bfin_i2c_board_info[] = { -#if defined(CONFIG_INPUT_AD714X_I2C) || defined(CONFIG_INPUT_AD714X_I2C_MODULE) +#if defined(CONFIG_INPUT_EVAL_AD7142EB) { I2C_BOARD_INFO("ad7142_captouch", 0x2C), .irq = IRQ_PG5, - .platform_data = (void *)&ad7142_i2c_platform_data, + .platform_data = (void *)&ad7142_platfrom_data, }, #endif #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE) @@ -1574,32 +1462,6 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = { I2C_BOARD_INFO("bfin-adv7393", 0x2B), }, #endif -#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) - { - I2C_BOARD_INFO("bf537-lq035-ad5280", 0x2C), - }, -#endif -#if defined(CONFIG_BACKLIGHT_ADP8870) || defined(CONFIG_BACKLIGHT_ADP8870_MODULE) - { - I2C_BOARD_INFO("adp8870", 0x2B), - .platform_data = (void *)&adp8870_pdata, - }, -#endif -#if defined(CONFIG_SND_SOC_ADAU1371) || defined(CONFIG_SND_SOC_ADAU1371_MODULE) - { - I2C_BOARD_INFO("adau1371", 0x1A), - }, -#endif -#if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE) - { - I2C_BOARD_INFO("adau1761", 0x38), - }, -#endif -#if defined(CONFIG_AD525X_DPOT) || defined(CONFIG_AD525X_DPOT_MODULE) - { - I2C_BOARD_INFO("ad5258", 0x18), - }, -#endif }; #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) @@ -1740,8 +1602,8 @@ static struct platform_device *stamp_devices[] __initdata = { &dm9000_device, #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) - &bfin_can_device, +#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) + &ax88180_device, #endif #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) diff --git a/trunk/arch/blackfin/mach-bf537/include/mach/bf537.h b/trunk/arch/blackfin/mach-bf537/include/mach/bf537.h index 8b291418ca32..17fab4474669 100644 --- a/trunk/arch/blackfin/mach-bf537/include/mach/bf537.h +++ b/trunk/arch/blackfin/mach-bf537/include/mach/bf537.h @@ -9,6 +9,16 @@ #ifndef __MACH_BF537_H__ #define __MACH_BF537_H__ +/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */ + +#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */ +#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORTx_STAT */ +#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ +#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ +#define UART_ERR_MASK_STAT1 (0x4) /* UARTx_IIR */ +#define UART_ERR_MASK_STAT0 (0x2) /* UARTx_IIR */ +#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ + #define OFFSET_(x) ((x) & 0x0000FFFF) /*some misc defines*/ diff --git a/trunk/arch/blackfin/mach-bf537/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf537/include/mach/blackfin.h index a12d4b6a221d..eab006d260c5 100644 --- a/trunk/arch/blackfin/mach-bf537/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf537/include/mach/blackfin.h @@ -40,4 +40,10 @@ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_GCTL 0x24 /* Global Control Register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h b/trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h index 066d5c261f47..a6d20ca57683 100644 --- a/trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h +++ b/trunk/arch/blackfin/mach-bf537/include/mach/defBF534.h @@ -958,6 +958,67 @@ ** modifier UNLESS the lower order bits are saved and ORed back in when ** the macro is used. *************************************************************************************/ +/* +** ********************* PLL AND RESET MASKS ****************************************/ +/* PLL_CTL Masks */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* PLL Not Powered */ +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Enter Deep Sleep Mode */ +#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */ +#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ +/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */ +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ +/* PLL_DIV Macros */ +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ + +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5 */ +#define GAIN_10 0x0004 /* GAIN = 10 */ +#define GAIN_20 0x0008 /* GAIN = 20 */ +#define GAIN_50 0x000C /* GAIN = 50 */ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ +#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ +#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ +#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ +#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 @@ -1584,6 +1645,34 @@ #define BGSTAT 0x0020 /* Bus Grant Status */ /* ************************** DMA CONTROLLER MASKS ********************************/ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* DMA Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */ +#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */ +#define RESTART 0x0020 /* DMA Buffer Clear */ +#define DI_SEL 0x0040 /* Data Interrupt Timing Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x0900 /* Next Descriptor Size */ + +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */ @@ -1601,6 +1690,12 @@ #define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */ #define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */ +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */ +#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */ + /* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/ /* PPI_CONTROL Masks */ #define PORT_EN 0x0001 /* PPI Port Enable */ diff --git a/trunk/arch/blackfin/mach-bf538/Makefile b/trunk/arch/blackfin/mach-bf538/Makefile index c0be54f2cd2b..8cd2719684db 100644 --- a/trunk/arch/blackfin/mach-bf538/Makefile +++ b/trunk/arch/blackfin/mach-bf538/Makefile @@ -3,4 +3,3 @@ # obj-y := ints-priority.o dma.o -obj-$(CONFIG_GPIOLIB) += ext-gpio.o diff --git a/trunk/arch/blackfin/mach-bf538/boards/ezkit.c b/trunk/arch/blackfin/mach-bf538/boards/ezkit.c index c296bb1ed503..14af5c2088d4 100644 --- a/trunk/arch/blackfin/mach-bf538/boards/ezkit.c +++ b/trunk/arch/blackfin/mach-bf538/boards/ezkit.c @@ -151,44 +151,6 @@ static struct platform_device bfin_sir2_device = { #endif #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN_RX, - .end = IRQ_CAN_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_TX, - .end = IRQ_CAN_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN_ERROR, - .end = IRQ_CAN_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif - /* * USB-LAN EzExtender board * Driver needs to know address, irq and flag pin. @@ -648,10 +610,6 @@ static struct platform_device *cm_bf538_devices[] __initdata = { #endif #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) - &bfin_can_device, -#endif - #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) &smc91x_device, #endif diff --git a/trunk/arch/blackfin/mach-bf538/ext-gpio.c b/trunk/arch/blackfin/mach-bf538/ext-gpio.c deleted file mode 100644 index 180b1252679f..000000000000 --- a/trunk/arch/blackfin/mach-bf538/ext-gpio.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * GPIOLIB interface for BF538/9 PORT C, D, and E GPIOs - * - * Copyright 2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#include -#include -#include -#include -#include - -#define DEFINE_REG(reg, off) \ -static inline u16 read_##reg(void __iomem *port) \ - { return bfin_read16(port + off); } \ -static inline void write_##reg(void __iomem *port, u16 v) \ - { bfin_write16(port + off, v); } - -DEFINE_REG(PORTIO, 0x00) -DEFINE_REG(PORTIO_CLEAR, 0x10) -DEFINE_REG(PORTIO_SET, 0x20) -DEFINE_REG(PORTIO_DIR, 0x40) -DEFINE_REG(PORTIO_INEN, 0x50) - -static void __iomem *gpio_chip_to_mmr(struct gpio_chip *chip) -{ - switch (chip->base) { - default: /* not really needed, but keeps gcc happy */ - case GPIO_PC0: return (void __iomem *)PORTCIO; - case GPIO_PD0: return (void __iomem *)PORTDIO; - case GPIO_PE0: return (void __iomem *)PORTEIO; - } -} - -static int bf538_gpio_get_value(struct gpio_chip *chip, unsigned gpio) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - return !!(read_PORTIO(port) & (1u << gpio)); -} - -static void bf538_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - if (value) - write_PORTIO_SET(port, (1u << gpio)); - else - write_PORTIO_CLEAR(port, (1u << gpio)); -} - -static int bf538_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - write_PORTIO_DIR(port, read_PORTIO_DIR(port) & ~(1u << gpio)); - write_PORTIO_INEN(port, read_PORTIO_INEN(port) | (1u << gpio)); - return 0; -} - -static int bf538_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value) -{ - void __iomem *port = gpio_chip_to_mmr(chip); - write_PORTIO_INEN(port, read_PORTIO_INEN(port) & ~(1u << gpio)); - bf538_gpio_set_value(port, gpio, value); - write_PORTIO_DIR(port, read_PORTIO_DIR(port) | (1u << gpio)); - return 0; -} - -static int bf538_gpio_request(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_special_gpio_request(chip->base + gpio, chip->label); -} - -static void bf538_gpio_free(struct gpio_chip *chip, unsigned gpio) -{ - return bfin_special_gpio_free(chip->base + gpio); -} - -/* We don't set the irq fields as these banks cannot generate interrupts */ - -static struct gpio_chip bf538_portc_chip = { - .label = "GPIO-PC", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PC0, - .ngpio = GPIO_PC9 - GPIO_PC0 + 1, -}; - -static struct gpio_chip bf538_portd_chip = { - .label = "GPIO-PD", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PD0, - .ngpio = GPIO_PD13 - GPIO_PD0 + 1, -}; - -static struct gpio_chip bf538_porte_chip = { - .label = "GPIO-PE", - .direction_input = bf538_gpio_direction_input, - .get = bf538_gpio_get_value, - .direction_output = bf538_gpio_direction_output, - .set = bf538_gpio_set_value, - .request = bf538_gpio_request, - .free = bf538_gpio_free, - .base = GPIO_PE0, - .ngpio = GPIO_PE15 - GPIO_PE0 + 1, -}; - -static int __init bf538_extgpio_setup(void) -{ - return gpiochip_add(&bf538_portc_chip) | - gpiochip_add(&bf538_portd_chip) | - gpiochip_add(&bf538_porte_chip); -} -arch_initcall(bf538_extgpio_setup); diff --git a/trunk/arch/blackfin/mach-bf538/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf538/include/mach/blackfin.h index 08b5eabb1ed5..278e8942eef2 100644 --- a/trunk/arch/blackfin/mach-bf538/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf538/include/mach/blackfin.h @@ -37,4 +37,10 @@ #define OFFSET_SCR 0x1C /* SCR Scratch Register */ #define OFFSET_GCTL 0x24 /* Global Control Register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h b/trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h index fac563e6f62f..5f6c34dfd08e 100644 --- a/trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h +++ b/trunk/arch/blackfin/mach-bf538/include/mach/defBF539.h @@ -468,31 +468,31 @@ /* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ /* GPIO Port C Register Names */ -#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ -#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ -#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ -#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ -#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ -#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ -#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ +#define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */ +#define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */ +#define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */ +#define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */ +#define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */ +#define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ +#define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ /* GPIO Port D Register Names */ -#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ -#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ -#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ -#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ -#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ -#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ -#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ +#define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */ +#define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */ +#define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */ +#define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */ +#define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */ +#define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ +#define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ /* GPIO Port E Register Names */ -#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ -#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ -#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ -#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ -#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ -#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ -#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ +#define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */ +#define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */ +#define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */ +#define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */ +#define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */ +#define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ +#define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ /* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ @@ -1422,6 +1422,81 @@ /* System MMR Register Bits and Macros */ /******************************************************************************* */ +/* ********************* PLL AND RESET MASKS ************************ */ +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */ +#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */ +#define PLL_OFF 0x0002 /* Shut off PLL clocks */ + +#define STOPCK 0x0008 /* Core Clock Off */ +#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */ +#define IN_DELAY 0x0014 /* EBIU Input Delay Select */ +#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */ +#define BYPASS 0x0100 /* Bypass the PLL */ +#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */ + +/* PLL_CTL Macros */ +#ifdef _MISRA_RULES +#define SET_MSEL(x) (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ +#define SET_OUT_DELAY(x) (((x)&0x03u) << 0x6) +#define SET_IN_DELAY(x) ((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2)) +#else +#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */ +#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6) +#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2)) +#endif /* _MISRA_RULES */ + +/* PLL_DIV Masks */ +#define SSEL 0x000F /* System Select */ +#define CSEL 0x0030 /* Core Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ + +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +/* PLL_DIV Macros */ +#ifdef _MISRA_RULES +#define SET_SSEL(x) ((x)&0xFu) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ +#else +#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ +#endif /* _MISRA_RULES */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ + +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5 */ +#define GAIN_10 0x0004 /* GAIN = 10 */ +#define GAIN_20 0x0008 /* GAIN = 20 */ +#define GAIN_50 0x000C /* GAIN = 50 */ + +#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ +#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + /* SWRST Mask */ #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ @@ -1534,6 +1609,91 @@ #endif /* _MISRA_RULES */ +/* ********* WATCHDOG TIMER MASKS ******************** */ +/* Watchdog Timer WDOG_CTL Register Masks */ +#ifdef _MISRA_RULES +#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */ +#else +#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */ +#endif /* _MISRA_RULES */ +#define WDEV_RESET 0x0000 /* generate reset event on roll over */ +#define WDEV_NMI 0x0002 /* generate NMI event on roll over */ +#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */ +#define WDEV_NONE 0x0006 /* no event on roll over */ +#define WDEN 0x0FF0 /* enable watchdog */ +#define WDDIS 0x0AD0 /* disable watchdog */ +#define WDRO 0x8000 /* watchdog rolled over latch */ + +/* deprecated WDOG_CTL Register Masks for legacy code */ +#define ICTL WDEV +#define ENABLE_RESET WDEV_RESET +#define WDOG_RESET WDEV_RESET +#define ENABLE_NMI WDEV_NMI +#define WDOG_NMI WDEV_NMI +#define ENABLE_GPI WDEV_GPI +#define WDOG_GPI WDEV_GPI +#define DISABLE_EVT WDEV_NONE +#define WDOG_NONE WDEV_NONE + +#define TMR_EN WDEN +#define WDOG_DISABLE WDDIS +#define TRO WDRO + +#define ICTL_P0 0x01 +#define ICTL_P1 0x02 +#define TRO_P 0x0F + + +/* *************** REAL TIME CLOCK MASKS **************************/ +/* RTC_STAT and RTC_ALARM register */ +#define RTSEC 0x0000003F /* Real-Time Clock Seconds */ +#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */ +#define RTHR 0x0001F000 /* Real-Time Clock Hours */ +#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */ + +/* RTC_ICTL register */ +#define SWIE 0x0001 /* Stopwatch Interrupt Enable */ +#define AIE 0x0002 /* Alarm Interrupt Enable */ +#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */ +#define MIE 0x0008 /* Minutes Interrupt Enable */ +#define HIE 0x0010 /* Hours Interrupt Enable */ +#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */ +#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WCIE 0x8000 /* Write Complete Interrupt Enable */ + +/* RTC_ISTAT register */ +#define SWEF 0x0001 /* Stopwatch Event Flag */ +#define AEF 0x0002 /* Alarm Event Flag */ +#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */ +#define MEF 0x0008 /* Minutes Event Flag */ +#define HEF 0x0010 /* Hours Event Flag */ +#define DEF 0x0020 /* 24 Hours (Days) Event Flag */ +#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */ +#define WPS 0x4000 /* Write Pending Status (RO) */ +#define WCOM 0x8000 /* Write Complete */ + +/* RTC_FAST Mask (RTC_PREN Mask) */ +#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */ +#define PREN 0x00000001 + /* ** Must be set after power-up for proper operation of RTC */ + +/* Deprecated RTC_STAT and RTC_ALARM Masks */ +#define RTC_SEC RTSEC /* Real-Time Clock Seconds */ +#define RTC_MIN RTMIN /* Real-Time Clock Minutes */ +#define RTC_HR RTHR /* Real-Time Clock Hours */ +#define RTC_DAY RTDAY /* Real-Time Clock Days */ + +/* Deprecated RTC_ICTL/RTC_ISTAT Masks */ +#define STOPWATCH SWIE /* Stopwatch Interrupt Enable */ +#define ALARM AIE /* Alarm Interrupt Enable */ +#define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */ +#define MINUTE MIE /* Minutes Interrupt Enable */ +#define HOUR HIE /* Hours Interrupt Enable */ +#define DAY DIE /* 24 Hours (Days) Interrupt Enable */ +#define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */ +#define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */ + + /* ***************************** UART CONTROLLER MASKS ********************** */ /* UARTx_LCR Register */ #ifdef _MISRA_RULES @@ -1757,6 +1917,52 @@ /* ********** DMA CONTROLLER MASKS ***********************/ +/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */ +#define DMAEN 0x0001 /* Channel Enable */ +#define WNR 0x0002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x0000 /* Word Size 8 bits */ +#define WDSIZE_16 0x0004 /* Word Size 16 bits */ +#define WDSIZE_32 0x0008 /* Word Size 32 bits */ +#define DMA2D 0x0010 /* 2D/1D* Mode */ +#define RESTART 0x0020 /* Restart */ +#define DI_SEL 0x0040 /* Data Interrupt Select */ +#define DI_EN 0x0080 /* Data Interrupt Enable */ +#define NDSIZE 0x0900 /* Next Descriptor Size */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ + +#define DMAFLOW 0x7000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +#define DMAEN_P 0x0 /* Channel Enable */ +#define WNR_P 0x1 /* Channel Direction (W/R*) */ +#define DMA2D_P 0x4 /* 2D/1D* Mode */ +#define RESTART_P 0x5 /* Restart */ +#define DI_SEL_P 0x6 /* Data Interrupt Select */ +#define DI_EN_P 0x7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */ +#define DMA_DONE 0x0001 /* DMA Done Indicator */ +#define DMA_ERR 0x0002 /* DMA Error Indicator */ +#define DFETCH 0x0004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x0008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0x0 /* DMA Done Indicator */ +#define DMA_ERR_P 0x1 /* DMA Error Indicator */ +#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 0x3 /* DMA Running Indicator */ /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ @@ -2419,6 +2625,1019 @@ #define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ +/********************************* MXVR MASKS ****************************************/ + +/* MXVR_CONFIG Masks */ + +#define MXVREN 0x00000001lu +#define MMSM 0x00000002lu +#define ACTIVE 0x00000004lu +#define SDELAY 0x00000008lu +#define NCMRXEN 0x00000010lu +#define RWRRXEN 0x00000020lu +#define MTXEN 0x00000040lu +#define MTXON 0x00000080lu /*legacy*/ +#define MTXONB 0x00000080lu +#define EPARITY 0x00000100lu +#define MSB 0x00001E00lu +#define APRXEN 0x00002000lu +#define WAKEUP 0x00004000lu +#define LMECH 0x00008000lu + +#ifdef _MISRA_RULES +#define SET_MSB(x) (((x)&0xFu) << 0x9) +#else +#define SET_MSB(x) (((x)&0xF) << 0x9) +#endif /* _MISRA_RULES */ + + +/* MXVR_PLL_CTL_0 Masks */ + +#define MXTALCEN 0x00000001lu +#define MXTALFEN 0x00000002lu +#define MPLLMS 0x00000008lu +#define MXTALMUL 0x00000030lu +#define MPLLEN 0x00000040lu +#define MPLLEN0 0x00000040lu /* legacy */ +#define MPLLEN1 0x00000080lu /* legacy */ +#define MMCLKEN 0x00000100lu +#define MMCLKMUL 0x00001E00lu +#define MPLLRSTB 0x00002000lu +#define MPLLRSTB0 0x00002000lu /* legacy */ +#define MPLLRSTB1 0x00004000lu /* legacy */ +#define MBCLKEN 0x00010000lu +#define MBCLKDIV 0x001E0000lu +#define MPLLCDR 0x00200000lu +#define MPLLCDR0 0x00200000lu /* legacy */ +#define MPLLCDR1 0x00400000lu /* legacy */ +#define INVRX 0x00800000lu +#define MFSEN 0x01000000lu +#define MFSDIV 0x1E000000lu +#define MFSSEL 0x60000000lu +#define MFSSYNC 0x80000000lu + +#define MXTALMUL_256FS 0x00000000lu /* legacy */ +#define MXTALMUL_384FS 0x00000010lu /* legacy */ +#define MXTALMUL_512FS 0x00000020lu /* legacy */ +#define MXTALMUL_1024FS 0x00000030lu + +#define MMCLKMUL_1024FS 0x00000000lu +#define MMCLKMUL_512FS 0x00000200lu +#define MMCLKMUL_256FS 0x00000400lu +#define MMCLKMUL_128FS 0x00000600lu +#define MMCLKMUL_64FS 0x00000800lu +#define MMCLKMUL_32FS 0x00000A00lu +#define MMCLKMUL_16FS 0x00000C00lu +#define MMCLKMUL_8FS 0x00000E00lu +#define MMCLKMUL_4FS 0x00001000lu +#define MMCLKMUL_2FS 0x00001200lu +#define MMCLKMUL_1FS 0x00001400lu +#define MMCLKMUL_1536FS 0x00001A00lu +#define MMCLKMUL_768FS 0x00001C00lu +#define MMCLKMUL_384FS 0x00001E00lu + +#define MBCLKDIV_DIV2 0x00020000lu +#define MBCLKDIV_DIV4 0x00040000lu +#define MBCLKDIV_DIV8 0x00060000lu +#define MBCLKDIV_DIV16 0x00080000lu +#define MBCLKDIV_DIV32 0x000A0000lu +#define MBCLKDIV_DIV64 0x000C0000lu +#define MBCLKDIV_DIV128 0x000E0000lu +#define MBCLKDIV_DIV256 0x00100000lu +#define MBCLKDIV_DIV512 0x00120000lu +#define MBCLKDIV_DIV1024 0x00140000lu + +#define MFSDIV_DIV2 0x02000000lu +#define MFSDIV_DIV4 0x04000000lu +#define MFSDIV_DIV8 0x06000000lu +#define MFSDIV_DIV16 0x08000000lu +#define MFSDIV_DIV32 0x0A000000lu +#define MFSDIV_DIV64 0x0C000000lu +#define MFSDIV_DIV128 0x0E000000lu +#define MFSDIV_DIV256 0x10000000lu +#define MFSDIV_DIV512 0x12000000lu +#define MFSDIV_DIV1024 0x14000000lu + +#define MFSSEL_CLOCK 0x00000000lu +#define MFSSEL_PULSE_HI 0x20000000lu +#define MFSSEL_PULSE_LO 0x40000000lu + + +/* MXVR_PLL_CTL_1 Masks */ + +#define MSTO 0x00000001lu +#define MSTO0 0x00000001lu /* legacy */ +#define MHOGGD 0x00000004lu +#define MHOGGD0 0x00000004lu /* legacy */ +#define MHOGGD1 0x00000008lu /* legacy */ +#define MSHAPEREN 0x00000010lu +#define MSHAPEREN0 0x00000010lu /* legacy */ +#define MSHAPEREN1 0x00000020lu /* legacy */ +#define MPLLCNTEN 0x00008000lu +#define MPLLCNT 0xFFFF0000lu + +#ifdef _MISRA_RULES +#define SET_MPLLCNT(x) (((x)&0xFFFFu) << 0x10) +#else +#define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10) +#endif /* _MISRA_RULES */ + + +/* MXVR_PLL_CTL_2 Masks */ + +#define MSHAPERSEL 0x00000007lu +#define MCPSEL 0x000000E0lu + +/* MXVR_INT_STAT_0 Masks */ + +#define NI2A 0x00000001lu +#define NA2I 0x00000002lu +#define SBU2L 0x00000004lu +#define SBL2U 0x00000008lu +#define PRU 0x00000010lu +#define MPRU 0x00000020lu +#define DRU 0x00000040lu +#define MDRU 0x00000080lu +#define SBU 0x00000100lu +#define ATU 0x00000200lu +#define FCZ0 0x00000400lu +#define FCZ1 0x00000800lu +#define PERR 0x00001000lu +#define MH2L 0x00002000lu +#define ML2H 0x00004000lu +#define WUP 0x00008000lu +#define FU2L 0x00010000lu +#define FL2U 0x00020000lu +#define BU2L 0x00040000lu +#define BL2U 0x00080000lu +#define PCZ 0x00400000lu +#define FERR 0x00800000lu +#define CMR 0x01000000lu +#define CMROF 0x02000000lu +#define CMTS 0x04000000lu +#define CMTC 0x08000000lu +#define RWRC 0x10000000lu +#define BCZ 0x20000000lu +#define BMERR 0x40000000lu +#define DERR 0x80000000lu + + +/* MXVR_INT_EN_0 Masks */ + +#define NI2AEN NI2A +#define NA2IEN NA2I +#define SBU2LEN SBU2L +#define SBL2UEN SBL2U +#define PRUEN PRU +#define MPRUEN MPRU +#define DRUEN DRU +#define MDRUEN MDRU +#define SBUEN SBU +#define ATUEN ATU +#define FCZ0EN FCZ0 +#define FCZ1EN FCZ1 +#define PERREN PERR +#define MH2LEN MH2L +#define ML2HEN ML2H +#define WUPEN WUP +#define FU2LEN FU2L +#define FL2UEN FL2U +#define BU2LEN BU2L +#define BL2UEN BL2U +#define PCZEN PCZ +#define FERREN FERR +#define CMREN CMR +#define CMROFEN CMROF +#define CMTSEN CMTS +#define CMTCEN CMTC +#define RWRCEN RWRC +#define BCZEN BCZ +#define BMERREN BMERR +#define DERREN DERR + + +/* MXVR_INT_STAT_1 Masks */ + +#define APR 0x00000004lu +#define APROF 0x00000008lu +#define APTS 0x00000040lu +#define APTC 0x00000080lu +#define APRCE 0x00000400lu +#define APRPE 0x00000800lu + +#define HDONE0 0x00000001lu +#define DONE0 0x00000002lu +#define HDONE1 0x00000010lu +#define DONE1 0x00000020lu +#define HDONE2 0x00000100lu +#define DONE2 0x00000200lu +#define HDONE3 0x00001000lu +#define DONE3 0x00002000lu +#define HDONE4 0x00010000lu +#define DONE4 0x00020000lu +#define HDONE5 0x00100000lu +#define DONE5 0x00200000lu +#define HDONE6 0x01000000lu +#define DONE6 0x02000000lu +#define HDONE7 0x10000000lu +#define DONE7 0x20000000lu + +#define DONEX(x) (0x00000002 << (4 * (x))) +#define HDONEX(x) (0x00000001 << (4 * (x))) + + +/* MXVR_INT_EN_1 Masks */ + +#define APREN APR +#define APROFEN APROF +#define APTSEN APTS +#define APTCEN APTC +#define APRCEEN APRCE +#define APRPEEN APRPE + +#define HDONEEN0 HDONE0 +#define DONEEN0 DONE0 +#define HDONEEN1 HDONE1 +#define DONEEN1 DONE1 +#define HDONEEN2 HDONE2 +#define DONEEN2 DONE2 +#define HDONEEN3 HDONE3 +#define DONEEN3 DONE3 +#define HDONEEN4 HDONE4 +#define DONEEN4 DONE4 +#define HDONEEN5 HDONE5 +#define DONEEN5 DONE5 +#define HDONEEN6 HDONE6 +#define DONEEN6 DONE6 +#define HDONEEN7 HDONE7 +#define DONEEN7 DONE7 + +#define DONEENX(x) (0x00000002 << (4 * (x))) +#define HDONEENX(x) (0x00000001 << (4 * (x))) + + +/* MXVR_STATE_0 Masks */ + +#define NACT 0x00000001lu +#define SBLOCK 0x00000002lu +#define PFDLOCK 0x00000004lu +#define PFDLOCK0 0x00000004lu /* legacy */ +#define PDD 0x00000008lu +#define PDD0 0x00000008lu /* legacy */ +#define PVCO 0x00000010lu +#define PVCO0 0x00000010lu /* legacy */ +#define PFDLOCK1 0x00000020lu /* legacy */ +#define PDD1 0x00000040lu /* legacy */ +#define PVCO1 0x00000080lu /* legacy */ +#define APBSY 0x00000100lu +#define APARB 0x00000200lu +#define APTX 0x00000400lu +#define APRX 0x00000800lu +#define CMBSY 0x00001000lu +#define CMARB 0x00002000lu +#define CMTX 0x00004000lu +#define CMRX 0x00008000lu +#define MRXONB 0x00010000lu +#define RGSIP 0x00020000lu +#define DALIP 0x00040000lu +#define ALIP 0x00080000lu +#define RRDIP 0x00100000lu +#define RWRIP 0x00200000lu +#define FLOCK 0x00400000lu +#define BLOCK 0x00800000lu +#define RSB 0x0F000000lu +#define DERRNUM 0xF0000000lu + + +/* MXVR_STATE_1 Masks */ + +#define STXNUMB 0x0000000Flu +#define SRXNUMB 0x000000F0lu +#define APCONT 0x00000100lu +#define DMAACTIVEX 0x00FF0000lu +#define DMAACTIVE0 0x00010000lu +#define DMAACTIVE1 0x00020000lu +#define DMAACTIVE2 0x00040000lu +#define DMAACTIVE3 0x00080000lu +#define DMAACTIVE4 0x00100000lu +#define DMAACTIVE5 0x00200000lu +#define DMAACTIVE6 0x00400000lu +#define DMAACTIVE7 0x00800000lu +#define DMAPMENX 0xFF000000lu +#define DMAPMEN0 0x01000000lu +#define DMAPMEN1 0x02000000lu +#define DMAPMEN2 0x04000000lu +#define DMAPMEN3 0x08000000lu +#define DMAPMEN4 0x10000000lu +#define DMAPMEN5 0x20000000lu +#define DMAPMEN6 0x40000000lu +#define DMAPMEN7 0x80000000lu + + +/* MXVR_POSITION Masks */ + +#define PVALID 0x8000 +#define POSITION 0x003F + + +/* MXVR_MAX_POSITION Masks */ + +#define MPVALID 0x8000 +#define MPOSITION 0x003F + + +/* MXVR_DELAY Masks */ + +#define DVALID 0x8000 +#define DELAY 0x003F + + +/* MXVR_MAX_DELAY Masks */ + +#define MDVALID 0x8000 +#define MDELAY 0x003F + + +/* MXVR_LADDR Masks */ + +#define LVALID 0x80000000lu +#define LADDR 0x0000FFFFlu + + +/* MXVR_GADDR Masks */ + +#define GVALID 0x8000 +#define GADDRL 0x00FF + + +/* MXVR_AADDR Masks */ + +#define AVALID 0x80000000lu +#define AADDR 0x0000FFFFlu + + +/* MXVR_ALLOC_0 Masks */ + +#define CIU0 0x00000080lu +#define CIU1 0x00008000lu +#define CIU2 0x00800000lu +#define CIU3 0x80000000lu + +#define CL0 0x0000007Flu +#define CL1 0x00007F00lu +#define CL2 0x007F0000lu +#define CL3 0x7F000000lu + + +/* MXVR_ALLOC_1 Masks */ + +#define CIU4 0x00000080lu +#define CIU5 0x00008000lu +#define CIU6 0x00800000lu +#define CIU7 0x80000000lu + +#define CL4 0x0000007Flu +#define CL5 0x00007F00lu +#define CL6 0x007F0000lu +#define CL7 0x7F000000lu + + +/* MXVR_ALLOC_2 Masks */ + +#define CIU8 0x00000080lu +#define CIU9 0x00008000lu +#define CIU10 0x00800000lu +#define CIU11 0x80000000lu + +#define CL8 0x0000007Flu +#define CL9 0x00007F00lu +#define CL10 0x007F0000lu +#define CL11 0x7F000000lu + + +/* MXVR_ALLOC_3 Masks */ + +#define CIU12 0x00000080lu +#define CIU13 0x00008000lu +#define CIU14 0x00800000lu +#define CIU15 0x80000000lu + +#define CL12 0x0000007Flu +#define CL13 0x00007F00lu +#define CL14 0x007F0000lu +#define CL15 0x7F000000lu + + +/* MXVR_ALLOC_4 Masks */ + +#define CIU16 0x00000080lu +#define CIU17 0x00008000lu +#define CIU18 0x00800000lu +#define CIU19 0x80000000lu + +#define CL16 0x0000007Flu +#define CL17 0x00007F00lu +#define CL18 0x007F0000lu +#define CL19 0x7F000000lu + + +/* MXVR_ALLOC_5 Masks */ + +#define CIU20 0x00000080lu +#define CIU21 0x00008000lu +#define CIU22 0x00800000lu +#define CIU23 0x80000000lu + +#define CL20 0x0000007Flu +#define CL21 0x00007F00lu +#define CL22 0x007F0000lu +#define CL23 0x7F000000lu + + +/* MXVR_ALLOC_6 Masks */ + +#define CIU24 0x00000080lu +#define CIU25 0x00008000lu +#define CIU26 0x00800000lu +#define CIU27 0x80000000lu + +#define CL24 0x0000007Flu +#define CL25 0x00007F00lu +#define CL26 0x007F0000lu +#define CL27 0x7F000000lu + + +/* MXVR_ALLOC_7 Masks */ + +#define CIU28 0x00000080lu +#define CIU29 0x00008000lu +#define CIU30 0x00800000lu +#define CIU31 0x80000000lu + +#define CL28 0x0000007Flu +#define CL29 0x00007F00lu +#define CL30 0x007F0000lu +#define CL31 0x7F000000lu + + +/* MXVR_ALLOC_8 Masks */ + +#define CIU32 0x00000080lu +#define CIU33 0x00008000lu +#define CIU34 0x00800000lu +#define CIU35 0x80000000lu + +#define CL32 0x0000007Flu +#define CL33 0x00007F00lu +#define CL34 0x007F0000lu +#define CL35 0x7F000000lu + + +/* MXVR_ALLOC_9 Masks */ + +#define CIU36 0x00000080lu +#define CIU37 0x00008000lu +#define CIU38 0x00800000lu +#define CIU39 0x80000000lu + +#define CL36 0x0000007Flu +#define CL37 0x00007F00lu +#define CL38 0x007F0000lu +#define CL39 0x7F000000lu + + +/* MXVR_ALLOC_10 Masks */ + +#define CIU40 0x00000080lu +#define CIU41 0x00008000lu +#define CIU42 0x00800000lu +#define CIU43 0x80000000lu + +#define CL40 0x0000007Flu +#define CL41 0x00007F00lu +#define CL42 0x007F0000lu +#define CL43 0x7F000000lu + + +/* MXVR_ALLOC_11 Masks */ + +#define CIU44 0x00000080lu +#define CIU45 0x00008000lu +#define CIU46 0x00800000lu +#define CIU47 0x80000000lu + +#define CL44 0x0000007Flu +#define CL45 0x00007F00lu +#define CL46 0x007F0000lu +#define CL47 0x7F000000lu + + +/* MXVR_ALLOC_12 Masks */ + +#define CIU48 0x00000080lu +#define CIU49 0x00008000lu +#define CIU50 0x00800000lu +#define CIU51 0x80000000lu + +#define CL48 0x0000007Flu +#define CL49 0x00007F00lu +#define CL50 0x007F0000lu +#define CL51 0x7F000000lu + + +/* MXVR_ALLOC_13 Masks */ + +#define CIU52 0x00000080lu +#define CIU53 0x00008000lu +#define CIU54 0x00800000lu +#define CIU55 0x80000000lu + +#define CL52 0x0000007Flu +#define CL53 0x00007F00lu +#define CL54 0x007F0000lu +#define CL55 0x7F000000lu + + +/* MXVR_ALLOC_14 Masks */ + +#define CIU56 0x00000080lu +#define CIU57 0x00008000lu +#define CIU58 0x00800000lu +#define CIU59 0x80000000lu + +#define CL56 0x0000007Flu +#define CL57 0x00007F00lu +#define CL58 0x007F0000lu +#define CL59 0x7F000000lu + + +/* MXVR_SYNC_LCHAN_0 Masks */ + +#define LCHANPC0 0x0000000Flu +#define LCHANPC1 0x000000F0lu +#define LCHANPC2 0x00000F00lu +#define LCHANPC3 0x0000F000lu +#define LCHANPC4 0x000F0000lu +#define LCHANPC5 0x00F00000lu +#define LCHANPC6 0x0F000000lu +#define LCHANPC7 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_1 Masks */ + +#define LCHANPC8 0x0000000Flu +#define LCHANPC9 0x000000F0lu +#define LCHANPC10 0x00000F00lu +#define LCHANPC11 0x0000F000lu +#define LCHANPC12 0x000F0000lu +#define LCHANPC13 0x00F00000lu +#define LCHANPC14 0x0F000000lu +#define LCHANPC15 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_2 Masks */ + +#define LCHANPC16 0x0000000Flu +#define LCHANPC17 0x000000F0lu +#define LCHANPC18 0x00000F00lu +#define LCHANPC19 0x0000F000lu +#define LCHANPC20 0x000F0000lu +#define LCHANPC21 0x00F00000lu +#define LCHANPC22 0x0F000000lu +#define LCHANPC23 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_3 Masks */ + +#define LCHANPC24 0x0000000Flu +#define LCHANPC25 0x000000F0lu +#define LCHANPC26 0x00000F00lu +#define LCHANPC27 0x0000F000lu +#define LCHANPC28 0x000F0000lu +#define LCHANPC29 0x00F00000lu +#define LCHANPC30 0x0F000000lu +#define LCHANPC31 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_4 Masks */ + +#define LCHANPC32 0x0000000Flu +#define LCHANPC33 0x000000F0lu +#define LCHANPC34 0x00000F00lu +#define LCHANPC35 0x0000F000lu +#define LCHANPC36 0x000F0000lu +#define LCHANPC37 0x00F00000lu +#define LCHANPC38 0x0F000000lu +#define LCHANPC39 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_5 Masks */ + +#define LCHANPC40 0x0000000Flu +#define LCHANPC41 0x000000F0lu +#define LCHANPC42 0x00000F00lu +#define LCHANPC43 0x0000F000lu +#define LCHANPC44 0x000F0000lu +#define LCHANPC45 0x00F00000lu +#define LCHANPC46 0x0F000000lu +#define LCHANPC47 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_6 Masks */ + +#define LCHANPC48 0x0000000Flu +#define LCHANPC49 0x000000F0lu +#define LCHANPC50 0x00000F00lu +#define LCHANPC51 0x0000F000lu +#define LCHANPC52 0x000F0000lu +#define LCHANPC53 0x00F00000lu +#define LCHANPC54 0x0F000000lu +#define LCHANPC55 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_7 Masks */ + +#define LCHANPC56 0x0000000Flu +#define LCHANPC57 0x000000F0lu +#define LCHANPC58 0x00000F00lu +#define LCHANPC59 0x0000F000lu + + +/* MXVR_DMAx_CONFIG Masks */ + +#define MDMAEN 0x00000001lu +#define DD 0x00000002lu +#define LCHAN 0x000003C0lu +#define BITSWAPEN 0x00000400lu +#define BYSWAPEN 0x00000800lu +#define MFLOW 0x00007000lu +#define FIXEDPM 0x00080000lu +#define STARTPAT 0x00300000lu +#define STOPPAT 0x00C00000lu +#define COUNTPOS 0x1C000000lu + +#define DD_TX 0x00000000lu +#define DD_RX 0x00000002lu + +#define LCHAN_0 0x00000000lu +#define LCHAN_1 0x00000040lu +#define LCHAN_2 0x00000080lu +#define LCHAN_3 0x000000C0lu +#define LCHAN_4 0x00000100lu +#define LCHAN_5 0x00000140lu +#define LCHAN_6 0x00000180lu +#define LCHAN_7 0x000001C0lu + +#define MFLOW_STOP 0x00000000lu +#define MFLOW_AUTO 0x00001000lu +#define MFLOW_PVC 0x00002000lu +#define MFLOW_PSS 0x00003000lu +#define MFLOW_PFC 0x00004000lu + +#define STARTPAT_0 0x00000000lu +#define STARTPAT_1 0x00100000lu + +#define STOPPAT_0 0x00000000lu +#define STOPPAT_1 0x00400000lu + +#define COUNTPOS_0 0x00000000lu +#define COUNTPOS_1 0x04000000lu +#define COUNTPOS_2 0x08000000lu +#define COUNTPOS_3 0x0C000000lu +#define COUNTPOS_4 0x10000000lu +#define COUNTPOS_5 0x14000000lu +#define COUNTPOS_6 0x18000000lu +#define COUNTPOS_7 0x1C000000lu + + +/* MXVR_AP_CTL Masks */ + +#define STARTAP 0x00000001lu +#define CANCELAP 0x00000002lu +#define RESETAP 0x00000004lu +#define APRBE0 0x00004000lu +#define APRBE1 0x00008000lu +#define APRBEX 0x0000C000lu + + +/* MXVR_CM_CTL Masks */ + +#define STARTCM 0x00000001lu +#define CANCELCM 0x00000002lu +#define CMRBEX 0xFFFF0000lu +#define CMRBE0 0x00010000lu +#define CMRBE1 0x00020000lu +#define CMRBE2 0x00040000lu +#define CMRBE3 0x00080000lu +#define CMRBE4 0x00100000lu +#define CMRBE5 0x00200000lu +#define CMRBE6 0x00400000lu +#define CMRBE7 0x00800000lu +#define CMRBE8 0x01000000lu +#define CMRBE9 0x02000000lu +#define CMRBE10 0x04000000lu +#define CMRBE11 0x08000000lu +#define CMRBE12 0x10000000lu +#define CMRBE13 0x20000000lu +#define CMRBE14 0x40000000lu +#define CMRBE15 0x80000000lu + + +/* MXVR_PAT_DATA_x Masks */ + +#define MATCH_DATA_0 0x000000FFlu +#define MATCH_DATA_1 0x0000FF00lu +#define MATCH_DATA_2 0x00FF0000lu +#define MATCH_DATA_3 0xFF000000lu + + + +/* MXVR_PAT_EN_x Masks */ + +#define MATCH_EN_0_0 0x00000001lu +#define MATCH_EN_0_1 0x00000002lu +#define MATCH_EN_0_2 0x00000004lu +#define MATCH_EN_0_3 0x00000008lu +#define MATCH_EN_0_4 0x00000010lu +#define MATCH_EN_0_5 0x00000020lu +#define MATCH_EN_0_6 0x00000040lu +#define MATCH_EN_0_7 0x00000080lu + +#define MATCH_EN_1_0 0x00000100lu +#define MATCH_EN_1_1 0x00000200lu +#define MATCH_EN_1_2 0x00000400lu +#define MATCH_EN_1_3 0x00000800lu +#define MATCH_EN_1_4 0x00001000lu +#define MATCH_EN_1_5 0x00002000lu +#define MATCH_EN_1_6 0x00004000lu +#define MATCH_EN_1_7 0x00008000lu + +#define MATCH_EN_2_0 0x00010000lu +#define MATCH_EN_2_1 0x00020000lu +#define MATCH_EN_2_2 0x00040000lu +#define MATCH_EN_2_3 0x00080000lu +#define MATCH_EN_2_4 0x00100000lu +#define MATCH_EN_2_5 0x00200000lu +#define MATCH_EN_2_6 0x00400000lu +#define MATCH_EN_2_7 0x00800000lu + +#define MATCH_EN_3_0 0x01000000lu +#define MATCH_EN_3_1 0x02000000lu +#define MATCH_EN_3_2 0x04000000lu +#define MATCH_EN_3_3 0x08000000lu +#define MATCH_EN_3_4 0x10000000lu +#define MATCH_EN_3_5 0x20000000lu +#define MATCH_EN_3_6 0x40000000lu +#define MATCH_EN_3_7 0x80000000lu + + +/* MXVR_ROUTING_0 Masks */ + +#define MUTE_CH0 0x00000080lu +#define MUTE_CH1 0x00008000lu +#define MUTE_CH2 0x00800000lu +#define MUTE_CH3 0x80000000lu + +#define TX_CH0 0x0000007Flu +#define TX_CH1 0x00007F00lu +#define TX_CH2 0x007F0000lu +#define TX_CH3 0x7F000000lu + + +/* MXVR_ROUTING_1 Masks */ + +#define MUTE_CH4 0x00000080lu +#define MUTE_CH5 0x00008000lu +#define MUTE_CH6 0x00800000lu +#define MUTE_CH7 0x80000000lu + +#define TX_CH4 0x0000007Flu +#define TX_CH5 0x00007F00lu +#define TX_CH6 0x007F0000lu +#define TX_CH7 0x7F000000lu + + +/* MXVR_ROUTING_2 Masks */ + +#define MUTE_CH8 0x00000080lu +#define MUTE_CH9 0x00008000lu +#define MUTE_CH10 0x00800000lu +#define MUTE_CH11 0x80000000lu + +#define TX_CH8 0x0000007Flu +#define TX_CH9 0x00007F00lu +#define TX_CH10 0x007F0000lu +#define TX_CH11 0x7F000000lu + +/* MXVR_ROUTING_3 Masks */ + +#define MUTE_CH12 0x00000080lu +#define MUTE_CH13 0x00008000lu +#define MUTE_CH14 0x00800000lu +#define MUTE_CH15 0x80000000lu + +#define TX_CH12 0x0000007Flu +#define TX_CH13 0x00007F00lu +#define TX_CH14 0x007F0000lu +#define TX_CH15 0x7F000000lu + + +/* MXVR_ROUTING_4 Masks */ + +#define MUTE_CH16 0x00000080lu +#define MUTE_CH17 0x00008000lu +#define MUTE_CH18 0x00800000lu +#define MUTE_CH19 0x80000000lu + +#define TX_CH16 0x0000007Flu +#define TX_CH17 0x00007F00lu +#define TX_CH18 0x007F0000lu +#define TX_CH19 0x7F000000lu + + +/* MXVR_ROUTING_5 Masks */ + +#define MUTE_CH20 0x00000080lu +#define MUTE_CH21 0x00008000lu +#define MUTE_CH22 0x00800000lu +#define MUTE_CH23 0x80000000lu + +#define TX_CH20 0x0000007Flu +#define TX_CH21 0x00007F00lu +#define TX_CH22 0x007F0000lu +#define TX_CH23 0x7F000000lu + + +/* MXVR_ROUTING_6 Masks */ + +#define MUTE_CH24 0x00000080lu +#define MUTE_CH25 0x00008000lu +#define MUTE_CH26 0x00800000lu +#define MUTE_CH27 0x80000000lu + +#define TX_CH24 0x0000007Flu +#define TX_CH25 0x00007F00lu +#define TX_CH26 0x007F0000lu +#define TX_CH27 0x7F000000lu + + +/* MXVR_ROUTING_7 Masks */ + +#define MUTE_CH28 0x00000080lu +#define MUTE_CH29 0x00008000lu +#define MUTE_CH30 0x00800000lu +#define MUTE_CH31 0x80000000lu + +#define TX_CH28 0x0000007Flu +#define TX_CH29 0x00007F00lu +#define TX_CH30 0x007F0000lu +#define TX_CH31 0x7F000000lu + + +/* MXVR_ROUTING_8 Masks */ + +#define MUTE_CH32 0x00000080lu +#define MUTE_CH33 0x00008000lu +#define MUTE_CH34 0x00800000lu +#define MUTE_CH35 0x80000000lu + +#define TX_CH32 0x0000007Flu +#define TX_CH33 0x00007F00lu +#define TX_CH34 0x007F0000lu +#define TX_CH35 0x7F000000lu + + +/* MXVR_ROUTING_9 Masks */ + +#define MUTE_CH36 0x00000080lu +#define MUTE_CH37 0x00008000lu +#define MUTE_CH38 0x00800000lu +#define MUTE_CH39 0x80000000lu + +#define TX_CH36 0x0000007Flu +#define TX_CH37 0x00007F00lu +#define TX_CH38 0x007F0000lu +#define TX_CH39 0x7F000000lu + + +/* MXVR_ROUTING_10 Masks */ + +#define MUTE_CH40 0x00000080lu +#define MUTE_CH41 0x00008000lu +#define MUTE_CH42 0x00800000lu +#define MUTE_CH43 0x80000000lu + +#define TX_CH40 0x0000007Flu +#define TX_CH41 0x00007F00lu +#define TX_CH42 0x007F0000lu +#define TX_CH43 0x7F000000lu + + +/* MXVR_ROUTING_11 Masks */ + +#define MUTE_CH44 0x00000080lu +#define MUTE_CH45 0x00008000lu +#define MUTE_CH46 0x00800000lu +#define MUTE_CH47 0x80000000lu + +#define TX_CH44 0x0000007Flu +#define TX_CH45 0x00007F00lu +#define TX_CH46 0x007F0000lu +#define TX_CH47 0x7F000000lu + + +/* MXVR_ROUTING_12 Masks */ + +#define MUTE_CH48 0x00000080lu +#define MUTE_CH49 0x00008000lu +#define MUTE_CH50 0x00800000lu +#define MUTE_CH51 0x80000000lu + +#define TX_CH48 0x0000007Flu +#define TX_CH49 0x00007F00lu +#define TX_CH50 0x007F0000lu +#define TX_CH51 0x7F000000lu + + +/* MXVR_ROUTING_13 Masks */ + +#define MUTE_CH52 0x00000080lu +#define MUTE_CH53 0x00008000lu +#define MUTE_CH54 0x00800000lu +#define MUTE_CH55 0x80000000lu + +#define TX_CH52 0x0000007Flu +#define TX_CH53 0x00007F00lu +#define TX_CH54 0x007F0000lu +#define TX_CH55 0x7F000000lu + + +/* MXVR_ROUTING_14 Masks */ + +#define MUTE_CH56 0x00000080lu +#define MUTE_CH57 0x00008000lu +#define MUTE_CH58 0x00800000lu +#define MUTE_CH59 0x80000000lu + +#define TX_CH56 0x0000007Flu +#define TX_CH57 0x00007F00lu +#define TX_CH58 0x007F0000lu +#define TX_CH59 0x7F000000lu + + +/* Control Message Receive Buffer (CMRB) Address Offsets */ + +#define CMRB_STRIDE 0x00000016lu + +#define CMRB_DST_OFFSET 0x00000000lu +#define CMRB_SRC_OFFSET 0x00000002lu +#define CMRB_DATA_OFFSET 0x00000005lu + + +/* Control Message Transmit Buffer (CMTB) Address Offsets */ + +#define CMTB_PRIO_OFFSET 0x00000000lu +#define CMTB_DST_OFFSET 0x00000002lu +#define CMTB_SRC_OFFSET 0x00000004lu +#define CMTB_TYPE_OFFSET 0x00000006lu +#define CMTB_DATA_OFFSET 0x00000007lu + +#define CMTB_ANSWER_OFFSET 0x0000000Alu + +#define CMTB_STAT_N_OFFSET 0x00000018lu +#define CMTB_STAT_A_OFFSET 0x00000016lu +#define CMTB_STAT_D_OFFSET 0x0000000Elu +#define CMTB_STAT_R_OFFSET 0x00000014lu +#define CMTB_STAT_W_OFFSET 0x00000014lu +#define CMTB_STAT_G_OFFSET 0x00000014lu + + +/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */ + +#define APRB_STRIDE 0x00000400lu + +#define APRB_DST_OFFSET 0x00000000lu +#define APRB_LEN_OFFSET 0x00000002lu +#define APRB_SRC_OFFSET 0x00000004lu +#define APRB_DATA_OFFSET 0x00000006lu + + +/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */ + +#define APTB_PRIO_OFFSET 0x00000000lu +#define APTB_DST_OFFSET 0x00000002lu +#define APTB_LEN_OFFSET 0x00000004lu +#define APTB_SRC_OFFSET 0x00000006lu +#define APTB_DATA_OFFSET 0x00000008lu + + +/* Remote Read Buffer (RRDB) Address Offsets */ + +#define RRDB_WADDR_OFFSET 0x00000100lu +#define RRDB_WLEN_OFFSET 0x00000101lu + + + /* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/ /* CAN_CONTROL Masks */ #define SRS 0x0001 /* Software Reset */ diff --git a/trunk/arch/blackfin/mach-bf538/include/mach/gpio.h b/trunk/arch/blackfin/mach-bf538/include/mach/gpio.h index 0c346fba9619..295c78a465c2 100644 --- a/trunk/arch/blackfin/mach-bf538/include/mach/gpio.h +++ b/trunk/arch/blackfin/mach-bf538/include/mach/gpio.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2009 Analog Devices Inc. + * Copyright (C) 2008 Analog Devices Inc. * Licensed under the GPL-2 or later. */ @@ -7,8 +7,11 @@ #ifndef _MACH_GPIO_H_ #define _MACH_GPIO_H_ + /* FIXME: + * For now only support PORTF GPIOs. + * PORT C,D and E are for peripheral usage only + */ #define MAX_BLACKFIN_GPIOS 16 -#define BFIN_SPECIAL_GPIO_BANKS 3 #define GPIO_PF0 0 /* PF */ #define GPIO_PF1 1 diff --git a/trunk/arch/blackfin/mach-bf538/include/mach/portmux.h b/trunk/arch/blackfin/mach-bf538/include/mach/portmux.h index 0083ba13ee9e..6121cf8b5872 100644 --- a/trunk/arch/blackfin/mach-bf538/include/mach/portmux.h +++ b/trunk/arch/blackfin/mach-bf538/include/mach/portmux.h @@ -7,7 +7,7 @@ #ifndef _MACH_PORTMUX_H_ #define _MACH_PORTMUX_H_ -#define MAX_RESOURCES 64 +#define MAX_RESOURCES MAX_BLACKFIN_GPIOS #define P_TMR2 (P_DONTCARE) #define P_TMR1 (P_DONTCARE) diff --git a/trunk/arch/blackfin/mach-bf548/Kconfig b/trunk/arch/blackfin/mach-bf548/Kconfig index 70189a0d1a19..a09623dfd550 100644 --- a/trunk/arch/blackfin/mach-bf548/Kconfig +++ b/trunk/arch/blackfin/mach-bf548/Kconfig @@ -1,27 +1,3 @@ -config BF542 - def_bool y - depends on BF542_std || BF542M -config BF544 - def_bool y - depends on BF544_std || BF544M -config BF547 - def_bool y - depends on BF547_std || BF547M -config BF548 - def_bool y - depends on BF548_std || BF548M -config BF549 - def_bool y - depends on BF549_std || BF549M - -config BF54xM - def_bool y - depends on (BF542M || BF544M || BF547M || BF548M || BF549M) - -config BF54x - def_bool y - depends on (BF542 || BF544 || BF547 || BF548 || BF549) - if (BF54x) source "arch/blackfin/mach-bf548/boards/Kconfig" diff --git a/trunk/arch/blackfin/mach-bf548/boards/ezkit.c b/trunk/arch/blackfin/mach-bf548/boards/ezkit.c index 60193f72777c..1a5286bbb3fa 100644 --- a/trunk/arch/blackfin/mach-bf548/boards/ezkit.c +++ b/trunk/arch/blackfin/mach-bf548/boards/ezkit.c @@ -62,7 +62,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -154,7 +154,7 @@ static struct platform_device bf54x_kpad_device = { }; #endif -#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) #include static struct bfin_rotary_platform_data bfin_rotary_data = { @@ -186,7 +186,7 @@ static struct platform_device bfin_rotary_device = { #endif #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE) -#include +#include static const struct adxl34x_platform_data adxl34x_info = { .x_axis_offset = 0, .y_axis_offset = 0, @@ -210,17 +210,14 @@ static const struct adxl34x_platform_data adxl34x_info = { .ev_code_y = ABS_Y, /* EV_REL */ .ev_code_z = ABS_Z, /* EV_REL */ - .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ + .ev_code_tap_x = BTN_TOUCH, /* EV_KEY */ + .ev_code_tap_y = BTN_TOUCH, /* EV_KEY */ + .ev_code_tap_z = BTN_TOUCH, /* EV_KEY */ /* .ev_code_ff = KEY_F,*/ /* EV_KEY */ /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, .fifo_mode = ADXL_FIFO_STREAM, - .orientation_enable = ADXL_EN_ORIENTATION_3D, - .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, - .divisor_length = ADXL_LP_FILTER_DIVISOR_16, - /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ - .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, }; #endif @@ -464,44 +461,6 @@ static struct platform_device musb_device = { }; #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) -unsigned short bfin_can_peripherals[] = { - P_CAN0_RX, P_CAN0_TX, 0 -}; - -static struct resource bfin_can_resources[] = { - { - .start = 0xFFC02A00, - .end = 0xFFC02FFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_CAN0_RX, - .end = IRQ_CAN0_RX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_TX, - .end = IRQ_CAN0_TX, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_CAN0_ERROR, - .end = IRQ_CAN0_ERROR, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device bfin_can_device = { - .name = "bfin_can", - .num_resources = ARRAY_SIZE(bfin_can_resources), - .resource = bfin_can_resources, - .dev = { - .platform_data = &bfin_can_peripherals, /* Passed to driver */ - }, -}; -#endif - #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) static struct resource bfin_atapi_resources[] = { { @@ -994,10 +953,6 @@ static struct platform_device *ezkit_devices[] __initdata = { &bfin_isp1760_device, #endif -#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) - &bfin_can_device, -#endif - #if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) &bfin_atapi_device, #endif @@ -1019,7 +974,7 @@ static struct platform_device *ezkit_devices[] __initdata = { &bf54x_kpad_device, #endif -#if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE) +#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE) &bfin_rotary_device, #endif diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/bf548.h b/trunk/arch/blackfin/mach-bf548/include/mach/bf548.h index 751e5e11ecf8..7bead5ce0f3b 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/bf548.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/bf548.h @@ -81,6 +81,18 @@ #define AMGCTLVAL (V_AMBEN | V_AMCKEN) +#if defined(CONFIG_BF542M) +# define CONFIG_BF542 +#elif defined(CONFIG_BF544M) +# define CONFIG_BF544 +#elif defined(CONFIG_BF547M) +# define CONFIG_BF547 +#elif defined(CONFIG_BF548M) +# define CONFIG_BF548 +#elif defined(CONFIG_BF549M) +# define CONFIG_BF549 +#endif + #if defined(CONFIG_BF542) # define CPU "BF542" # define CPUID 0x27de diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/blackfin.h b/trunk/arch/blackfin/mach-bf548/include/mach/blackfin.h index 5684030ccc21..13302b67857a 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/blackfin.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/blackfin.h @@ -64,4 +64,10 @@ #define OFFSET_THR 0x28 /* Transmit Holding register */ #define OFFSET_RBR 0x2C /* Receive Buffer register */ +/* PLL_DIV Masks */ +#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */ + #endif diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF547.h index bc650e6ea482..423421515134 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF547.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF547.h @@ -4,21 +4,21 @@ * Licensed under the GPL-2 or later. */ -#ifndef _CDEF_BF547_H -#define _CDEF_BF547_H +#ifndef _CDEF_BF548_H +#define _CDEF_BF548_H /* include all Core registers and bit definitions */ -#include "defBF547.h" +#include "defBF548.h" /* include core sbfin_read_()ecific register pointer definitions */ #include -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */ +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" -/* The following are the #defines needed by ADSP-BF547 that are not in the common header */ +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ /* Timer Registers */ @@ -805,4 +805,4 @@ #define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) #define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) -#endif /* _CDEF_BF547_H */ +#endif /* _CDEF_BF548_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF548.h index 3523e08f7968..df84180410c4 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF548.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF548.h @@ -18,8 +18,165 @@ /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" -/* The BF548 is like the BF547, but has additional CANs */ -#include "cdefBF547.h" +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* SPORT0 Registers */ + +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* UART2 Registers */ + +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) +#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) +#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) +#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) +#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) + +/* Two Wire Interface Registers (TWI1) */ + +/* SPI2 Registers */ + +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) /* CAN Controller 1 Config 1 Registers */ @@ -766,4 +923,631 @@ #define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) #define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + #endif /* _CDEF_BF548_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF549.h index 80201ed41f80..34c84c7fb256 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF549.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF549.h @@ -18,8 +18,165 @@ /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */ #include "cdefBF54x_base.h" -/* The BF549 is like the BF544, but has MXVR */ -#include "cdefBF547.h" +/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ + +/* Timer Registers */ + +#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG) +#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val) +#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER) +#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val) +#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD) +#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val) +#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH) +#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val) +#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG) +#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val) +#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER) +#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val) +#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD) +#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val) +#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH) +#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val) +#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG) +#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val) +#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER) +#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val) +#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD) +#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val) +#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH) +#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val) + +/* Timer Groubfin_read_() of 3 */ + +#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1) +#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val) +#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1) +#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val) +#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1) +#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val) + +/* SPORT0 Registers */ + +#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1) +#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val) +#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2) +#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val) +#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV) +#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val) +#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val) +#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1) +#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val) +#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2) +#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val) +#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV) +#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL) +#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val) +#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val) +#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val) +#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val) +#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val) +#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val) +#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val) +#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val) + +/* EPPI0 Registers */ + +#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS) +#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val) +#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT) +#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val) +#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY) +#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val) +#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT) +#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val) +#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY) +#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val) +#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME) +#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val) +#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE) +#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val) +#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV) +#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val) +#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL) +#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val) +#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL) +#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val) +#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL) +#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val) +#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB) +#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val) +#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF) +#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val) +#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP) +#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val) + +/* UART2 Registers */ + +#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL) +#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val) +#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH) +#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val) +#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL) +#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val) +#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR) +#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val) +#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR) +#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val) +#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR) +#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val) +#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR) +#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val) +#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR) +#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val) +#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET) +#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val) +#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR) +#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val) +#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR) +#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val) + +/* Two Wire Interface Registers (TWI1) */ + +/* SPI2 Registers */ + +#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL) +#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val) +#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG) +#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val) +#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT) +#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val) +#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR) +#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val) +#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR) +#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val) +#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD) +#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val) +#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW) +#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val) /* MXVR Registers */ @@ -307,4 +464,1376 @@ #define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT) #define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val) +/* CAN Controller 1 Config 1 Registers */ + +#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1) +#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val) +#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1) +#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val) +#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1) +#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val) +#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1) +#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val) +#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1) +#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val) +#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1) +#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val) +#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1) +#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val) +#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1) +#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val) +#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1) +#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val) +#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1) +#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val) +#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1) +#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val) +#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1) +#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val) +#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1) +#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val) + +/* CAN Controller 1 Config 2 Registers */ + +#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2) +#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val) +#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2) +#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val) +#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2) +#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val) +#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2) +#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val) +#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2) +#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val) +#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2) +#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val) +#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2) +#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val) +#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2) +#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val) +#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2) +#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val) +#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2) +#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val) +#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2) +#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val) +#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2) +#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val) +#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2) +#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val) + +/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */ + +#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK) +#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val) +#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING) +#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val) +#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG) +#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val) +#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS) +#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val) +#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC) +#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val) +#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS) +#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val) +#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM) +#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val) +#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF) +#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val) +#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL) +#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val) +#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR) +#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val) +#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD) +#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val) +#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR) +#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val) +#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR) +#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val) +#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT) +#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val) +#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC) +#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val) +#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF) +#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L) +#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val) +#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H) +#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val) +#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L) +#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val) +#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H) +#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val) +#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L) +#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val) +#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H) +#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val) +#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L) +#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val) +#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H) +#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val) +#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L) +#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val) +#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H) +#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val) +#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L) +#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val) +#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H) +#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val) +#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L) +#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val) +#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H) +#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val) +#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L) +#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val) +#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H) +#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val) +#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L) +#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val) +#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H) +#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val) +#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L) +#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val) +#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H) +#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val) +#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L) +#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val) +#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H) +#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val) +#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L) +#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val) +#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H) +#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val) +#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L) +#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val) +#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H) +#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val) +#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L) +#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val) +#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H) +#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val) +#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L) +#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val) +#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H) +#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val) +#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L) +#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val) +#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H) +#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val) + +/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */ + +#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L) +#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val) +#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H) +#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val) +#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L) +#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val) +#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H) +#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val) +#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L) +#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val) +#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H) +#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val) +#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L) +#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val) +#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H) +#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val) +#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L) +#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val) +#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H) +#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val) +#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L) +#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val) +#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H) +#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val) +#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L) +#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val) +#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H) +#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val) +#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L) +#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val) +#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H) +#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val) +#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L) +#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val) +#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H) +#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val) +#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L) +#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val) +#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H) +#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val) +#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L) +#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val) +#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H) +#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val) +#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L) +#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val) +#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H) +#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val) +#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L) +#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val) +#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H) +#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val) +#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L) +#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val) +#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H) +#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val) +#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L) +#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val) +#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H) +#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val) +#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L) +#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val) +#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H) +#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0) +#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val) +#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1) +#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val) +#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2) +#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val) +#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3) +#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val) +#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH) +#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val) +#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP) +#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val) +#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0) +#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val) +#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1) +#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val) +#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0) +#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val) +#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1) +#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val) +#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2) +#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val) +#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3) +#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val) +#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH) +#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val) +#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP) +#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val) +#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0) +#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val) +#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1) +#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val) +#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0) +#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val) +#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1) +#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val) +#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2) +#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val) +#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3) +#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val) +#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH) +#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val) +#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP) +#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val) +#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0) +#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val) +#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1) +#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val) +#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0) +#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val) +#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1) +#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val) +#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2) +#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val) +#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3) +#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val) +#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH) +#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val) +#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP) +#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val) +#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0) +#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val) +#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1) +#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val) +#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0) +#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val) +#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1) +#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val) +#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2) +#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val) +#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3) +#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val) +#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH) +#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val) +#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP) +#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val) +#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0) +#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val) +#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1) +#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val) +#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0) +#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val) +#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1) +#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val) +#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2) +#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val) +#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3) +#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val) +#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH) +#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val) +#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP) +#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val) +#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0) +#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val) +#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1) +#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val) +#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0) +#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val) +#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1) +#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val) +#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2) +#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val) +#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3) +#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val) +#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH) +#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val) +#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP) +#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val) +#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0) +#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val) +#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1) +#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val) +#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0) +#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val) +#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1) +#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val) +#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2) +#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val) +#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3) +#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val) +#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH) +#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val) +#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP) +#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val) +#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0) +#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val) +#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1) +#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val) +#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0) +#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val) +#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1) +#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val) +#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2) +#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val) +#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3) +#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val) +#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH) +#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val) +#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP) +#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val) +#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0) +#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val) +#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1) +#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val) +#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0) +#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val) +#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1) +#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val) +#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2) +#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val) +#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3) +#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val) +#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH) +#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val) +#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP) +#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val) +#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0) +#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val) +#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1) +#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val) +#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0) +#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val) +#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1) +#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val) +#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2) +#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val) +#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3) +#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val) +#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH) +#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val) +#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP) +#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val) +#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0) +#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val) +#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1) +#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val) +#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0) +#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val) +#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1) +#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val) +#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2) +#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val) +#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3) +#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val) +#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH) +#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val) +#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP) +#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val) +#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0) +#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val) +#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1) +#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val) +#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0) +#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val) +#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1) +#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val) +#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2) +#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val) +#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3) +#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val) +#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH) +#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val) +#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP) +#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val) +#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0) +#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val) +#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1) +#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val) +#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0) +#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val) +#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1) +#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val) +#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2) +#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val) +#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3) +#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val) +#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH) +#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val) +#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP) +#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val) +#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0) +#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val) +#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1) +#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val) +#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0) +#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val) +#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1) +#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val) +#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2) +#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val) +#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3) +#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val) +#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH) +#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val) +#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP) +#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val) +#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0) +#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val) +#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1) +#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val) +#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0) +#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val) +#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1) +#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val) +#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2) +#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val) +#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3) +#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val) +#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH) +#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val) +#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP) +#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val) +#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0) +#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val) +#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1) +#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val) + +/* CAN Controller 1 Mailbox Data Registers */ + +#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0) +#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val) +#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1) +#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val) +#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2) +#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val) +#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3) +#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val) +#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH) +#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val) +#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP) +#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val) +#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0) +#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val) +#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1) +#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val) +#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0) +#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val) +#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1) +#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val) +#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2) +#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val) +#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3) +#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val) +#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH) +#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val) +#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP) +#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val) +#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0) +#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val) +#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1) +#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val) +#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0) +#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val) +#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1) +#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val) +#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2) +#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val) +#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3) +#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val) +#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH) +#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val) +#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP) +#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val) +#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0) +#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val) +#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1) +#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val) +#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0) +#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val) +#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1) +#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val) +#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2) +#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val) +#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3) +#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val) +#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH) +#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val) +#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP) +#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val) +#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0) +#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val) +#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1) +#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val) +#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0) +#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val) +#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1) +#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val) +#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2) +#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val) +#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3) +#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val) +#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH) +#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val) +#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP) +#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val) +#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0) +#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val) +#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1) +#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val) +#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0) +#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val) +#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1) +#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val) +#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2) +#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val) +#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3) +#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val) +#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH) +#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val) +#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP) +#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val) +#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0) +#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val) +#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1) +#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val) +#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0) +#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val) +#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1) +#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val) +#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2) +#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val) +#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3) +#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val) +#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH) +#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val) +#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP) +#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val) +#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0) +#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val) +#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1) +#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val) +#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0) +#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val) +#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1) +#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val) +#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2) +#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val) +#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3) +#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val) +#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH) +#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val) +#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP) +#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val) +#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0) +#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val) +#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1) +#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val) +#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0) +#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val) +#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1) +#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val) +#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2) +#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val) +#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3) +#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val) +#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH) +#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val) +#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP) +#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val) +#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0) +#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val) +#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1) +#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val) +#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0) +#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val) +#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1) +#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val) +#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2) +#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val) +#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3) +#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val) +#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH) +#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val) +#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP) +#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val) +#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0) +#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val) +#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1) +#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val) +#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0) +#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val) +#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1) +#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val) +#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2) +#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val) +#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3) +#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val) +#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH) +#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val) +#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP) +#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val) +#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0) +#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val) +#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1) +#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val) +#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0) +#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val) +#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1) +#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val) +#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2) +#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val) +#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3) +#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val) +#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH) +#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val) +#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP) +#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val) +#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0) +#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val) +#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1) +#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val) +#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0) +#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val) +#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1) +#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val) +#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2) +#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val) +#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3) +#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val) +#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH) +#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val) +#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP) +#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val) +#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0) +#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val) +#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1) +#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val) +#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0) +#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val) +#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1) +#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val) +#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2) +#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val) +#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3) +#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val) +#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH) +#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val) +#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP) +#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val) +#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0) +#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val) +#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1) +#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val) +#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0) +#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val) +#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1) +#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val) +#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2) +#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val) +#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3) +#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val) +#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH) +#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val) +#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP) +#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val) +#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0) +#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val) +#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1) +#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val) +#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0) +#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val) +#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1) +#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val) +#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2) +#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val) +#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3) +#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val) +#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH) +#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val) +#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP) +#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val) +#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0) +#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val) +#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1) +#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val) + +/* ATAPI Registers */ + +#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL) +#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val) +#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS) +#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val) +#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR) +#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val) +#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF) +#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val) +#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF) +#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val) +#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK) +#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val) +#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS) +#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val) +#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN) +#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val) +#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS) +#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val) +#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE) +#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val) +#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE) +#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val) +#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT) +#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val) +#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT) +#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val) +#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT) +#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val) +#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT) +#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val) +#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0) +#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0) +#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val) +#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1) +#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0) +#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val) +#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1) +#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val) +#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2) +#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0) +#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val) +#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1) +#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val) +#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2) +#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val) +#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3) +#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val) + +/* SDH Registers */ + +#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL) +#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val) +#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL) +#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val) +#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT) +#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val) +#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND) +#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val) +#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD) +#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val) +#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0) +#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val) +#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1) +#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val) +#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2) +#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val) +#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3) +#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val) +#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER) +#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val) +#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH) +#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val) +#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL) +#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val) +#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT) +#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val) +#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS) +#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val) +#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR) +#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val) +#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0) +#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val) +#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1) +#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val) +#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT) +#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val) +#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO) +#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val) +#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS) +#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val) +#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK) +#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val) +#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG) +#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val) +#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN) +#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val) +#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0) +#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val) +#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1) +#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val) +#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2) +#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val) +#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3) +#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val) +#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4) +#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val) +#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5) +#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val) +#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6) +#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val) +#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7) +#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val) + +/* HOST Port Registers */ + +#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL) +#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val) +#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS) +#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val) +#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT) +#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val) + +/* USB Control Registers */ + +#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR) +#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val) +#define bfin_read_USB_POWER() bfin_read16(USB_POWER) +#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val) +#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX) +#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val) +#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX) +#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val) +#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE) +#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val) +#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE) +#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val) +#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB) +#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val) +#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE) +#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val) +#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME) +#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val) +#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX) +#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val) +#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE) +#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val) +#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR) +#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val) +#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL) +#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val) + +/* USB Packet Control Registers */ + +#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET) +#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val) +#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0) +#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val) +#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR) +#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val) +#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET) +#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val) +#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR) +#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val) +#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0) +#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val) +#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT) +#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val) +#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE) +#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val) +#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0) +#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val) +#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL) +#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val) +#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE) +#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val) +#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL) +#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val) +#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT) +#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val) + +/* USB Endbfin_read_()oint FIFO Registers */ + +#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO) +#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val) +#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO) +#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val) +#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO) +#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val) +#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO) +#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val) +#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO) +#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val) +#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO) +#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val) +#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO) +#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val) +#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO) +#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val) + +/* USB OTG Control Registers */ + +#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL) +#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val) +#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ) +#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val) +#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK) +#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val) + +/* USB Phy Control Registers */ + +#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO) +#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val) +#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN) +#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val) +#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1) +#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val) +#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1) +#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val) +#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1) +#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val) + +/* (APHY_CNTRL is for ADI usage only) */ + +#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL) +#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val) + +/* (APHY_CALIB is for ADI usage only) */ + +#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB) +#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val) +#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2) +#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val) + +/* (PHY_TEST is for ADI usage only) */ + +#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST) +#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val) +#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL) +#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val) +#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV) +#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val) + +/* USB Endbfin_read_()oint 0 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP) +#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val) +#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR) +#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val) +#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP) +#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val) +#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR) +#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val) +#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT) +#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val) +#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE) +#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val) +#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL) +#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val) +#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE) +#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val) +#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL) +#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 1 Control Registers */ + +#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT) +#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP) +#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val) +#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR) +#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val) +#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP) +#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val) +#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR) +#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val) +#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT) +#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val) +#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE) +#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val) +#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL) +#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val) +#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE) +#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val) +#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL) +#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 2 Control Registers */ + +#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT) +#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP) +#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val) +#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR) +#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val) +#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP) +#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val) +#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR) +#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val) +#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT) +#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val) +#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE) +#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val) +#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL) +#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val) +#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE) +#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val) +#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL) +#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 3 Control Registers */ + +#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT) +#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP) +#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val) +#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR) +#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val) +#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP) +#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val) +#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR) +#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val) +#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT) +#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val) +#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE) +#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val) +#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL) +#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val) +#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE) +#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val) +#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL) +#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 4 Control Registers */ + +#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT) +#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP) +#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val) +#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR) +#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val) +#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP) +#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val) +#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR) +#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val) +#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT) +#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val) +#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE) +#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val) +#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL) +#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val) +#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE) +#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val) +#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL) +#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 5 Control Registers */ + +#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT) +#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP) +#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val) +#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR) +#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val) +#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP) +#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val) +#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR) +#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val) +#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT) +#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val) +#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE) +#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val) +#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL) +#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val) +#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE) +#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val) +#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL) +#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 6 Control Registers */ + +#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT) +#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP) +#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val) +#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR) +#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val) +#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP) +#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val) +#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR) +#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val) +#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT) +#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val) +#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE) +#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val) +#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL) +#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val) +#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE) +#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val) +#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL) +#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val) + +/* USB Endbfin_read_()oint 7 Control Registers */ + +#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT) +#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP) +#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val) +#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR) +#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val) +#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP) +#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val) +#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR) +#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val) +#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT) +#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val) +#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE) +#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val) +#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL) +#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val) +#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE) +#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val) +#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL) +#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val) +#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT) +#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val) +#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT) +#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val) + +/* USB Channel 0 Config Registers */ + +#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL) +#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val) +#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW) +#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val) +#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH) +#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val) +#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW) +#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val) +#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH) +#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val) + +/* USB Channel 1 Config Registers */ + +#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL) +#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val) +#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW) +#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val) +#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH) +#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val) +#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW) +#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val) +#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH) +#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val) + +/* USB Channel 2 Config Registers */ + +#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL) +#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val) +#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW) +#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val) +#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH) +#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val) +#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW) +#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val) +#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH) +#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val) + +/* USB Channel 3 Config Registers */ + +#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL) +#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val) +#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW) +#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val) +#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH) +#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val) +#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW) +#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val) +#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH) +#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val) + +/* USB Channel 4 Config Registers */ + +#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL) +#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val) +#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW) +#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val) +#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH) +#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val) +#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW) +#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val) +#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH) +#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val) + +/* USB Channel 5 Config Registers */ + +#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL) +#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val) +#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW) +#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val) +#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH) +#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val) +#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW) +#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val) +#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH) +#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val) + +/* USB Channel 6 Config Registers */ + +#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL) +#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val) +#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW) +#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val) +#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH) +#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val) +#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW) +#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val) +#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH) +#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val) + +/* USB Channel 7 Config Registers */ + +#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL) +#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val) +#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW) +#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val) +#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH) +#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val) +#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW) +#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val) +#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH) +#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val) + +/* Keybfin_read_()ad Registers */ + +#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL) +#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val) +#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE) +#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val) +#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL) +#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val) +#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL) +#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val) +#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT) +#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val) +#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL) +#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val) + +/* Pixel Combfin_read_()ositor (PIXC) Registers */ + +#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL) +#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val) +#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL) +#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val) +#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF) +#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val) +#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART) +#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val) +#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND) +#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val) +#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART) +#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val) +#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND) +#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val) +#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP) +#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val) +#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART) +#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val) +#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND) +#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val) +#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART) +#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val) +#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND) +#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val) +#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP) +#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val) +#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT) +#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val) +#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON) +#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val) +#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON) +#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val) +#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON) +#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val) +#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS) +#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val) +#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC) +#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val) + +/* Handshake MDMA 0 Registers */ + +#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL) +#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val) +#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT) +#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val) +#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT) +#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val) +#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT) +#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val) +#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW) +#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val) +#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT) +#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val) +#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT) +#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val) + +/* Handshake MDMA 1 Registers */ + +#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL) +#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val) +#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT) +#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val) +#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT) +#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val) +#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT) +#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val) +#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW) +#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val) +#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT) +#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val) +#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT) +#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val) + #endif /* _CDEF_BF549_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h index 32f71e6a7c15..a2e9d9849eba 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h @@ -2615,6 +2615,17 @@ #define bfin_read_CNT_MIN() bfin_read32(CNT_MIN) #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val) +/* OTP/FUSE Registers */ + +#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL) +#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val) +#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN) +#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val) +#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS) +#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val) +#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING) +#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val) + /* Security Registers */ #define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT) @@ -2629,6 +2640,17 @@ #define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX) #define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val) +/* OTP Read/Write Data Buffer Registers */ + +#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0) +#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val) +#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1) +#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val) +#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2) +#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val) +#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3) +#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val) + /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */ /* legacy definitions */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h index f916c52a148a..39f588dcd382 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF544.h @@ -624,9 +624,9 @@ #define DMA_READY 0x1 /* DMA Ready */ #define FIFOFULL 0x2 /* FIFO Full */ #define FIFOEMPTY 0x4 /* FIFO Empty */ -#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define COMPLETE 0x8 /* DMA Complete */ #define HSHK 0x10 /* Host Handshake */ -#define HSTIMEOUT 0x20 /* Host Timeout */ +#define TIMEOUT 0x20 /* Host Timeout */ #define HIRQ 0x40 /* Host Interrupt Request */ #define ALLOW_CNFG 0x80 /* Allow New Configuration */ #define DMA_DIR 0x100 /* DMA Direction */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h index 72c343646b2a..c4dcf302d9f5 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF547.h @@ -4,18 +4,18 @@ * Licensed under the ADI BSD license or the GPL-2 (or later) */ -#ifndef _DEF_BF547_H -#define _DEF_BF547_H +#ifndef _DEF_BF548_H +#define _DEF_BF548_H /* Include all Core registers and bit definitions */ #include -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */ +/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */ /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" -/* The following are the #defines needed by ADSP-BF547 that are not in the common header */ +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ /* Timer Registers */ @@ -1217,4 +1217,4 @@ /* ******************************************* */ -#endif /* _DEF_BF547_H */ +#endif /* _DEF_BF548_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF548.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF548.h index 3fb33b040ab7..a5079980968c 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF548.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF548.h @@ -15,8 +15,115 @@ /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" -/* The BF548 is like the BF547, but has additional CANs */ -#include "defBF547.h" +/* The following are the #defines needed by ADSP-BF548 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* SPORT0 Registers */ + +#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ +#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ +#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ +#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ +#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ +#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ +#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ +#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* UART2 Registers */ + +#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ +#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ +#define UART2_GCTL 0xffc02108 /* Global Control Register */ +#define UART2_LCR 0xffc0210c /* Line Control Register */ +#define UART2_MCR 0xffc02110 /* Modem Control Register */ +#define UART2_LSR 0xffc02114 /* Line Status Register */ +#define UART2_MSR 0xffc02118 /* Modem Status Register */ +#define UART2_SCR 0xffc0211c /* Scratch Register */ +#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ +#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ +#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPI2 Registers */ + +#define SPI2_REGBASE 0xffc02400 +#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ +#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ +#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ +#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ /* CAN Controller 1 Config 1 Registers */ @@ -401,4 +508,1096 @@ #define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ #define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define HSTIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + + #endif /* _DEF_BF548_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF549.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF549.h index 5a04e6d4017e..f7f043560c6f 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF549.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF549.h @@ -10,13 +10,121 @@ /* Include all Core registers and bit definitions */ #include + /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */ /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */ #include "defBF54x_base.h" -/* The BF549 is like the BF544, but has MXVR */ -#include "defBF547.h" +/* The following are the #defines needed by ADSP-BF549 that are not in the common header */ + +/* Timer Registers */ + +#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */ +#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */ +#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */ +#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */ +#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */ +#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */ +#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */ +#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */ +#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */ +#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */ +#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */ +#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */ + +/* Timer Group of 3 Registers */ + +#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */ +#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */ +#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */ + +/* SPORT0 Registers */ + +#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */ +#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */ +#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ +#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */ +#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */ +#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */ +#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */ +#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */ +#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */ +#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */ +#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */ +#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */ +#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */ +#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */ +#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */ +#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */ +#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */ +#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */ +#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */ +#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */ +#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */ +#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */ + +/* EPPI0 Registers */ + +#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */ +#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */ +#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */ +#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */ +#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */ +#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */ +#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */ +#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */ +#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */ +#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */ +#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */ +#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */ +#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */ +#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */ + +/* UART2 Registers */ + +#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */ +#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */ +#define UART2_GCTL 0xffc02108 /* Global Control Register */ +#define UART2_LCR 0xffc0210c /* Line Control Register */ +#define UART2_MCR 0xffc02110 /* Modem Control Register */ +#define UART2_LSR 0xffc02114 /* Line Status Register */ +#define UART2_MSR 0xffc02118 /* Modem Status Register */ +#define UART2_SCR 0xffc0211c /* Scratch Register */ +#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */ +#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */ +#define UART2_RBR 0xffc0212c /* Receive Buffer Register */ + +/* Two Wire Interface Registers (TWI1) */ + +#define TWI1_REGBASE 0xffc02200 +#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ +#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ +#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ +#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */ +#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */ +#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */ +#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */ +#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */ +#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */ +#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */ +#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */ +#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */ +#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */ +#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */ +#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */ +#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */ + +/* SPI2 Registers */ + +#define SPI2_REGBASE 0xffc02400 +#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ +#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ +#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ +#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */ +#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */ +#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */ +#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */ /* MXVR Registers */ @@ -188,4 +296,2418 @@ #define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */ #define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */ +/* CAN Controller 1 Config 1 Registers */ + +#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */ +#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */ +#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */ +#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */ +#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */ +#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */ +#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */ +#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */ +#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */ +#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */ +#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */ +#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */ +#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */ + +/* CAN Controller 1 Config 2 Registers */ + +#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */ +#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */ +#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */ +#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */ +#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */ +#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */ +#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */ +#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */ +#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */ +#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */ +#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */ +#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */ +#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */ + +/* CAN Controller 1 Clock/Interrupt/Counter Registers */ + +#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */ +#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */ +#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */ +#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */ +#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */ +#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */ +#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */ +#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */ +#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */ +#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */ +#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */ +#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */ +#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */ +#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */ +#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */ +#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */ +#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */ +#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */ +#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */ +#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */ +#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */ +#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */ +#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */ +#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */ +#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */ +#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */ +#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */ +#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */ +#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */ +#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */ +#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */ +#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */ +#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */ +#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */ +#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */ +#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */ +#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */ +#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */ +#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */ +#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */ +#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */ +#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */ +#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */ +#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */ +#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */ +#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */ +#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Acceptance Registers */ + +#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */ +#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */ +#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */ +#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */ +#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */ +#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */ +#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */ +#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */ +#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */ +#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */ +#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */ +#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */ +#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */ +#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */ +#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */ +#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */ +#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */ +#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */ +#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */ +#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */ +#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */ +#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */ +#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */ +#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */ +#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */ +#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */ +#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */ +#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */ +#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */ +#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */ +#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */ +#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */ +#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */ +#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */ +#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */ +#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */ +#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */ +#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */ +#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */ +#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */ +#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */ +#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */ +#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */ +#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */ +#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */ +#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */ +#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */ +#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */ +#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */ +#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */ +#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */ +#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */ +#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */ +#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */ +#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */ +#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */ +#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */ +#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */ +#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */ +#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */ +#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */ +#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */ +#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */ +#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */ +#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */ +#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */ +#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */ +#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */ +#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */ +#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */ +#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */ +#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */ +#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */ +#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */ +#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */ +#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */ +#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */ +#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */ +#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */ +#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */ +#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */ +#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */ +#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */ +#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */ +#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */ +#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */ +#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */ +#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */ +#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */ +#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */ +#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */ +#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */ +#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */ +#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */ +#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */ +#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */ +#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */ +#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */ +#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */ +#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */ +#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */ +#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */ +#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */ +#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */ +#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */ +#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */ +#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */ +#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */ +#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */ +#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */ +#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */ +#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */ +#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */ +#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */ +#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */ +#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */ +#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */ +#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */ +#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */ +#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */ +#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */ +#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */ +#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */ +#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */ +#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */ +#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */ +#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */ +#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */ +#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */ +#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */ +#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */ +#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */ +#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */ +#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */ +#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */ +#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */ +#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */ +#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */ +#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */ +#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */ +#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */ +#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */ +#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */ +#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */ +#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */ +#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */ +#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */ +#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */ +#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */ +#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */ +#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */ +#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */ +#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */ +#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */ +#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */ +#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */ +#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */ +#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */ +#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */ + +/* CAN Controller 1 Mailbox Data Registers */ + +#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */ +#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */ +#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */ +#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */ +#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */ +#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */ +#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */ +#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */ +#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */ +#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */ +#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */ +#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */ +#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */ +#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */ +#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */ +#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */ +#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */ +#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */ +#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */ +#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */ +#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */ +#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */ +#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */ +#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */ +#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */ +#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */ +#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */ +#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */ +#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */ +#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */ +#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */ +#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */ +#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */ +#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */ +#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */ +#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */ +#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */ +#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */ +#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */ +#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */ +#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */ +#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */ +#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */ +#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */ +#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */ +#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */ +#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */ +#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */ +#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */ +#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */ +#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */ +#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */ +#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */ +#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */ +#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */ +#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */ +#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */ +#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */ +#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */ +#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */ +#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */ +#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */ +#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */ +#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */ +#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */ +#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */ +#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */ +#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */ +#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */ +#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */ +#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */ +#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */ +#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */ +#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */ +#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */ +#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */ +#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */ +#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */ +#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */ +#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */ +#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */ +#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */ +#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */ +#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */ +#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */ +#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */ +#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */ +#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */ +#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */ +#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */ +#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */ +#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */ +#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */ +#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */ +#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */ +#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */ +#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */ +#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */ +#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */ +#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */ +#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */ +#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */ +#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */ +#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */ +#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */ +#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */ +#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */ +#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */ +#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */ +#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */ +#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */ +#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */ +#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */ +#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */ +#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */ +#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */ +#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */ +#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */ +#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */ +#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */ +#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */ +#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */ +#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */ +#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */ +#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */ +#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */ +#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */ +#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */ + +/* ATAPI Registers */ + +#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */ +#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */ +#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */ +#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */ +#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */ +#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */ +#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */ +#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */ +#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */ +#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */ +#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */ +#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */ +#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */ +#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */ +#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */ +#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */ +#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */ +#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */ +#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */ +#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */ +#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */ +#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */ +#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */ +#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */ + +/* SDH Registers */ + +#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */ +#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */ +#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */ +#define SDH_COMMAND 0xffc0390c /* SDH Command */ +#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */ +#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */ +#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */ +#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */ +#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */ +#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */ +#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */ +#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */ +#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */ +#define SDH_STATUS 0xffc03934 /* SDH Status */ +#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */ +#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */ +#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */ +#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */ +#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */ +#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */ +#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */ +#define SDH_CFG 0xffc039c8 /* SDH Configuration */ +#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */ +#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */ +#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */ +#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */ +#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */ +#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */ +#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */ +#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */ +#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */ + +/* HOST Port Registers */ + +#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */ +#define HOST_STATUS 0xffc03a04 /* HOST Status Register */ +#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */ + +/* USB Control Registers */ + +#define USB_FADDR 0xffc03c00 /* Function address register */ +#define USB_POWER 0xffc03c04 /* Power management register */ +#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */ +#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */ +#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */ +#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */ +#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */ +#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */ +#define USB_FRAME 0xffc03c20 /* USB frame number */ +#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */ +#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */ +#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */ +#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */ + +/* USB Packet Control Registers */ + +#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */ +#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */ +#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */ +#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */ +#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */ +#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */ +#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */ +#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */ +#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */ +#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* USB Endpoint FIFO Registers */ + +#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */ +#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */ +#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */ +#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */ +#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */ +#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */ +#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */ +#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */ + +/* USB OTG Control Registers */ + +#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */ +#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */ +#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */ + +/* USB Phy Control Registers */ + +#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */ +#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */ +#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */ +#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */ +#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */ + +/* (APHY_CNTRL is for ADI usage only) */ + +#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */ + +/* (APHY_CALIB is for ADI usage only) */ + +#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */ +#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */ + +/* (PHY_TEST is for ADI usage only) */ + +#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */ +#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */ +#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */ + +/* USB Endpoint 0 Control Registers */ + +#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */ +#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */ +#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */ +#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */ +#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */ +#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */ +#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */ +#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */ + +/* USB Endpoint 1 Control Registers */ + +#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */ +#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */ +#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */ +#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */ +#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */ +#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */ +#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */ +#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */ +#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */ + +/* USB Endpoint 2 Control Registers */ + +#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */ +#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */ +#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */ +#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */ +#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */ +#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */ +#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */ +#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */ +#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */ + +/* USB Endpoint 3 Control Registers */ + +#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */ +#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */ +#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */ +#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */ +#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */ +#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */ +#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */ +#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */ +#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */ + +/* USB Endpoint 4 Control Registers */ + +#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */ +#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */ +#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */ +#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */ +#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */ +#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */ +#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */ +#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */ +#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */ + +/* USB Endpoint 5 Control Registers */ + +#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */ +#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */ +#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */ +#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */ +#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */ +#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */ +#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */ +#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */ +#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */ + +/* USB Endpoint 6 Control Registers */ + +#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */ +#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */ +#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */ +#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */ +#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */ +#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */ +#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */ +#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */ +#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */ + +/* USB Endpoint 7 Control Registers */ + +#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */ +#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */ +#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */ +#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */ +#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */ +#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */ +#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */ +#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */ +#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */ +#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */ +#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */ + +/* USB Channel 0 Config Registers */ + +#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */ +#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */ +#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */ +#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */ + +/* USB Channel 1 Config Registers */ + +#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */ +#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */ +#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */ +#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */ + +/* USB Channel 2 Config Registers */ + +#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */ +#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */ +#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */ +#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */ + +/* USB Channel 3 Config Registers */ + +#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */ +#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */ +#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */ +#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */ + +/* USB Channel 4 Config Registers */ + +#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */ +#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */ +#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */ +#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */ + +/* USB Channel 5 Config Registers */ + +#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */ +#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */ +#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */ +#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */ + +/* USB Channel 6 Config Registers */ + +#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */ +#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */ +#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */ +#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */ + +/* USB Channel 7 Config Registers */ + +#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */ +#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */ +#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */ +#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */ + +/* Keypad Registers */ + +#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */ +#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */ +#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */ +#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */ +#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */ +#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */ + +/* Pixel Compositor (PIXC) Registers */ + +#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */ +#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */ +#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */ +#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */ +#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */ +#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */ +#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */ +#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */ +#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */ +#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */ +#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */ +#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */ +#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */ +#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */ +#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */ +#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */ +#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */ +#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */ +#define PIXC_TC 0xffc04450 /* Holds the transparent color value */ + +/* Handshake MDMA 0 Registers */ + +#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */ +#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */ +#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */ +#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshold Register */ +#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */ +#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */ +#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */ + +/* Handshake MDMA 1 Registers */ + +#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */ +#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */ +#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */ +#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshold Register */ +#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */ +#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */ +#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */ + + +/* ********************************************************** */ +/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ +/* and MULTI BIT READ MACROS */ +/* ********************************************************** */ + +/* Bit masks for PIXC_CTL */ + +#define PIXC_EN 0x1 /* Pixel Compositor Enable */ +#define OVR_A_EN 0x2 /* Overlay A Enable */ +#define OVR_B_EN 0x4 /* Overlay B Enable */ +#define IMG_FORM 0x8 /* Image Data Format */ +#define OVR_FORM 0x10 /* Overlay Data Format */ +#define OUT_FORM 0x20 /* Output Data Format */ +#define UDS_MOD 0x40 /* Resampling Mode */ +#define TC_EN 0x80 /* Transparent Color Enable */ +#define IMG_STAT 0x300 /* Image FIFO Status */ +#define OVR_STAT 0xc00 /* Overlay FIFO Status */ +#define WM_LVL 0x3000 /* FIFO Watermark Level */ + +/* Bit masks for PIXC_AHSTART */ + +#define A_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_AHEND */ + +#define A_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_AVSTART */ + +#define A_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_AVEND */ + +#define A_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_ATRANSP */ + +#define A_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_BHSTART */ + +#define B_HSTART 0xfff /* Horizontal Start Coordinates */ + +/* Bit masks for PIXC_BHEND */ + +#define B_HEND 0xfff /* Horizontal End Coordinates */ + +/* Bit masks for PIXC_BVSTART */ + +#define B_VSTART 0x3ff /* Vertical Start Coordinates */ + +/* Bit masks for PIXC_BVEND */ + +#define B_VEND 0x3ff /* Vertical End Coordinates */ + +/* Bit masks for PIXC_BTRANSP */ + +#define B_TRANSP 0xf /* Transparency Value */ + +/* Bit masks for PIXC_INTRSTAT */ + +#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ +#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ +#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ +#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ + +/* Bit masks for PIXC_RYCON */ + +#define A11 0x3ff /* A11 in the Coefficient Matrix */ +#define A12 0xffc00 /* A12 in the Coefficient Matrix */ +#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ +#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_GUCON */ + +#define A21 0x3ff /* A21 in the Coefficient Matrix */ +#define A22 0xffc00 /* A22 in the Coefficient Matrix */ +#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ +#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_BVCON */ + +#define A31 0x3ff /* A31 in the Coefficient Matrix */ +#define A32 0xffc00 /* A32 in the Coefficient Matrix */ +#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ +#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ + +/* Bit masks for PIXC_CCBIAS */ + +#define A14 0x3ff /* A14 in the Bias Vector */ +#define A24 0xffc00 /* A24 in the Bias Vector */ +#define A34 0x3ff00000 /* A34 in the Bias Vector */ + +/* Bit masks for PIXC_TC */ + +#define RY_TRANS 0xff /* Transparent Color - R/Y Component */ +#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */ +#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */ + +/* Bit masks for HOST_CONTROL */ + +#define HOST_EN 0x1 /* Host Enable */ +#define HOST_END 0x2 /* Host Endianess */ +#define DATA_SIZE 0x4 /* Data Size */ +#define HOST_RST 0x8 /* Host Reset */ +#define HRDY_OVR 0x20 /* Host Ready Override */ +#define INT_MODE 0x40 /* Interrupt Mode */ +#define BT_EN 0x80 /* Bus Timeout Enable */ +#define EHW 0x100 /* Enable Host Write */ +#define EHR 0x200 /* Enable Host Read */ +#define BDR 0x400 /* Burst DMA Requests */ + +/* Bit masks for HOST_STATUS */ + +#define DMA_READY 0x1 /* DMA Ready */ +#define FIFOFULL 0x2 /* FIFO Full */ +#define FIFOEMPTY 0x4 /* FIFO Empty */ +#define DMA_COMPLETE 0x8 /* DMA Complete */ +#define HSHK 0x10 /* Host Handshake */ +#define TIMEOUT 0x20 /* Host Timeout */ +#define HIRQ 0x40 /* Host Interrupt Request */ +#define ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define DMA_DIR 0x100 /* DMA Direction */ +#define BTE 0x200 /* Bus Timeout Enabled */ + +/* Bit masks for HOST_TIMEOUT */ + +#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ + +/* Bit masks for MXVR_CONFIG */ + +#define MXVREN 0x1 /* MXVR Enable */ +#define MMSM 0x2 /* MXVR Master/Slave Mode Select */ +#define ACTIVE 0x4 /* Active Mode */ +#define SDELAY 0x8 /* Synchronous Data Delay */ +#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ +#define RWRRXEN 0x20 /* Remote Write Receive Enable */ +#define MTXEN 0x40 /* MXVR Transmit Data Enable */ +#define MTXONB 0x80 /* MXVR Phy Transmitter On */ +#define EPARITY 0x100 /* Even Parity Select */ +#define MSB 0x1e00 /* Master Synchronous Boundary */ +#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ +#define WAKEUP 0x4000 /* Wake-Up */ +#define LMECH 0x8000 /* Lock Mechanism Select */ + +/* Bit masks for MXVR_STATE_0 */ + +#define NACT 0x1 /* Network Activity */ +#define SBLOCK 0x2 /* Super Block Lock */ +#define FMPLLST 0xc /* Frequency Multiply PLL SM State */ +#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ +#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ +#define APARB 0x200 /* Asynchronous Packet Arbitrating */ +#define APTX 0x400 /* Asynchronous Packet Transmitting */ +#define APRX 0x800 /* Receiving Asynchronous Packet */ +#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ +#define CMARB 0x2000 /* Control Message Arbitrating */ +#define CMTX 0x4000 /* Control Message Transmitting */ +#define CMRX 0x8000 /* Receiving Control Message */ +#define MRXONB 0x10000 /* MRXONB Pin State */ +#define RGSIP 0x20000 /* Remote Get Source In Progress */ +#define DALIP 0x40000 /* Resource Deallocate In Progress */ +#define ALIP 0x80000 /* Resource Allocate In Progress */ +#define RRDIP 0x100000 /* Remote Read In Progress */ +#define RWRIP 0x200000 /* Remote Write In Progress */ +#define FLOCK 0x400000 /* Frame Lock */ +#define BLOCK 0x800000 /* Block Lock */ +#define RSB 0xf000000 /* Received Synchronous Boundary */ +#define DERRNUM 0xf0000000 /* DMA Error Channel Number */ + +/* Bit masks for MXVR_STATE_1 */ + +#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ +#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ +#define APCONT 0x100 /* Asynchronous Packet Continuation */ +#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ +#define DMAACTIVE0 0x10000 /* DMA0 Active */ +#define DMAACTIVE1 0x20000 /* DMA1 Active */ +#define DMAACTIVE2 0x40000 /* DMA2 Active */ +#define DMAACTIVE3 0x80000 /* DMA3 Active */ +#define DMAACTIVE4 0x100000 /* DMA4 Active */ +#define DMAACTIVE5 0x200000 /* DMA5 Active */ +#define DMAACTIVE6 0x400000 /* DMA6 Active */ +#define DMAACTIVE7 0x800000 /* DMA7 Active */ +#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ +#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ +#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ +#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ +#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ +#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ +#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ +#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ + +/* Bit masks for MXVR_INT_STAT_0 */ + +#define NI2A 0x1 /* Network Inactive to Active */ +#define NA2I 0x2 /* Network Active to Inactive */ +#define SBU2L 0x4 /* Super Block Unlock to Lock */ +#define SBL2U 0x8 /* Super Block Lock to Unlock */ +#define PRU 0x10 /* Position Register Updated */ +#define MPRU 0x20 /* Maximum Position Register Updated */ +#define DRU 0x40 /* Delay Register Updated */ +#define MDRU 0x80 /* Maximum Delay Register Updated */ +#define SBU 0x100 /* Synchronous Boundary Updated */ +#define ATU 0x200 /* Allocation Table Updated */ +#define FCZ0 0x400 /* Frame Counter 0 Zero */ +#define FCZ1 0x800 /* Frame Counter 1 Zero */ +#define PERR 0x1000 /* Parity Error */ +#define MH2L 0x2000 /* MRXONB High to Low */ +#define ML2H 0x4000 /* MRXONB Low to High */ +#define WUP 0x8000 /* Wake-Up Preamble Received */ +#define FU2L 0x10000 /* Frame Unlock to Lock */ +#define FL2U 0x20000 /* Frame Lock to Unlock */ +#define BU2L 0x40000 /* Block Unlock to Lock */ +#define BL2U 0x80000 /* Block Lock to Unlock */ +#define OBERR 0x100000 /* DMA Out of Bounds Error */ +#define PFL 0x200000 /* PLL Frequency Locked */ +#define SCZ 0x400000 /* System Clock Counter Zero */ +#define FERR 0x800000 /* FIFO Error */ +#define CMR 0x1000000 /* Control Message Received */ +#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ +#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ +#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ +#define RWRC 0x10000000 /* Remote Write Control Message Completed */ +#define BCZ 0x20000000 /* Block Counter Zero */ +#define BMERR 0x40000000 /* Biphase Mark Coding Error */ +#define DERR 0x80000000 /* DMA Error */ + +/* Bit masks for MXVR_INT_STAT_1 */ + +#define HDONE0 0x1 /* DMA0 Half Done */ +#define DONE0 0x2 /* DMA0 Done */ +#define APR 0x4 /* Asynchronous Packet Received */ +#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ +#define HDONE1 0x10 /* DMA1 Half Done */ +#define DONE1 0x20 /* DMA1 Done */ +#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ +#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ +#define HDONE2 0x100 /* DMA2 Half Done */ +#define DONE2 0x200 /* DMA2 Done */ +#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ +#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ +#define HDONE3 0x1000 /* DMA3 Half Done */ +#define DONE3 0x2000 /* DMA3 Done */ +#define HDONE4 0x10000 /* DMA4 Half Done */ +#define DONE4 0x20000 /* DMA4 Done */ +#define HDONE5 0x100000 /* DMA5 Half Done */ +#define DONE5 0x200000 /* DMA5 Done */ +#define HDONE6 0x1000000 /* DMA6 Half Done */ +#define DONE6 0x2000000 /* DMA6 Done */ +#define HDONE7 0x10000000 /* DMA7 Half Done */ +#define DONE7 0x20000000 /* DMA7 Done */ + +/* Bit masks for MXVR_INT_EN_0 */ + +#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ +#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ +#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ +#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ +#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ +#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ +#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ +#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ +#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ +#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ +#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ +#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ +#define PERREN 0x1000 /* Parity Error Interrupt Enable */ +#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ +#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ +#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ +#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ +#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ +#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ +#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ +#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ +#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ +#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ +#define FERREN 0x800000 /* FIFO Error Interrupt Enable */ +#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ +#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ +#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ +#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ +#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ +#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ +#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ +#define DERREN 0x80000000 /* DMA Error Interrupt Enable */ + +/* Bit masks for MXVR_INT_EN_1 */ + +#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ +#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ +#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ +#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ +#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ +#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ +#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ +#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ +#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ +#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ +#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ +#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ +#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ +#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ +#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ +#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ +#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ +#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ +#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ +#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ +#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ +#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ + +/* Bit masks for MXVR_POSITION */ + +#define POSITION 0x3f /* Node Position */ +#define PVALID 0x8000 /* Node Position Valid */ + +/* Bit masks for MXVR_MAX_POSITION */ + +#define MPOSITION 0x3f /* Maximum Node Position */ +#define MPVALID 0x8000 /* Maximum Node Position Valid */ + +/* Bit masks for MXVR_DELAY */ + +#define DELAY 0x3f /* Node Frame Delay */ +#define DVALID 0x8000 /* Node Frame Delay Valid */ + +/* Bit masks for MXVR_MAX_DELAY */ + +#define MDELAY 0x3f /* Maximum Node Frame Delay */ +#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ + +/* Bit masks for MXVR_LADDR */ + +#define LADDR 0xffff /* Logical Address */ +#define LVALID 0x80000000 /* Logical Address Valid */ + +/* Bit masks for MXVR_GADDR */ + +#define GADDRL 0xff /* Group Address Lower Byte */ +#define GVALID 0x8000 /* Group Address Valid */ + +/* Bit masks for MXVR_AADDR */ + +#define AADDR 0xffff /* Alternate Address */ +#define AVALID 0x80000000 /* Alternate Address Valid */ + +/* Bit masks for MXVR_ALLOC_0 */ + +#define CL0 0x7f /* Channel 0 Connection Label */ +#define CIU0 0x80 /* Channel 0 In Use */ +#define CL1 0x7f00 /* Channel 0 Connection Label */ +#define CIU1 0x8000 /* Channel 0 In Use */ +#define CL2 0x7f0000 /* Channel 0 Connection Label */ +#define CIU2 0x800000 /* Channel 0 In Use */ +#define CL3 0x7f000000 /* Channel 0 Connection Label */ +#define CIU3 0x80000000 /* Channel 0 In Use */ + +/* Bit masks for MXVR_ALLOC_1 */ + +#define CL4 0x7f /* Channel 4 Connection Label */ +#define CIU4 0x80 /* Channel 4 In Use */ +#define CL5 0x7f00 /* Channel 5 Connection Label */ +#define CIU5 0x8000 /* Channel 5 In Use */ +#define CL6 0x7f0000 /* Channel 6 Connection Label */ +#define CIU6 0x800000 /* Channel 6 In Use */ +#define CL7 0x7f000000 /* Channel 7 Connection Label */ +#define CIU7 0x80000000 /* Channel 7 In Use */ + +/* Bit masks for MXVR_ALLOC_2 */ + +#define CL8 0x7f /* Channel 8 Connection Label */ +#define CIU8 0x80 /* Channel 8 In Use */ +#define CL9 0x7f00 /* Channel 9 Connection Label */ +#define CIU9 0x8000 /* Channel 9 In Use */ +#define CL10 0x7f0000 /* Channel 10 Connection Label */ +#define CIU10 0x800000 /* Channel 10 In Use */ +#define CL11 0x7f000000 /* Channel 11 Connection Label */ +#define CIU11 0x80000000 /* Channel 11 In Use */ + +/* Bit masks for MXVR_ALLOC_3 */ + +#define CL12 0x7f /* Channel 12 Connection Label */ +#define CIU12 0x80 /* Channel 12 In Use */ +#define CL13 0x7f00 /* Channel 13 Connection Label */ +#define CIU13 0x8000 /* Channel 13 In Use */ +#define CL14 0x7f0000 /* Channel 14 Connection Label */ +#define CIU14 0x800000 /* Channel 14 In Use */ +#define CL15 0x7f000000 /* Channel 15 Connection Label */ +#define CIU15 0x80000000 /* Channel 15 In Use */ + +/* Bit masks for MXVR_ALLOC_4 */ + +#define CL16 0x7f /* Channel 16 Connection Label */ +#define CIU16 0x80 /* Channel 16 In Use */ +#define CL17 0x7f00 /* Channel 17 Connection Label */ +#define CIU17 0x8000 /* Channel 17 In Use */ +#define CL18 0x7f0000 /* Channel 18 Connection Label */ +#define CIU18 0x800000 /* Channel 18 In Use */ +#define CL19 0x7f000000 /* Channel 19 Connection Label */ +#define CIU19 0x80000000 /* Channel 19 In Use */ + +/* Bit masks for MXVR_ALLOC_5 */ + +#define CL20 0x7f /* Channel 20 Connection Label */ +#define CIU20 0x80 /* Channel 20 In Use */ +#define CL21 0x7f00 /* Channel 21 Connection Label */ +#define CIU21 0x8000 /* Channel 21 In Use */ +#define CL22 0x7f0000 /* Channel 22 Connection Label */ +#define CIU22 0x800000 /* Channel 22 In Use */ +#define CL23 0x7f000000 /* Channel 23 Connection Label */ +#define CIU23 0x80000000 /* Channel 23 In Use */ + +/* Bit masks for MXVR_ALLOC_6 */ + +#define CL24 0x7f /* Channel 24 Connection Label */ +#define CIU24 0x80 /* Channel 24 In Use */ +#define CL25 0x7f00 /* Channel 25 Connection Label */ +#define CIU25 0x8000 /* Channel 25 In Use */ +#define CL26 0x7f0000 /* Channel 26 Connection Label */ +#define CIU26 0x800000 /* Channel 26 In Use */ +#define CL27 0x7f000000 /* Channel 27 Connection Label */ +#define CIU27 0x80000000 /* Channel 27 In Use */ + +/* Bit masks for MXVR_ALLOC_7 */ + +#define CL28 0x7f /* Channel 28 Connection Label */ +#define CIU28 0x80 /* Channel 28 In Use */ +#define CL29 0x7f00 /* Channel 29 Connection Label */ +#define CIU29 0x8000 /* Channel 29 In Use */ +#define CL30 0x7f0000 /* Channel 30 Connection Label */ +#define CIU30 0x800000 /* Channel 30 In Use */ +#define CL31 0x7f000000 /* Channel 31 Connection Label */ +#define CIU31 0x80000000 /* Channel 31 In Use */ + +/* Bit masks for MXVR_ALLOC_8 */ + +#define CL32 0x7f /* Channel 32 Connection Label */ +#define CIU32 0x80 /* Channel 32 In Use */ +#define CL33 0x7f00 /* Channel 33 Connection Label */ +#define CIU33 0x8000 /* Channel 33 In Use */ +#define CL34 0x7f0000 /* Channel 34 Connection Label */ +#define CIU34 0x800000 /* Channel 34 In Use */ +#define CL35 0x7f000000 /* Channel 35 Connection Label */ +#define CIU35 0x80000000 /* Channel 35 In Use */ + +/* Bit masks for MXVR_ALLOC_9 */ + +#define CL36 0x7f /* Channel 36 Connection Label */ +#define CIU36 0x80 /* Channel 36 In Use */ +#define CL37 0x7f00 /* Channel 37 Connection Label */ +#define CIU37 0x8000 /* Channel 37 In Use */ +#define CL38 0x7f0000 /* Channel 38 Connection Label */ +#define CIU38 0x800000 /* Channel 38 In Use */ +#define CL39 0x7f000000 /* Channel 39 Connection Label */ +#define CIU39 0x80000000 /* Channel 39 In Use */ + +/* Bit masks for MXVR_ALLOC_10 */ + +#define CL40 0x7f /* Channel 40 Connection Label */ +#define CIU40 0x80 /* Channel 40 In Use */ +#define CL41 0x7f00 /* Channel 41 Connection Label */ +#define CIU41 0x8000 /* Channel 41 In Use */ +#define CL42 0x7f0000 /* Channel 42 Connection Label */ +#define CIU42 0x800000 /* Channel 42 In Use */ +#define CL43 0x7f000000 /* Channel 43 Connection Label */ +#define CIU43 0x80000000 /* Channel 43 In Use */ + +/* Bit masks for MXVR_ALLOC_11 */ + +#define CL44 0x7f /* Channel 44 Connection Label */ +#define CIU44 0x80 /* Channel 44 In Use */ +#define CL45 0x7f00 /* Channel 45 Connection Label */ +#define CIU45 0x8000 /* Channel 45 In Use */ +#define CL46 0x7f0000 /* Channel 46 Connection Label */ +#define CIU46 0x800000 /* Channel 46 In Use */ +#define CL47 0x7f000000 /* Channel 47 Connection Label */ +#define CIU47 0x80000000 /* Channel 47 In Use */ + +/* Bit masks for MXVR_ALLOC_12 */ + +#define CL48 0x7f /* Channel 48 Connection Label */ +#define CIU48 0x80 /* Channel 48 In Use */ +#define CL49 0x7f00 /* Channel 49 Connection Label */ +#define CIU49 0x8000 /* Channel 49 In Use */ +#define CL50 0x7f0000 /* Channel 50 Connection Label */ +#define CIU50 0x800000 /* Channel 50 In Use */ +#define CL51 0x7f000000 /* Channel 51 Connection Label */ +#define CIU51 0x80000000 /* Channel 51 In Use */ + +/* Bit masks for MXVR_ALLOC_13 */ + +#define CL52 0x7f /* Channel 52 Connection Label */ +#define CIU52 0x80 /* Channel 52 In Use */ +#define CL53 0x7f00 /* Channel 53 Connection Label */ +#define CIU53 0x8000 /* Channel 53 In Use */ +#define CL54 0x7f0000 /* Channel 54 Connection Label */ +#define CIU54 0x800000 /* Channel 54 In Use */ +#define CL55 0x7f000000 /* Channel 55 Connection Label */ +#define CIU55 0x80000000 /* Channel 55 In Use */ + +/* Bit masks for MXVR_ALLOC_14 */ + +#define CL56 0x7f /* Channel 56 Connection Label */ +#define CIU56 0x80 /* Channel 56 In Use */ +#define CL57 0x7f00 /* Channel 57 Connection Label */ +#define CIU57 0x8000 /* Channel 57 In Use */ +#define CL58 0x7f0000 /* Channel 58 Connection Label */ +#define CIU58 0x800000 /* Channel 58 In Use */ +#define CL59 0x7f000000 /* Channel 59 Connection Label */ +#define CIU59 0x80000000 /* Channel 59 In Use */ + +/* MXVR_SYNC_LCHAN_0 Masks */ + +#define LCHANPC0 0x0000000Flu +#define LCHANPC1 0x000000F0lu +#define LCHANPC2 0x00000F00lu +#define LCHANPC3 0x0000F000lu +#define LCHANPC4 0x000F0000lu +#define LCHANPC5 0x00F00000lu +#define LCHANPC6 0x0F000000lu +#define LCHANPC7 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_1 Masks */ + +#define LCHANPC8 0x0000000Flu +#define LCHANPC9 0x000000F0lu +#define LCHANPC10 0x00000F00lu +#define LCHANPC11 0x0000F000lu +#define LCHANPC12 0x000F0000lu +#define LCHANPC13 0x00F00000lu +#define LCHANPC14 0x0F000000lu +#define LCHANPC15 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_2 Masks */ + +#define LCHANPC16 0x0000000Flu +#define LCHANPC17 0x000000F0lu +#define LCHANPC18 0x00000F00lu +#define LCHANPC19 0x0000F000lu +#define LCHANPC20 0x000F0000lu +#define LCHANPC21 0x00F00000lu +#define LCHANPC22 0x0F000000lu +#define LCHANPC23 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_3 Masks */ + +#define LCHANPC24 0x0000000Flu +#define LCHANPC25 0x000000F0lu +#define LCHANPC26 0x00000F00lu +#define LCHANPC27 0x0000F000lu +#define LCHANPC28 0x000F0000lu +#define LCHANPC29 0x00F00000lu +#define LCHANPC30 0x0F000000lu +#define LCHANPC31 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_4 Masks */ + +#define LCHANPC32 0x0000000Flu +#define LCHANPC33 0x000000F0lu +#define LCHANPC34 0x00000F00lu +#define LCHANPC35 0x0000F000lu +#define LCHANPC36 0x000F0000lu +#define LCHANPC37 0x00F00000lu +#define LCHANPC38 0x0F000000lu +#define LCHANPC39 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_5 Masks */ + +#define LCHANPC40 0x0000000Flu +#define LCHANPC41 0x000000F0lu +#define LCHANPC42 0x00000F00lu +#define LCHANPC43 0x0000F000lu +#define LCHANPC44 0x000F0000lu +#define LCHANPC45 0x00F00000lu +#define LCHANPC46 0x0F000000lu +#define LCHANPC47 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_6 Masks */ + +#define LCHANPC48 0x0000000Flu +#define LCHANPC49 0x000000F0lu +#define LCHANPC50 0x00000F00lu +#define LCHANPC51 0x0000F000lu +#define LCHANPC52 0x000F0000lu +#define LCHANPC53 0x00F00000lu +#define LCHANPC54 0x0F000000lu +#define LCHANPC55 0xF0000000lu + + +/* MXVR_SYNC_LCHAN_7 Masks */ + +#define LCHANPC56 0x0000000Flu +#define LCHANPC57 0x000000F0lu +#define LCHANPC58 0x00000F00lu +#define LCHANPC59 0x0000F000lu + +/* Bit masks for MXVR_DMAx_CONFIG */ + +#define MDMAEN 0x1 /* DMA Channel Enable */ +#define DMADD 0x2 /* DMA Channel Direction */ +#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ +#define LCHAN 0x3c0 /* DMA Channel Logical Channel */ +#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ +#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ +#define MFLOW 0x7000 /* DMA Channel Operation Flow */ +#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ +#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ +#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ +#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ + +/* Bit masks for MXVR_AP_CTL */ + +#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ +#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ +#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ +#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ +#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ + +/* Bit masks for MXVR_APRB_START_ADDR */ + +#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ + +/* Bit masks for MXVR_APRB_CURR_ADDR */ + +#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ + +/* Bit masks for MXVR_APTB_START_ADDR */ + +#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ + +/* Bit masks for MXVR_APTB_CURR_ADDR */ + +#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ + +/* Bit masks for MXVR_CM_CTL */ + +#define STARTCM 0x1 /* Start Control Message Transmission */ +#define CANCELCM 0x2 /* Cancel Control Message Transmission */ +#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ +#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ +#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ +#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ +#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ +#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ +#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ +#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ +#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ +#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ +#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ +#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ +#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ +#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ +#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ +#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ + +/* Bit masks for MXVR_CMRB_START_ADDR */ + +#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */ + +/* Bit masks for MXVR_CMRB_CURR_ADDR */ + +#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */ + +/* Bit masks for MXVR_CMTB_START_ADDR */ + +#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */ + +/* Bit masks for MXVR_CMTB_CURR_ADDR */ + +#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */ + +/* Bit masks for MXVR_RRDB_START_ADDR */ + +#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */ + +/* Bit masks for MXVR_RRDB_CURR_ADDR */ + +#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */ + +/* Bit masks for MXVR_PAT_DATAx */ + +#define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */ +#define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */ +#define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */ +#define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */ + +/* Bit masks for MXVR_PAT_EN_0 */ + +#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ +#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ +#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ +#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ +#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ +#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ +#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ +#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ +#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ +#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ +#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ +#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ +#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ +#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ +#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ +#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ +#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ +#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ +#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ +#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ +#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ +#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ +#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ +#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ +#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ +#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ +#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ +#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ +#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ +#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ +#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ +#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ + +/* Bit masks for MXVR_PAT_EN_1 */ + +#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ +#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ +#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ +#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ +#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ +#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ +#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ +#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ +#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ +#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ +#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ +#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ +#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ +#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ +#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ +#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ +#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ +#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ +#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ +#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ +#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ +#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ +#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ +#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ +#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ +#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ +#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ +#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ +#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ +#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ +#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ +#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ + +/* Bit masks for MXVR_FRAME_CNT_0 */ + +#define FCNT 0xffff /* Frame Count */ + +/* Bit masks for MXVR_FRAME_CNT_1 */ + +#define FCNT 0xffff /* Frame Count */ + +/* Bit masks for MXVR_ROUTING_0 */ + +#define TX_CH0 0x3f /* Transmit Channel 0 */ +#define MUTE_CH0 0x80 /* Mute Channel 0 */ +#define TX_CH1 0x3f00 /* Transmit Channel 0 */ +#define MUTE_CH1 0x8000 /* Mute Channel 0 */ +#define TX_CH2 0x3f0000 /* Transmit Channel 0 */ +#define MUTE_CH2 0x800000 /* Mute Channel 0 */ +#define TX_CH3 0x3f000000 /* Transmit Channel 0 */ +#define MUTE_CH3 0x80000000 /* Mute Channel 0 */ + +/* Bit masks for MXVR_ROUTING_1 */ + +#define TX_CH4 0x3f /* Transmit Channel 4 */ +#define MUTE_CH4 0x80 /* Mute Channel 4 */ +#define TX_CH5 0x3f00 /* Transmit Channel 5 */ +#define MUTE_CH5 0x8000 /* Mute Channel 5 */ +#define TX_CH6 0x3f0000 /* Transmit Channel 6 */ +#define MUTE_CH6 0x800000 /* Mute Channel 6 */ +#define TX_CH7 0x3f000000 /* Transmit Channel 7 */ +#define MUTE_CH7 0x80000000 /* Mute Channel 7 */ + +/* Bit masks for MXVR_ROUTING_2 */ + +#define TX_CH8 0x3f /* Transmit Channel 8 */ +#define MUTE_CH8 0x80 /* Mute Channel 8 */ +#define TX_CH9 0x3f00 /* Transmit Channel 9 */ +#define MUTE_CH9 0x8000 /* Mute Channel 9 */ +#define TX_CH10 0x3f0000 /* Transmit Channel 10 */ +#define MUTE_CH10 0x800000 /* Mute Channel 10 */ +#define TX_CH11 0x3f000000 /* Transmit Channel 11 */ +#define MUTE_CH11 0x80000000 /* Mute Channel 11 */ + +/* Bit masks for MXVR_ROUTING_3 */ + +#define TX_CH12 0x3f /* Transmit Channel 12 */ +#define MUTE_CH12 0x80 /* Mute Channel 12 */ +#define TX_CH13 0x3f00 /* Transmit Channel 13 */ +#define MUTE_CH13 0x8000 /* Mute Channel 13 */ +#define TX_CH14 0x3f0000 /* Transmit Channel 14 */ +#define MUTE_CH14 0x800000 /* Mute Channel 14 */ +#define TX_CH15 0x3f000000 /* Transmit Channel 15 */ +#define MUTE_CH15 0x80000000 /* Mute Channel 15 */ + +/* Bit masks for MXVR_ROUTING_4 */ + +#define TX_CH16 0x3f /* Transmit Channel 16 */ +#define MUTE_CH16 0x80 /* Mute Channel 16 */ +#define TX_CH17 0x3f00 /* Transmit Channel 17 */ +#define MUTE_CH17 0x8000 /* Mute Channel 17 */ +#define TX_CH18 0x3f0000 /* Transmit Channel 18 */ +#define MUTE_CH18 0x800000 /* Mute Channel 18 */ +#define TX_CH19 0x3f000000 /* Transmit Channel 19 */ +#define MUTE_CH19 0x80000000 /* Mute Channel 19 */ + +/* Bit masks for MXVR_ROUTING_5 */ + +#define TX_CH20 0x3f /* Transmit Channel 20 */ +#define MUTE_CH20 0x80 /* Mute Channel 20 */ +#define TX_CH21 0x3f00 /* Transmit Channel 21 */ +#define MUTE_CH21 0x8000 /* Mute Channel 21 */ +#define TX_CH22 0x3f0000 /* Transmit Channel 22 */ +#define MUTE_CH22 0x800000 /* Mute Channel 22 */ +#define TX_CH23 0x3f000000 /* Transmit Channel 23 */ +#define MUTE_CH23 0x80000000 /* Mute Channel 23 */ + +/* Bit masks for MXVR_ROUTING_6 */ + +#define TX_CH24 0x3f /* Transmit Channel 24 */ +#define MUTE_CH24 0x80 /* Mute Channel 24 */ +#define TX_CH25 0x3f00 /* Transmit Channel 25 */ +#define MUTE_CH25 0x8000 /* Mute Channel 25 */ +#define TX_CH26 0x3f0000 /* Transmit Channel 26 */ +#define MUTE_CH26 0x800000 /* Mute Channel 26 */ +#define TX_CH27 0x3f000000 /* Transmit Channel 27 */ +#define MUTE_CH27 0x80000000 /* Mute Channel 27 */ + +/* Bit masks for MXVR_ROUTING_7 */ + +#define TX_CH28 0x3f /* Transmit Channel 28 */ +#define MUTE_CH28 0x80 /* Mute Channel 28 */ +#define TX_CH29 0x3f00 /* Transmit Channel 29 */ +#define MUTE_CH29 0x8000 /* Mute Channel 29 */ +#define TX_CH30 0x3f0000 /* Transmit Channel 30 */ +#define MUTE_CH30 0x800000 /* Mute Channel 30 */ +#define TX_CH31 0x3f000000 /* Transmit Channel 31 */ +#define MUTE_CH31 0x80000000 /* Mute Channel 31 */ + +/* Bit masks for MXVR_ROUTING_8 */ + +#define TX_CH32 0x3f /* Transmit Channel 32 */ +#define MUTE_CH32 0x80 /* Mute Channel 32 */ +#define TX_CH33 0x3f00 /* Transmit Channel 33 */ +#define MUTE_CH33 0x8000 /* Mute Channel 33 */ +#define TX_CH34 0x3f0000 /* Transmit Channel 34 */ +#define MUTE_CH34 0x800000 /* Mute Channel 34 */ +#define TX_CH35 0x3f000000 /* Transmit Channel 35 */ +#define MUTE_CH35 0x80000000 /* Mute Channel 35 */ + +/* Bit masks for MXVR_ROUTING_9 */ + +#define TX_CH36 0x3f /* Transmit Channel 36 */ +#define MUTE_CH36 0x80 /* Mute Channel 36 */ +#define TX_CH37 0x3f00 /* Transmit Channel 37 */ +#define MUTE_CH37 0x8000 /* Mute Channel 37 */ +#define TX_CH38 0x3f0000 /* Transmit Channel 38 */ +#define MUTE_CH38 0x800000 /* Mute Channel 38 */ +#define TX_CH39 0x3f000000 /* Transmit Channel 39 */ +#define MUTE_CH39 0x80000000 /* Mute Channel 39 */ + +/* Bit masks for MXVR_ROUTING_10 */ + +#define TX_CH40 0x3f /* Transmit Channel 40 */ +#define MUTE_CH40 0x80 /* Mute Channel 40 */ +#define TX_CH41 0x3f00 /* Transmit Channel 41 */ +#define MUTE_CH41 0x8000 /* Mute Channel 41 */ +#define TX_CH42 0x3f0000 /* Transmit Channel 42 */ +#define MUTE_CH42 0x800000 /* Mute Channel 42 */ +#define TX_CH43 0x3f000000 /* Transmit Channel 43 */ +#define MUTE_CH43 0x80000000 /* Mute Channel 43 */ + +/* Bit masks for MXVR_ROUTING_11 */ + +#define TX_CH44 0x3f /* Transmit Channel 44 */ +#define MUTE_CH44 0x80 /* Mute Channel 44 */ +#define TX_CH45 0x3f00 /* Transmit Channel 45 */ +#define MUTE_CH45 0x8000 /* Mute Channel 45 */ +#define TX_CH46 0x3f0000 /* Transmit Channel 46 */ +#define MUTE_CH46 0x800000 /* Mute Channel 46 */ +#define TX_CH47 0x3f000000 /* Transmit Channel 47 */ +#define MUTE_CH47 0x80000000 /* Mute Channel 47 */ + +/* Bit masks for MXVR_ROUTING_12 */ + +#define TX_CH48 0x3f /* Transmit Channel 48 */ +#define MUTE_CH48 0x80 /* Mute Channel 48 */ +#define TX_CH49 0x3f00 /* Transmit Channel 49 */ +#define MUTE_CH49 0x8000 /* Mute Channel 49 */ +#define TX_CH50 0x3f0000 /* Transmit Channel 50 */ +#define MUTE_CH50 0x800000 /* Mute Channel 50 */ +#define TX_CH51 0x3f000000 /* Transmit Channel 51 */ +#define MUTE_CH51 0x80000000 /* Mute Channel 51 */ + +/* Bit masks for MXVR_ROUTING_13 */ + +#define TX_CH52 0x3f /* Transmit Channel 52 */ +#define MUTE_CH52 0x80 /* Mute Channel 52 */ +#define TX_CH53 0x3f00 /* Transmit Channel 53 */ +#define MUTE_CH53 0x8000 /* Mute Channel 53 */ +#define TX_CH54 0x3f0000 /* Transmit Channel 54 */ +#define MUTE_CH54 0x800000 /* Mute Channel 54 */ +#define TX_CH55 0x3f000000 /* Transmit Channel 55 */ +#define MUTE_CH55 0x80000000 /* Mute Channel 55 */ + +/* Bit masks for MXVR_ROUTING_14 */ + +#define TX_CH56 0x3f /* Transmit Channel 56 */ +#define MUTE_CH56 0x80 /* Mute Channel 56 */ +#define TX_CH57 0x3f00 /* Transmit Channel 57 */ +#define MUTE_CH57 0x8000 /* Mute Channel 57 */ +#define TX_CH58 0x3f0000 /* Transmit Channel 58 */ +#define MUTE_CH58 0x800000 /* Mute Channel 58 */ +#define TX_CH59 0x3f000000 /* Transmit Channel 59 */ +#define MUTE_CH59 0x80000000 /* Mute Channel 59 */ + +/* Bit masks for MXVR_BLOCK_CNT */ + +#define BCNT 0xffff /* Block Count */ + +/* Bit masks for MXVR_CLK_CTL */ + +#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ +#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ +#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ +#define CLKX3SEL 0x80 /* Clock Generation Source Select */ +#define MMCLKEN 0x100 /* Master Clock Enable */ +#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ +#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ +#define MBCLKEN 0x10000 /* Bit Clock Enable */ +#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ +#define INVRX 0x800000 /* Invert Receive Data */ +#define MFSEN 0x1000000 /* Frame Sync Enable */ +#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ +#define MFSSEL 0x60000000 /* Frame Sync Select */ +#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ + +/* Bit masks for MXVR_CDRPLL_CTL */ + +#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ +#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ +#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ +#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ +#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ +#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ +#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ +#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ +#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ + +/* Bit masks for MXVR_FMPLL_CTL */ + +#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ +#define FMRSTB 0x2 /* MXVR FMPLL Reset */ +#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ +#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ +#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ +#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ + +/* Bit masks for MXVR_PIN_CTL */ + +#define MTXONBOD 0x1 /* MTXONB Open Drain Select */ +#define MTXONBG 0x2 /* MTXONB Gates MTX Select */ +#define MFSOE 0x10 /* MFS Output Enable */ +#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ +#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ + +/* Bit masks for MXVR_SCLK_CNT */ + +#define SCNT 0xffff /* System Clock Count */ + +/* Bit masks for KPAD_CTL */ + +#define KPAD_EN 0x1 /* Keypad Enable */ +#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ +#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ +#define KPAD_COLEN 0xe000 /* Column Enable Width */ + +/* Bit masks for KPAD_PRESCALE */ + +#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */ + +/* Bit masks for KPAD_MSEL */ + +#define DBON_SCALE 0xff /* Debounce Scale Value */ +#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */ + +/* Bit masks for KPAD_ROWCOL */ + +#define KPAD_ROW 0xff /* Rows Pressed */ +#define KPAD_COL 0xff00 /* Columns Pressed */ + +/* Bit masks for KPAD_STAT */ + +#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ +#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ +#define KPAD_PRESSED 0x8 /* Key press current status */ + +/* Bit masks for KPAD_SOFTEVAL */ + +#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ + +/* Bit masks for SDH_COMMAND */ + +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ + +#define PWR_ON 0x3 /* Power On */ +#if 0 +#define TBD 0x3c /* TBD */ +#endif +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ + +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ + +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ + +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ + +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ + +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ + +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ + +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ + +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ + +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ + +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ + +#define RWR 0x1 /* Read Wait Request */ + +/* Bit masks for ATAPI_CONTROL */ + +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ + +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ + +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ + +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ + +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ + +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ + +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ + +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ + +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ + +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ + +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ + +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ + +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ + +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ + +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ + +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ + +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ + +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for TIMER_ENABLE1 */ + +#define TIMEN8 0x1 /* Timer 8 Enable */ +#define TIMEN9 0x2 /* Timer 9 Enable */ +#define TIMEN10 0x4 /* Timer 10 Enable */ + +/* Bit masks for TIMER_DISABLE1 */ + +#define TIMDIS8 0x1 /* Timer 8 Disable */ +#define TIMDIS9 0x2 /* Timer 9 Disable */ +#define TIMDIS10 0x4 /* Timer 10 Disable */ + +/* Bit masks for TIMER_STATUS1 */ + +#define TIMIL8 0x1 /* Timer 8 Interrupt */ +#define TIMIL9 0x2 /* Timer 9 Interrupt */ +#define TIMIL10 0x4 /* Timer 10 Interrupt */ +#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ +#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ +#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ +#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ +#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ +#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ + +/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ +#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ +#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x1 /* Suspend indicator */ +#define RESUME_B 0x2 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ +#define SOF_B 0x8 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ +#define RESUME_BE 0x2 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ +#define SOF_BE 0x8 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x1 /* enables USB module */ +#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +/* Bit masks for USB_DMAxADDRHIGH */ + +#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxADDRLOW */ + +#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTHIGH */ + +#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for USB_DMAxCOUNTLOW */ + +#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ + +/* Bit masks for HMDMAx_CONTROL */ + +#define HMDMAEN 0x1 /* Handshake MDMA Enable */ +#define REP 0x2 /* Handshake MDMA Request Polarity */ +#define UTE 0x8 /* Urgency Threshold Enable */ +#define OIE 0x10 /* Overflow Interrupt Enable */ +#define BDIE 0x20 /* Block Done Interrupt Enable */ +#define MBDI 0x40 /* Mask Block Done Interrupt */ +#define DRQ 0x300 /* Handshake MDMA Request Type */ +#define RBC 0x1000 /* Force Reload of BCOUNT */ +#define PS 0x2000 /* Pin Status */ +#define OI 0x4000 /* Overflow Interrupt Generated */ +#define BDI 0x8000 /* Block Done Interrupt Generated */ + +/* ******************************************* */ +/* MULTI BIT MACRO ENUMERATIONS */ +/* ******************************************* */ + +/* ************************ */ +/* MXVR Address Offsets */ +/* ************************ */ + +/* Control Message Receive Buffer (CMRB) Address Offsets */ + +#define CMRB_STRIDE 0x00000016lu + +#define CMRB_DST_OFFSET 0x00000000lu +#define CMRB_SRC_OFFSET 0x00000002lu +#define CMRB_DATA_OFFSET 0x00000005lu + +/* Control Message Transmit Buffer (CMTB) Address Offsets */ + +#define CMTB_PRIO_OFFSET 0x00000000lu +#define CMTB_DST_OFFSET 0x00000002lu +#define CMTB_SRC_OFFSET 0x00000004lu +#define CMTB_TYPE_OFFSET 0x00000006lu +#define CMTB_DATA_OFFSET 0x00000007lu + +#define CMTB_ANSWER_OFFSET 0x0000000Alu + +#define CMTB_STAT_N_OFFSET 0x00000018lu +#define CMTB_STAT_A_OFFSET 0x00000016lu +#define CMTB_STAT_D_OFFSET 0x0000000Elu +#define CMTB_STAT_R_OFFSET 0x00000014lu +#define CMTB_STAT_W_OFFSET 0x00000014lu +#define CMTB_STAT_G_OFFSET 0x00000014lu + +/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */ + +#define APRB_STRIDE 0x00000400lu + +#define APRB_DST_OFFSET 0x00000000lu +#define APRB_LEN_OFFSET 0x00000002lu +#define APRB_SRC_OFFSET 0x00000004lu +#define APRB_DATA_OFFSET 0x00000006lu + +/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */ + +#define APTB_PRIO_OFFSET 0x00000000lu +#define APTB_DST_OFFSET 0x00000002lu +#define APTB_LEN_OFFSET 0x00000004lu +#define APTB_SRC_OFFSET 0x00000006lu +#define APTB_DATA_OFFSET 0x00000008lu + +/* Remote Read Buffer (RRDB) Address Offsets */ + +#define RRDB_WADDR_OFFSET 0x00000100lu +#define RRDB_WLEN_OFFSET 0x00000101lu + +/* **************** */ +/* MXVR Macros */ +/* **************** */ + +/* MXVR_CONFIG Macros */ + +#define SET_MSB(x) ( ( (x) & 0xF ) << 9) + +/* MXVR_INT_STAT_1 Macros */ + +#define DONEX(x) (0x00000002 << (4 * (x))) +#define HDONEX(x) (0x00000001 << (4 * (x))) + +/* MXVR_INT_EN_1 Macros */ + +#define DONEENX(x) (0x00000002 << (4 * (x))) +#define HDONEENX(x) (0x00000001 << (4 * (x))) + +/* MXVR_CDRPLL_CTL Macros */ + +#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16) + +/* MXVR_FMPLL_CTL Macros */ + +#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24) +#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24) + #endif /* _DEF_BF549_H */ diff --git a/trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h index ab04d137fd8b..8590c8c78336 100644 --- a/trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h +++ b/trunk/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h @@ -1609,6 +1609,44 @@ #define PINT2 0x40000000 /* Pin Interrupt 2 */ #define PINT3 0x80000000 /* Pin Interrupt 3 */ +/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ + +#define DMAEN 0x1 /* DMA Channel Enable */ +#define WNR 0x2 /* DMA Direction */ +#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */ +#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */ +#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */ +#define DMA2D 0x10 /* DMA Mode */ +#define RESTART 0x20 /* Work Unit Transitions */ +#define DI_SEL 0x40 /* Data Interrupt Timing Select */ +#define DI_EN 0x80 /* Data Interrupt Enable */ + +#define NDSIZE 0xf00 /* Flex Descriptor Size */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ + +#define DMAFLOW 0xf000 /* Next Operation */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ + +#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ +#define DMA_ERR 0x2 /* DMA Error Interrupt Status */ +#define DFETCH 0x4 /* DMA Descriptor Fetch */ +#define DMA_RUN 0x8 /* DMA Channel Running */ + /* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ #define CTYPE 0x40 /* DMA Channel Type */ @@ -1777,6 +1815,10 @@ #define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ #define CORE_MERROR 0x80 /* Core Error (2nd) */ +/* Bit masks for EBIU_ERRADD */ + +#define ERROR_ADDRESS 0xffffffff /* Error Address */ + /* Bit masks for EBIU_RSTCTL */ #define DDRSRESET 0x1 /* DDR soft reset */ @@ -1785,6 +1827,98 @@ #define SRACK 0x10 /* Self-refresh acknowledge */ #define MDDRENABLE 0x20 /* Mobile DDR enable */ +/* Bit masks for EBIU_DDRBRC0 */ + +#define BRC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC1 */ + +#define BRC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC2 */ + +#define BRC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC3 */ + +#define BRC3 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC4 */ + +#define BRC4 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC5 */ + +#define BRC5 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC6 */ + +#define BRC6 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBRC7 */ + +#define BRC7 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC0 */ + +#define BWC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC1 */ + +#define BWC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC2 */ + +#define BWC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC3 */ + +#define BWC3 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC4 */ + +#define BWC4 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC5 */ + +#define BWC5 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC6 */ + +#define BWC6 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRBWC7 */ + +#define BWC7 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRACCT */ + +#define ACCT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRTACT */ + +#define TECT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRARCT */ + +#define ARCT 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC0 */ + +#define GC0 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC1 */ + +#define GC1 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC2 */ + +#define GC2 0xffffffff /* Count */ + +/* Bit masks for EBIU_DDRGC3 */ + +#define GC3 0xffffffff /* Count */ + /* Bit masks for EBIU_DDRMCEN */ #define B0WCENABLE 0x1 /* Bank 0 write count enable */ @@ -1958,6 +2092,12 @@ #define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ #define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ +/* Bit masks for WDOG_CTL */ + +#define WDEV 0x6 /* Watchdog Event */ +#define WDEN 0xff0 /* Watchdog Enable */ +#define WDRO 0x8000 /* Watchdog Rolled Over */ + /* Bit masks for CNT_CONFIG */ #define CNTE 0x1 /* Counter Enable */ @@ -2009,6 +2149,81 @@ #define DPRESCALE 0xf /* Load Counter Register */ +/* Bit masks for RTC_STAT */ + +#define SECONDS 0x3f /* Seconds */ +#define MINUTES 0xfc0 /* Minutes */ +#define HOURS 0x1f000 /* Hours */ +#define DAY_COUNTER 0xfffe0000 /* Day Counter */ + +/* Bit masks for RTC_ICTL */ + +#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ +#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ +#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ +#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ +#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ +#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ +#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ +#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ + +/* Bit masks for RTC_ISTAT */ + +#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ +#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ +#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ +#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ +#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ +#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ +#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ +#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ +#define WRITE_COMPLETE 0x8000 /* Write Complete */ + +/* Bit masks for RTC_SWCNT */ + +#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */ + +/* Bit masks for RTC_ALARM */ + +#define SECONDS 0x3f /* Seconds */ +#define MINUTES 0xfc0 /* Minutes */ +#define HOURS 0x1f000 /* Hours */ +#define DAY 0xfffe0000 /* Day */ + +/* Bit masks for RTC_PREN */ + +#define PREN 0x1 /* Prescaler Enable */ + +/* Bit masks for OTP_CONTROL */ + +#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ +#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ +#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ +#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ +#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ +#define FWREN 0x8000 /* OTP/Fuse Write Enable */ + +/* Bit masks for OTP_BEN */ + +#define FBEN 0xffff /* OTP/Fuse Byte Enable */ + +/* Bit masks for OTP_STATUS */ + +#define FCOMP 0x1 /* OTP/Fuse Access Complete */ +#define FERROR 0x2 /* OTP/Fuse Access Error */ +#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ +#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ +#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ + +/* Bit masks for OTP_TIMING */ + +#define USECDIV 0xff /* Micro Second Divider */ +#define READACC 0x7f00 /* Read Access Time */ +#define CPUMPRL 0x38000 /* Charge Pump Release Time */ +#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */ +#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */ +#define PGMTIME 0xff000000 /* Program Time */ + /* Bit masks for SECURE_SYSSWT */ #define EMUDABL 0x1 /* Emulation Disable. */ @@ -2037,6 +2252,26 @@ #define AFEXIT 0x10 /* Authentication Firmware Exit */ #define SECSTAT 0xe0 /* Secure Status */ +/* Bit masks for PLL_DIV */ + +#define CSEL 0x30 /* Core Select */ +#define SSEL 0xf /* System Select */ +#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */ +#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */ +#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */ +#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */ + +/* Bit masks for PLL_CTL */ + +#define MSEL 0x7e00 /* Multiplier Select */ +#define BYPASS 0x100 /* PLL Bypass Enable */ +#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ +#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ +#define PDWN 0x20 /* Power Down */ +#define STOPCK 0x8 /* Stop Clock */ +#define PLL_OFF 0x2 /* Disable PLL */ +#define DF 0x1 /* Divide Frequency */ + /* SWRST Masks */ #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ @@ -2044,6 +2279,52 @@ #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ +/* Bit masks for PLL_STAT */ + +#define PLL_LOCKED 0x20 /* PLL Locked Status */ +#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ +#define FULL_ON 0x2 /* Full-On Mode */ +#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ +#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ +#define CANWS 0x800 /* CAN Wake-Up Status */ +#define USBWS 0x2000 /* USB Wake-Up Status */ +#define KPADWS 0x4000 /* Keypad Wake-Up Status */ +#define ROTWS 0x8000 /* Rotary Wake-Up Status */ +#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ + +/* Bit masks for VR_CTL */ + +#define FREQ 0x3 /* Regulator Switching Frequency */ +#define GAIN 0xc /* Voltage Output Level Gain */ +#define VLEV 0xf0 /* Internal Voltage Level */ +#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ +#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ +#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ +#define GPWE 0x400 /* General-Purpose Wake-Up Enable */ +#define USBWE 0x800 /* USB Wake-Up Enable */ +#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ +#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ + +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + /* Bit masks for NFC_CTL */ #define WR_DLY 0xf /* Write Strobe Delay */ @@ -2208,6 +2489,14 @@ #define UCCT 0x40 /* Universal Counter CAN Trigger */ #define UCE 0x80 /* Universal Counter Enable */ +/* Bit masks for CAN0_UCCNT */ + +#define UCCNT 0xffff /* Universal Counter Count Value */ + +/* Bit masks for CAN0_UCRC */ + +#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */ + /* Bit masks for CAN0_CEC */ #define RXECNT 0xff /* Receive Error Counter */ diff --git a/trunk/arch/blackfin/mach-bf561/boards/Kconfig b/trunk/arch/blackfin/mach-bf561/boards/Kconfig index 1aa529b9f8bb..e4bc6d7c5a6a 100644 --- a/trunk/arch/blackfin/mach-bf561/boards/Kconfig +++ b/trunk/arch/blackfin/mach-bf561/boards/Kconfig @@ -19,11 +19,4 @@ config BFIN561_BLUETECHNIX_CM help CM-BF561 support for EVAL- and DEV-Board. -config BFIN561_ACVILON - bool "BF561-ACVILON" - help - BF561-ACVILON System On Module support (SO-DIMM 144). - For more information about Acvilon BF561 SoM - please go to http://www.niistt.ru/ - endchoice diff --git a/trunk/arch/blackfin/mach-bf561/boards/Makefile b/trunk/arch/blackfin/mach-bf561/boards/Makefile index a5879f7857ad..3a152559e957 100644 --- a/trunk/arch/blackfin/mach-bf561/boards/Makefile +++ b/trunk/arch/blackfin/mach-bf561/boards/Makefile @@ -2,7 +2,6 @@ # arch/blackfin/mach-bf561/boards/Makefile # -obj-$(CONFIG_BFIN561_ACVILON) += acvilon.o obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o obj-$(CONFIG_BFIN561_TEPLA) += tepla.o diff --git a/trunk/arch/blackfin/mach-bf561/boards/acvilon.c b/trunk/arch/blackfin/mach-bf561/boards/acvilon.c deleted file mode 100644 index 07e8dc8770da..000000000000 --- a/trunk/arch/blackfin/mach-bf561/boards/acvilon.c +++ /dev/null @@ -1,551 +0,0 @@ -/* - * File: arch/blackfin/mach-bf561/acvilon.c - * Based on: arch/blackfin/mach-bf561/ezkit.c - * Author: - * - * Created: - * Description: - * - * Modified: - * Copyright 2004-2006 Analog Devices Inc. - * Copyright 2009 CJSC "NII STT" - * - * Bugs: - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see the file COPYING, or write - * to the Free Software Foundation, Inc., - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - * - * For more information about Acvilon BF561 SoM please - * go to http://www.niistt.ru/ - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Name the Board for the /proc/cpuinfo - */ -const char bfin_board_name[] = "Acvilon board"; - -#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) -#include -static struct resource bfin_isp1760_resources[] = { - [0] = { - .start = 0x20000000, - .end = 0x20000000 + 0x000fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PF15, - .end = IRQ_PF15, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct isp1760_platform_data isp1760_priv = { - .is_isp1761 = 0, - .port1_disable = 0, - .bus_width_16 = 1, - .port1_otg = 0, - .analog_oc = 0, - .dack_polarity_high = 0, - .dreq_polarity_high = 0, -}; - -static struct platform_device bfin_isp1760_device = { - .name = "isp1760-hcd", - .id = 0, - .dev = { - .platform_data = &isp1760_priv, - }, - .num_resources = ARRAY_SIZE(bfin_isp1760_resources), - .resource = bfin_isp1760_resources, -}; -#endif - -static struct resource bfin_i2c_pca_resources[] = { - { - .name = "pca9564-regs", - .start = 0x2C000000, - .end = 0x2C000000 + 16, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, - }, { - - .start = IRQ_PF8, - .end = IRQ_PF8, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -struct i2c_pca9564_pf_platform_data pca9564_platform_data = { - .gpio = -1, - .i2c_clock_speed = 330000, - .timeout = 10000 -}; - -/* PCA9564 I2C Bus driver */ -static struct platform_device bfin_i2c_pca_device = { - .name = "i2c-pca-platform", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources), - .resource = bfin_i2c_pca_resources, - .dev = { - .platform_data = &pca9564_platform_data, - } -}; - -/* I2C devices fitted. */ -static struct i2c_board_info acvilon_i2c_devs[] __initdata = { - { - I2C_BOARD_INFO("ds1339", 0x68), - }, - { - I2C_BOARD_INFO("tcn75", 0x49), - }, -}; - -#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) -static struct platdata_mtd_ram mtd_ram_data = { - .mapname = "rootfs(RAM)", - .bankwidth = 4, -}; - -static struct resource mtd_ram_resource = { - .start = 0x4000000, - .end = 0x5ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device mtd_ram_device = { - .name = "mtd-ram", - .id = 0, - .dev = { - .platform_data = &mtd_ram_data, - }, - .num_resources = 1, - .resource = &mtd_ram_resource, -}; -#endif - -#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -#include -static struct resource smsc911x_resources[] = { - { - .name = "smsc911x-memory", - .start = 0x28000000, - .end = 0x28000000 + 0xFF, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_PF7, - .end = IRQ_PF7, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, - }, -}; - -static struct smsc911x_platform_config smsc911x_config = { - .flags = SMSC911X_USE_32BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, - .phy_interface = PHY_INTERFACE_MODE_MII, -}; - -static struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = 0, - .num_resources = ARRAY_SIZE(smsc911x_resources), - .resource = smsc911x_resources, - .dev = { - .platform_data = &smsc911x_config, - }, -}; -#endif - -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -#ifdef CONFIG_SERIAL_BFIN_UART0 -static struct resource bfin_uart0_resources[] = { - { - .start = BFIN_UART_THR, - .end = BFIN_UART_GCTL + 2, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_UART_RX, - .end = IRQ_UART_RX + 1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_UART_ERROR, - .end = IRQ_UART_ERROR, - .flags = IORESOURCE_IRQ, - }, - { - .start = CH_UART_TX, - .end = CH_UART_TX, - .flags = IORESOURCE_DMA, - }, - { - .start = CH_UART_RX, - .end = CH_UART_RX, - .flags = IORESOURCE_DMA, - }, -}; - -unsigned short bfin_uart0_peripherals[] = { - P_UART0_TX, P_UART0_RX, 0 -}; - -static struct platform_device bfin_uart0_device = { - .name = "bfin-uart", - .id = 0, - .num_resources = ARRAY_SIZE(bfin_uart0_resources), - .resource = bfin_uart0_resources, - .dev = { - /* Passed to driver */ - .platform_data = &bfin_uart0_peripherals, - }, -}; -#endif -#endif - -#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) - -#ifdef CONFIG_MTD_PARTITIONS -const char *part_probes[] = { "cmdlinepart", NULL }; - -static struct mtd_partition bfin_plat_nand_partitions[] = { - { - .name = "params(nand)", - .size = 32 * 1024 * 1024, - .offset = 0, - }, { - .name = "userfs(nand)", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; -#endif - -#define BFIN_NAND_PLAT_CLE 2 -#define BFIN_NAND_PLAT_ALE 3 - -static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE)); - else - writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE)); -} - -#define BFIN_NAND_PLAT_READY GPIO_PF10 -static int bfin_plat_nand_dev_ready(struct mtd_info *mtd) -{ - return gpio_get_value(BFIN_NAND_PLAT_READY); -} - -static struct platform_nand_data bfin_plat_nand_data = { - .chip = { - .chip_delay = 30, -#ifdef CONFIG_MTD_PARTITIONS - .part_probe_types = part_probes, - .partitions = bfin_plat_nand_partitions, - .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), -#endif - }, - .ctrl = { - .cmd_ctrl = bfin_plat_nand_cmd_ctrl, - .dev_ready = bfin_plat_nand_dev_ready, - }, -}; - -#define MAX(x, y) (x > y ? x : y) -static struct resource bfin_plat_nand_resources = { - .start = 0x24000000, - .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), - .flags = IORESOURCE_IO, -}; - -static struct platform_device bfin_async_nand_device = { - .name = "gen_nand", - .id = -1, - .num_resources = 1, - .resource = &bfin_plat_nand_resources, - .dev = { - .platform_data = &bfin_plat_nand_data, - }, -}; - -static void bfin_plat_nand_init(void) -{ - gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); -} -#else -static void bfin_plat_nand_init(void) -{ -} -#endif - -#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) -static struct mtd_partition bfin_spi_dataflash_partitions[] = { - { - .name = "bootloader", - .size = 0x4200, - .offset = 0, - .mask_flags = MTD_CAP_ROM}, - { - .name = "u-boot", - .size = 0x42000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "u-boot(params)", - .size = 0x4200, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "kernel", - .size = 0x294000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "params", - .size = 0x42000, - .offset = MTDPART_OFS_APPEND, - }, - { - .name = "rootfs", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct flash_platform_data bfin_spi_dataflash_data = { - .name = "SPI Dataflash", - .parts = bfin_spi_dataflash_partitions, - .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), -}; - -/* DataFlash chip */ -static struct bfin5xx_spi_chip data_flash_chip_info = { - .enable_dma = 0, /* use dma transfer with this chip */ - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) -static struct bfin5xx_spi_chip spidev_chip_info = { - .enable_dma = 0, - .bits_per_word = 8, -}; -#endif - -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) -/* SPI (0) */ -static struct resource bfin_spi0_resource[] = { - [0] = { - .start = SPI0_REGBASE, - .end = SPI0_REGBASE + 0xFF, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = CH_SPI, - .end = CH_SPI, - .flags = IORESOURCE_DMA, - }, - [2] = { - .start = IRQ_SPI, - .end = IRQ_SPI, - .flags = IORESOURCE_IRQ, - }, -}; - -/* SPI controller data */ -static struct bfin5xx_spi_master bfin_spi0_info = { - .num_chipselect = 8, - .enable_dma = 1, /* master has the ability to do dma transfer */ - .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, -}; - -static struct platform_device bfin_spi0_device = { - .name = "bfin-spi", - .id = 0, /* Bus number */ - .num_resources = ARRAY_SIZE(bfin_spi0_resource), - .resource = bfin_spi0_resource, - .dev = { - .platform_data = &bfin_spi0_info, /* Passed to driver */ - }, -}; -#endif - -static struct spi_board_info bfin_spi_board_info[] __initdata = { -#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) - { - .modalias = "spidev", - .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, - .chip_select = 3, - .controller_data = &spidev_chip_info, - }, -#endif -#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) - { /* DataFlash chip */ - .modalias = "mtd_dataflash", - .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */ - .bus_num = 0, /* Framework bus number */ - .chip_select = 2, /* Framework chip select */ - .platform_data = &bfin_spi_dataflash_data, - .controller_data = &data_flash_chip_info, - .mode = SPI_MODE_3, - }, -#endif -}; - -static struct resource bfin_gpios_resources = { - .start = 31, -/* .end = MAX_BLACKFIN_GPIOS - 1, */ - .end = 32, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device bfin_gpios_device = { - .name = "simple-gpio", - .id = -1, - .num_resources = 1, - .resource = &bfin_gpios_resources, -}; - -static const unsigned int cclk_vlev_datasheet[] = { - VRPAIR(VLEV_085, 250000000), - VRPAIR(VLEV_090, 300000000), - VRPAIR(VLEV_095, 313000000), - VRPAIR(VLEV_100, 350000000), - VRPAIR(VLEV_105, 400000000), - VRPAIR(VLEV_110, 444000000), - VRPAIR(VLEV_115, 450000000), - VRPAIR(VLEV_120, 475000000), - VRPAIR(VLEV_125, 500000000), - VRPAIR(VLEV_130, 600000000), -}; - -static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { - .tuple_tab = cclk_vlev_datasheet, - .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), - .vr_settling_time = 25 /* us */ , -}; - -static struct platform_device bfin_dpmc = { - .name = "bfin dpmc", - .dev = { - .platform_data = &bfin_dmpc_vreg_data, - }, -}; - -static struct platform_device *acvilon_devices[] __initdata = { - &bfin_dpmc, - -#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) - &bfin_spi0_device, -#endif - -#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif - - &bfin_gpios_device, - -#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) - &smsc911x_device, -#endif - - &bfin_i2c_pca_device, - -#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) - &bfin_async_nand_device, -#endif - -#if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) - &mtd_ram_device, -#endif - -}; - -static int __init acvilon_init(void) -{ - int ret; - - printk(KERN_INFO "%s(): registering device resources\n", __func__); - - bfin_plat_nand_init(); - ret = - platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices)); - if (ret < 0) - return ret; - - i2c_register_board_info(0, acvilon_i2c_devs, - ARRAY_SIZE(acvilon_i2c_devs)); - - bfin_write_FIO0_FLAG_C(1 << 14); - msleep(5); - bfin_write_FIO0_FLAG_S(1 << 14); - - spi_register_board_info(bfin_spi_board_info, - ARRAY_SIZE(bfin_spi_board_info)); - return 0; -} - -arch_initcall(acvilon_init); - -static struct platform_device *acvilon_early_devices[] __initdata = { -#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) -#ifdef CONFIG_SERIAL_BFIN_UART0 - &bfin_uart0_device, -#endif -#endif -}; - -void __init native_machine_early_platform_add_devices(void) -{ - printk(KERN_INFO "register early platform devices\n"); - early_platform_add_devices(acvilon_early_devices, - ARRAY_SIZE(acvilon_early_devices)); -} diff --git a/trunk/arch/blackfin/mach-bf561/boards/ezkit.c b/trunk/arch/blackfin/mach-bf561/boards/ezkit.c index ffd3e6a80d1a..9e2d8cfba546 100644 --- a/trunk/arch/blackfin/mach-bf561/boards/ezkit.c +++ b/trunk/arch/blackfin/mach-bf561/boards/ezkit.c @@ -49,7 +49,7 @@ static struct isp1760_platform_data isp1760_priv = { }; static struct platform_device bfin_isp1760_device = { - .name = "isp1760", + .name = "isp1760-hcd", .id = 0, .dev = { .platform_data = &isp1760_priv, @@ -159,6 +159,28 @@ static struct platform_device smc91x_device = { }; #endif +#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) +static struct resource ax88180_resources[] = { + [0] = { + .start = 0x2c000000, + .end = 0x2c000000 + 0x8000, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_PF10, + .end = IRQ_PF10, + .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL), + }, +}; + +static struct platform_device ax88180_device = { + .name = "ax88180", + .id = -1, + .num_resources = ARRAY_SIZE(ax88180_resources), + .resource = ax88180_resources, +}; +#endif + #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) static struct resource bfin_uart_resources[] = { { @@ -399,6 +421,10 @@ static struct platform_device *ezkit_devices[] __initdata = { &smc91x_device, #endif +#if defined(CONFIG_AX88180) || defined(CONFIG_AX88180_MODULE) + &ax88180_device, +#endif + #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) &net2272_bfin_device, #endif diff --git a/trunk/arch/blackfin/mach-bf561/coreb.c b/trunk/arch/blackfin/mach-bf561/coreb.c index deb2271d09a3..1e60a92dd602 100644 --- a/trunk/arch/blackfin/mach-bf561/coreb.c +++ b/trunk/arch/blackfin/mach-bf561/coreb.c @@ -22,8 +22,8 @@ #define CMD_COREB_STOP 3 #define CMD_COREB_RESET 4 -static long -coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +static int +coreb_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { int ret = 0; @@ -49,8 +49,8 @@ coreb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } static const struct file_operations coreb_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = coreb_ioctl, + .owner = THIS_MODULE, + .ioctl = coreb_ioctl, }; static struct miscdevice coreb_dev = { diff --git a/trunk/arch/blackfin/mach-bf561/include/mach/defBF561.h b/trunk/arch/blackfin/mach-bf561/include/mach/defBF561.h index 4c8e36b7fb33..a31e509553fb 100644 --- a/trunk/arch/blackfin/mach-bf561/include/mach/defBF561.h +++ b/trunk/arch/blackfin/mach-bf561/include/mach/defBF561.h @@ -884,11 +884,65 @@ /* System MMR Register Bits */ /******************************************************************************* */ +/* ********************* PLL AND RESET MASKS ************************ */ + +/* PLL_CTL Masks */ +#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ +#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ +#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ +#define STOPCK_OFF 0x00000008 /* Core clock off */ +#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ +#define BYPASS 0x00000100 /* Bypass the PLL */ + /* CHIPID Masks */ #define CHIPID_VERSION 0xF0000000 #define CHIPID_FAMILY 0x0FFFF000 #define CHIPID_MANUFACTURE 0x00000FFE +/* VR_CTL Masks */ +#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ +#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ +#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ +#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ +#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ + +#define GAIN 0x000C /* Voltage Level Gain */ +#define GAIN_5 0x0000 /* GAIN = 5*/ +#define GAIN_10 0x0004 /* GAIN = 1*/ +#define GAIN_20 0x0008 /* GAIN = 2*/ +#define GAIN_50 0x000C /* GAIN = 5*/ + +#define VLEV 0x00F0 /* Internal Voltage Level */ +#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ +#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */ +#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */ +#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */ +#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */ +#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */ +#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */ +#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */ +#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */ +#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ + +#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ +#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */ + +/* PLL_DIV Masks */ +#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ + +#define CSEL 0x30 /* Core Select */ +#define SSEL 0xf /* System Select */ +#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */ +#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ +#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ +#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ + +/* PLL_STAT Masks */ +#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ +#define FULL_ON 0x0002 /* Processor In Full On Mode */ +#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ +#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ + /* SICA_SYSCR Masks */ #define COREB_SRAM_INIT 0x0020 @@ -1096,6 +1150,53 @@ /* ********** DMA CONTROLLER MASKS *********************8 */ +/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */ +#define DMAEN 0x00000001 /* Channel Enable */ +#define WNR 0x00000002 /* Channel Direction (W/R*) */ +#define WDSIZE_8 0x00000000 /* Word Size 8 bits */ +#define WDSIZE_16 0x00000004 /* Word Size 16 bits */ +#define WDSIZE_32 0x00000008 /* Word Size 32 bits */ +#define DMA2D 0x00000010 /* 2D/1D* Mode */ +#define RESTART 0x00000020 /* Restart */ +#define DI_SEL 0x00000040 /* Data Interrupt Select */ +#define DI_EN 0x00000080 /* Data Interrupt Enable */ +#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */ +#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */ +#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */ +#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */ +#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */ +#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */ +#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */ +#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */ +#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */ +#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */ +#define NDSIZE 0x00000900 /* Next Descriptor Size */ +#define DMAFLOW 0x00007000 /* Flow Control */ +#define DMAFLOW_STOP 0x0000 /* Stop Mode */ +#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */ +#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */ +#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */ +#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */ + +#define DMAEN_P 0 /* Channel Enable */ +#define WNR_P 1 /* Channel Direction (W/R*) */ +#define DMA2D_P 4 /* 2D/1D* Mode */ +#define RESTART_P 5 /* Restart */ +#define DI_SEL_P 6 /* Data Interrupt Select */ +#define DI_EN_P 7 /* Data Interrupt Enable */ + +/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */ + +#define DMA_DONE 0x00000001 /* DMA Done Indicator */ +#define DMA_ERR 0x00000002 /* DMA Error Indicator */ +#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */ +#define DMA_RUN 0x00000008 /* DMA Running Indicator */ + +#define DMA_DONE_P 0 /* DMA Done Indicator */ +#define DMA_ERR_P 1 /* DMA Error Indicator */ +#define DFETCH_P 2 /* Descriptor Fetch Indicator */ +#define DMA_RUN_P 3 /* DMA Running Indicator */ + /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */ #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ diff --git a/trunk/arch/blackfin/mach-bf561/smp.c b/trunk/arch/blackfin/mach-bf561/smp.c index 0192532e96a2..510f57641495 100644 --- a/trunk/arch/blackfin/mach-bf561/smp.c +++ b/trunk/arch/blackfin/mach-bf561/smp.c @@ -52,6 +52,8 @@ int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ void __cpuinit platform_secondary_init(unsigned int cpu) { + local_irq_disable(); + /* Clone setup for peripheral interrupt sources from CoreA. */ bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0()); bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1()); @@ -68,6 +70,11 @@ void __cpuinit platform_secondary_init(unsigned int cpu) bfin_write_SICB_IAR7(bfin_read_SICA_IAR7()); SSYNC(); + local_irq_enable(); + + /* Calibrate loops per jiffy value. */ + calibrate_delay(); + /* Store CPU-private information to the cpu_data array. */ bfin_setup_cpudata(cpu); @@ -101,13 +108,9 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle barrier(); } - if (cpu_isset(cpu, cpu_callin_map)) { - cpu_set(cpu, cpu_online_map); - /* release the lock and let coreb run */ - spin_unlock(&boot_lock); - return 0; - } else - panic("CPU%u: processor failed to boot\n", cpu); + spin_unlock(&boot_lock); + + return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS; } void __init platform_request_ipi(irq_handler_t handler) diff --git a/trunk/arch/blackfin/mach-common/clocks-init.c b/trunk/arch/blackfin/mach-common/clocks-init.c index d5cfe611b778..ef6870e9eea6 100644 --- a/trunk/arch/blackfin/mach-common/clocks-init.c +++ b/trunk/arch/blackfin/mach-common/clocks-init.c @@ -13,7 +13,6 @@ #include #include #include -#include #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ #define PLL_CTL_VAL \ diff --git a/trunk/arch/blackfin/mach-common/cpufreq.c b/trunk/arch/blackfin/mach-common/cpufreq.c index 777582897253..01506504e6d0 100644 --- a/trunk/arch/blackfin/mach-common/cpufreq.c +++ b/trunk/arch/blackfin/mach-common/cpufreq.c @@ -13,7 +13,7 @@ #include #include #include -#include + /* this is the table of CCLK frequencies, in Hz */ /* .index is the entry in the auxillary dpm_state_table[] */ @@ -138,8 +138,7 @@ static int __init __bfin_cpu_init(struct cpufreq_policy *policy) dpm_state_table[index].tscale); } - policy->cpuinfo.transition_latency = 50000; /* 50us assumed */ - + policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000; /*Now ,only support one cpu */ policy->cur = cclk; cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu); diff --git a/trunk/arch/blackfin/mach-common/dpmc_modes.S b/trunk/arch/blackfin/mach-common/dpmc_modes.S index b03716896051..8009a512fb11 100644 --- a/trunk/arch/blackfin/mach-common/dpmc_modes.S +++ b/trunk/arch/blackfin/mach-common/dpmc_modes.S @@ -404,21 +404,6 @@ ENTRY(_do_hibernate) PM_SYS_PUSH(EBIU_FCTL) #endif -#ifdef PORTCIO_FER - PM_SYS_PUSH16(PORTCIO_DIR) - PM_SYS_PUSH16(PORTCIO_INEN) - PM_SYS_PUSH16(PORTCIO) - PM_SYS_PUSH16(PORTCIO_FER) - PM_SYS_PUSH16(PORTDIO_DIR) - PM_SYS_PUSH16(PORTDIO_INEN) - PM_SYS_PUSH16(PORTDIO) - PM_SYS_PUSH16(PORTDIO_FER) - PM_SYS_PUSH16(PORTEIO_DIR) - PM_SYS_PUSH16(PORTEIO_INEN) - PM_SYS_PUSH16(PORTEIO) - PM_SYS_PUSH16(PORTEIO_FER) -#endif - PM_SYS_PUSH16(SYSCR) /* Save Core MMRs */ @@ -731,21 +716,6 @@ ENTRY(_do_hibernate) P0.L = lo(PLL_CTL); PM_SYS_POP16(SYSCR) -#ifdef PORTCIO_FER - PM_SYS_POP16(PORTEIO_FER) - PM_SYS_POP16(PORTEIO) - PM_SYS_POP16(PORTEIO_INEN) - PM_SYS_POP16(PORTEIO_DIR) - PM_SYS_POP16(PORTDIO_FER) - PM_SYS_POP16(PORTDIO) - PM_SYS_POP16(PORTDIO_INEN) - PM_SYS_POP16(PORTDIO_DIR) - PM_SYS_POP16(PORTCIO_FER) - PM_SYS_POP16(PORTCIO) - PM_SYS_POP16(PORTCIO_INEN) - PM_SYS_POP16(PORTCIO_DIR) -#endif - #ifdef EBIU_FCTL PM_SYS_POP(EBIU_FCTL) PM_SYS_POP(EBIU_MODE) diff --git a/trunk/arch/blackfin/mach-common/entry.S b/trunk/arch/blackfin/mach-common/entry.S index b0ed0b487ff2..f3f8bb46b517 100644 --- a/trunk/arch/blackfin/mach-common/entry.S +++ b/trunk/arch/blackfin/mach-common/entry.S @@ -713,8 +713,6 @@ ENTRY(_system_call) cc = BITTST(r7, TIF_RESTORE_SIGMASK); if cc jump .Lsyscall_do_signals; cc = BITTST(r7, TIF_SIGPENDING); - if cc jump .Lsyscall_do_signals; - cc = BITTST(r7, TIF_NOTIFY_RESUME); if !cc jump .Lsyscall_really_exit; .Lsyscall_do_signals: /* Reenable interrupts. */ @@ -723,7 +721,7 @@ ENTRY(_system_call) r0 = sp; SP += -12; - call _do_notify_resume; + call _do_signal; SP += 12; .Lsyscall_really_exit: diff --git a/trunk/arch/blackfin/mach-common/ints-priority.c b/trunk/arch/blackfin/mach-common/ints-priority.c index 1873b2c1fede..660ea1bec54c 100644 --- a/trunk/arch/blackfin/mach-common/ints-priority.c +++ b/trunk/arch/blackfin/mach-common/ints-priority.c @@ -25,20 +25,11 @@ #include #include #include -#include -#include -#include #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) #ifdef BF537_FAMILY # define BF537_GENERIC_ERROR_INT_DEMUX -# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */ -# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */ -# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */ -# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */ -# define UART_ERR_MASK (0x6) /* UART_IIR */ -# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */ #else # undef BF537_GENERIC_ERROR_INT_DEMUX #endif @@ -333,9 +324,11 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, irq = IRQ_CAN_ERROR; else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) irq = IRQ_SPI_ERROR; - else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK) + else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) && + (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0)) irq = IRQ_UART0_ERROR; - else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK) + else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) && + (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0)) irq = IRQ_UART1_ERROR; if (irq) { diff --git a/trunk/arch/blackfin/mach-common/smp.c b/trunk/arch/blackfin/mach-common/smp.c index 369e687582b7..d92b168c8328 100644 --- a/trunk/arch/blackfin/mach-common/smp.c +++ b/trunk/arch/blackfin/mach-common/smp.c @@ -336,6 +336,13 @@ int __cpuinit __cpu_up(unsigned int cpu) ret = platform_boot_secondary(cpu, idle); + if (ret) { + cpu_clear(cpu, cpu_present_map); + printk(KERN_CRIT "CPU%u: processor failed to boot (%d)\n", cpu, ret); + free_task(idle); + } else + cpu_set(cpu, cpu_online_map); + secondary_stack = NULL; return ret; @@ -411,16 +418,9 @@ void __cpuinit secondary_start_kernel(void) setup_secondary(cpu); - platform_secondary_init(cpu); - local_irq_enable(); - /* - * Calibrate loops per jiffy value. - * IRQs need to be enabled here - D-cache can be invalidated - * in timer irq handler, so core B can read correct jiffies. - */ - calibrate_delay(); + platform_secondary_init(cpu); cpu_idle(); } diff --git a/trunk/arch/cris/include/asm/elf.h b/trunk/arch/cris/include/asm/elf.h index 8a3d8e2b33c1..0f51b10b9f4f 100644 --- a/trunk/arch/cris/include/asm/elf.h +++ b/trunk/arch/cris/include/asm/elf.h @@ -64,6 +64,8 @@ typedef unsigned long elf_fpregset_t; #define EF_CRIS_VARIANT_COMMON_V10_V32 0x00000004 /* End of excerpt from {binutils}/include/elf/cris.h. */ +#define USE_ELF_CORE_DUMP + #define ELF_EXEC_PAGESIZE 8192 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/frv/include/asm/elf.h b/trunk/arch/frv/include/asm/elf.h index c3819804a74b..7bbf6e47f8c8 100644 --- a/trunk/arch/frv/include/asm/elf.h +++ b/trunk/arch/frv/include/asm/elf.h @@ -115,6 +115,7 @@ do { \ __kernel_frame0_ptr->gr29 = 0; \ } while(0) +#define USE_ELF_CORE_DUMP #define CORE_DUMP_USE_REGSET #define ELF_FDPIC_CORE_EFLAGS EF_FRV_FDPIC #define ELF_EXEC_PAGESIZE 16384 diff --git a/trunk/arch/h8300/Kconfig b/trunk/arch/h8300/Kconfig index 53cc669e6d59..9420648352b8 100644 --- a/trunk/arch/h8300/Kconfig +++ b/trunk/arch/h8300/Kconfig @@ -10,10 +10,6 @@ config H8300 default y select HAVE_IDE -config SYMBOL_PREFIX - string - default "_" - config MMU bool default n diff --git a/trunk/arch/h8300/include/asm/elf.h b/trunk/arch/h8300/include/asm/elf.h index c24fa250d653..94e2284c8816 100644 --- a/trunk/arch/h8300/include/asm/elf.h +++ b/trunk/arch/h8300/include/asm/elf.h @@ -34,6 +34,7 @@ typedef unsigned long elf_fpregset_t; #define ELF_PLAT_INIT(_r) _r->er1 = 0 +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/h8300/include/asm/module.h b/trunk/arch/h8300/include/asm/module.h index 8e46724b7c09..de23231f3196 100644 --- a/trunk/arch/h8300/include/asm/module.h +++ b/trunk/arch/h8300/include/asm/module.h @@ -8,4 +8,6 @@ struct mod_arch_specific { }; #define Elf_Sym Elf32_Sym #define Elf_Ehdr Elf32_Ehdr +#define MODULE_SYMBOL_PREFIX "_" + #endif /* _ASM_H8/300_MODULE_H */ diff --git a/trunk/arch/h8300/kernel/vmlinux.lds.S b/trunk/arch/h8300/kernel/vmlinux.lds.S index 03d356d96e5d..b9e24907e6ea 100644 --- a/trunk/arch/h8300/kernel/vmlinux.lds.S +++ b/trunk/arch/h8300/kernel/vmlinux.lds.S @@ -1,3 +1,4 @@ +#define VMLINUX_SYMBOL(_sym_) _##_sym_ #include #include diff --git a/trunk/arch/ia64/hp/common/sba_iommu.c b/trunk/arch/ia64/hp/common/sba_iommu.c index e14c492a8a93..f332e3fe4237 100644 --- a/trunk/arch/ia64/hp/common/sba_iommu.c +++ b/trunk/arch/ia64/hp/common/sba_iommu.c @@ -677,19 +677,12 @@ sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size) spin_unlock_irqrestore(&ioc->saved_lock, flags); pide = sba_search_bitmap(ioc, dev, pages_needed, 0); - if (unlikely(pide >= (ioc->res_size << 3))) { - printk(KERN_WARNING "%s: I/O MMU @ %p is" - "out of mapping resources, %u %u %lx\n", - __func__, ioc->ioc_hpa, ioc->res_size, - pages_needed, dma_get_seg_boundary(dev)); - return -1; - } + if (unlikely(pide >= (ioc->res_size << 3))) + panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n", + ioc->ioc_hpa); #else - printk(KERN_WARNING "%s: I/O MMU @ %p is" - "out of mapping resources, %u %u %lx\n", - __func__, ioc->ioc_hpa, ioc->res_size, - pages_needed, dma_get_seg_boundary(dev)); - return -1; + panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n", + ioc->ioc_hpa); #endif } } @@ -972,8 +965,6 @@ static dma_addr_t sba_map_page(struct device *dev, struct page *page, #endif pide = sba_alloc_range(ioc, dev, size); - if (pide < 0) - return 0; iovp = (dma_addr_t) pide << iovp_shift; @@ -1329,7 +1320,6 @@ sba_coalesce_chunks(struct ioc *ioc, struct device *dev, unsigned long dma_offset, dma_len; /* start/len of DMA stream */ int n_mappings = 0; unsigned int max_seg_size = dma_get_max_seg_size(dev); - int idx; while (nents > 0) { unsigned long vaddr = (unsigned long) sba_sg_address(startsg); @@ -1428,22 +1418,16 @@ sba_coalesce_chunks(struct ioc *ioc, struct device *dev, vcontig_sg->dma_length = vcontig_len; dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask; ASSERT(dma_len <= DMA_CHUNK_SIZE); - idx = sba_alloc_range(ioc, dev, dma_len); - if (idx < 0) { - dma_sg->dma_length = 0; - return -1; - } - dma_sg->dma_address = (dma_addr_t)(PIDE_FLAG | (idx << iovp_shift) - | dma_offset); + dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG + | (sba_alloc_range(ioc, dev, dma_len) << iovp_shift) + | dma_offset); n_mappings++; } return n_mappings; } -static void sba_unmap_sg_attrs(struct device *dev, struct scatterlist *sglist, - int nents, enum dma_data_direction dir, - struct dma_attrs *attrs); + /** * sba_map_sg - map Scatter/Gather list * @dev: instance of PCI owned by the driver that's asking. @@ -1509,10 +1493,6 @@ static int sba_map_sg_attrs(struct device *dev, struct scatterlist *sglist, ** Access to the virtual address is what forces a two pass algorithm. */ coalesced = sba_coalesce_chunks(ioc, dev, sglist, nents); - if (coalesced < 0) { - sba_unmap_sg_attrs(dev, sglist, nents, dir, attrs); - return 0; - } /* ** Program the I/O Pdir diff --git a/trunk/arch/ia64/ia32/elfcore32.h b/trunk/arch/ia64/ia32/elfcore32.h index 657725742617..9a3abf58cea3 100644 --- a/trunk/arch/ia64/ia32/elfcore32.h +++ b/trunk/arch/ia64/ia32/elfcore32.h @@ -11,6 +11,8 @@ #include #include +#define USE_ELF_CORE_DUMP 1 + /* Override elfcore.h */ #define _LINUX_ELFCORE_H 1 typedef unsigned int elf_greg_t; diff --git a/trunk/arch/ia64/include/asm/dma-mapping.h b/trunk/arch/ia64/include/asm/dma-mapping.h index 7d09a09cdaad..8d3c79cd81e7 100644 --- a/trunk/arch/ia64/include/asm/dma-mapping.h +++ b/trunk/arch/ia64/include/asm/dma-mapping.h @@ -73,7 +73,7 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) if (!dev->dma_mask) return 0; - return addr + size - 1 <= *dev->dma_mask; + return addr + size <= *dev->dma_mask; } static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) diff --git a/trunk/arch/ia64/include/asm/elf.h b/trunk/arch/ia64/include/asm/elf.h index e14108b19c09..86eddee029cb 100644 --- a/trunk/arch/ia64/include/asm/elf.h +++ b/trunk/arch/ia64/include/asm/elf.h @@ -25,6 +25,7 @@ #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_IA_64 +#define USE_ELF_CORE_DUMP #define CORE_DUMP_USE_REGSET /* Least-significant four bits of ELF header's e_flags are OS-specific. The bits are diff --git a/trunk/arch/ia64/include/asm/hw_irq.h b/trunk/arch/ia64/include/asm/hw_irq.h index bf2e37493e04..91619b31dbf5 100644 --- a/trunk/arch/ia64/include/asm/hw_irq.h +++ b/trunk/arch/ia64/include/asm/hw_irq.h @@ -59,13 +59,7 @@ typedef u16 ia64_vector; extern int ia64_first_device_vector; extern int ia64_last_device_vector; -#if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined (CONFIG_IA64_DIG)) -/* Reserve the lower priority vector than device vectors for "move IRQ" IPI */ -#define IA64_IRQ_MOVE_VECTOR 0x30 /* "move IRQ" IPI */ -#define IA64_DEF_FIRST_DEVICE_VECTOR 0x31 -#else #define IA64_DEF_FIRST_DEVICE_VECTOR 0x30 -#endif #define IA64_DEF_LAST_DEVICE_VECTOR 0xe7 #define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector #define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector diff --git a/trunk/arch/ia64/include/asm/io.h b/trunk/arch/ia64/include/asm/io.h index cc8335eb3110..0d9d16e2d949 100644 --- a/trunk/arch/ia64/include/asm/io.h +++ b/trunk/arch/ia64/include/asm/io.h @@ -424,8 +424,6 @@ __writeq (unsigned long val, volatile void __iomem *addr) extern void __iomem * ioremap(unsigned long offset, unsigned long size); extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size); extern void iounmap (volatile void __iomem *addr); -extern void __iomem * early_ioremap (unsigned long phys_addr, unsigned long size); -extern void early_iounmap (volatile void __iomem *addr, unsigned long size); /* * String version of IO memory access ops: diff --git a/trunk/arch/ia64/include/asm/mca.h b/trunk/arch/ia64/include/asm/mca.h index 43f96ab18fa0..c171cdf0a789 100644 --- a/trunk/arch/ia64/include/asm/mca.h +++ b/trunk/arch/ia64/include/asm/mca.h @@ -106,11 +106,6 @@ struct ia64_sal_os_state { unsigned long os_status; /* OS status to SAL, enum below */ unsigned long context; /* 0 if return to same context 1 if return to new context */ - - /* I-resources */ - unsigned long iip; - unsigned long ipsr; - unsigned long ifs; }; enum { diff --git a/trunk/arch/ia64/include/asm/rwsem.h b/trunk/arch/ia64/include/asm/rwsem.h index e8762688e8e3..fbee74b15782 100644 --- a/trunk/arch/ia64/include/asm/rwsem.h +++ b/trunk/arch/ia64/include/asm/rwsem.h @@ -47,7 +47,7 @@ struct rw_semaphore { #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) #define __RWSEM_INITIALIZER(name) \ - { RWSEM_UNLOCKED_VALUE, __SPIN_LOCK_UNLOCKED((name).wait_lock), \ + { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ LIST_HEAD_INIT((name).wait_list) } #define DECLARE_RWSEM(name) \ diff --git a/trunk/arch/ia64/kernel/irq_ia64.c b/trunk/arch/ia64/kernel/irq_ia64.c index d4093a173a3e..70e4bad23432 100644 --- a/trunk/arch/ia64/kernel/irq_ia64.c +++ b/trunk/arch/ia64/kernel/irq_ia64.c @@ -260,6 +260,7 @@ void __setup_vector_irq(int cpu) } #if defined(CONFIG_SMP) && (defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG)) +#define IA64_IRQ_MOVE_VECTOR IA64_DEF_FIRST_DEVICE_VECTOR static enum vector_domain_type { VECTOR_DOMAIN_NONE, @@ -658,8 +659,11 @@ init_IRQ (void) register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL); #ifdef CONFIG_SMP #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_DIG) - if (vector_domain_type != VECTOR_DOMAIN_NONE) + if (vector_domain_type != VECTOR_DOMAIN_NONE) { + BUG_ON(IA64_FIRST_DEVICE_VECTOR != IA64_IRQ_MOVE_VECTOR); + IA64_FIRST_DEVICE_VECTOR++; register_percpu_irq(IA64_IRQ_MOVE_VECTOR, &irq_move_irqaction); + } #endif #endif #ifdef CONFIG_PERFMON diff --git a/trunk/arch/ia64/kernel/mca.c b/trunk/arch/ia64/kernel/mca.c index 32f2639e9b0a..496ac7a99488 100644 --- a/trunk/arch/ia64/kernel/mca.c +++ b/trunk/arch/ia64/kernel/mca.c @@ -888,10 +888,9 @@ ia64_mca_modify_comm(const struct task_struct *previous_current) } static void -finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos, +finish_pt_regs(struct pt_regs *regs, const pal_min_state_area_t *ms, unsigned long *nat) { - const pal_min_state_area_t *ms = sos->pal_min_state; const u64 *bank; /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use @@ -905,10 +904,6 @@ finish_pt_regs(struct pt_regs *regs, struct ia64_sal_os_state *sos, regs->cr_iip = ms->pmsa_xip; regs->cr_ipsr = ms->pmsa_xpsr; regs->cr_ifs = ms->pmsa_xfs; - - sos->iip = ms->pmsa_iip; - sos->ipsr = ms->pmsa_ipsr; - sos->ifs = ms->pmsa_ifs; } regs->pr = ms->pmsa_pr; regs->b0 = ms->pmsa_br0; @@ -1084,7 +1079,7 @@ ia64_mca_modify_original_stack(struct pt_regs *regs, memcpy(old_regs, regs, sizeof(*regs)); old_regs->loadrs = loadrs; old_unat = old_regs->ar_unat; - finish_pt_regs(old_regs, sos, &old_unat); + finish_pt_regs(old_regs, ms, &old_unat); /* Next stack a struct switch_stack. mca_asm.S built a partial * switch_stack, copy it and fill in the blanks using pt_regs and @@ -1155,7 +1150,7 @@ ia64_mca_modify_original_stack(struct pt_regs *regs, mprintk(KERN_INFO "cpu %d, %s %s, original stack not modified\n", smp_processor_id(), type, msg); old_unat = regs->ar_unat; - finish_pt_regs(regs, sos, &old_unat); + finish_pt_regs(regs, ms, &old_unat); return previous_current; } diff --git a/trunk/arch/ia64/mm/ioremap.c b/trunk/arch/ia64/mm/ioremap.c index 3dccdd8eb275..2a140627dfd6 100644 --- a/trunk/arch/ia64/mm/ioremap.c +++ b/trunk/arch/ia64/mm/ioremap.c @@ -21,12 +21,6 @@ __ioremap (unsigned long phys_addr) return (void __iomem *) (__IA64_UNCACHED_OFFSET | phys_addr); } -void __iomem * -early_ioremap (unsigned long phys_addr, unsigned long size) -{ - return __ioremap(phys_addr); -} - void __iomem * ioremap (unsigned long phys_addr, unsigned long size) { @@ -107,11 +101,6 @@ ioremap_nocache (unsigned long phys_addr, unsigned long size) } EXPORT_SYMBOL(ioremap_nocache); -void -early_iounmap (volatile void __iomem *addr, unsigned long size) -{ -} - void iounmap (volatile void __iomem *addr) { diff --git a/trunk/arch/ia64/sn/pci/tioca_provider.c b/trunk/arch/ia64/sn/pci/tioca_provider.c index efb454534e52..35b2a27d2e77 100644 --- a/trunk/arch/ia64/sn/pci/tioca_provider.c +++ b/trunk/arch/ia64/sn/pci/tioca_provider.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -370,7 +369,7 @@ tioca_dma_d48(struct pci_dev *pdev, u64 paddr) static dma_addr_t tioca_dma_mapped(struct pci_dev *pdev, unsigned long paddr, size_t req_size) { - int ps, ps_shift, entry, entries, mapsize; + int i, ps, ps_shift, entry, entries, mapsize, last_entry; u64 xio_addr, end_xio_addr; struct tioca_common *tioca_common; struct tioca_kernel *tioca_kern; @@ -411,13 +410,23 @@ tioca_dma_mapped(struct pci_dev *pdev, unsigned long paddr, size_t req_size) map = tioca_kern->ca_pcigart_pagemap; mapsize = tioca_kern->ca_pcigart_entries; - entry = bitmap_find_next_zero_area(map, mapsize, 0, entries, 0); - if (entry >= mapsize) { + entry = find_first_zero_bit(map, mapsize); + while (entry < mapsize) { + last_entry = find_next_bit(map, mapsize, entry); + + if (last_entry - entry >= entries) + break; + + entry = find_next_zero_bit(map, mapsize, last_entry); + } + + if (entry > mapsize) { kfree(ca_dmamap); goto map_return; } - bitmap_set(map, entry, entries); + for (i = 0; i < entries; i++) + set_bit(entry + i, map); bus_addr = tioca_kern->ca_pciap_base + (entry * ps); diff --git a/trunk/arch/m32r/include/asm/elf.h b/trunk/arch/m32r/include/asm/elf.h index 2f85412ef730..0cc34c94bf2b 100644 --- a/trunk/arch/m32r/include/asm/elf.h +++ b/trunk/arch/m32r/include/asm/elf.h @@ -102,6 +102,7 @@ typedef elf_fpreg_t elf_fpregset_t; */ #define ELF_PLAT_INIT(_r, load_addr) (_r)->r0 = 0 +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE /* diff --git a/trunk/arch/m68k/include/asm/elf.h b/trunk/arch/m68k/include/asm/elf.h index 01c193d91412..0b0f49eb876b 100644 --- a/trunk/arch/m68k/include/asm/elf.h +++ b/trunk/arch/m68k/include/asm/elf.h @@ -59,6 +59,7 @@ typedef struct user_m68kfp_struct elf_fpregset_t; is actually used on ASV. */ #define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 +#define USE_ELF_CORE_DUMP #ifndef CONFIG_SUN3 #define ELF_EXEC_PAGESIZE 4096 #else diff --git a/trunk/arch/microblaze/include/asm/elf.h b/trunk/arch/microblaze/include/asm/elf.h index 7d4acf2b278e..f92fc0dda006 100644 --- a/trunk/arch/microblaze/include/asm/elf.h +++ b/trunk/arch/microblaze/include/asm/elf.h @@ -77,6 +77,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #define ELF_DATA ELFDATA2MSB #endif +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 diff --git a/trunk/arch/mips/include/asm/elf.h b/trunk/arch/mips/include/asm/elf.h index 7a6a35dbe529..7990694cda22 100644 --- a/trunk/arch/mips/include/asm/elf.h +++ b/trunk/arch/mips/include/asm/elf.h @@ -326,6 +326,7 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ dump_task_fpu(tsk, elf_fpregs) +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This yields a mask that user programs can use to figure out what diff --git a/trunk/arch/mn10300/include/asm/elf.h b/trunk/arch/mn10300/include/asm/elf.h index e5fa97cd9a14..75a70aa9fd6f 100644 --- a/trunk/arch/mn10300/include/asm/elf.h +++ b/trunk/arch/mn10300/include/asm/elf.h @@ -77,6 +77,7 @@ do { \ _ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \ } while (0) +#define USE_ELF_CORE_DUMP #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE 4096 diff --git a/trunk/arch/parisc/hpux/sys_hpux.c b/trunk/arch/parisc/hpux/sys_hpux.c index 18072e03a019..92343bd35fa3 100644 --- a/trunk/arch/parisc/hpux/sys_hpux.c +++ b/trunk/arch/parisc/hpux/sys_hpux.c @@ -445,12 +445,7 @@ int hpux_getdomainname(char __user *name, int len) int hpux_pipe(int *kstack_fildes) { - int error; - - lock_kernel(); - error = do_pipe_flags(kstack_fildes, 0); - unlock_kernel(); - return error; + return do_pipe_flags(kstack_fildes, 0); } /* lies - says it works, but it really didn't lock anything */ diff --git a/trunk/arch/parisc/include/asm/bug.h b/trunk/arch/parisc/include/asm/bug.h index 75e46c557a16..8cfc553fc837 100644 --- a/trunk/arch/parisc/include/asm/bug.h +++ b/trunk/arch/parisc/include/asm/bug.h @@ -32,14 +32,14 @@ "\t.popsection" \ : : "i" (__FILE__), "i" (__LINE__), \ "i" (0), "i" (sizeof(struct bug_entry)) ); \ - unreachable(); \ + for(;;) ; \ } while(0) #else #define BUG() \ do { \ asm volatile(PARISC_BUG_BREAK_ASM : : ); \ - unreachable(); \ + for(;;) ; \ } while(0) #endif diff --git a/trunk/arch/parisc/include/asm/elf.h b/trunk/arch/parisc/include/asm/elf.h index 19f6cb1a4a1c..9c802eb4be84 100644 --- a/trunk/arch/parisc/include/asm/elf.h +++ b/trunk/arch/parisc/include/asm/elf.h @@ -328,6 +328,7 @@ struct pt_regs; /* forward declaration... */ such function. */ #define ELF_PLAT_INIT(_r, load_addr) _r->gr[23] = 0 +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/parisc/include/asm/ftrace.h b/trunk/arch/parisc/include/asm/ftrace.h index 72c0fafaa039..2fa05dd6aeee 100644 --- a/trunk/arch/parisc/include/asm/ftrace.h +++ b/trunk/arch/parisc/include/asm/ftrace.h @@ -20,20 +20,6 @@ struct ftrace_ret_stack { * Defined in entry.S */ extern void return_to_handler(void); - - -extern unsigned long return_address(unsigned int); - -#define HAVE_ARCH_CALLER_ADDR - -#define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0)) -#define CALLER_ADDR1 return_address(1) -#define CALLER_ADDR2 return_address(2) -#define CALLER_ADDR3 return_address(3) -#define CALLER_ADDR4 return_address(4) -#define CALLER_ADDR5 return_address(5) -#define CALLER_ADDR6 return_address(6) - #endif /* __ASSEMBLY__ */ #endif /* _ASM_PARISC_FTRACE_H */ diff --git a/trunk/arch/parisc/kernel/asm-offsets.c b/trunk/arch/parisc/kernel/asm-offsets.c index ec787b411e9a..fcd3c707bf12 100644 --- a/trunk/arch/parisc/kernel/asm-offsets.c +++ b/trunk/arch/parisc/kernel/asm-offsets.c @@ -244,6 +244,9 @@ int main(void) DEFINE(THREAD_SZ, sizeof(struct thread_info)); DEFINE(THREAD_SZ_ALGN, align(sizeof(struct thread_info), 64)); BLANK(); + DEFINE(IRQSTAT_SIRQ_PEND, offsetof(irq_cpustat_t, __softirq_pending)); + DEFINE(IRQSTAT_SZ, sizeof(irq_cpustat_t)); + BLANK(); DEFINE(ICACHE_BASE, offsetof(struct pdc_cache_info, ic_base)); DEFINE(ICACHE_STRIDE, offsetof(struct pdc_cache_info, ic_stride)); DEFINE(ICACHE_COUNT, offsetof(struct pdc_cache_info, ic_count)); diff --git a/trunk/arch/parisc/kernel/irq.c b/trunk/arch/parisc/kernel/irq.c index efbcee5d2220..f47465e8d040 100644 --- a/trunk/arch/parisc/kernel/irq.c +++ b/trunk/arch/parisc/kernel/irq.c @@ -145,7 +145,7 @@ static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) #endif static struct irq_chip cpu_interrupt_type = { - .name = "CPU", + .typename = "CPU", .startup = cpu_startup_irq, .shutdown = cpu_disable_irq, .enable = cpu_enable_irq, @@ -192,7 +192,7 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, "%10u ", kstat_irqs(i)); #endif - seq_printf(p, " %14s", irq_desc[i].chip->name); + seq_printf(p, " %14s", irq_desc[i].chip->typename); #ifndef PARISC_IRQ_CR16_COUNTS seq_printf(p, " %s", action->name); diff --git a/trunk/arch/parisc/kernel/signal.c b/trunk/arch/parisc/kernel/signal.c index fb37ac52e46c..e8467e4aa8d1 100644 --- a/trunk/arch/parisc/kernel/signal.c +++ b/trunk/arch/parisc/kernel/signal.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include diff --git a/trunk/arch/parisc/kernel/smp.c b/trunk/arch/parisc/kernel/smp.c index 3f2fce8ce6b6..1fd0f0cec037 100644 --- a/trunk/arch/parisc/kernel/smp.c +++ b/trunk/arch/parisc/kernel/smp.c @@ -60,6 +60,8 @@ static int smp_debug_lvl = 0; #define smp_debug(lvl, ...) do { } while(0) #endif /* DEBUG_SMP */ +DEFINE_SPINLOCK(smp_lock); + volatile struct task_struct *smp_init_current_idle_task; /* track which CPU is booting */ @@ -67,7 +69,7 @@ static volatile int cpu_now_booting __cpuinitdata; static int parisc_max_cpus __cpuinitdata = 1; -static DEFINE_PER_CPU(spinlock_t, ipi_lock); +DEFINE_PER_CPU(spinlock_t, ipi_lock) = SPIN_LOCK_UNLOCKED; enum ipi_message_type { IPI_NOP=0, @@ -436,11 +438,6 @@ void __init smp_prepare_boot_cpu(void) */ void __init smp_prepare_cpus(unsigned int max_cpus) { - int cpu; - - for_each_possible_cpu(cpu) - spin_lock_init(&per_cpu(ipi_lock, cpu)); - init_cpu_present(cpumask_of(0)); parisc_max_cpus = max_cpus; diff --git a/trunk/arch/parisc/kernel/sys_parisc32.c b/trunk/arch/parisc/kernel/sys_parisc32.c index 9779ece2b070..76d23ec8dfaa 100644 --- a/trunk/arch/parisc/kernel/sys_parisc32.c +++ b/trunk/arch/parisc/kernel/sys_parisc32.c @@ -26,7 +26,13 @@ #include #include #include +#include #include +#include +#include +#include +#include +#include #include #include #include diff --git a/trunk/arch/parisc/kernel/unwind.c b/trunk/arch/parisc/kernel/unwind.c index d58eac1a8288..a36799e85693 100644 --- a/trunk/arch/parisc/kernel/unwind.c +++ b/trunk/arch/parisc/kernel/unwind.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include @@ -116,18 +115,24 @@ unwind_table_init(struct unwind_table *table, const char *name, } } -static int cmp_unwind_table_entry(const void *a, const void *b) -{ - return ((const struct unwind_table_entry *)a)->region_start - - ((const struct unwind_table_entry *)b)->region_start; -} - static void unwind_table_sort(struct unwind_table_entry *start, struct unwind_table_entry *finish) { - sort(start, finish - start, sizeof(struct unwind_table_entry), - cmp_unwind_table_entry, NULL); + struct unwind_table_entry el, *p, *q; + + for (p = start + 1; p < finish; ++p) { + if (p[0].region_start < p[-1].region_start) { + el = *p; + q = p; + do { + q[0] = q[-1]; + --q; + } while (q > start && + el.region_start < q[-1].region_start); + *q = el; + } + } } struct unwind_table * @@ -412,30 +417,3 @@ int unwind_to_user(struct unwind_frame_info *info) return ret; } - -unsigned long return_address(unsigned int level) -{ - struct unwind_frame_info info; - struct pt_regs r; - unsigned long sp; - - /* initialize unwind info */ - asm volatile ("copy %%r30, %0" : "=r"(sp)); - memset(&r, 0, sizeof(struct pt_regs)); - r.iaoq[0] = (unsigned long) current_text_addr(); - r.gr[2] = (unsigned long) __builtin_return_address(0); - r.gr[30] = sp; - unwind_frame_init(&info, current, &r); - - /* unwind stack */ - ++level; - do { - if (unwind_once(&info) < 0 || info.ip == 0) - return 0; - if (!__kernel_text_address(info.ip)) { - return 0; - } - } while (info.ip && level--); - - return info.ip; -} diff --git a/trunk/arch/powerpc/include/asm/async_tx.h b/trunk/arch/powerpc/include/asm/async_tx.h deleted file mode 100644 index 8b2dc55d01ab..000000000000 --- a/trunk/arch/powerpc/include/asm/async_tx.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2008-2009 DENX Software Engineering. - * - * Author: Yuri Tikhonov - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., 59 - * Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * The full GNU General Public License is included in this distribution in the - * file called COPYING. - */ -#ifndef _ASM_POWERPC_ASYNC_TX_H_ -#define _ASM_POWERPC_ASYNC_TX_H_ - -#if defined(CONFIG_440SPe) || defined(CONFIG_440SP) -extern struct dma_chan * -ppc440spe_async_tx_find_best_channel(enum dma_transaction_type cap, - struct page **dst_lst, int dst_cnt, struct page **src_lst, - int src_cnt, size_t src_sz); - -#define async_tx_find_channel(dep, cap, dst_lst, dst_cnt, src_lst, \ - src_cnt, src_sz) \ - ppc440spe_async_tx_find_best_channel(cap, dst_lst, dst_cnt, src_lst, \ - src_cnt, src_sz) -#else - -#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \ - __async_tx_find_channel(dep, type) - -struct dma_chan * -__async_tx_find_channel(struct async_submit_ctl *submit, - enum dma_transaction_type tx_type); - -#endif - -#endif diff --git a/trunk/arch/powerpc/include/asm/dcr-regs.h b/trunk/arch/powerpc/include/asm/dcr-regs.h index 380274de429f..828e3aa1f2fc 100644 --- a/trunk/arch/powerpc/include/asm/dcr-regs.h +++ b/trunk/arch/powerpc/include/asm/dcr-regs.h @@ -157,27 +157,4 @@ #define L2C_SNP_SSR_32G 0x0000f000 #define L2C_SNP_ESR 0x00000800 -/* - * DCR register offsets for 440SP/440SPe I2O/DMA controller. - * The base address is configured in the device tree. - */ -#define DCRN_I2O0_IBAL 0x006 -#define DCRN_I2O0_IBAH 0x007 -#define I2O_REG_ENABLE 0x00000001 /* Enable I2O/DMA access */ - -/* 440SP/440SPe Software Reset DCR */ -#define DCRN_SDR0_SRST 0x0200 -#define DCRN_SDR0_SRST_I2ODMA (0x80000000 >> 15) /* Reset I2O/DMA */ - -/* 440SP/440SPe Memory Queue DCR offsets */ -#define DCRN_MQ0_XORBA 0x04 -#define DCRN_MQ0_CF2H 0x06 -#define DCRN_MQ0_CFBHL 0x0f -#define DCRN_MQ0_BAUH 0x10 - -/* HB/LL Paths Configuration Register */ -#define MQ0_CFBHL_TPLM 28 -#define MQ0_CFBHL_HBCL 23 -#define MQ0_CFBHL_POLY 15 - #endif /* __DCR_REGS_H__ */ diff --git a/trunk/arch/powerpc/include/asm/dma-mapping.h b/trunk/arch/powerpc/include/asm/dma-mapping.h index 80a973bb9e71..e281daebddca 100644 --- a/trunk/arch/powerpc/include/asm/dma-mapping.h +++ b/trunk/arch/powerpc/include/asm/dma-mapping.h @@ -197,7 +197,7 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) if (!dev->dma_mask) return 0; - return addr + size - 1 <= *dev->dma_mask; + return addr + size <= *dev->dma_mask; } static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) diff --git a/trunk/arch/powerpc/include/asm/elf.h b/trunk/arch/powerpc/include/asm/elf.h index 17828ad411eb..014a624f4c8e 100644 --- a/trunk/arch/powerpc/include/asm/elf.h +++ b/trunk/arch/powerpc/include/asm/elf.h @@ -170,6 +170,7 @@ typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG]; #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) #define compat_elf_check_arch(x) ((x)->e_machine == EM_PPC) +#define USE_ELF_CORE_DUMP #define CORE_DUMP_USE_REGSET #define ELF_EXEC_PAGESIZE PAGE_SIZE diff --git a/trunk/arch/powerpc/include/asm/module.h b/trunk/arch/powerpc/include/asm/module.h index 0192a4ee2bc2..08454880a2c0 100644 --- a/trunk/arch/powerpc/include/asm/module.h +++ b/trunk/arch/powerpc/include/asm/module.h @@ -87,10 +87,5 @@ struct exception_table_entry; void sort_ex_table(struct exception_table_entry *start, struct exception_table_entry *finish); -#ifdef CONFIG_MODVERSIONS -#define ARCH_RELOCATES_KCRCTAB - -extern const unsigned long reloc_start[]; -#endif #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_MODULE_H */ diff --git a/trunk/arch/powerpc/include/asm/ptrace.h b/trunk/arch/powerpc/include/asm/ptrace.h index cbd759e3cd78..8c341490cfc5 100644 --- a/trunk/arch/powerpc/include/asm/ptrace.h +++ b/trunk/arch/powerpc/include/asm/ptrace.h @@ -140,8 +140,6 @@ extern void user_enable_single_step(struct task_struct *); extern void user_enable_block_step(struct task_struct *); extern void user_disable_single_step(struct task_struct *); -#define ARCH_HAS_USER_SINGLE_STEP_INFO - #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ diff --git a/trunk/arch/powerpc/kernel/iommu.c b/trunk/arch/powerpc/kernel/iommu.c index 5547ae6e6b0b..fd51578e29dd 100644 --- a/trunk/arch/powerpc/kernel/iommu.c +++ b/trunk/arch/powerpc/kernel/iommu.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include @@ -251,7 +251,7 @@ static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, } ppc_md.tce_free(tbl, entry, npages); - bitmap_clear(tbl->it_map, free_entry, npages); + iommu_area_free(tbl->it_map, free_entry, npages); } static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, diff --git a/trunk/arch/powerpc/kernel/traps.c b/trunk/arch/powerpc/kernel/traps.c index d069ff8a7e03..804f0f30f227 100644 --- a/trunk/arch/powerpc/kernel/traps.c +++ b/trunk/arch/powerpc/kernel/traps.c @@ -174,15 +174,6 @@ int die(const char *str, struct pt_regs *regs, long err) return 0; } -void user_single_step_siginfo(struct task_struct *tsk, - struct pt_regs *regs, siginfo_t *info) -{ - memset(info, 0, sizeof(*info)); - info->si_signo = SIGTRAP; - info->si_code = TRAP_TRACE; - info->si_addr = (void __user *)regs->nip; -} - void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) { siginfo_t info; diff --git a/trunk/arch/powerpc/kernel/vmlinux.lds.S b/trunk/arch/powerpc/kernel/vmlinux.lds.S index dcd01c82e701..27735a7ac12b 100644 --- a/trunk/arch/powerpc/kernel/vmlinux.lds.S +++ b/trunk/arch/powerpc/kernel/vmlinux.lds.S @@ -38,9 +38,6 @@ jiffies = jiffies_64 + 4; #endif SECTIONS { - . = 0; - reloc_start = .; - . = KERNELBASE; /* diff --git a/trunk/arch/s390/include/asm/elf.h b/trunk/arch/s390/include/asm/elf.h index 354d42616c7e..e885442c1dfe 100644 --- a/trunk/arch/s390/include/asm/elf.h +++ b/trunk/arch/s390/include/asm/elf.h @@ -155,6 +155,7 @@ extern unsigned int vdso_enabled; } while (0) #define CORE_DUMP_USE_REGSET +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 /* This is the location that an ET_DYN program is loaded if exec'ed. Typical diff --git a/trunk/arch/score/include/asm/elf.h b/trunk/arch/score/include/asm/elf.h index f478ce94181f..43526d9fda93 100644 --- a/trunk/arch/score/include/asm/elf.h +++ b/trunk/arch/score/include/asm/elf.h @@ -61,6 +61,7 @@ struct task_struct; struct pt_regs; #define CORE_DUMP_USE_REGSET +#define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE PAGE_SIZE /* This yields a mask that user programs can use to figure out what diff --git a/trunk/arch/sh/Kconfig.debug b/trunk/arch/sh/Kconfig.debug index 12fec72fec5f..55907af1dc25 100644 --- a/trunk/arch/sh/Kconfig.debug +++ b/trunk/arch/sh/Kconfig.debug @@ -19,6 +19,50 @@ config SH_STANDARD_BIOS mask ROM and no flash (WindowsCE machines fall in this category). If unsure, say N. +config EARLY_SCIF_CONSOLE + bool "Use early SCIF console" + help + This enables an early console using a fixed SCIF port. This can + be used by platforms that are either not running the SH + standard BIOS, or do not wish to use the BIOS callbacks for the + serial I/O. + +config EARLY_SCIF_CONSOLE_PORT + hex + depends on EARLY_SCIF_CONSOLE + default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705 + default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721 + default "0xf8420000" if CPU_SUBTYPE_SH7619 + default "0xff804000" if CPU_SUBTYPE_MXG + default "0xffc30000" if CPU_SUBTYPE_SHX3 + default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \ + CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \ + CPU_SUBTYPE_SH7343 + default "0xfe4c0000" if CPU_SUBTYPE_SH7757 + default "0xffeb0000" if CPU_SUBTYPE_SH7785 + default "0xffeb0000" if CPU_SUBTYPE_SH7786 + default "0xfffe8000" if CPU_SUBTYPE_SH7203 + default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 + default "0xffe80000" if CPU_SH4 + default "0xa4000150" if CPU_SH3 + default "0x00000000" + +config EARLY_PRINTK + bool "Early printk support" + depends on SH_STANDARD_BIOS || EARLY_SCIF_CONSOLE + help + Say Y here to redirect kernel printk messages to the serial port + used by the SH-IPL bootloader, starting very early in the boot + process and ending when the kernel's serial console is initialised. + This option is only useful porting the kernel to a new machine, + when the kernel may crash or hang before the serial console is + initialised. If unsure, say N. + + On devices that are running SH-IPL and want to keep the port + initialization consistent while not using the BIOS callbacks, + select both the EARLY_SCIF_CONSOLE and SH_STANDARD_BIOS, using + the kernel command line option to toggle back and forth. + config STACK_DEBUG bool "Check for stack overflows" depends on DEBUG_KERNEL && SUPERH32 diff --git a/trunk/arch/sh/boards/mach-ap325rxa/setup.c b/trunk/arch/sh/boards/mach-ap325rxa/setup.c index 1f5fa5c44f6d..cf9dc12dfeb1 100644 --- a/trunk/arch/sh/boards/mach-ap325rxa/setup.c +++ b/trunk/arch/sh/boards/mach-ap325rxa/setup.c @@ -316,24 +316,20 @@ static struct soc_camera_platform_info camera_info = { .format_name = "UYVY", .format_depth = 16, .format = { - .code = V4L2_MBUS_FMT_YUYV8_2X8_BE, + .pixelformat = V4L2_PIX_FMT_UYVY, .colorspace = V4L2_COLORSPACE_SMPTE170M, - .field = V4L2_FIELD_NONE, .width = 640, .height = 480, }, .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | - SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8 | - SOCAM_DATA_ACTIVE_HIGH, + SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, .set_capture = camera_set_capture, -}; - -struct soc_camera_link camera_link = { - .bus_id = 0, - .add_device = ap325rxa_camera_add, - .del_device = ap325rxa_camera_del, - .module_name = "soc_camera_platform", - .priv = &camera_info, + .link = { + .bus_id = 0, + .add_device = ap325rxa_camera_add, + .del_device = ap325rxa_camera_del, + .module_name = "soc_camera_platform", + }, }; static void dummy_release(struct device *dev) @@ -351,7 +347,7 @@ static struct platform_device camera_device = { static int ap325rxa_camera_add(struct soc_camera_link *icl, struct device *dev) { - if (icl != &camera_link || camera_probe() <= 0) + if (icl != &camera_info.link || camera_probe() <= 0) return -ENODEV; camera_info.dev = dev; @@ -361,7 +357,7 @@ static int ap325rxa_camera_add(struct soc_camera_link *icl, static void ap325rxa_camera_del(struct soc_camera_link *icl) { - if (icl != &camera_link) + if (icl != &camera_info.link) return; platform_device_unregister(&camera_device); @@ -474,15 +470,13 @@ static struct ov772x_camera_info ov7725_info = { .buswidth = SOCAM_DATAWIDTH_8, .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP, .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0), -}; - -static struct soc_camera_link ov7725_link = { - .bus_id = 0, - .power = ov7725_power, - .board_info = &ap325rxa_i2c_camera[0], - .i2c_adapter_id = 0, - .module_name = "ov772x", - .priv = &ov7725_info, + .link = { + .bus_id = 0, + .power = ov7725_power, + .board_info = &ap325rxa_i2c_camera[0], + .i2c_adapter_id = 0, + .module_name = "ov772x", + }, }; static struct platform_device ap325rxa_camera[] = { @@ -490,13 +484,13 @@ static struct platform_device ap325rxa_camera[] = { .name = "soc-camera-pdrv", .id = 0, .dev = { - .platform_data = &ov7725_link, + .platform_data = &ov7725_info.link, }, }, { .name = "soc-camera-pdrv", .id = 1, .dev = { - .platform_data = &camera_link, + .platform_data = &camera_info.link, }, }, }; diff --git a/trunk/arch/sh/boards/mach-ecovec24/setup.c b/trunk/arch/sh/boards/mach-ecovec24/setup.c index 194aaca22d47..826e62326d51 100644 --- a/trunk/arch/sh/boards/mach-ecovec24/setup.c +++ b/trunk/arch/sh/boards/mach-ecovec24/setup.c @@ -19,18 +19,11 @@ #include #include #include -#include -#include -#include -#include #include #include #include #include