From c7ae96991683b0786e02bfc32119663338bf3863 Mon Sep 17 00:00:00 2001
From: Will Deacon <will.deacon@arm.com>
Date: Thu, 5 Aug 2010 11:20:51 +0100
Subject: [PATCH] --- yaml --- r: 208575 b: refs/heads/master c:
 cdf357f1e13a08a11261edacb3083746f65c1ed9 h: refs/heads/master i:   208573:
 8ec9b8828c80da190614b6962d20f8d0e92efd97   208571:
 447431cdd0f53050c0368acb3c5e415769c4e32c   208567:
 f66cff4f347fe66daa94685ebcde1df11c90714f   208559:
 2bc7c68b246ce8f7374c1ff97e670ff9de41127f   208543:
 7e0da1c3d4a80dc0881e889be08952e9c52990a9   208511:
 ddb7fb554d7d59bfbe6bf76e258f417dbbb79a2a v: v3

---
 [refs]                                |  2 +-
 trunk/arch/arm/Kconfig                | 12 ++++++++++++
 trunk/arch/arm/include/asm/tlbflush.h |  8 ++++++++
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 3d01a676984f..3beae1195d7e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 988257cfcbc468cb26b3addfcab1d0187c4e2399
+refs/heads/master: cdf357f1e13a08a11261edacb3083746f65c1ed9
diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig
index 232f0c758252..e3956042892c 100644
--- a/trunk/arch/arm/Kconfig
+++ b/trunk/arch/arm/Kconfig
@@ -1040,6 +1040,18 @@ config PL310_ERRATA_588369
 	   is not correctly implemented in PL310 as clean lines are not
 	   invalidated as a result of these operations. Note that this errata
 	   uses Texas Instrument's secure monitor api.
+
+config ARM_ERRATA_720789
+	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
+	depends on CPU_V7 && SMP
+	help
+	  This option enables the workaround for the 720789 Cortex-A9 (prior to
+	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
+	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
+	  As a consequence of this erratum, some TLB entries which should be
+	  invalidated are not, resulting in an incoherency in the system page
+	  tables. The workaround changes the TLB flushing routines to invalidate
+	  entries regardless of the ASID.
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/trunk/arch/arm/include/asm/tlbflush.h b/trunk/arch/arm/include/asm/tlbflush.h
index bd863d8608cd..33b546ae72d4 100644
--- a/trunk/arch/arm/include/asm/tlbflush.h
+++ b/trunk/arch/arm/include/asm/tlbflush.h
@@ -378,7 +378,11 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
 	if (tlb_flag(TLB_V6_I_ASID))
 		asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
 	if (tlb_flag(TLB_V7_UIS_ASID))
+#ifdef CONFIG_ARM_ERRATA_720789
+		asm("mcr p15, 0, %0, c8, c3, 0" : : "r" (zero) : "cc");
+#else
 		asm("mcr p15, 0, %0, c8, c3, 2" : : "r" (asid) : "cc");
+#endif
 
 	if (tlb_flag(TLB_BTB)) {
 		/* flush the branch target cache */
@@ -424,7 +428,11 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 	if (tlb_flag(TLB_V6_I_PAGE))
 		asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
 	if (tlb_flag(TLB_V7_UIS_PAGE))
+#ifdef CONFIG_ARM_ERRATA_720789
+		asm("mcr p15, 0, %0, c8, c3, 3" : : "r" (uaddr & PAGE_MASK) : "cc");
+#else
 		asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (uaddr) : "cc");
+#endif
 
 	if (tlb_flag(TLB_BTB)) {
 		/* flush the branch target cache */