From c7f8e630ec65084e552a89911601b1ccb1e7fc25 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Thu, 6 Sep 2012 15:45:40 +0300 Subject: [PATCH] --- yaml --- r: 325741 b: refs/heads/master c: 6721ab7f77f2614ab43e3de2f908b1d7436331df h: refs/heads/master i: 325739: c3768b9e894dcd81894f917fbcf3476ced183a4d v: v3 --- [refs] | 2 +- trunk/drivers/tty/serial/omap-serial.c | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 38c89e95d262..8bbb7c523e72 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d37c6cebcb0c7ab4fc9e000061c93cca9d2a3941 +refs/heads/master: 6721ab7f77f2614ab43e3de2f908b1d7436331df diff --git a/trunk/drivers/tty/serial/omap-serial.c b/trunk/drivers/tty/serial/omap-serial.c index 164c3c94067e..cfd209485af7 100644 --- a/trunk/drivers/tty/serial/omap-serial.c +++ b/trunk/drivers/tty/serial/omap-serial.c @@ -56,8 +56,8 @@ #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) /* FCR register bitmasks */ -#define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) +#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) /* MVR register bitmasks */ #define OMAP_UART_MVR_SCHEME_SHIFT 30 @@ -834,9 +834,13 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; - /* Set receive FIFO threshold to 1 byte */ + /* Set receive FIFO threshold to 16 characters and + * transmit FIFO threshold to 16 spaces + */ up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; - up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT); + up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; + up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | + UART_FCR_ENABLE_FIFO; serial_out(up, UART_FCR, up->fcr); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);