From c80d6406b4656fb97b218b2161f535fd7b61d350 Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@snapgear.com>
Date: Mon, 26 Jun 2006 10:33:10 +1000
Subject: [PATCH] --- yaml --- r: 30155 b: refs/heads/master c:
 76aa698f331475147825ae135eae98bfd457825b h: refs/heads/master i:   30153:
 161a45b555ef2325e59382460532c9dac95d3c6b   30151:
 6c89e59e07d4ded97e30aecadd231fff0829d0a8 v: v3

---
 [refs]                           |  2 +-
 trunk/drivers/serial/mcfserial.c | 28 +++++++++++++++++++++++++---
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index eeb7c7aa784e..5b67b7d89350 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 7c99df64f0be6763bf5079560ccd96911c231b7b
+refs/heads/master: 76aa698f331475147825ae135eae98bfd457825b
diff --git a/trunk/drivers/serial/mcfserial.c b/trunk/drivers/serial/mcfserial.c
index 8cbbb954df2c..8ad242934368 100644
--- a/trunk/drivers/serial/mcfserial.c
+++ b/trunk/drivers/serial/mcfserial.c
@@ -60,11 +60,11 @@ struct timer_list mcfrs_timer_struct;
 #if defined(CONFIG_HW_FEITH)
 #define	CONSOLE_BAUD_RATE	38400
 #define	DEFAULT_CBAUD		B38400
-#elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB)
+#elif defined(CONFIG_MOD5272) || defined(CONFIG_M5208EVB) || defined(CONFIG_M5329EVB)
 #define CONSOLE_BAUD_RATE 	115200
 #define DEFAULT_CBAUD		B115200
 #elif defined(CONFIG_ARNEWSH) || defined(CONFIG_FREESCALE) || \
-      defined(CONFIG_senTec) || defined(CONFIG_SNEHA)
+      defined(CONFIG_senTec) || defined(CONFIG_SNEHA) || defined(CONFIG_AVNET)
 #define	CONSOLE_BAUD_RATE	19200
 #define	DEFAULT_CBAUD		B19200
 #endif
@@ -93,7 +93,7 @@ static struct tty_driver *mcfrs_serial_driver;
 #undef SERIAL_DEBUG_FLOW
 
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x)
+    defined(CONFIG_M520x) || defined(CONFIG_M532x)
 #define	IRQBASE	(MCFINT_VECBASE+MCFINT_UART0)
 #else
 #define	IRQBASE	73
@@ -1545,6 +1545,28 @@ static void mcfrs_irqinit(struct mcf_serial *info)
 			*feci2c_par |=  MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2
 				    | MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
 		}
+#elif defined(CONFIG_M532x)
+	volatile unsigned char *uartp;
+	uartp = info->addr;
+	switch (info->line) {
+	case 0:
+		MCF_INTC0_ICR26 = 0x3;
+		MCF_INTC0_CIMR = 26;
+		/* GPIO initialization */
+		MCF_GPIO_PAR_UART |= 0x000F;
+		break;
+	case 1:
+		MCF_INTC0_ICR27 = 0x3;
+		MCF_INTC0_CIMR = 27;
+		/* GPIO initialization */
+		MCF_GPIO_PAR_UART |= 0x0FF0;
+		break;
+	case 2:
+		MCF_INTC0_ICR28 = 0x3;
+		MCF_INTC0_CIMR = 28;
+		/* GPIOs also must be initalized, depends on board */
+		break;
+	}
 #else
 	volatile unsigned char	*icrp, *uartp;