From c8383e8d691aa31119a90ccc6a7f4fcb1e572dd3 Mon Sep 17 00:00:00 2001
From: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Date: Wed, 12 May 2010 05:52:18 +0100
Subject: [PATCH] --- yaml --- r: 190883 b: refs/heads/master c:
 f4a27aed48584b9e4699e9ee76288618a8574d77 h: refs/heads/master i:   190881:
 1e66caba5dc2f7e1ad898e62a9c3161d45589a5c   190879:
 24d2ca69a47342ff39539f234d5be5aa64ad82c8 v: v3

---
 [refs]                               |  2 +-
 trunk/arch/arm/include/asm/smp_twd.h | 17 +++++++++++++++++
 trunk/arch/arm/kernel/smp_twd.c      | 17 -----------------
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/[refs] b/[refs]
index 8463e90eeb94..6f182f915a4a 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: e814d826dc1821dbce3aa1ddb7f2f739f420ffd8
+refs/heads/master: f4a27aed48584b9e4699e9ee76288618a8574d77
diff --git a/trunk/arch/arm/include/asm/smp_twd.h b/trunk/arch/arm/include/asm/smp_twd.h
index 7be0978b2625..634f357be6bb 100644
--- a/trunk/arch/arm/include/asm/smp_twd.h
+++ b/trunk/arch/arm/include/asm/smp_twd.h
@@ -1,6 +1,23 @@
 #ifndef __ASMARM_SMP_TWD_H
 #define __ASMARM_SMP_TWD_H
 
+#define TWD_TIMER_LOAD			0x00
+#define TWD_TIMER_COUNTER		0x04
+#define TWD_TIMER_CONTROL		0x08
+#define TWD_TIMER_INTSTAT		0x0C
+
+#define TWD_WDOG_LOAD			0x20
+#define TWD_WDOG_COUNTER		0x24
+#define TWD_WDOG_CONTROL		0x28
+#define TWD_WDOG_INTSTAT		0x2C
+#define TWD_WDOG_RESETSTAT		0x30
+#define TWD_WDOG_DISABLE		0x34
+
+#define TWD_TIMER_CONTROL_ENABLE	(1 << 0)
+#define TWD_TIMER_CONTROL_ONESHOT	(0 << 1)
+#define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)
+#define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)
+
 struct clock_event_device;
 
 extern void __iomem *twd_base;
diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c
index ea02a7b1c244..7c5f0c024db7 100644
--- a/trunk/arch/arm/kernel/smp_twd.c
+++ b/trunk/arch/arm/kernel/smp_twd.c
@@ -21,23 +21,6 @@
 #include <asm/smp_twd.h>
 #include <asm/hardware/gic.h>
 
-#define TWD_TIMER_LOAD 			0x00
-#define TWD_TIMER_COUNTER		0x04
-#define TWD_TIMER_CONTROL		0x08
-#define TWD_TIMER_INTSTAT		0x0C
-
-#define TWD_WDOG_LOAD			0x20
-#define TWD_WDOG_COUNTER		0x24
-#define TWD_WDOG_CONTROL		0x28
-#define TWD_WDOG_INTSTAT		0x2C
-#define TWD_WDOG_RESETSTAT		0x30
-#define TWD_WDOG_DISABLE		0x34
-
-#define TWD_TIMER_CONTROL_ENABLE	(1 << 0)
-#define TWD_TIMER_CONTROL_ONESHOT	(0 << 1)
-#define TWD_TIMER_CONTROL_PERIODIC	(1 << 1)
-#define TWD_TIMER_CONTROL_IT_ENABLE	(1 << 2)
-
 /* set up by the platform code */
 void __iomem *twd_base;