diff --git a/[refs] b/[refs]
index 808b8f76588f..d6b9af313488 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 685abecfc2a6036b713229617570980c566c7500
+refs/heads/master: a9eb4f6d1a168c830a206306dfbb1f95a7fed6b3
diff --git a/trunk/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/trunk/arch/sh/include/cpu-sh4/cpu/mmu_context.h
index 03ea75c5315d..310ec92f2759 100644
--- a/trunk/arch/sh/include/cpu-sh4/cpu/mmu_context.h
+++ b/trunk/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -19,6 +19,8 @@
 
 #define MMUCR		0xFF000010	/* MMU Control Register */
 
+#define MMU_ITLB_ADDRESS_ARRAY  0xF2000000
+#define MMU_ITLB_ADDRESS_ARRAY2	0xF2800000
 #define MMU_UTLB_ADDRESS_ARRAY	0xF6000000
 #define MMU_UTLB_ADDRESS_ARRAY2	0xF6800000
 #define MMU_PAGE_ASSOC_BIT	0x80
diff --git a/trunk/arch/sh/mm/tlb-pteaex.c b/trunk/arch/sh/mm/tlb-pteaex.c
index 32dc674c550c..bdd0982b56ee 100644
--- a/trunk/arch/sh/mm/tlb-pteaex.c
+++ b/trunk/arch/sh/mm/tlb-pteaex.c
@@ -73,5 +73,7 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
 	jump_to_uncached();
 	__raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
 	__raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
+	__raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
+	__raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
 	back_to_cached();
 }