diff --git a/[refs] b/[refs]
index 926150a81e8a..6e1786d6e878 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: e04018e8e49c8c78cebd627ea9b5d02b807662ad
+refs/heads/master: b64c4c937daaa04a0a5c188718fb77e8041b5686
diff --git a/trunk/arch/powerpc/sysdev/ppc4xx_pci.c b/trunk/arch/powerpc/sysdev/ppc4xx_pci.c
index 6c925b7975f9..aa856ea9fed8 100644
--- a/trunk/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/trunk/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -940,17 +940,9 @@ static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
 	 * PCIe boards don't show this problem.
 	 * This has to be re-tested and fixed in a later release!
 	 */
-#if 0 /* XXX FIXME: Not resetting the PHY will leave all resources
-       * configured as done previously by U-Boot. Then Linux will currently
-       * not reassign them. So the PHY reset is now done always. This will
-       * lead to problems with the Atheros PCIe board again.
-       */
 	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
 	if (!(val & 0x00001000))
 		ppc405ex_pcie_phy_reset(port);
-#else
-	ppc405ex_pcie_phy_reset(port);
-#endif
 
 	dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000);  /* guarded on */