From c888358fa7569e15d4acc9cc09243ac74be9d9aa Mon Sep 17 00:00:00 2001
From: Pawel Moll <pawel.moll@arm.com>
Date: Fri, 20 May 2011 14:39:29 +0100
Subject: [PATCH] --- yaml --- r: 258312 b: refs/heads/master c:
 15eb169bfec291faf25b158cfa9842b72f7803ad h: refs/heads/master v: v3

---
 [refs]                      |  2 +-
 trunk/arch/arm/mm/proc-v7.S | 11 +++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 0460d227774b..1e8e86db2d5a 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: dc939cd835d0e2d3ff4197d6e2c017d269616d20
+refs/heads/master: 15eb169bfec291faf25b158cfa9842b72f7803ad
diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S
index a759ccafeaca..3185da27a537 100644
--- a/trunk/arch/arm/mm/proc-v7.S
+++ b/trunk/arch/arm/mm/proc-v7.S
@@ -278,6 +278,7 @@ cpu_resume_l1_flags:
  *	It is assumed that:
  *	- cache type register is implemented
  */
+__v7_ca5mp_setup:
 __v7_ca9mp_setup:
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
@@ -443,6 +444,16 @@ __v7_setup_stack:
 	.long	v7_cache_fns
 .endm
 
+	/*
+	 * ARM Ltd. Cortex A5 processor.
+	 */
+	.type   __v7_ca5mp_proc_info, #object
+__v7_ca5mp_proc_info:
+	.long	0x410fc050
+	.long	0xff0ffff0
+	__v7_proc __v7_ca5mp_setup
+	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
+
 	/*
 	 * ARM Ltd. Cortex A9 processor.
 	 */