From c8fc42b6c3d195fb8bb1a4d2657f7027954bf15b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Kristian=20H=C3=B8gsberg?= <krh@bitplanet.net>
Date: Mon, 19 Oct 2009 14:35:30 -0400
Subject: [PATCH] --- yaml --- r: 174530 b: refs/heads/master c:
 a4f45cf178f0d0ad4e516e020818b5f1c00e3d63 h: refs/heads/master v: v3

---
 [refs]                                     | 2 +-
 trunk/drivers/gpu/drm/i915/i915_reg.h      | 1 +
 trunk/drivers/gpu/drm/i915/intel_display.c | 5 ++++-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 90a5cf94051b..adc44236560c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: f3cd474bb235f2331c1a6f579bdbf892386e5c7c
+refs/heads/master: a4f45cf178f0d0ad4e516e020818b5f1c00e3d63
diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h
index d1be1849580d..e8c6d00cde97 100644
--- a/trunk/drivers/gpu/drm/i915/i915_reg.h
+++ b/trunk/drivers/gpu/drm/i915/i915_reg.h
@@ -1915,6 +1915,7 @@
 #define   DISPPLANE_16BPP			(0x5<<26)
 #define   DISPPLANE_32BPP_NO_ALPHA		(0x6<<26)
 #define   DISPPLANE_32BPP			(0x7<<26)
+#define   DISPPLANE_32BPP_30BIT_NO_ALPHA	(0xa<<26)
 #define   DISPPLANE_STEREO_ENABLE		(1<<25)
 #define   DISPPLANE_STEREO_DISABLE		0
 #define   DISPPLANE_SEL_PIPE_MASK		(1<<24)
diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c
index 8df81401c149..e4221b8844ce 100644
--- a/trunk/drivers/gpu/drm/i915/intel_display.c
+++ b/trunk/drivers/gpu/drm/i915/intel_display.c
@@ -1289,7 +1289,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 		break;
 	case 24:
 	case 32:
-		dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
+		if (crtc->fb->depth == 30)
+			dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
+		else
+			dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 		break;
 	default:
 		DRM_ERROR("Unknown color depth\n");