diff --git a/[refs] b/[refs] index bb9e7c80d42c..9752cfac1d6b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c3310e7766ebe7491910715c3161a4f29fa0112e +refs/heads/master: 9f6532519feab921856f41b30a2397ee25f4de49 diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index c547f4a2bb62..ef03abed595a 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -3448,7 +3448,7 @@ P: Matt Porter M: mporter@kernel.crashing.org W: http://www.penguinppc.org/ L: linuxppc-dev@ozlabs.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc.git S: Maintained LINUX FOR POWERPC EMBEDDED XILINX VIRTEX diff --git a/trunk/arch/powerpc/boot/4xx.c b/trunk/arch/powerpc/boot/4xx.c index 325b310573b9..5c878436f348 100644 --- a/trunk/arch/powerpc/boot/4xx.c +++ b/trunk/arch/powerpc/boot/4xx.c @@ -158,46 +158,6 @@ void ibm440spe_fixup_memsize(void) #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) -/* - * Some U-Boot versions set the number of chipselects to two - * for Sequoia/Rainier boards while they only have one chipselect - * hardwired. Hardcode the number of chipselects to one - * for sequioa/rainer board models or read the actual value - * from the memory controller register DDR0_10 otherwise. - */ -static inline u32 ibm4xx_denali_get_cs(void) -{ - void *devp; - char model[64]; - u32 val, cs; - - devp = finddevice("/"); - if (!devp) - goto read_cs; - - if (getprop(devp, "model", model, sizeof(model)) <= 0) - goto read_cs; - - model[sizeof(model)-1] = 0; - - if (!strcmp(model, "amcc,sequoia") || - !strcmp(model, "amcc,rainier")) - return 1; - -read_cs: - /* get CS value */ - val = SDRAM0_READ(DDR0_10); - - val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); - cs = 0; - while (val) { - if (val & 0x1) - cs++; - val = val >> 1; - } - return cs; -} - void ibm4xx_denali_fixup_memsize(void) { u32 val, max_cs, max_col, max_row; @@ -213,7 +173,17 @@ void ibm4xx_denali_fixup_memsize(void) max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); - cs = ibm4xx_denali_get_cs(); + /* get CS value */ + val = SDRAM0_READ(DDR0_10); + + val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); + cs = 0; + while (val) { + if (val & 0x1) + cs++; + val = val >> 1; + } + if (!cs) fatal("No memory installed\n"); if (cs > max_cs) @@ -223,9 +193,9 @@ void ibm4xx_denali_fixup_memsize(void) val = SDRAM0_READ(DDR0_14); if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) - dpath = 4; /* 32 bits */ - else dpath = 8; /* 64 bits */ + else + dpath = 4; /* 32 bits */ /* get address pins (rows) */ val = SDRAM0_READ(DDR0_42); diff --git a/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts b/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts index 53a7a6255909..d47ad0718759 100644 --- a/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts +++ b/trunk/arch/powerpc/boot/dts/gef_ppc9a.dts @@ -161,7 +161,6 @@ #address-cells = <1>; #size-cells = <1>; #interrupt-cells = <2>; - device_type = "soc"; compatible = "fsl,mpc8641-soc", "simple-bus"; ranges = <0x0 0xfef00000 0x00100000>; reg = <0xfef00000 0x100000>; // CCSRBAR 1M diff --git a/trunk/arch/powerpc/include/asm/elf.h b/trunk/arch/powerpc/include/asm/elf.h index d6b4a12cdeff..087c22f1d368 100644 --- a/trunk/arch/powerpc/include/asm/elf.h +++ b/trunk/arch/powerpc/include/asm/elf.h @@ -260,7 +260,6 @@ do { \ #else # define SET_PERSONALITY(ex) \ set_personality(PER_LINUX | (current->personality & (~PER_MASK))) -# define elf_read_implies_exec(ex, exec_stk) (exec_stk != EXSTACK_DISABLE_X) #endif /* __powerpc64__ */ extern int dcache_bsize; diff --git a/trunk/arch/powerpc/include/asm/mmu.h b/trunk/arch/powerpc/include/asm/mmu.h index cbf154387091..86d2366ab6a1 100644 --- a/trunk/arch/powerpc/include/asm/mmu.h +++ b/trunk/arch/powerpc/include/asm/mmu.h @@ -52,6 +52,12 @@ */ #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) +/* This indicates that the processor uses the wrong opcode for tlbilx + * instructions. During the ISA 2.06 development the opcode for tlbilx + * changed and some early implementations used to old opcode + */ +#define MMU_FTR_TLBILX_EARLY_OPCODE ASM_CONST(0x00400000) + #ifndef __ASSEMBLY__ #include diff --git a/trunk/arch/powerpc/include/asm/ppc-opcode.h b/trunk/arch/powerpc/include/asm/ppc-opcode.h index 640ccbbc0977..ef4da37f3c10 100644 --- a/trunk/arch/powerpc/include/asm/ppc-opcode.h +++ b/trunk/arch/powerpc/include/asm/ppc-opcode.h @@ -44,6 +44,7 @@ #define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWX 0x7c00052a #define PPC_INST_TLBILX 0x7c000024 +#define PPC_INST_TLBILX_EARLY 0x7c000626 #define PPC_INST_WAIT 0x7c00007c /* macros to insert fields into opcodes */ @@ -63,10 +64,18 @@ #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ - __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b)) + __PPC_T_TLB(t) | \ + __PPC_RA(a) | __PPC_RB(b)) #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) + +#define PPC_TLBILX_EARLY(t, a, b) stringify_in_c(.long PPC_INST_TLBILX_EARLY | \ + __PPC_T_TLB(t) | \ + __PPC_RA(a) | __PPC_RB(b)) +#define PPC_TLBILX_ALL_EARLY(a, b) PPC_TLBILX_EARLY(0, a, b) +#define PPC_TLBILX_PID_EARLY(a, b) PPC_TLBILX_EARLY(1, a, b) +#define PPC_TLBILX_VA_EARLY(a, b) PPC_TLBILX_EARLY(3, a, b) #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ __PPC_WC(w)) diff --git a/trunk/arch/powerpc/kernel/cputable.c b/trunk/arch/powerpc/kernel/cputable.c index cd1b687544f3..57db50f40289 100644 --- a/trunk/arch/powerpc/kernel/cputable.c +++ b/trunk/arch/powerpc/kernel/cputable.c @@ -1766,7 +1766,7 @@ static struct cpu_spec __initdata cpu_specs[] = { .cpu_features = CPU_FTRS_E500MC, .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | - MMU_FTR_USE_TLBILX, + MMU_FTR_USE_TLBILX | MMU_FTR_TLBILX_EARLY_OPCODE, .icache_bsize = 64, .dcache_bsize = 64, .num_pmcs = 4, diff --git a/trunk/arch/powerpc/kernel/vmlinux.lds.S b/trunk/arch/powerpc/kernel/vmlinux.lds.S index a047a6cfca4d..433ae118406d 100644 --- a/trunk/arch/powerpc/kernel/vmlinux.lds.S +++ b/trunk/arch/powerpc/kernel/vmlinux.lds.S @@ -54,8 +54,8 @@ SECTIONS ALIGN_FUNCTION(); HEAD_TEXT _text = .; - /* careful! __ftr_alt_* sections need to be close to .text */ - *(.text .fixup __ftr_alt_* .ref.text) + TEXT_TEXT + *(.fixup __ftr_alt_*) SCHED_TEXT LOCK_TEXT KPROBES_TEXT diff --git a/trunk/arch/powerpc/mm/tlb_nohash_low.S b/trunk/arch/powerpc/mm/tlb_nohash_low.S index 3037911279b1..45fed3698349 100644 --- a/trunk/arch/powerpc/mm/tlb_nohash_low.S +++ b/trunk/arch/powerpc/mm/tlb_nohash_low.S @@ -138,7 +138,11 @@ BEGIN_MMU_FTR_SECTION andi. r3,r3,MMUCSR0_TLBFI@l bne 1b MMU_FTR_SECTION_ELSE - PPC_TLBILX_ALL(0,0) + BEGIN_MMU_FTR_SECTION_NESTED(96) + PPC_TLBILX_ALL(0,r3) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_ALL_EARLY(0,r3) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync @@ -151,7 +155,11 @@ BEGIN_MMU_FTR_SECTION wrteei 0 mfspr r4,SPRN_MAS6 /* save MAS6 */ mtspr SPRN_MAS6,r3 + BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_PID(0,0) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_PID_EARLY(0,0) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) mtspr SPRN_MAS6,r4 /* restore MAS6 */ wrtee r10 MMU_FTR_SECTION_ELSE @@ -185,12 +193,16 @@ BEGIN_MMU_FTR_SECTION mtspr SPRN_MAS1,r4 tlbwe MMU_FTR_SECTION_ELSE + BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_VA(0,r3) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_VA_EARLY(0,r3) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync 1: wrtee r10 blr -#else +#elif #error Unsupported processor type ! #endif diff --git a/trunk/arch/powerpc/platforms/cell/Kconfig b/trunk/arch/powerpc/platforms/cell/Kconfig index 50f17bdd3c16..40e24c39ad06 100644 --- a/trunk/arch/powerpc/platforms/cell/Kconfig +++ b/trunk/arch/powerpc/platforms/cell/Kconfig @@ -13,6 +13,7 @@ config PPC_CELL_COMMON config PPC_CELL_NATIVE bool select PPC_CELL_COMMON + select PPC_OF_PLATFORM_PCI select MPIC select IBM_NEW_EMAC_EMAC4 select IBM_NEW_EMAC_RGMII @@ -24,8 +25,6 @@ config PPC_IBM_CELL_BLADE bool "IBM Cell Blade" depends on PPC64 && PPC_BOOK3S select PPC_CELL_NATIVE - select PPC_OF_PLATFORM_PCI - select PCI select MMIO_NVRAM select PPC_UDBG_16550 select UDBG_RTAS_CONSOLE @@ -34,8 +33,6 @@ config PPC_CELLEB bool "Toshiba's Cell Reference Set 'Celleb' Architecture" depends on PPC64 && PPC_BOOK3S select PPC_CELL_NATIVE - select PPC_OF_PLATFORM_PCI - select PCI select HAS_TXX9_SERIAL select PPC_UDBG_BEAT select USB_OHCI_BIG_ENDIAN_MMIO diff --git a/trunk/arch/powerpc/platforms/ps3/setup.c b/trunk/arch/powerpc/platforms/ps3/setup.c index 1a7b5ae0c83e..66181821322a 100644 --- a/trunk/arch/powerpc/platforms/ps3/setup.c +++ b/trunk/arch/powerpc/platforms/ps3/setup.c @@ -45,6 +45,10 @@ DEFINE_MUTEX(ps3_gpu_mutex); EXPORT_SYMBOL_GPL(ps3_gpu_mutex); +#if !defined(CONFIG_SMP) +static void smp_send_stop(void) {} +#endif + static union ps3_firmware_version ps3_firmware_version; void ps3_get_firmware_version(union ps3_firmware_version *v) diff --git a/trunk/include/linux/regulator/driver.h b/trunk/include/linux/regulator/driver.h index 4848d8dacd90..225f733e7533 100644 --- a/trunk/include/linux/regulator/driver.h +++ b/trunk/include/linux/regulator/driver.h @@ -50,6 +50,7 @@ enum regulator_status { * @set_current_limit: Configure a limit for a current-limited regulator. * @get_current_limit: Get the configured limit for a current-limited regulator. * + * @set_mode: Set the configured operating mode for the regulator. * @get_mode: Get the configured operating mode for the regulator. * @get_status: Return actual (not as-configured) status of regulator, as a * REGULATOR_STATUS value (or negative errno)