From c9df853880018139ad37747511738e8c4681d47d Mon Sep 17 00:00:00 2001
From: Cyrill Gorcunov <gorcunov@openvz.org>
Date: Wed, 19 May 2010 01:19:17 +0400
Subject: [PATCH] --- yaml --- r: 199103 b: refs/heads/master c:
 623aab896ee1a532cb540bcf0d5ae8a88275afd5 h: refs/heads/master i:   199101:
 9416ec1a4274c00c8ae78ad649735ee8ca3deead   199099:
 03398ec7fcf807c027b2151e4530340351d976f4   199095:
 7ff3109cd2b7e982b27b3c59b19d3d7c123d2730   199087:
 aae160382b60a22970b2e8919d444b94d9a142de   199071:
 0a0898b41bd993f75d21b34fb424649a70a630e7   199039:
 7634633ccd98b1fa7fd9e9b47708427ed28730fc v: v3

---
 [refs]                                    | 2 +-
 trunk/arch/x86/kernel/cpu/perf_event_p4.c | 7 ++++---
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index 4f3b4379345e..a8988974059e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 151f85a471d29fc81f70348143d009a729901bc0
+refs/heads/master: 623aab896ee1a532cb540bcf0d5ae8a88275afd5
diff --git a/trunk/arch/x86/kernel/cpu/perf_event_p4.c b/trunk/arch/x86/kernel/cpu/perf_event_p4.c
index 87e1803e67a6..5f8e36d62793 100644
--- a/trunk/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/trunk/arch/x86/kernel/cpu/perf_event_p4.c
@@ -670,7 +670,7 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
 
 /*
  * ESCR address hashing is tricky, ESCRs are not sequential
- * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03e0) and
+ * in memory but all starts from MSR_P4_BSU_ESCR0 (0x03a0) and
  * the metric between any ESCRs is laid in range [0xa0,0xe1]
  *
  * so we make ~70% filled hashtable
@@ -735,8 +735,9 @@ static int p4_get_escr_idx(unsigned int addr)
 {
 	unsigned int idx = P4_ESCR_MSR_IDX(addr);
 
-	if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE ||
-			!p4_escr_table[idx])) {
+	if (unlikely(idx >= P4_ESCR_MSR_TABLE_SIZE	||
+			!p4_escr_table[idx]		||
+			p4_escr_table[idx] != addr)) {
 		WARN_ONCE(1, "P4 PMU: Wrong address passed: %x\n", addr);
 		return -1;
 	}