diff --git a/[refs] b/[refs]
index 1c7eb10f6ff9..d7e546edde80 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9598111f49ade848aa44f431ee81a42a000c8b3c
+refs/heads/master: 3572a2c37f667ee49333f8863722b8f43eac506b
diff --git a/trunk/arch/mips/ath79/Kconfig b/trunk/arch/mips/ath79/Kconfig
index f44feee2d67f..e0fae8f4442b 100644
--- a/trunk/arch/mips/ath79/Kconfig
+++ b/trunk/arch/mips/ath79/Kconfig
@@ -26,18 +26,6 @@ config ATH79_MACH_AP81
 	  Say 'Y' here if you want your kernel to support the
 	  Atheros AP81 reference board.
 
-config ATH79_MACH_DB120
-	bool "Atheros DB120 reference board"
-	select SOC_AR934X
-	select ATH79_DEV_GPIO_BUTTONS
-	select ATH79_DEV_LEDS_GPIO
-	select ATH79_DEV_SPI
-	select ATH79_DEV_USB
-	select ATH79_DEV_WMAC
-	help
-	  Say 'Y' here if you want your kernel to support the
-	  Atheros DB120 reference board.
-
 config ATH79_MACH_PB44
 	bool "Atheros PB44 reference board"
 	select SOC_AR71XX
@@ -64,14 +52,12 @@ endmenu
 config SOC_AR71XX
 	select USB_ARCH_HAS_EHCI
 	select USB_ARCH_HAS_OHCI
-	select HW_HAS_PCI
 	def_bool n
 
 config SOC_AR724X
 	select USB_ARCH_HAS_EHCI
 	select USB_ARCH_HAS_OHCI
 	select HW_HAS_PCI
-	select PCI_AR724X if PCI
 	def_bool n
 
 config SOC_AR913X
@@ -82,15 +68,6 @@ config SOC_AR933X
 	select USB_ARCH_HAS_EHCI
 	def_bool n
 
-config SOC_AR934X
-	select USB_ARCH_HAS_EHCI
-	select HW_HAS_PCI
-	select PCI_AR724X if PCI
-	def_bool n
-
-config PCI_AR724X
-	def_bool n
-
 config ATH79_DEV_GPIO_BUTTONS
 	def_bool n
 
@@ -104,7 +81,7 @@ config ATH79_DEV_USB
 	def_bool n
 
 config ATH79_DEV_WMAC
-	depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X)
+	depends on (SOC_AR913X || SOC_AR933X)
 	def_bool n
 
 endif
diff --git a/trunk/arch/mips/ath79/Makefile b/trunk/arch/mips/ath79/Makefile
index 2b54d98263f3..3b911e09dbec 100644
--- a/trunk/arch/mips/ath79/Makefile
+++ b/trunk/arch/mips/ath79/Makefile
@@ -11,7 +11,6 @@
 obj-y	:= prom.o setup.o irq.o common.o clock.o gpio.o
 
 obj-$(CONFIG_EARLY_PRINTK)		+= early_printk.o
-obj-$(CONFIG_PCI)			+= pci.o
 
 #
 # Devices
@@ -28,6 +27,5 @@ obj-$(CONFIG_ATH79_DEV_WMAC)		+= dev-wmac.o
 #
 obj-$(CONFIG_ATH79_MACH_AP121)		+= mach-ap121.o
 obj-$(CONFIG_ATH79_MACH_AP81)		+= mach-ap81.o
-obj-$(CONFIG_ATH79_MACH_DB120)		+= mach-db120.o
 obj-$(CONFIG_ATH79_MACH_PB44)		+= mach-pb44.o
 obj-$(CONFIG_ATH79_MACH_UBNT_XM)	+= mach-ubnt-xm.o
diff --git a/trunk/arch/mips/ath79/clock.c b/trunk/arch/mips/ath79/clock.c
index b91ad3efe29e..54d0eb4db987 100644
--- a/trunk/arch/mips/ath79/clock.c
+++ b/trunk/arch/mips/ath79/clock.c
@@ -1,11 +1,8 @@
 /*
  *  Atheros AR71XX/AR724X/AR913X common routines
  *
- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  *  Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
  *
- *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
  *  by the Free Software Foundation.
@@ -166,82 +163,6 @@ static void __init ar933x_clocks_init(void)
 	ath79_uart_clk.rate = ath79_ref_clk.rate;
 }
 
-static void __init ar934x_clocks_init(void)
-{
-	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
-	u32 cpu_pll, ddr_pll;
-	u32 bootstrap;
-
-	bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-	if (bootstrap &	AR934X_BOOTSTRAP_REF_CLK_40)
-		ath79_ref_clk.rate = 40 * 1000 * 1000;
-	else
-		ath79_ref_clk.rate = 25 * 1000 * 1000;
-
-	pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
-	out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
-		  AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
-	ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
-		  AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
-	nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
-	       AR934X_PLL_CPU_CONFIG_NINT_MASK;
-	frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
-	       AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
-
-	cpu_pll = nint * ath79_ref_clk.rate / ref_div;
-	cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 6));
-	cpu_pll /= (1 << out_div);
-
-	pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
-	out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
-		  AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
-	ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
-		  AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
-	nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
-	       AR934X_PLL_DDR_CONFIG_NINT_MASK;
-	frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
-	       AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
-
-	ddr_pll = nint * ath79_ref_clk.rate / ref_div;
-	ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (2 << 10));
-	ddr_pll /= (1 << out_div);
-
-	clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
-
-	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
-		  AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
-
-	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
-		ath79_cpu_clk.rate = ath79_ref_clk.rate;
-	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
-		ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
-	else
-		ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
-
-	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
-		  AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
-
-	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
-		ath79_ddr_clk.rate = ath79_ref_clk.rate;
-	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
-		ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
-	else
-		ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
-
-	postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
-		  AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
-
-	if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
-		ath79_ahb_clk.rate = ath79_ref_clk.rate;
-	else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
-		ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
-	else
-		ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
-
-	ath79_wdt_clk.rate = ath79_ref_clk.rate;
-	ath79_uart_clk.rate = ath79_ref_clk.rate;
-}
-
 void __init ath79_clocks_init(void)
 {
 	if (soc_is_ar71xx())
@@ -252,8 +173,6 @@ void __init ath79_clocks_init(void)
 		ar913x_clocks_init();
 	else if (soc_is_ar933x())
 		ar933x_clocks_init();
-	else if (soc_is_ar934x())
-		ar934x_clocks_init();
 	else
 		BUG();
 
diff --git a/trunk/arch/mips/ath79/common.c b/trunk/arch/mips/ath79/common.c
index 5a4adfc9d79d..f0fda982b965 100644
--- a/trunk/arch/mips/ath79/common.c
+++ b/trunk/arch/mips/ath79/common.c
@@ -1,12 +1,9 @@
 /*
  *  Atheros AR71XX/AR724X/AR913X common routines
  *
- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
- *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
  *  by the Free Software Foundation.
@@ -70,8 +67,6 @@ void ath79_device_reset_set(u32 mask)
 		reg = AR913X_RESET_REG_RESET_MODULE;
 	else if (soc_is_ar933x())
 		reg = AR933X_RESET_REG_RESET_MODULE;
-	else if (soc_is_ar934x())
-		reg = AR934X_RESET_REG_RESET_MODULE;
 	else
 		BUG();
 
@@ -96,8 +91,6 @@ void ath79_device_reset_clear(u32 mask)
 		reg = AR913X_RESET_REG_RESET_MODULE;
 	else if (soc_is_ar933x())
 		reg = AR933X_RESET_REG_RESET_MODULE;
-	else if (soc_is_ar934x())
-		reg = AR934X_RESET_REG_RESET_MODULE;
 	else
 		BUG();
 
diff --git a/trunk/arch/mips/ath79/dev-common.c b/trunk/arch/mips/ath79/dev-common.c
index 45efc63b08b6..f4956f809072 100644
--- a/trunk/arch/mips/ath79/dev-common.c
+++ b/trunk/arch/mips/ath79/dev-common.c
@@ -89,8 +89,7 @@ void __init ath79_register_uart(void)
 
 	if (soc_is_ar71xx() ||
 	    soc_is_ar724x() ||
-	    soc_is_ar913x() ||
-	    soc_is_ar934x()) {
+	    soc_is_ar913x()) {
 		ath79_uart_data[0].uartclk = clk_get_rate(clk);
 		platform_device_register(&ath79_uart_device);
 	} else if (soc_is_ar933x()) {
diff --git a/trunk/arch/mips/ath79/dev-gpio-buttons.c b/trunk/arch/mips/ath79/dev-gpio-buttons.c
index 366b35fb164d..4b0168a11c01 100644
--- a/trunk/arch/mips/ath79/dev-gpio-buttons.c
+++ b/trunk/arch/mips/ath79/dev-gpio-buttons.c
@@ -25,10 +25,12 @@ void __init ath79_register_gpio_keys_polled(int id,
 	struct gpio_keys_button *p;
 	int err;
 
-	p = kmemdup(buttons, nbuttons * sizeof(*p), GFP_KERNEL);
+	p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
 	if (!p)
 		return;
 
+	memcpy(p, buttons, nbuttons * sizeof(*p));
+
 	pdev = platform_device_alloc("gpio-keys-polled", id);
 	if (!pdev)
 		goto err_free_buttons;
diff --git a/trunk/arch/mips/ath79/dev-leds-gpio.c b/trunk/arch/mips/ath79/dev-leds-gpio.c
index dcb1debcefb8..cdade68dcd17 100644
--- a/trunk/arch/mips/ath79/dev-leds-gpio.c
+++ b/trunk/arch/mips/ath79/dev-leds-gpio.c
@@ -24,10 +24,12 @@ void __init ath79_register_leds_gpio(int id,
 	struct gpio_led *p;
 	int err;
 
-	p = kmemdup(leds, num_leds * sizeof(*p), GFP_KERNEL);
+	p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
 	if (!p)
 		return;
 
+	memcpy(p, leds, num_leds * sizeof(*p));
+
 	pdev = platform_device_alloc("leds-gpio", id);
 	if (!pdev)
 		goto err_free_leds;
diff --git a/trunk/arch/mips/ath79/dev-wmac.c b/trunk/arch/mips/ath79/dev-wmac.c
index d6d893c16ad4..9c717bf98ffe 100644
--- a/trunk/arch/mips/ath79/dev-wmac.c
+++ b/trunk/arch/mips/ath79/dev-wmac.c
@@ -1,12 +1,9 @@
 /*
  *  Atheros AR913X/AR933X SoC built-in WMAC device support
  *
- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
- *  Parts of this file are based on Atheros 2.6.15/2.6.31 BSP
- *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
  *  by the Free Software Foundation.
@@ -29,7 +26,8 @@ static struct resource ath79_wmac_resources[] = {
 		/* .start and .end fields are filled dynamically */
 		.flags	= IORESOURCE_MEM,
 	}, {
-		/* .start and .end fields are filled dynamically */
+		.start	= ATH79_CPU_IRQ_IP2,
+		.end	= ATH79_CPU_IRQ_IP2,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
@@ -55,8 +53,6 @@ static void __init ar913x_wmac_setup(void)
 
 	ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
 	ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
-	ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
-	ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
 }
 
 
@@ -83,8 +79,6 @@ static void __init ar933x_wmac_setup(void)
 
 	ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
 	ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
-	ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
-	ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
 
 	t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 	if (t & AR933X_BOOTSTRAP_REF_CLK_40)
@@ -98,32 +92,12 @@ static void __init ar933x_wmac_setup(void)
 	ath79_wmac_data.external_reset = ar933x_wmac_reset;
 }
 
-static void ar934x_wmac_setup(void)
-{
-	u32 t;
-
-	ath79_wmac_device.name = "ar934x_wmac";
-
-	ath79_wmac_resources[0].start = AR934X_WMAC_BASE;
-	ath79_wmac_resources[0].end = AR934X_WMAC_BASE + AR934X_WMAC_SIZE - 1;
-	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-	ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
-
-	t = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-	if (t & AR934X_BOOTSTRAP_REF_CLK_40)
-		ath79_wmac_data.is_clk_25mhz = false;
-	else
-		ath79_wmac_data.is_clk_25mhz = true;
-}
-
 void __init ath79_register_wmac(u8 *cal_data)
 {
 	if (soc_is_ar913x())
 		ar913x_wmac_setup();
 	else if (soc_is_ar933x())
 		ar933x_wmac_setup();
-	else if (soc_is_ar934x())
-		ar934x_wmac_setup();
 	else
 		BUG();
 
diff --git a/trunk/arch/mips/ath79/early_printk.c b/trunk/arch/mips/ath79/early_printk.c
index dc938cb2ba58..6a51ced7a293 100644
--- a/trunk/arch/mips/ath79/early_printk.c
+++ b/trunk/arch/mips/ath79/early_printk.c
@@ -71,9 +71,6 @@ static void prom_putchar_init(void)
 	case REV_ID_MAJOR_AR7241:
 	case REV_ID_MAJOR_AR7242:
 	case REV_ID_MAJOR_AR913X:
-	case REV_ID_MAJOR_AR9341:
-	case REV_ID_MAJOR_AR9342:
-	case REV_ID_MAJOR_AR9344:
 		_prom_putchar = prom_putchar_ar71xx;
 		break;
 
diff --git a/trunk/arch/mips/ath79/gpio.c b/trunk/arch/mips/ath79/gpio.c
index 29054f211832..a2f8ca630ed6 100644
--- a/trunk/arch/mips/ath79/gpio.c
+++ b/trunk/arch/mips/ath79/gpio.c
@@ -1,12 +1,9 @@
 /*
  *  Atheros AR71XX/AR724X/AR913X GPIO API support
  *
- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
- *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
- *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
  *  by the Free Software Foundation.
@@ -92,42 +89,6 @@ static int ath79_gpio_direction_output(struct gpio_chip *chip,
 	return 0;
 }
 
-static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
-	void __iomem *base = ath79_gpio_base;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ath79_gpio_lock, flags);
-
-	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
-		     base + AR71XX_GPIO_REG_OE);
-
-	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
-
-	return 0;
-}
-
-static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-					int value)
-{
-	void __iomem *base = ath79_gpio_base;
-	unsigned long flags;
-
-	spin_lock_irqsave(&ath79_gpio_lock, flags);
-
-	if (value)
-		__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
-	else
-		__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
-
-	__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
-		     base + AR71XX_GPIO_REG_OE);
-
-	spin_unlock_irqrestore(&ath79_gpio_lock, flags);
-
-	return 0;
-}
-
 static struct gpio_chip ath79_gpio_chip = {
 	.label			= "ath79",
 	.get			= ath79_gpio_get_value,
@@ -194,17 +155,11 @@ void __init ath79_gpio_init(void)
 		ath79_gpio_count = AR913X_GPIO_COUNT;
 	else if (soc_is_ar933x())
 		ath79_gpio_count = AR933X_GPIO_COUNT;
-	else if (soc_is_ar934x())
-		ath79_gpio_count = AR934X_GPIO_COUNT;
 	else
 		BUG();
 
 	ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 	ath79_gpio_chip.ngpio = ath79_gpio_count;
-	if (soc_is_ar934x()) {
-		ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
-		ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
-	}
 
 	err = gpiochip_add(&ath79_gpio_chip);
 	if (err)
diff --git a/trunk/arch/mips/ath79/irq.c b/trunk/arch/mips/ath79/irq.c
index 90d09fc15398..1b073de44680 100644
--- a/trunk/arch/mips/ath79/irq.c
+++ b/trunk/arch/mips/ath79/irq.c
@@ -1,11 +1,10 @@
 /*
  *  Atheros AR71xx/AR724x/AR913x specific interrupt handling
  *
- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
- *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
@@ -24,8 +23,8 @@
 #include <asm/mach-ath79/ar71xx_regs.h>
 #include "common.h"
 
-static void (*ath79_ip2_handler)(void);
-static void (*ath79_ip3_handler)(void);
+static unsigned int ath79_ip2_flush_reg;
+static unsigned int ath79_ip3_flush_reg;
 
 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
@@ -130,7 +129,7 @@ static void __init ath79_misc_irq_init(void)
 
 	if (soc_is_ar71xx() || soc_is_ar913x())
 		ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
-	else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
+	else if (soc_is_ar724x() || soc_is_ar933x())
 		ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 	else
 		BUG();
@@ -144,39 +143,6 @@ static void __init ath79_misc_irq_init(void)
 	irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
 }
 
-static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
-{
-	u32 status;
-
-	disable_irq_nosync(irq);
-
-	status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
-
-	if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
-		ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
-		generic_handle_irq(ATH79_IP2_IRQ(0));
-	} else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
-		ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
-		generic_handle_irq(ATH79_IP2_IRQ(1));
-	} else {
-		spurious_interrupt();
-	}
-
-	enable_irq(irq);
-}
-
-static void ar934x_ip2_irq_init(void)
-{
-	int i;
-
-	for (i = ATH79_IP2_IRQ_BASE;
-	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
-		irq_set_chip_and_handler(i, &dummy_irq_chip,
-					 handle_level_irq);
-
-	irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
-}
-
 asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned long pending;
@@ -186,8 +152,10 @@ asmlinkage void plat_irq_dispatch(void)
 	if (pending & STATUSF_IP7)
 		do_IRQ(ATH79_CPU_IRQ_TIMER);
 
-	else if (pending & STATUSF_IP2)
-		ath79_ip2_handler();
+	else if (pending & STATUSF_IP2) {
+		ath79_ddr_wb_flush(ath79_ip2_flush_reg);
+		do_IRQ(ATH79_CPU_IRQ_IP2);
+	}
 
 	else if (pending & STATUSF_IP4)
 		do_IRQ(ATH79_CPU_IRQ_GE0);
@@ -195,8 +163,10 @@ asmlinkage void plat_irq_dispatch(void)
 	else if (pending & STATUSF_IP5)
 		do_IRQ(ATH79_CPU_IRQ_GE1);
 
-	else if (pending & STATUSF_IP3)
-		ath79_ip3_handler();
+	else if (pending & STATUSF_IP3) {
+		ath79_ddr_wb_flush(ath79_ip3_flush_reg);
+		do_IRQ(ATH79_CPU_IRQ_USB);
+	}
 
 	else if (pending & STATUSF_IP6)
 		do_IRQ(ATH79_CPU_IRQ_MISC);
@@ -205,97 +175,24 @@ asmlinkage void plat_irq_dispatch(void)
 		spurious_interrupt();
 }
 
-/*
- * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
- * these devices typically allocate coherent DMA memory, however the
- * DMA controller may still have some unsynchronized data in the FIFO.
- * Issue a flush in the handlers to ensure that the driver sees
- * the update.
- */
-static void ar71xx_ip2_handler(void)
-{
-	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
-	do_IRQ(ATH79_CPU_IRQ_IP2);
-}
-
-static void ar724x_ip2_handler(void)
-{
-	ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
-	do_IRQ(ATH79_CPU_IRQ_IP2);
-}
-
-static void ar913x_ip2_handler(void)
-{
-	ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
-	do_IRQ(ATH79_CPU_IRQ_IP2);
-}
-
-static void ar933x_ip2_handler(void)
-{
-	ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
-	do_IRQ(ATH79_CPU_IRQ_IP2);
-}
-
-static void ar934x_ip2_handler(void)
-{
-	do_IRQ(ATH79_CPU_IRQ_IP2);
-}
-
-static void ar71xx_ip3_handler(void)
-{
-	ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
-	do_IRQ(ATH79_CPU_IRQ_USB);
-}
-
-static void ar724x_ip3_handler(void)
-{
-	ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
-	do_IRQ(ATH79_CPU_IRQ_USB);
-}
-
-static void ar913x_ip3_handler(void)
-{
-	ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
-	do_IRQ(ATH79_CPU_IRQ_USB);
-}
-
-static void ar933x_ip3_handler(void)
-{
-	ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
-	do_IRQ(ATH79_CPU_IRQ_USB);
-}
-
-static void ar934x_ip3_handler(void)
-{
-	ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
-	do_IRQ(ATH79_CPU_IRQ_USB);
-}
-
 void __init arch_init_irq(void)
 {
 	if (soc_is_ar71xx()) {
-		ath79_ip2_handler = ar71xx_ip2_handler;
-		ath79_ip3_handler = ar71xx_ip3_handler;
+		ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
+		ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
 	} else if (soc_is_ar724x()) {
-		ath79_ip2_handler = ar724x_ip2_handler;
-		ath79_ip3_handler = ar724x_ip3_handler;
+		ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
+		ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
 	} else if (soc_is_ar913x()) {
-		ath79_ip2_handler = ar913x_ip2_handler;
-		ath79_ip3_handler = ar913x_ip3_handler;
+		ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
+		ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
 	} else if (soc_is_ar933x()) {
-		ath79_ip2_handler = ar933x_ip2_handler;
-		ath79_ip3_handler = ar933x_ip3_handler;
-	} else if (soc_is_ar934x()) {
-		ath79_ip2_handler = ar934x_ip2_handler;
-		ath79_ip3_handler = ar934x_ip3_handler;
-	} else {
+		ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
+		ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
+	} else
 		BUG();
-	}
 
 	cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
 	mips_cpu_irq_init();
 	ath79_misc_irq_init();
-
-	if (soc_is_ar934x())
-		ar934x_ip2_irq_init();
 }
diff --git a/trunk/arch/mips/ath79/mach-db120.c b/trunk/arch/mips/ath79/mach-db120.c
deleted file mode 100644
index 1983e4d2af4b..000000000000
--- a/trunk/arch/mips/ath79/mach-db120.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Atheros DB120 reference board support
- *
- * Copyright (c) 2011 Qualcomm Atheros
- * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include <linux/pci.h>
-#include <linux/ath9k_platform.h>
-
-#include "machtypes.h"
-#include "dev-gpio-buttons.h"
-#include "dev-leds-gpio.h"
-#include "dev-spi.h"
-#include "dev-wmac.h"
-#include "pci.h"
-
-#define DB120_GPIO_LED_WLAN_5G		12
-#define DB120_GPIO_LED_WLAN_2G		13
-#define DB120_GPIO_LED_STATUS		14
-#define DB120_GPIO_LED_WPS		15
-
-#define DB120_GPIO_BTN_WPS		16
-
-#define DB120_KEYS_POLL_INTERVAL	20	/* msecs */
-#define DB120_KEYS_DEBOUNCE_INTERVAL	(3 * DB120_KEYS_POLL_INTERVAL)
-
-#define DB120_WMAC_CALDATA_OFFSET 0x1000
-#define DB120_PCIE_CALDATA_OFFSET 0x5000
-
-static struct gpio_led db120_leds_gpio[] __initdata = {
-	{
-		.name		= "db120:green:status",
-		.gpio		= DB120_GPIO_LED_STATUS,
-		.active_low	= 1,
-	},
-	{
-		.name		= "db120:green:wps",
-		.gpio		= DB120_GPIO_LED_WPS,
-		.active_low	= 1,
-	},
-	{
-		.name		= "db120:green:wlan-5g",
-		.gpio		= DB120_GPIO_LED_WLAN_5G,
-		.active_low	= 1,
-	},
-	{
-		.name		= "db120:green:wlan-2g",
-		.gpio		= DB120_GPIO_LED_WLAN_2G,
-		.active_low	= 1,
-	},
-};
-
-static struct gpio_keys_button db120_gpio_keys[] __initdata = {
-	{
-		.desc		= "WPS button",
-		.type		= EV_KEY,
-		.code		= KEY_WPS_BUTTON,
-		.debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
-		.gpio		= DB120_GPIO_BTN_WPS,
-		.active_low	= 1,
-	},
-};
-
-static struct spi_board_info db120_spi_info[] = {
-	{
-		.bus_num	= 0,
-		.chip_select	= 0,
-		.max_speed_hz	= 25000000,
-		.modalias	= "s25sl064a",
-	}
-};
-
-static struct ath79_spi_platform_data db120_spi_data = {
-	.bus_num	= 0,
-	.num_chipselect	= 1,
-};
-
-#ifdef CONFIG_PCI
-static struct ath9k_platform_data db120_ath9k_data;
-
-static int db120_pci_plat_dev_init(struct pci_dev *dev)
-{
-	switch (PCI_SLOT(dev->devfn)) {
-	case 0:
-		dev->dev.platform_data = &db120_ath9k_data;
-		break;
-	}
-
-	return 0;
-}
-
-static void __init db120_pci_init(u8 *eeprom)
-{
-	memcpy(db120_ath9k_data.eeprom_data, eeprom,
-	       sizeof(db120_ath9k_data.eeprom_data));
-
-	ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
-	ath79_register_pci();
-}
-#else
-static inline void db120_pci_init(void) {}
-#endif /* CONFIG_PCI */
-
-static void __init db120_setup(void)
-{
-	u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
-
-	ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
-				 db120_leds_gpio);
-	ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
-					ARRAY_SIZE(db120_gpio_keys),
-					db120_gpio_keys);
-	ath79_register_spi(&db120_spi_data, db120_spi_info,
-			   ARRAY_SIZE(db120_spi_info));
-	ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
-	db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
-}
-
-MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
-	     db120_setup);
diff --git a/trunk/arch/mips/ath79/mach-pb44.c b/trunk/arch/mips/ath79/mach-pb44.c
index c5f0ea5e00c3..fe9701a32291 100644
--- a/trunk/arch/mips/ath79/mach-pb44.c
+++ b/trunk/arch/mips/ath79/mach-pb44.c
@@ -19,7 +19,6 @@
 #include "dev-leds-gpio.h"
 #include "dev-spi.h"
 #include "dev-usb.h"
-#include "pci.h"
 
 #define PB44_GPIO_I2C_SCL	0
 #define PB44_GPIO_I2C_SDA	1
@@ -115,7 +114,6 @@ static void __init pb44_init(void)
 	ath79_register_spi(&pb44_spi_data, pb44_spi_info,
 			   ARRAY_SIZE(pb44_spi_info));
 	ath79_register_usb();
-	ath79_register_pci();
 }
 
 MIPS_MACHINE(ATH79_MACH_PB44, "PB44", "Atheros PB44 reference board",
diff --git a/trunk/arch/mips/ath79/mach-ubnt-xm.c b/trunk/arch/mips/ath79/mach-ubnt-xm.c
index 4a3c60694c75..3c311a539347 100644
--- a/trunk/arch/mips/ath79/mach-ubnt-xm.c
+++ b/trunk/arch/mips/ath79/mach-ubnt-xm.c
@@ -12,15 +12,16 @@
 
 #include <linux/init.h>
 #include <linux/pci.h>
-#include <linux/ath9k_platform.h>
 
-#include <asm/mach-ath79/irq.h>
+#ifdef CONFIG_PCI
+#include <linux/ath9k_platform.h>
+#include <asm/mach-ath79/pci-ath724x.h>
+#endif /* CONFIG_PCI */
 
 #include "machtypes.h"
 #include "dev-gpio-buttons.h"
 #include "dev-leds-gpio.h"
 #include "dev-spi.h"
-#include "pci.h"
 
 #define UBNT_XM_GPIO_LED_L1		0
 #define UBNT_XM_GPIO_LED_L2		1
@@ -32,6 +33,7 @@
 #define UBNT_XM_KEYS_POLL_INTERVAL	20
 #define UBNT_XM_KEYS_DEBOUNCE_INTERVAL	(3 * UBNT_XM_KEYS_POLL_INTERVAL)
 
+#define UBNT_XM_PCI_IRQ			48
 #define UBNT_XM_EEPROM_ADDR		(u8 *) KSEG1ADDR(0x1fff1000)
 
 static struct gpio_led ubnt_xm_leds_gpio[] __initdata = {
@@ -82,27 +84,12 @@ static struct ath79_spi_platform_data ubnt_xm_spi_data = {
 #ifdef CONFIG_PCI
 static struct ath9k_platform_data ubnt_xm_eeprom_data;
 
-static int ubnt_xm_pci_plat_dev_init(struct pci_dev *dev)
-{
-	switch (PCI_SLOT(dev->devfn)) {
-	case 0:
-		dev->dev.platform_data = &ubnt_xm_eeprom_data;
-		break;
-	}
-
-	return 0;
-}
-
-static void __init ubnt_xm_pci_init(void)
-{
-	memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
-	       sizeof(ubnt_xm_eeprom_data.eeprom_data));
-
-	ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
-	ath79_register_pci();
-}
-#else
-static inline void ubnt_xm_pci_init(void) {}
+static struct ath724x_pci_data ubnt_xm_pci_data[] = {
+	{
+		.irq	= UBNT_XM_PCI_IRQ,
+		.pdata	= &ubnt_xm_eeprom_data,
+	},
+};
 #endif /* CONFIG_PCI */
 
 static void __init ubnt_xm_init(void)
@@ -117,7 +104,13 @@ static void __init ubnt_xm_init(void)
 	ath79_register_spi(&ubnt_xm_spi_data, ubnt_xm_spi_info,
 			   ARRAY_SIZE(ubnt_xm_spi_info));
 
-	ubnt_xm_pci_init();
+#ifdef CONFIG_PCI
+	memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
+	       sizeof(ubnt_xm_eeprom_data.eeprom_data));
+
+	ath724x_pci_add_data(ubnt_xm_pci_data, ARRAY_SIZE(ubnt_xm_pci_data));
+#endif /* CONFIG_PCI */
+
 }
 
 MIPS_MACHINE(ATH79_MACH_UBNT_XM,
diff --git a/trunk/arch/mips/ath79/machtypes.h b/trunk/arch/mips/ath79/machtypes.h
index af92e5c30d66..9a1f3826626e 100644
--- a/trunk/arch/mips/ath79/machtypes.h
+++ b/trunk/arch/mips/ath79/machtypes.h
@@ -18,7 +18,6 @@ enum ath79_mach_type {
 	ATH79_MACH_GENERIC = 0,
 	ATH79_MACH_AP121,		/* Atheros AP121 reference board */
 	ATH79_MACH_AP81,		/* Atheros AP81 reference board */
-	ATH79_MACH_DB120,		/* Atheros DB120 reference board */
 	ATH79_MACH_PB44,		/* Atheros PB44 reference board */
 	ATH79_MACH_UBNT_XM,		/* Ubiquiti Networks XM board rev 1.0 */
 };
diff --git a/trunk/arch/mips/ath79/pci.c b/trunk/arch/mips/ath79/pci.c
deleted file mode 100644
index ca83abd9d31e..000000000000
--- a/trunk/arch/mips/ath79/pci.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- *  Atheros AR71XX/AR724X specific PCI setup code
- *
- *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  Parts of this file are based on Atheros' 2.6.15 BSP
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/irq.h>
-#include <asm/mach-ath79/pci.h>
-#include "pci.h"
-
-static int (*ath79_pci_plat_dev_init)(struct pci_dev *dev);
-static const struct ath79_pci_irq *ath79_pci_irq_map __initdata;
-static unsigned ath79_pci_nr_irqs __initdata;
-
-static const struct ath79_pci_irq ar71xx_pci_irq_map[] __initconst = {
-	{
-		.slot	= 17,
-		.pin	= 1,
-		.irq	= ATH79_PCI_IRQ(0),
-	}, {
-		.slot	= 18,
-		.pin	= 1,
-		.irq	= ATH79_PCI_IRQ(1),
-	}, {
-		.slot	= 19,
-		.pin	= 1,
-		.irq	= ATH79_PCI_IRQ(2),
-	}
-};
-
-static const struct ath79_pci_irq ar724x_pci_irq_map[] __initconst = {
-	{
-		.slot	= 0,
-		.pin	= 1,
-		.irq	= ATH79_PCI_IRQ(0),
-	}
-};
-
-int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
-{
-	int irq = -1;
-	int i;
-
-	if (ath79_pci_nr_irqs == 0 ||
-	    ath79_pci_irq_map == NULL) {
-		if (soc_is_ar71xx()) {
-			ath79_pci_irq_map = ar71xx_pci_irq_map;
-			ath79_pci_nr_irqs = ARRAY_SIZE(ar71xx_pci_irq_map);
-		} else if (soc_is_ar724x() ||
-			   soc_is_ar9342() ||
-			   soc_is_ar9344()) {
-			ath79_pci_irq_map = ar724x_pci_irq_map;
-			ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
-		} else {
-			pr_crit("pci %s: invalid irq map\n",
-				pci_name((struct pci_dev *) dev));
-			return irq;
-		}
-	}
-
-	for (i = 0; i < ath79_pci_nr_irqs; i++) {
-		const struct ath79_pci_irq *entry;
-
-		entry = &ath79_pci_irq_map[i];
-		if (entry->slot == slot && entry->pin == pin) {
-			irq = entry->irq;
-			break;
-		}
-	}
-
-	if (irq < 0)
-		pr_crit("pci %s: no irq found for pin %u\n",
-			pci_name((struct pci_dev *) dev), pin);
-	else
-		pr_info("pci %s: using irq %d for pin %u\n",
-			pci_name((struct pci_dev *) dev), irq, pin);
-
-	return irq;
-}
-
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	if (ath79_pci_plat_dev_init)
-		return ath79_pci_plat_dev_init(dev);
-
-	return 0;
-}
-
-void __init ath79_pci_set_irq_map(unsigned nr_irqs,
-				  const struct ath79_pci_irq *map)
-{
-	ath79_pci_nr_irqs = nr_irqs;
-	ath79_pci_irq_map = map;
-}
-
-void __init ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev))
-{
-	ath79_pci_plat_dev_init = func;
-}
-
-int __init ath79_register_pci(void)
-{
-	if (soc_is_ar71xx())
-		return ar71xx_pcibios_init();
-
-	if (soc_is_ar724x())
-		return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
-
-	if (soc_is_ar9342() || soc_is_ar9344()) {
-		u32 bootstrap;
-
-		bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
-		if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
-			return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
-	}
-
-	return -ENODEV;
-}
diff --git a/trunk/arch/mips/ath79/pci.h b/trunk/arch/mips/ath79/pci.h
deleted file mode 100644
index 51c6625dcc6d..000000000000
--- a/trunk/arch/mips/ath79/pci.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- *  Atheros AR71XX/AR724X PCI support
- *
- *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#ifndef _ATH79_PCI_H
-#define _ATH79_PCI_H
-
-struct ath79_pci_irq {
-	u8	slot;
-	u8	pin;
-	int	irq;
-};
-
-#ifdef CONFIG_PCI
-void ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map);
-void ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *dev));
-int ath79_register_pci(void);
-#else
-static inline void
-ath79_pci_set_irq_map(unsigned nr_irqs, const struct ath79_pci_irq *map) {}
-static inline void
-ath79_pci_set_plat_dev_init(int (*func)(struct pci_dev *)) {}
-static inline int ath79_register_pci(void) { return 0; }
-#endif
-
-#endif /* _ATH79_PCI_H */
diff --git a/trunk/arch/mips/ath79/setup.c b/trunk/arch/mips/ath79/setup.c
index 60d212ef8629..80a7d4023d7f 100644
--- a/trunk/arch/mips/ath79/setup.c
+++ b/trunk/arch/mips/ath79/setup.c
@@ -1,11 +1,10 @@
 /*
  *  Atheros AR71XX/AR724X/AR913X specific setup
  *
- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
- *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
@@ -117,6 +116,18 @@ static void __init ath79_detect_sys_type(void)
 		rev = id & AR724X_REV_ID_REVISION_MASK;
 		break;
 
+	case REV_ID_MAJOR_AR9330:
+		ath79_soc = ATH79_SOC_AR9330;
+		chip = "9330";
+		rev = id & AR933X_REV_ID_REVISION_MASK;
+		break;
+
+	case REV_ID_MAJOR_AR9331:
+		ath79_soc = ATH79_SOC_AR9331;
+		chip = "9331";
+		rev = id & AR933X_REV_ID_REVISION_MASK;
+		break;
+
 	case REV_ID_MAJOR_AR913X:
 		minor = id & AR913X_REV_ID_MINOR_MASK;
 		rev = id >> AR913X_REV_ID_REVISION_SHIFT;
@@ -134,36 +145,6 @@ static void __init ath79_detect_sys_type(void)
 		}
 		break;
 
-	case REV_ID_MAJOR_AR9330:
-		ath79_soc = ATH79_SOC_AR9330;
-		chip = "9330";
-		rev = id & AR933X_REV_ID_REVISION_MASK;
-		break;
-
-	case REV_ID_MAJOR_AR9331:
-		ath79_soc = ATH79_SOC_AR9331;
-		chip = "9331";
-		rev = id & AR933X_REV_ID_REVISION_MASK;
-		break;
-
-	case REV_ID_MAJOR_AR9341:
-		ath79_soc = ATH79_SOC_AR9341;
-		chip = "9341";
-		rev = id & AR934X_REV_ID_REVISION_MASK;
-		break;
-
-	case REV_ID_MAJOR_AR9342:
-		ath79_soc = ATH79_SOC_AR9342;
-		chip = "9342";
-		rev = id & AR934X_REV_ID_REVISION_MASK;
-		break;
-
-	case REV_ID_MAJOR_AR9344:
-		ath79_soc = ATH79_SOC_AR9344;
-		chip = "9344";
-		rev = id & AR934X_REV_ID_REVISION_MASK;
-		break;
-
 	default:
 		panic("ath79: unknown SoC, id:0x%08x", id);
 	}
diff --git a/trunk/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/trunk/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 1caa78ad06d5..2f0becb4ec8f 100644
--- a/trunk/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/trunk/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -1,11 +1,10 @@
 /*
  *  Atheros AR71XX/AR724X/AR913X SoC register definitions
  *
- *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
- *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
@@ -61,9 +60,6 @@
 #define AR933X_EHCI_BASE	0x1b000000
 #define AR933X_EHCI_SIZE	0x1000
 
-#define AR934X_WMAC_BASE	(AR71XX_APB_BASE + 0x00100000)
-#define AR934X_WMAC_SIZE	0x20000
-
 /*
  * DDR_CTRL block
  */
@@ -95,12 +91,6 @@
 #define AR933X_DDR_REG_FLUSH_USB	0x84
 #define AR933X_DDR_REG_FLUSH_WMAC	0x88
 
-#define AR934X_DDR_REG_FLUSH_GE0	0x9c
-#define AR934X_DDR_REG_FLUSH_GE1	0xa0
-#define AR934X_DDR_REG_FLUSH_USB	0xa4
-#define AR934X_DDR_REG_FLUSH_PCIE	0xa8
-#define AR934X_DDR_REG_FLUSH_WMAC	0xac
-
 /*
  * PLL block
  */
@@ -160,41 +150,6 @@
 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT	15
 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK	0x7
 
-#define AR934X_PLL_CPU_CONFIG_REG		0x00
-#define AR934X_PLL_DDR_CONFIG_REG		0x04
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG		0x08
-
-#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT	0
-#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK	0x3f
-#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT	6
-#define AR934X_PLL_CPU_CONFIG_NINT_MASK		0x3f
-#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT	12
-#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK	0x1f
-#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT	19
-#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK	0x3
-
-#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT	0
-#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK	0x3ff
-#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT	10
-#define AR934X_PLL_DDR_CONFIG_NINT_MASK		0x3f
-#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT	16
-#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK	0x1f
-#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT	23
-#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK	0x7
-
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS	BIT(2)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS	BIT(3)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS	BIT(4)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT	5
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK	0x1f
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT	10
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK	0x1f
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT	15
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK	0x1f
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL	BIT(20)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL	BIT(21)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL	BIT(24)
-
 /*
  * USB_CONFIG block
  */
@@ -230,10 +185,6 @@
 #define AR933X_RESET_REG_RESET_MODULE		0x1c
 #define AR933X_RESET_REG_BOOTSTRAP		0xac
 
-#define AR934X_RESET_REG_RESET_MODULE		0x1c
-#define AR934X_RESET_REG_BOOTSTRAP		0xb0
-#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS	0xac
-
 #define MISC_INT_ETHSW			BIT(12)
 #define MISC_INT_TIMER4			BIT(10)
 #define MISC_INT_TIMER3			BIT(9)
@@ -290,40 +241,6 @@
 
 #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)
 
-#define AR934X_BOOTSTRAP_SW_OPTION8	BIT(23)
-#define AR934X_BOOTSTRAP_SW_OPTION7	BIT(22)
-#define AR934X_BOOTSTRAP_SW_OPTION6	BIT(21)
-#define AR934X_BOOTSTRAP_SW_OPTION5	BIT(20)
-#define AR934X_BOOTSTRAP_SW_OPTION4	BIT(19)
-#define AR934X_BOOTSTRAP_SW_OPTION3	BIT(18)
-#define AR934X_BOOTSTRAP_SW_OPTION2	BIT(17)
-#define AR934X_BOOTSTRAP_SW_OPTION1	BIT(16)
-#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
-#define AR934X_BOOTSTRAP_PCIE_RC	BIT(6)
-#define AR934X_BOOTSTRAP_EJTAG_MODE	BIT(5)
-#define AR934X_BOOTSTRAP_REF_CLK_40	BIT(4)
-#define AR934X_BOOTSTRAP_BOOT_FROM_SPI	BIT(2)
-#define AR934X_BOOTSTRAP_SDRAM_DISABLED	BIT(1)
-#define AR934X_BOOTSTRAP_DDR1		BIT(0)
-
-#define AR934X_PCIE_WMAC_INT_WMAC_MISC		BIT(0)
-#define AR934X_PCIE_WMAC_INT_WMAC_TX		BIT(1)
-#define AR934X_PCIE_WMAC_INT_WMAC_RXLP		BIT(2)
-#define AR934X_PCIE_WMAC_INT_WMAC_RXHP		BIT(3)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC		BIT(4)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC0		BIT(5)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC1		BIT(6)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC2		BIT(7)
-#define AR934X_PCIE_WMAC_INT_PCIE_RC3		BIT(8)
-#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
-	(AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
-	 AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
-
-#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
-	(AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
-	 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
-	 AR934X_PCIE_WMAC_INT_PCIE_RC3)
-
 #define REV_ID_MAJOR_MASK		0xfff0
 #define REV_ID_MAJOR_AR71XX		0x00a0
 #define REV_ID_MAJOR_AR913X		0x00b0
@@ -332,9 +249,6 @@
 #define REV_ID_MAJOR_AR7242		0x1100
 #define REV_ID_MAJOR_AR9330		0x0110
 #define REV_ID_MAJOR_AR9331		0x1110
-#define REV_ID_MAJOR_AR9341		0x0120
-#define REV_ID_MAJOR_AR9342		0x1120
-#define REV_ID_MAJOR_AR9344		0x2120
 
 #define AR71XX_REV_ID_MINOR_MASK	0x3
 #define AR71XX_REV_ID_MINOR_AR7130	0x0
@@ -353,8 +267,6 @@
 
 #define AR724X_REV_ID_REVISION_MASK	0x3
 
-#define AR934X_REV_ID_REVISION_MASK     0xf
-
 /*
  * SPI block
  */
@@ -396,6 +308,5 @@
 #define AR724X_GPIO_COUNT		18
 #define AR913X_GPIO_COUNT		22
 #define AR933X_GPIO_COUNT		30
-#define AR934X_GPIO_COUNT		23
 
 #endif /* __ASM_MACH_AR71XX_REGS_H */
diff --git a/trunk/arch/mips/include/asm/mach-ath79/ath79.h b/trunk/arch/mips/include/asm/mach-ath79/ath79.h
index 4f248c3d7b23..6d0c6c9d5622 100644
--- a/trunk/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/trunk/arch/mips/include/asm/mach-ath79/ath79.h
@@ -29,9 +29,6 @@ enum ath79_soc_type {
 	ATH79_SOC_AR9132,
 	ATH79_SOC_AR9330,
 	ATH79_SOC_AR9331,
-	ATH79_SOC_AR9341,
-	ATH79_SOC_AR9342,
-	ATH79_SOC_AR9344,
 };
 
 extern enum ath79_soc_type ath79_soc;
@@ -78,26 +75,6 @@ static inline int soc_is_ar933x(void)
 		ath79_soc == ATH79_SOC_AR9331);
 }
 
-static inline int soc_is_ar9341(void)
-{
-	return (ath79_soc == ATH79_SOC_AR9341);
-}
-
-static inline int soc_is_ar9342(void)
-{
-	return (ath79_soc == ATH79_SOC_AR9342);
-}
-
-static inline int soc_is_ar9344(void)
-{
-	return (ath79_soc == ATH79_SOC_AR9344);
-}
-
-static inline int soc_is_ar934x(void)
-{
-	return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
-}
-
 extern void __iomem *ath79_ddr_base;
 extern void __iomem *ath79_pll_base;
 extern void __iomem *ath79_reset_base;
diff --git a/trunk/arch/mips/include/asm/mach-ath79/irq.h b/trunk/arch/mips/include/asm/mach-ath79/irq.h
index 0968f69e2018..519958fe4e3c 100644
--- a/trunk/arch/mips/include/asm/mach-ath79/irq.h
+++ b/trunk/arch/mips/include/asm/mach-ath79/irq.h
@@ -10,19 +10,11 @@
 #define __ASM_MACH_ATH79_IRQ_H
 
 #define MIPS_CPU_IRQ_BASE	0
-#define NR_IRQS			48
+#define NR_IRQS			40
 
 #define ATH79_MISC_IRQ_BASE	8
 #define ATH79_MISC_IRQ_COUNT	32
 
-#define ATH79_PCI_IRQ_BASE	(ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT)
-#define ATH79_PCI_IRQ_COUNT	6
-#define ATH79_PCI_IRQ(_x)	(ATH79_PCI_IRQ_BASE + (_x))
-
-#define ATH79_IP2_IRQ_BASE	(ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
-#define ATH79_IP2_IRQ_COUNT	2
-#define ATH79_IP2_IRQ(_x)	(ATH79_IP2_IRQ_BASE + (_x))
-
 #define ATH79_CPU_IRQ_IP2	(MIPS_CPU_IRQ_BASE + 2)
 #define ATH79_CPU_IRQ_USB	(MIPS_CPU_IRQ_BASE + 3)
 #define ATH79_CPU_IRQ_GE0	(MIPS_CPU_IRQ_BASE + 4)
diff --git a/trunk/arch/mips/include/asm/mach-ath79/pci-ath724x.h b/trunk/arch/mips/include/asm/mach-ath79/pci-ath724x.h
new file mode 100644
index 000000000000..454885fa30c3
--- /dev/null
+++ b/trunk/arch/mips/include/asm/mach-ath79/pci-ath724x.h
@@ -0,0 +1,21 @@
+/*
+ *  Atheros 724x PCI support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_ATH79_PCI_ATH724X_H
+#define __ASM_MACH_ATH79_PCI_ATH724X_H
+
+struct ath724x_pci_data {
+	int irq;
+	void *pdata;
+};
+
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size);
+
+#endif /* __ASM_MACH_ATH79_PCI_ATH724X_H */
diff --git a/trunk/arch/mips/include/asm/mach-ath79/pci.h b/trunk/arch/mips/include/asm/mach-ath79/pci.h
deleted file mode 100644
index 7868f7fa028f..000000000000
--- a/trunk/arch/mips/include/asm/mach-ath79/pci.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *  Atheros AR71XX/AR724X PCI support
- *
- *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_ATH79_PCI_H
-#define __ASM_MACH_ATH79_PCI_H
-
-#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
-int ar71xx_pcibios_init(void);
-#else
-static inline int ar71xx_pcibios_init(void) { return 0; }
-#endif
-
-#if defined(CONFIG_PCI_AR724X)
-int ar724x_pcibios_init(int irq);
-#else
-static inline int ar724x_pcibios_init(int irq) { return 0; }
-#endif
-
-#endif /* __ASM_MACH_ATH79_PCI_H */
diff --git a/trunk/arch/mips/kernel/perf_event_mipsxx.c b/trunk/arch/mips/kernel/perf_event_mipsxx.c
index 811084f4e422..574b4e9df50f 100644
--- a/trunk/arch/mips/kernel/perf_event_mipsxx.c
+++ b/trunk/arch/mips/kernel/perf_event_mipsxx.c
@@ -1532,7 +1532,8 @@ init_hw_perf_events(void)
 		irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
 	} else {
 #endif
-		if (cp0_perfcount_irq >= 0)
+		if ((cp0_perfcount_irq >= 0) &&
+				(cp0_compare_irq != cp0_perfcount_irq))
 			irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 		else
 			irq = -1;
diff --git a/trunk/arch/mips/oprofile/op_model_mipsxx.c b/trunk/arch/mips/oprofile/op_model_mipsxx.c
index 54759f1669d3..baba3bcaa3c2 100644
--- a/trunk/arch/mips/oprofile/op_model_mipsxx.c
+++ b/trunk/arch/mips/oprofile/op_model_mipsxx.c
@@ -298,6 +298,11 @@ static void reset_counters(void *arg)
 	}
 }
 
+static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
+{
+	return mipsxx_perfcount_handler();
+}
+
 static int __init mipsxx_init(void)
 {
 	int counters;
@@ -374,6 +379,10 @@ static int __init mipsxx_init(void)
 	save_perf_irq = perf_irq;
 	perf_irq = mipsxx_perfcount_handler;
 
+	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
+		return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
+			0, "Perfcounter", save_perf_irq);
+
 	return 0;
 }
 
@@ -381,6 +390,9 @@ static void mipsxx_exit(void)
 {
 	int counters = op_model_mipsxx_ops.num_counters;
 
+	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
+		free_irq(cp0_perfcount_irq, save_perf_irq);
+
 	counters = counters_per_cpu_to_total(counters);
 	on_each_cpu(reset_counters, (void *)(long)counters, 1);
 
diff --git a/trunk/arch/mips/pci/Makefile b/trunk/arch/mips/pci/Makefile
index 43c5138a8498..c3ac4b086eb2 100644
--- a/trunk/arch/mips/pci/Makefile
+++ b/trunk/arch/mips/pci/Makefile
@@ -19,8 +19,7 @@ obj-$(CONFIG_BCM47XX)		+= pci-bcm47xx.o
 obj-$(CONFIG_BCM63XX)		+= pci-bcm63xx.o fixup-bcm63xx.o \
 					ops-bcm63xx.o
 obj-$(CONFIG_MIPS_ALCHEMY)	+= pci-alchemy.o
-obj-$(CONFIG_SOC_AR71XX)	+= pci-ar71xx.o
-obj-$(CONFIG_PCI_AR724X)	+= pci-ar724x.o
+obj-$(CONFIG_SOC_AR724X)	+= pci-ath724x.o
 
 #
 # These are still pretty much in the old state, watch, go blind.
diff --git a/trunk/arch/mips/pci/pci-ar71xx.c b/trunk/arch/mips/pci/pci-ar71xx.c
deleted file mode 100644
index 1552522b8718..000000000000
--- a/trunk/arch/mips/pci/pci-ar71xx.c
+++ /dev/null
@@ -1,375 +0,0 @@
-/*
- *  Atheros AR71xx PCI host controller driver
- *
- *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
- *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
- *
- *  Parts of this file are based on Atheros' 2.6.15 BSP
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#include <linux/resource.h>
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/bitops.h>
-#include <linux/pci.h>
-#include <linux/pci_regs.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/pci.h>
-
-#define AR71XX_PCI_MEM_BASE	0x10000000
-#define AR71XX_PCI_MEM_SIZE	0x08000000
-
-#define AR71XX_PCI_WIN0_OFFS		0x10000000
-#define AR71XX_PCI_WIN1_OFFS		0x11000000
-#define AR71XX_PCI_WIN2_OFFS		0x12000000
-#define AR71XX_PCI_WIN3_OFFS		0x13000000
-#define AR71XX_PCI_WIN4_OFFS		0x14000000
-#define AR71XX_PCI_WIN5_OFFS		0x15000000
-#define AR71XX_PCI_WIN6_OFFS		0x16000000
-#define AR71XX_PCI_WIN7_OFFS		0x07000000
-
-#define AR71XX_PCI_CFG_BASE		\
-	(AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
-#define AR71XX_PCI_CFG_SIZE		0x100
-
-#define AR71XX_PCI_REG_CRP_AD_CBE	0x00
-#define AR71XX_PCI_REG_CRP_WRDATA	0x04
-#define AR71XX_PCI_REG_CRP_RDDATA	0x08
-#define AR71XX_PCI_REG_CFG_AD		0x0c
-#define AR71XX_PCI_REG_CFG_CBE		0x10
-#define AR71XX_PCI_REG_CFG_WRDATA	0x14
-#define AR71XX_PCI_REG_CFG_RDDATA	0x18
-#define AR71XX_PCI_REG_PCI_ERR		0x1c
-#define AR71XX_PCI_REG_PCI_ERR_ADDR	0x20
-#define AR71XX_PCI_REG_AHB_ERR		0x24
-#define AR71XX_PCI_REG_AHB_ERR_ADDR	0x28
-
-#define AR71XX_PCI_CRP_CMD_WRITE	0x00010000
-#define AR71XX_PCI_CRP_CMD_READ		0x00000000
-#define AR71XX_PCI_CFG_CMD_READ		0x0000000a
-#define AR71XX_PCI_CFG_CMD_WRITE	0x0000000b
-
-#define AR71XX_PCI_INT_CORE		BIT(4)
-#define AR71XX_PCI_INT_DEV2		BIT(2)
-#define AR71XX_PCI_INT_DEV1		BIT(1)
-#define AR71XX_PCI_INT_DEV0		BIT(0)
-
-#define AR71XX_PCI_IRQ_COUNT		5
-
-static DEFINE_SPINLOCK(ar71xx_pci_lock);
-static void __iomem *ar71xx_pcicfg_base;
-
-/* Byte lane enable bits */
-static const u8 ar71xx_pci_ble_table[4][4] = {
-	{0x0, 0xf, 0xf, 0xf},
-	{0xe, 0xd, 0xb, 0x7},
-	{0xc, 0xf, 0x3, 0xf},
-	{0xf, 0xf, 0xf, 0xf},
-};
-
-static const u32 ar71xx_pci_read_mask[8] = {
-	0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
-};
-
-static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
-{
-	u32 t;
-
-	t = ar71xx_pci_ble_table[size & 3][where & 3];
-	BUG_ON(t == 0xf);
-	t <<= (local) ? 20 : 4;
-
-	return t;
-}
-
-static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
-				      int where)
-{
-	u32 ret;
-
-	if (!bus->number) {
-		/* type 0 */
-		ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
-		      (where & ~3);
-	} else {
-		/* type 1 */
-		ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
-		      (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
-	}
-
-	return ret;
-}
-
-static int ar71xx_pci_check_error(int quiet)
-{
-	void __iomem *base = ar71xx_pcicfg_base;
-	u32 pci_err;
-	u32 ahb_err;
-
-	pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
-	if (pci_err) {
-		if (!quiet) {
-			u32 addr;
-
-			addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
-			pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
-				"PCI", pci_err, addr);
-		}
-
-		/* clear PCI error status */
-		__raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
-	}
-
-	ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
-	if (ahb_err) {
-		if (!quiet) {
-			u32 addr;
-
-			addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
-			pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
-				"AHB", ahb_err, addr);
-		}
-
-		/* clear AHB error status */
-		__raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
-	}
-
-	return !!(ahb_err | pci_err);
-}
-
-static inline void ar71xx_pci_local_write(int where, int size, u32 value)
-{
-	void __iomem *base = ar71xx_pcicfg_base;
-	u32 ad_cbe;
-
-	value = value << (8 * (where & 3));
-
-	ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
-	ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
-
-	__raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
-	__raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
-}
-
-static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
-					 unsigned int devfn,
-					 int where, int size, u32 cmd)
-{
-	void __iomem *base = ar71xx_pcicfg_base;
-	u32 addr;
-
-	addr = ar71xx_pci_bus_addr(bus, devfn, where);
-
-	__raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
-	__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
-		     base + AR71XX_PCI_REG_CFG_CBE);
-
-	return ar71xx_pci_check_error(1);
-}
-
-static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
-				  int where, int size, u32 *value)
-{
-	void __iomem *base = ar71xx_pcicfg_base;
-	unsigned long flags;
-	u32 data;
-	int err;
-	int ret;
-
-	ret = PCIBIOS_SUCCESSFUL;
-	data = ~0;
-
-	spin_lock_irqsave(&ar71xx_pci_lock, flags);
-
-	err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
-				     AR71XX_PCI_CFG_CMD_READ);
-	if (err)
-		ret = PCIBIOS_DEVICE_NOT_FOUND;
-	else
-		data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
-
-	spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
-
-	*value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
-
-	return ret;
-}
-
-static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
-				   int where, int size, u32 value)
-{
-	void __iomem *base = ar71xx_pcicfg_base;
-	unsigned long flags;
-	int err;
-	int ret;
-
-	value = value << (8 * (where & 3));
-	ret = PCIBIOS_SUCCESSFUL;
-
-	spin_lock_irqsave(&ar71xx_pci_lock, flags);
-
-	err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
-				     AR71XX_PCI_CFG_CMD_WRITE);
-	if (err)
-		ret = PCIBIOS_DEVICE_NOT_FOUND;
-	else
-		__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
-
-	spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
-
-	return ret;
-}
-
-static struct pci_ops ar71xx_pci_ops = {
-	.read	= ar71xx_pci_read_config,
-	.write	= ar71xx_pci_write_config,
-};
-
-static struct resource ar71xx_pci_io_resource = {
-	.name		= "PCI IO space",
-	.start		= 0,
-	.end		= 0,
-	.flags		= IORESOURCE_IO,
-};
-
-static struct resource ar71xx_pci_mem_resource = {
-	.name		= "PCI memory space",
-	.start		= AR71XX_PCI_MEM_BASE,
-	.end		= AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
-	.flags		= IORESOURCE_MEM
-};
-
-static struct pci_controller ar71xx_pci_controller = {
-	.pci_ops	= &ar71xx_pci_ops,
-	.mem_resource	= &ar71xx_pci_mem_resource,
-	.io_resource	= &ar71xx_pci_io_resource,
-};
-
-static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-	void __iomem *base = ath79_reset_base;
-	u32 pending;
-
-	pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
-		  __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
-	if (pending & AR71XX_PCI_INT_DEV0)
-		generic_handle_irq(ATH79_PCI_IRQ(0));
-
-	else if (pending & AR71XX_PCI_INT_DEV1)
-		generic_handle_irq(ATH79_PCI_IRQ(1));
-
-	else if (pending & AR71XX_PCI_INT_DEV2)
-		generic_handle_irq(ATH79_PCI_IRQ(2));
-
-	else if (pending & AR71XX_PCI_INT_CORE)
-		generic_handle_irq(ATH79_PCI_IRQ(4));
-
-	else
-		spurious_interrupt();
-}
-
-static void ar71xx_pci_irq_unmask(struct irq_data *d)
-{
-	unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
-	void __iomem *base = ath79_reset_base;
-	u32 t;
-
-	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
-	/* flush write */
-	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-}
-
-static void ar71xx_pci_irq_mask(struct irq_data *d)
-{
-	unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
-	void __iomem *base = ath79_reset_base;
-	u32 t;
-
-	t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-
-	/* flush write */
-	__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-}
-
-static struct irq_chip ar71xx_pci_irq_chip = {
-	.name		= "AR71XX PCI",
-	.irq_mask	= ar71xx_pci_irq_mask,
-	.irq_unmask	= ar71xx_pci_irq_unmask,
-	.irq_mask_ack	= ar71xx_pci_irq_mask,
-};
-
-static __init void ar71xx_pci_irq_init(void)
-{
-	void __iomem *base = ath79_reset_base;
-	int i;
-
-	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
-	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
-
-	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
-
-	for (i = ATH79_PCI_IRQ_BASE;
-	     i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
-		irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
-					 handle_level_irq);
-
-	irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
-}
-
-static __init void ar71xx_pci_reset(void)
-{
-	void __iomem *ddr_base = ath79_ddr_base;
-
-	ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
-	mdelay(100);
-
-	ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
-	mdelay(100);
-
-	__raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
-	__raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
-	__raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
-	__raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
-	__raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
-	__raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
-	__raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
-	__raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
-
-	mdelay(100);
-}
-
-__init int ar71xx_pcibios_init(void)
-{
-	u32 t;
-
-	ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
-	if (ar71xx_pcicfg_base == NULL)
-		return -ENOMEM;
-
-	ar71xx_pci_reset();
-
-	/* setup COMMAND register */
-	t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
-	  | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
-	ar71xx_pci_local_write(PCI_COMMAND, 4, t);
-
-	/* clear bus errors */
-	ar71xx_pci_check_error(1);
-
-	ar71xx_pci_irq_init();
-
-	register_pci_controller(&ar71xx_pci_controller);
-
-	return 0;
-}
diff --git a/trunk/arch/mips/pci/pci-ar724x.c b/trunk/arch/mips/pci/pci-ar724x.c
deleted file mode 100644
index 414a7459858d..000000000000
--- a/trunk/arch/mips/pci/pci-ar724x.c
+++ /dev/null
@@ -1,292 +0,0 @@
-/*
- *  Atheros AR724X PCI host controller driver
- *
- *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
- *  Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- */
-
-#include <linux/irq.h>
-#include <linux/pci.h>
-#include <asm/mach-ath79/ath79.h>
-#include <asm/mach-ath79/ar71xx_regs.h>
-#include <asm/mach-ath79/pci.h>
-
-#define AR724X_PCI_CFG_BASE	0x14000000
-#define AR724X_PCI_CFG_SIZE	0x1000
-#define AR724X_PCI_CTRL_BASE	(AR71XX_APB_BASE + 0x000f0000)
-#define AR724X_PCI_CTRL_SIZE	0x100
-
-#define AR724X_PCI_MEM_BASE	0x10000000
-#define AR724X_PCI_MEM_SIZE	0x08000000
-
-#define AR724X_PCI_REG_INT_STATUS	0x4c
-#define AR724X_PCI_REG_INT_MASK		0x50
-
-#define AR724X_PCI_INT_DEV0		BIT(14)
-
-#define AR724X_PCI_IRQ_COUNT		1
-
-#define AR7240_BAR0_WAR_VALUE	0xffff
-
-static DEFINE_SPINLOCK(ar724x_pci_lock);
-static void __iomem *ar724x_pci_devcfg_base;
-static void __iomem *ar724x_pci_ctrl_base;
-
-static u32 ar724x_pci_bar0_value;
-static bool ar724x_pci_bar0_is_cached;
-
-static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
-			    int size, uint32_t *value)
-{
-	unsigned long flags;
-	void __iomem *base;
-	u32 data;
-
-	if (devfn)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	base = ar724x_pci_devcfg_base;
-
-	spin_lock_irqsave(&ar724x_pci_lock, flags);
-	data = __raw_readl(base + (where & ~3));
-
-	switch (size) {
-	case 1:
-		if (where & 1)
-			data >>= 8;
-		if (where & 2)
-			data >>= 16;
-		data &= 0xff;
-		break;
-	case 2:
-		if (where & 2)
-			data >>= 16;
-		data &= 0xffff;
-		break;
-	case 4:
-		break;
-	default:
-		spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
-		return PCIBIOS_BAD_REGISTER_NUMBER;
-	}
-
-	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
-	if (where == PCI_BASE_ADDRESS_0 && size == 4 &&
-	    ar724x_pci_bar0_is_cached) {
-		/* use the cached value */
-		*value = ar724x_pci_bar0_value;
-	} else {
-		*value = data;
-	}
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
-			     int size, uint32_t value)
-{
-	unsigned long flags;
-	void __iomem *base;
-	u32 data;
-	int s;
-
-	if (devfn)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	if (soc_is_ar7240() && where == PCI_BASE_ADDRESS_0 && size == 4) {
-		if (value != 0xffffffff) {
-			/*
-			 * WAR for a hw issue. If the BAR0 register of the
-			 * device is set to the proper base address, the
-			 * memory space of the device is not accessible.
-			 *
-			 * Cache the intended value so it can be read back,
-			 * and write a SoC specific constant value to the
-			 * BAR0 register in order to make the device memory
-			 * accessible.
-			 */
-			ar724x_pci_bar0_is_cached = true;
-			ar724x_pci_bar0_value = value;
-
-			value = AR7240_BAR0_WAR_VALUE;
-		} else {
-			ar724x_pci_bar0_is_cached = false;
-		}
-	}
-
-	base = ar724x_pci_devcfg_base;
-
-	spin_lock_irqsave(&ar724x_pci_lock, flags);
-	data = __raw_readl(base + (where & ~3));
-
-	switch (size) {
-	case 1:
-		s = ((where & 3) * 8);
-		data &= ~(0xff << s);
-		data |= ((value & 0xff) << s);
-		break;
-	case 2:
-		s = ((where & 2) * 8);
-		data &= ~(0xffff << s);
-		data |= ((value & 0xffff) << s);
-		break;
-	case 4:
-		data = value;
-		break;
-	default:
-		spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
-		return PCIBIOS_BAD_REGISTER_NUMBER;
-	}
-
-	__raw_writel(data, base + (where & ~3));
-	/* flush write */
-	__raw_readl(base + (where & ~3));
-	spin_unlock_irqrestore(&ar724x_pci_lock, flags);
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops ar724x_pci_ops = {
-	.read	= ar724x_pci_read,
-	.write	= ar724x_pci_write,
-};
-
-static struct resource ar724x_io_resource = {
-	.name   = "PCI IO space",
-	.start  = 0,
-	.end    = 0,
-	.flags  = IORESOURCE_IO,
-};
-
-static struct resource ar724x_mem_resource = {
-	.name   = "PCI memory space",
-	.start  = AR724X_PCI_MEM_BASE,
-	.end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
-	.flags  = IORESOURCE_MEM,
-};
-
-static struct pci_controller ar724x_pci_controller = {
-	.pci_ops        = &ar724x_pci_ops,
-	.io_resource    = &ar724x_io_resource,
-	.mem_resource	= &ar724x_mem_resource,
-};
-
-static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-	void __iomem *base;
-	u32 pending;
-
-	base = ar724x_pci_ctrl_base;
-
-	pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
-		  __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-
-	if (pending & AR724X_PCI_INT_DEV0)
-		generic_handle_irq(ATH79_PCI_IRQ(0));
-
-	else
-		spurious_interrupt();
-}
-
-static void ar724x_pci_irq_unmask(struct irq_data *d)
-{
-	void __iomem *base;
-	u32 t;
-
-	base = ar724x_pci_ctrl_base;
-
-	switch (d->irq) {
-	case ATH79_PCI_IRQ(0):
-		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-		__raw_writel(t | AR724X_PCI_INT_DEV0,
-			     base + AR724X_PCI_REG_INT_MASK);
-		/* flush write */
-		__raw_readl(base + AR724X_PCI_REG_INT_MASK);
-	}
-}
-
-static void ar724x_pci_irq_mask(struct irq_data *d)
-{
-	void __iomem *base;
-	u32 t;
-
-	base = ar724x_pci_ctrl_base;
-
-	switch (d->irq) {
-	case ATH79_PCI_IRQ(0):
-		t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
-		__raw_writel(t & ~AR724X_PCI_INT_DEV0,
-			     base + AR724X_PCI_REG_INT_MASK);
-
-		/* flush write */
-		__raw_readl(base + AR724X_PCI_REG_INT_MASK);
-
-		t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
-		__raw_writel(t | AR724X_PCI_INT_DEV0,
-			     base + AR724X_PCI_REG_INT_STATUS);
-
-		/* flush write */
-		__raw_readl(base + AR724X_PCI_REG_INT_STATUS);
-	}
-}
-
-static struct irq_chip ar724x_pci_irq_chip = {
-	.name		= "AR724X PCI ",
-	.irq_mask	= ar724x_pci_irq_mask,
-	.irq_unmask	= ar724x_pci_irq_unmask,
-	.irq_mask_ack	= ar724x_pci_irq_mask,
-};
-
-static void __init ar724x_pci_irq_init(int irq)
-{
-	void __iomem *base;
-	int i;
-
-	base = ar724x_pci_ctrl_base;
-
-	__raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
-	__raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
-
-	BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR724X_PCI_IRQ_COUNT);
-
-	for (i = ATH79_PCI_IRQ_BASE;
-	     i < ATH79_PCI_IRQ_BASE + AR724X_PCI_IRQ_COUNT; i++)
-		irq_set_chip_and_handler(i, &ar724x_pci_irq_chip,
-					 handle_level_irq);
-
-	irq_set_chained_handler(irq, ar724x_pci_irq_handler);
-}
-
-int __init ar724x_pcibios_init(int irq)
-{
-	int ret;
-
-	ret = -ENOMEM;
-
-	ar724x_pci_devcfg_base = ioremap(AR724X_PCI_CFG_BASE,
-					 AR724X_PCI_CFG_SIZE);
-	if (ar724x_pci_devcfg_base == NULL)
-		goto err;
-
-	ar724x_pci_ctrl_base = ioremap(AR724X_PCI_CTRL_BASE,
-				       AR724X_PCI_CTRL_SIZE);
-	if (ar724x_pci_ctrl_base == NULL)
-		goto err_unmap_devcfg;
-
-	ar724x_pci_irq_init(irq);
-	register_pci_controller(&ar724x_pci_controller);
-
-	return PCIBIOS_SUCCESSFUL;
-
-err_unmap_devcfg:
-	iounmap(ar724x_pci_devcfg_base);
-err:
-	return ret;
-}
diff --git a/trunk/arch/mips/pci/pci-ath724x.c b/trunk/arch/mips/pci/pci-ath724x.c
new file mode 100644
index 000000000000..a4dd24a4130b
--- /dev/null
+++ b/trunk/arch/mips/pci/pci-ath724x.c
@@ -0,0 +1,174 @@
+/*
+ *  Atheros 724x PCI support
+ *
+ *  Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/pci.h>
+#include <asm/mach-ath79/pci-ath724x.h>
+
+#define reg_read(_phys)		(*(unsigned int *) KSEG1ADDR(_phys))
+#define reg_write(_phys, _val)	((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
+
+#define ATH724X_PCI_DEV_BASE	0x14000000
+#define ATH724X_PCI_MEM_BASE	0x10000000
+#define ATH724X_PCI_MEM_SIZE	0x08000000
+
+static DEFINE_SPINLOCK(ath724x_pci_lock);
+static struct ath724x_pci_data *pci_data;
+static int pci_data_size;
+
+static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
+			    int size, uint32_t *value)
+{
+	unsigned long flags, addr, tval, mask;
+
+	if (devfn)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (where & (size - 1))
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	spin_lock_irqsave(&ath724x_pci_lock, flags);
+
+	switch (size) {
+	case 1:
+		addr = where & ~3;
+		mask = 0xff000000 >> ((where % 4) * 8);
+		tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+		tval = tval & ~mask;
+		*value = (tval >> ((4 - (where % 4))*8));
+		break;
+	case 2:
+		addr = where & ~3;
+		mask = 0xffff0000 >> ((where % 4)*8);
+		tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
+		tval = tval & ~mask;
+		*value = (tval >> ((4 - (where % 4))*8));
+		break;
+	case 4:
+		*value = reg_read(ATH724X_PCI_DEV_BASE + where);
+		break;
+	default:
+		spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
+			     int size, uint32_t value)
+{
+	unsigned long flags, tval, addr, mask;
+
+	if (devfn)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (where & (size - 1))
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+
+	spin_lock_irqsave(&ath724x_pci_lock, flags);
+
+	switch (size) {
+	case 1:
+		addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+		mask = 0xff000000 >> ((where % 4)*8);
+		tval = reg_read(addr);
+		tval = tval & ~mask;
+		tval |= (value << ((4 - (where % 4))*8)) & mask;
+		reg_write(addr, tval);
+		break;
+	case 2:
+		addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
+		mask = 0xffff0000 >> ((where % 4)*8);
+		tval = reg_read(addr);
+		tval = tval & ~mask;
+		tval |= (value << ((4 - (where % 4))*8)) & mask;
+		reg_write(addr, tval);
+		break;
+	case 4:
+		reg_write((ATH724X_PCI_DEV_BASE + where), value);
+		break;
+	default:
+		spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+		return PCIBIOS_BAD_REGISTER_NUMBER;
+	}
+
+	spin_unlock_irqrestore(&ath724x_pci_lock, flags);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops ath724x_pci_ops = {
+	.read	= ath724x_pci_read,
+	.write	= ath724x_pci_write,
+};
+
+static struct resource ath724x_io_resource = {
+	.name   = "PCI IO space",
+	.start  = 0,
+	.end    = 0,
+	.flags  = IORESOURCE_IO,
+};
+
+static struct resource ath724x_mem_resource = {
+	.name   = "PCI memory space",
+	.start  = ATH724X_PCI_MEM_BASE,
+	.end    = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
+	.flags  = IORESOURCE_MEM,
+};
+
+static struct pci_controller ath724x_pci_controller = {
+	.pci_ops        = &ath724x_pci_ops,
+	.io_resource    = &ath724x_io_resource,
+	.mem_resource	= &ath724x_mem_resource,
+};
+
+void ath724x_pci_add_data(struct ath724x_pci_data *data, int size)
+{
+	pci_data	= data;
+	pci_data_size	= size;
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+{
+	unsigned int devfn = dev->devfn;
+	int irq = -1;
+
+	if (devfn > pci_data_size - 1)
+		return irq;
+
+	irq = pci_data[devfn].irq;
+
+	return irq;
+}
+
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+	unsigned int devfn = dev->devfn;
+
+	if (devfn > pci_data_size - 1)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	dev->dev.platform_data = pci_data[devfn].pdata;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int __init ath724x_pcibios_init(void)
+{
+	register_pci_controller(&ath724x_pci_controller);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+arch_initcall(ath724x_pcibios_init);