From cb6b1893c74ce3157198dd4de8f6bc98cd24ff0f Mon Sep 17 00:00:00 2001 From: Jaecheol Lee Date: Mon, 18 Jul 2011 19:25:03 +0900 Subject: [PATCH] --- yaml --- r: 260628 b: refs/heads/master c: f4ba4b01ef28100070608d915feda173d2a61c0c h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-exynos4/pm.c | 26 +++++++++++++++++++++++++- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index aa91a3b9cbc4..ddf037b9eb22 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 12974e9f707888044a3af3a12ebdebf0a509a1fa +refs/heads/master: f4ba4b01ef28100070608d915feda173d2a61c0c diff --git a/trunk/arch/arm/mach-exynos4/pm.c b/trunk/arch/arm/mach-exynos4/pm.c index aa27b90068c0..e978e76beed7 100644 --- a/trunk/arch/arm/mach-exynos4/pm.c +++ b/trunk/arch/arm/mach-exynos4/pm.c @@ -207,7 +207,10 @@ static struct sleep_save exynos4_l2cc_save[] = { SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL), }; -void exynos4_cpu_suspend(void) +/* For Cortex-A9 Diagnostic and Power control register */ +static unsigned int save_arm_register[2]; + +void exynos4_cpu_suspend(unsigned long arg) { outer_flush_all(); @@ -301,6 +304,16 @@ static int exynos4_pm_suspend(void) tmp &= ~S5P_CENTRAL_LOWPWR_CFG; __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION); + /* Save Power control register */ + asm ("mrc p15, 0, %0, c15, c0, 0" + : "=r" (tmp) : : "cc"); + save_arm_register[0] = tmp; + + /* Save Diagnostic register */ + asm ("mrc p15, 0, %0, c15, c0, 1" + : "=r" (tmp) : : "cc"); + save_arm_register[1] = tmp; + return 0; } @@ -321,6 +334,17 @@ static void exynos4_pm_resume(void) /* No need to perform below restore code */ goto early_wakeup; } + /* Restore Power control register */ + tmp = save_arm_register[0]; + asm volatile ("mcr p15, 0, %0, c15, c0, 0" + : : "r" (tmp) + : "cc"); + + /* Restore Diagnostic register */ + tmp = save_arm_register[1]; + asm volatile ("mcr p15, 0, %0, c15, c0, 1" + : : "r" (tmp) + : "cc"); /* For release retention */