From cbdb84ea15b0f662e0c018f33566e844725141be Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Tue, 30 Oct 2012 19:16:34 +0800 Subject: [PATCH] --- yaml --- r: 345211 b: refs/heads/master c: 263b30d4b1a52432075069070328cfa641179f92 h: refs/heads/master i: 345209: e0f98f7de6b47d6e9f43d4041671dddce341441d 345207: e78b214cd9972cebea6304ecd495133116d2c796 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_pm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index a7fb4f478614..8448c1e87652 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 14f86147a90cb47db7ccfd90bf14f830fb34fba9 +refs/heads/master: 263b30d4b1a52432075069070328cfa641179f92 diff --git a/trunk/drivers/gpu/drm/i915/intel_pm.c b/trunk/drivers/gpu/drm/i915/intel_pm.c index f85043ca41b5..59c31f6238c1 100644 --- a/trunk/drivers/gpu/drm/i915/intel_pm.c +++ b/trunk/drivers/gpu/drm/i915/intel_pm.c @@ -3842,7 +3842,7 @@ void intel_init_power_wells(struct drm_device *dev) if ((well & HSW_PWR_WELL_STATE) == 0) { I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); - if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20)) + if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); } }