From cbe59140d9c63249706c83d97f66270672262dda Mon Sep 17 00:00:00 2001 From: Afzal Mohammed Date: Wed, 23 Jan 2013 17:12:11 +0530 Subject: [PATCH] --- yaml --- r: 359844 b: refs/heads/master c: 0c3c22f9c53e2fc282d0fb221a6e8c9cf9eeafe8 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/cclock33xx_data.c | 10 ++++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index db761cd87810..2c29408313d3 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 601155b04c2e93c00644003811f59444a9e356e2 +refs/heads/master: 0c3c22f9c53e2fc282d0fb221a6e8c9cf9eeafe8 diff --git a/trunk/arch/arm/mach-omap2/cclock33xx_data.c b/trunk/arch/arm/mach-omap2/cclock33xx_data.c index ea64ad606759..476b82066cb6 100644 --- a/trunk/arch/arm/mach-omap2/cclock33xx_data.c +++ b/trunk/arch/arm/mach-omap2/cclock33xx_data.c @@ -284,9 +284,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops); * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 * and ALT_CLK1/2) */ -DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0, - AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT, - AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); +DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, + CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP, + AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH, + CLK_DIVIDER_ONE_BASED, NULL); /* DPLL_PER */ static struct dpll_data dpll_per_dd = { @@ -723,7 +724,8 @@ static struct clk_hw_omap lcd_gclk_hw = { .clksel_mask = AM33XX_CLKSEL_0_1_MASK, }; -DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops); +DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents, + gpio_fck_ops, CLK_SET_RATE_PARENT); DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);